Semiconductor device, power conversion device, and method for manufacturing same

Abstract

According to an embodiment of the present invention, a semiconductor device comprises: a semiconductor chip in which a source electrode and a gate electrode are provided on a first surface, and a drain electrode is provided on a second surface on the opposite side from the first surface; a source terminal which has a fourth surface that is exposed from a third surface of the package and a fifth surface that is connected to the source electrode and that has a different shape from the fourth surface; a gate terminal which has a sixth surface that is exposed from the third surface of the package and a seventh surface that is connected to the gate electrode and that has a different shape from the sixth surface; and a drain terminal which is connected to the drain electrode and has an eighth surface that is exposed from the third surface of the package.

Description

Semiconductor device, power conversion device, and manufacturing method thereof

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a power conversion device, and a manufacturing method thereof.

[0002] 2. Description of the Related Art Known switching elements used in power conversion devices (for example, DC-DC converters) include semiconductor devices such as power MOSFETs that are surface-mounted on printed circuit boards.

[0003] Japanese Patent Application Publication No. 2022-145046

[0004] A semiconductor device capable of improving the mounting capacity of semiconductor chips is provided.

[0005] The semiconductor device of the embodiment includes a semiconductor chip having a source electrode and a gate electrode on a first surface and a drain electrode on a second surface opposite the first surface, a source terminal connected to the source electrode and a fourth surface exposed from the third surface of the package and having a fifth surface having a shape different from the fourth surface, a gate terminal connected to the gate electrode and a sixth surface exposed from the third surface of the package and having a seventh surface having a shape different from the sixth surface, and a drain terminal connected to the drain electrode and having an eighth surface exposed from the third surface of the package.

[0006] 16 is a plan view of the front surface of a package of a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view taken along line A1-A2 in FIGS. 1 and 2. FIG. 4 is a cross-sectional view taken along line B1-B2 in FIGS. 1 and 2. FIG. 5 is a cross-sectional view taken along line C1-C2 in FIGS. 3 and 4. FIG. 6 is a cross-sectional view taken along line D1-D2 in FIGS. 3 and 4. FIG. 7 is a diagram showing the assembly process flow of a semiconductor device according to the first embodiment. FIG. 8 is a plan view of the front surface of a package of a semiconductor device according to a second embodiment. FIG. 9 is a plan view of the back surface of a package of a semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view taken along line A3-A4 in FIGS. 9 and 10. FIG. 11 is a cross-sectional view taken along line B3-B4 in FIGS. 11 and 12. FIG. 12 is a cross-sectional view taken along line D3-D4 in FIGS. 11 and 12. FIG. 16 is a diagram showing the assembly process flow of a semiconductor device according to the second embodiment. FIG. 17 is a cross-sectional view taken along line A5-A6 in FIG. 29. A cross-sectional view taken along line B5-B6 in FIG. 16. A diagram showing the flow of an assembly process for a semiconductor device according to a third embodiment. A plan view of the package surface of a semiconductor device according to a fourth embodiment. A cross-sectional view taken along line A7-A8 in FIG. 20. A cross-sectional view taken along line B7-B8 in FIG. 20. A diagram showing the flow of an assembly process for a semiconductor device according to a fourth embodiment. A circuit diagram of a power conversion device according to a fifth embodiment. A plan view of a power conversion device according to a fifth embodiment. A cross-sectional view taken along line X1-X2 in FIG. 25. A plan view of a power conversion device according to a sixth embodiment. A cross-sectional view taken along line X3-X4 in FIG. 27. A plan view of a power conversion device according to a seventh embodiment. A cross-sectional view taken along line X5-X6 in FIG. 29. Embodiment

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration will be assigned the same reference numerals. Furthermore, the embodiments shown below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and the materials, shapes, structures, and arrangements of the components are not limited to those described below. Furthermore, in the drawings referred to below, components such as insulating layers, coating films, wiring, and contacts are omitted as appropriate in this specification to make the drawings easier to understand.

[0008] 1. First Embodiment First, a first embodiment will be described. In the first embodiment, a semiconductor device 1 including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that functions as a switching element will be described. The MOSFET is used in a power conversion device, such as a DC-DC converter or an inverter. The substrate on which the MOSFET is formed may be a Si substrate or a SiC substrate. Furthermore, the semiconductor device 1 may include an IGBT (Insulated Gate Bipolar Transistor) formed on the Si substrate instead of the MOSFET.

[0009] 1.1 Configuration of Semiconductor Device 1.1.1 Planar Configuration of Semiconductor Device First, an example of the planar configuration of the semiconductor device 1 will be described. FIG. 1 is a plan view of the package front surface of the semiconductor device 1. FIG. 2 is a plan view of the package back surface of the semiconductor device 1. In the following description, when the semiconductor device 1 is surface-mounted on a printed circuit board, for example, the mounting surface that is joined to the printed circuit board will be referred to as the "package back surface." Furthermore, the surface of the semiconductor device 1 that faces the package back surface will be referred to as the "package front surface." In the examples of FIGS. 1 and 2, the plane along the package front surface and package back surface will be referred to as the XY plane. Furthermore, on the package back surface, the direction connecting the drain terminal and the source terminal will be referred to as the X direction, and the direction intersecting the X direction will be referred to as the Y direction. Furthermore, the direction intersecting the XY plane will be referred to as the Z direction. The surface of the semiconductor device 1 facing the X direction or the Y direction will be referred to as the "package side surface."

[0010] As shown in FIGS. 1 and 2 , the semiconductor device 1 includes a source terminal 10, a gate terminal 11, a drain terminal 12, and a molded resin 13. Etched lead frames (hereinafter also referred to as “etched frames”) are used for the source terminal 10, the gate terminal 11, and the drain terminal 12. The source terminal 10, the gate terminal 11, and the drain terminal 12 are made of a conductive material, such as copper. The conductive material may also include a high-melting-point material. The surfaces of each terminal exposed from the molded resin 13 (hereinafter referred to as “exposed surfaces”) may or may not be covered with tin (Sn), solder, or the like. The semiconductor device 1 of this embodiment can be applied to surface mounting and vertical mounting. For example, in surface mounting applications, the exposed surfaces are covered with tin, solder, or the like. For example, in vertical mounting applications, the exposed surfaces of each terminal are not covered with tin, solder, or the like. For example, when the semiconductor device 1 is embedded in a printed circuit board using vertical mounting, Cu-plated wiring is formed. For this reason, it is preferable that the exposed surfaces of the terminals are not covered with tin, solder, etc. While Figures 1 and 2 show a structure in which the terminals (lead terminals) do not protrude from the molded resin 13 (i.e., the package), such as DFN (Dual Flatpack Non-leaded), this is not limiting. The terminals may protrude from the molded resin 13.

[0011] The source terminal 10 and the gate terminal 11 have exposed surfaces on the back surface of the package. The exposed surfaces of the source terminal 10 and the gate terminal 11 are electrically connected to a printed circuit board via solder or the like. The exposed surfaces of the source terminal 10 and the gate terminal 11 may have any shape. In the example of FIG. 2 , four protrusions are provided on one end of the source terminal 10 facing the X direction. For example, the four protrusions extend to the end of the molded resin 13 (package) facing the X direction. The four protrusions are exposed on the side of the package facing the X direction on the extending side. Note that, when multiple semiconductor devices 1 are diced into individual pieces during the assembly process of the semiconductor device 1, the cut surface of the etching frame forming the source terminal 10 may be exposed from the side of the package.

[0012] The exposed surface of the gate terminal 11 has, for example, a rectangular shape. For example, one end of the gate terminal 11 facing the Y direction extends to an end of the mold resin 13 facing the Y direction. The gate terminal 11 is exposed on a side surface of the package facing the Y direction.

[0013] The exposed surfaces of the drain terminal 12 are provided on the front and back surfaces of the package. For example, the drain terminal 12 can be electrically connected to a printed circuit board on the front or back surface of the package. The exposed surface of the drain terminal 12 may have any shape. In the example of FIG. 1, the exposed surface of the drain terminal 12 on the front surface of the package is rectangular. For example, one end of the drain terminal 12 facing the X direction extends to an end of the molded resin 13 facing the X direction. In the example of FIG. 2, the exposed surface of the drain terminal 12 on the back surface of the package faces the source terminal 10 in the X direction. Four protrusions are provided on one end of the drain terminal 12 facing the X direction. For example, the four protrusions extend to an end of the molded resin 13 facing the X direction. The drain terminal 12 is exposed on a side surface of the package facing the X direction.

[0014] The mold resin 13 seals the semiconductor device 1. The mold resin 13 stably maintains the insulating state and arrangement between the semiconductor chip (not shown), the source terminal 10, the gate terminal 11, and the drain terminal 12 within the semiconductor device 1. The mold resin 13 may be, for example, an epoxy resin. The mold resin 13 may contain a filler such as silicon oxide.

[0015] 1.1.2 Cross-sectional Configuration of Semiconductor Device Next, an example of the cross-sectional configuration of the semiconductor device 1 will be described. Fig. 3 is a cross-sectional view taken along line A1-A2 in Figs. 1 and 2. Fig. 4 is a cross-sectional view taken along line B1-B2 in Figs. 1 and 2. Fig. 5 is a plan view of the first surface of the semiconductor chip 20. Note that in the example of Fig. 5, conductive layers 23s and 23g, which will be described later, are omitted.

[0016] As shown in FIGS. 3 and 4, the semiconductor device 1 further includes a semiconductor chip 20, and mounting materials 31s, 31g, and 31g.

[0017] The semiconductor chip 20 is, for example, a MOSFET. The semiconductor chip 20 is disposed between the source terminal 10, the gate terminal 11, and the drain terminal 12. In the following description, the surface of the semiconductor chip 20 that intersects with the Z direction and faces the source terminal 10 and the gate terminal 11 will be referred to as the "first surface." Furthermore, the surface of the semiconductor chip 20 that faces the first surface and the drain terminal 12 will be referred to as the "second surface."

[0018] The semiconductor chip 20 includes a source electrode 21s, a gate electrode 21g, a drain electrode 21d, a passivation film 22, and conductive layers 23s and 23g.

[0019] A source electrode 21s and a gate electrode 21g are provided on the first surface of the semiconductor chip 20. As shown in Fig. 5, a passivation film 22 is provided so as to surround the source electrode 21s and the gate electrode 21g. A conductive layer 23s and a conductive layer 23g are provided on the source electrode 21s and the gate electrode 21g, respectively. A configuration in which the second surface of the semiconductor chip 20 on which the source electrode 21s and the like are provided faces the package back surface SF2 may also be referred to as a "source-down package."

[0020] As shown in FIGS. 3 and 4, a drain electrode 21d is provided on the second surface of the semiconductor chip 20.

[0021] The source electrode 21s is connected to the source of the MOSFET. The gate electrode 21g is connected to the gate of the MOSFET. The drain electrode 21d is connected to the drain of the MOSFET. The source electrode 21s, the gate electrode 21g, and the drain electrode 21d are made of a conductive material. The source electrode 21s and the gate electrode 21g include, for example, aluminum. The drain electrode 21d includes, for example, a titanium / nickel / gold stacked film, a gold-silver alloy, or silver.

[0022] The passivation film 22 physically and electrically separates the source electrode 21s from the gate electrode 21g, and is made of a resin material such as polyimide.

[0023] The conductive layers 23s and 23g are formed by, for example, a dry process such as sputtering or vapor deposition, or a wet process such as electrolytic plating or electroless plating, and include, for example, at least one of copper, nickel, silver, gold, and palladium.

[0024] The mounting material 31s bonds the conductive layer 23s to the source terminal 10. The mounting material 31g bonds the conductive layer 23g to the gate terminal 11. The mounting material 31d bonds the drain electrode 21d to the drain terminal 12. Hereinafter, the surfaces of the source terminal 10, the gate terminal 11, and the drain terminal 12 that are bonded to the semiconductor chip 20 will be referred to as "chip bonding surfaces." The mounting materials 31s, 31g, and 31d are made of a conductive material. For example, solder is used for the mounting materials 31s, 31g, and 31d. Note that a sintered material that is difficult to melt (e.g., copper, silver, lead, a tin-copper compound, a tin-silver compound, or a tin-nickel compound) may be used instead of solder. In this case, a pressure-sintered material with excellent pressure resistance may be used.

[0025] The source terminal 10 and the gate terminal 11 are formed from the same etching frame, and therefore the thickness (height in the Z direction) of the source terminal 10 and the gate terminal 11 are approximately the same.

[0026] The source terminal 10 has a half-etched region HE that is half-etched in the Z direction from the exposed surface of the package back surface SF2. In other words, the source terminal 10 has a protrusion on the chip bonding surface side that protrudes from the exposed surface in the X and / or Y directions. A portion of the end of the chip bonding surface of the source terminal 10 protrudes from the exposed surface. The height of the half-etched region HE in the Z direction is arbitrary. In the examples of FIGS. 3 and 4 , half-etched regions HE are provided at both ends in the X direction, extending from the exposed surface of the package back surface SF2 (the lower side of the drawing) toward the chip bonding surface with the semiconductor chip 20. Therefore, the area and shape of the exposed surface of the source terminal 10 are different from the area and shape of the chip bonding surface. Also, in the examples of FIGS. 3 and 4 , the protrusion on the chip bonding surface side of the source terminal 10 in the X direction is exposed from the side of the package. By expanding the chip bonding surface to the side of the package, the chip size of the semiconductor chip 20 that can be mounted on the semiconductor device 1 can be increased.

[0027] As shown in FIG. 4 , the gate terminal 11 has a half-etched region HE half-etched in the Z direction from the exposed surface and a half-etched region HE half-etched in the Z direction from the chip bonding surface. That is, the gate terminal 11 has a shape half-etched from both the exposed surface and the chip bonding surface. In other words, the gate terminal 11 has a protrusion protruding in the X direction and / or Y direction from the exposed surface on the chip bonding surface side, and a protrusion protruding in the X direction and / or Y direction from the chip bonding surface on the exposed surface side. The Z-direction height of the half-etched region HE half-etched in the Z direction from the exposed surface of the gate terminal 11 is approximately the same as the Z-direction height of the half-etched region HE of the source terminal 10. The area and shape of the exposed surface of the gate terminal 11 are different from those of the chip bonding surface. This allows the exposed surface of the gate terminal 11 to be located at any position on the package back surface SF2, regardless of the position of the gate electrode 21g of the semiconductor chip 20.

[0028] For example, the etching frame that forms the drain terminal 12 is formed by etching a lead frame that is thicker than the etching frames that form the source terminal 10 and the gate terminal 11. For example, the etching frame used for the drain terminal 12 has the same thickness as the package. The etching frame is etched from the back surface side of the package to form areas on which the semiconductor chip 20, the source terminal 10, and the gate terminal 11 are mounted.

[0029] The drain terminal 12 includes a first portion 12a and a second portion 12b. The first portion 12a is a plate-shaped portion extending on the XY plane. The surface of the first portion 12a facing the front surface of the package is exposed from the package surface SF1. The surface of the first portion 12a facing the back surface of the package is a chip bonding surface to which the drain electrode 21d is bonded via a mounting material 31d. One end of the second portion 12b is connected to the end of the first portion 12a in the X direction. The second portion 12b extends in the Z direction. The other end of the second portion 12b is exposed on the package back surface SF2.

[0030] The second portion 12b of the drain terminal 12 has a half-etched region HE that is half-etched in the Z direction from the exposed surface of the package back surface SF2 on the package side surface facing the X direction. In other words, the drain terminal 12 has a protrusion that protrudes in the X direction from the exposed surface. The height in the Z direction of the half-etched region HE of the drain terminal 12 may be different from the height in the Z direction of the half-etched regions HE of the source terminal 10 and the gate terminal 11. For example, the length in the Z direction of the half-etched region HE of the drain terminal 12 is longer than the length in the Z direction of the half-etched regions HE of the source terminal 10 and the gate terminal 11. In the X direction, the end (protrusion) of the drain terminal that is not half-etched is exposed from the package side surface.

[0031] 3 and 4, the half-etched regions HE of the source terminal 10 and the drain terminal 12 on the side surface of the package are sealed with molded resin 13, but the molded resin 13 in this region may be omitted. That is, the half-etched regions HE of each terminal may be exposed on the side surface of the package. The same applies to the Y-direction end of the gate terminal 11 (not shown). This allows the semiconductor device 1 to be compatible with wettable flanks. For example, when the semiconductor device 1 is surface-mounted on a printed circuit board, solder can flow into the half-etched regions HE exposed on the side surface of the package, confirming that the soldering operation was performed correctly.

[0032] Furthermore, the source terminal 10 may have a half-etched region HE that is half-etched in the Z direction from the chip bonding surface, similar to the gate terminal 11. In order to improve the mounting accuracy of the semiconductor chip 20, a slit (half-etched region HE) that matches the chip size may be formed in the chip bonding surface of the source terminal 10.

[0033] 1.1.3 Planar Configuration of Each Terminal Next, an example of the planar configuration of each terminal will be described. FIG. 6 is a plan view taken along line C1-C2 in FIGS. 3 and 4. FIG. 7 is a plan view taken along line D1-D2 in FIGS. 3 and 4. FIG. 6 shows the shape of the chip bonding surfaces of the source terminal 10 and gate terminal 11, and the portion of the drain terminal 12 that does not include the half-etched region HE. FIG. 7 shows the shape of the exposed surfaces of the source terminal 10, gate terminal 11, and drain terminal 12 on the package back surface SF2. FIGS. 6 and 7 show plan views as seen from the package front surface side. In FIGS. 6 and 7, the chip area where the semiconductor chip 20 is disposed is indicated by dashed lines. The following description will focus on the source terminal 10 and gate terminal 11.

[0034] 6 and 7 , the shapes of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 are different from the shapes of the exposed surfaces of the package back surface SF2. For example, the areas of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 are larger than the areas of the exposed surfaces of the package back surface SF2. For example, the position of the bonding surface of the gate terminal 11 on the XY plane is different from the position of the exposed surface of the gate terminal 11 on the XY plane.

[0035] The shapes of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 are designed based on the semiconductor chip 20 to be mounted on the semiconductor device 1. For example, the end of the chip bonding surface of the source terminal 10 extends to the side surface of the package. This improves the degree of freedom in the layout of the source electrode 21s and the gate electrode 21g of the compatible semiconductor chip 20. Furthermore, the chip size of the mountable semiconductor chip 20 can be made larger than the layout of the exposed surfaces of the source terminal 10 and the gate terminal 11. This improves the mounting capacity of the semiconductor chip 20.

[0036] The shapes of the exposed surfaces of the source terminal 10, the gate terminal 11, and the drain terminal 12 on the package back surface SF2 can be made compatible with the layout of, for example, an existing DFN, etc. This improves the versatility (compatibility) of the semiconductor device 1.

[0037] 1.2 Manufacturing Method of Semiconductor Device Next, an example of a manufacturing method of the semiconductor device 1 will be described. Figure 8 is a diagram showing the flow of the assembly process. Note that, for the sake of simplicity, the example of Figure 8 shows a cross section of the semiconductor device 1 taken along line A1-A2 in Figures 1 and 2, and the gate terminal 11 is omitted. Furthermore, in the example of Figure 8, the source electrode 21s, gate electrode 21g, drain electrode 21d, passivation film 22, and conductive layers 23s and 23g are omitted.

[0038] As shown in FIG. 8A, a first etching frame is first prepared, on which a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 are provided. A semiconductor chip 20 is mounted on the source terminals 10 and gate terminals 11, respectively, with mounting materials 31s and 31g interposed therebetween, so that the source terminals 10 are connected to the source electrodes 21s and the gate terminals 11 are connected to the gate electrodes 21g (S1). Next, a second etching frame on which the drain terminals 12 are provided is mounted on the drain electrodes 21d of the semiconductor chip 20, with mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. Cleaning may be omitted if the residue of the mounting material 31 does not cause problems such as poor insulation or peeling. In addition, the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame provided with the source terminal 10 and the gate terminal 11 may be mounted in this order on the second etching frame provided with the drain terminal 12.

[0039] 8B, the plurality of semiconductor devices 1 sharing the first and second etching frames are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed. During molding, the etching frames may be covered with a release film to prevent the molding resin from getting into the half-etched portions.

[0040] 8(c), the molding resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6), thereby dividing the semiconductor device 1 into individual pieces. The cut surfaces of the first etching frame and the second etching frame cut by dicing may be exposed on the side surface of the package.

[0041] With the configuration according to this embodiment, a half-etched etching frame can be applied to the source terminal 10, gate terminal 11, and drain terminal 12 of the semiconductor device 1. This allows the exposed surfaces of the source terminal 10 and gate terminal 11 to have a different shape from the chip bonding surface. The layout of the chip bonding surface is not limited by the layout of the exposed surface. This improves the degree of freedom in the layout of the semiconductor chip 20. Furthermore, the mountable chip size can be increased. This improves the mounting capacity of the semiconductor chip 20.

[0042] Furthermore, the exposed surfaces of the source terminal 10 and the gate terminal 11 can be the same as those of existing products, thereby improving the compatibility and versatility of the semiconductor device 1.

[0043] Furthermore, with the configuration according to this embodiment, the drain terminal 12 can be exposed on both the package front surface SF1 and the package back surface SF2, thereby improving the heat dissipation performance of the semiconductor device 1.

[0044] Furthermore, the drain terminal 12 can be electrically connected to the printed circuit board from either the package front surface SF1 or the package back surface SF2. That is, the semiconductor device 1 has two mounting surfaces. Therefore, the semiconductor device 1 can be applied not only to surface mounting but also to vertical mounting, such as embedding in a printed circuit board. That is, the degree of freedom in mounting the semiconductor device 1 can be improved.

[0045] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, a configuration of the semiconductor device 1 that is different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0046] 2.1 Configuration of Semiconductor Device 2.1.1 Planar Configuration of Semiconductor Device First, an example of the planar configuration of the semiconductor device 1 will be described. Fig. 9 is a plan view of the package front surface SF1 of the semiconductor device 1. Fig. 10 is a plan view of the package back surface SF2 of the semiconductor device 1.

[0047] As shown in Figures 9 and 10 , in this embodiment, exposed surfaces of the drain terminal 12 are provided at both ends in the X direction on the package back surface SF2. In the example of Figure 9 , the exposed surface of the drain terminal 12 on the package front surface SF1 has a rectangular shape. For example, both ends of the drain terminal 12 facing in the X direction extend to both ends of the molded resin 13 facing in the X direction. In addition, in the example of Figure 10 , four protrusions are provided on each of the two exposed surfaces of the drain terminal 12 provided at both ends in the X direction. For example, the four protrusions extend to the ends of the molded resin 13 facing in the X direction.

[0048] The exposed surface of the source terminal 10 is provided in the center of the rear surface SF2 of the package and is not in contact with any end of the molded resin 13. Note that the end of the exposed surface of the source terminal 10 facing the Y direction may extend to the end of the molded resin 13 facing the Y direction.

[0049] The exposed surface of the gate terminal 11 is the same as that described with reference to FIG. 2 in the first embodiment.

[0050] 2.1.2 Cross-sectional Configuration of Semiconductor Device Next, an example of the cross-sectional configuration of the semiconductor device 1 will be described. Fig. 11 is a cross-sectional view taken along line A3-A4 in Fig. 9 and Fig. 10. Fig. 12 is a cross-sectional view taken along line B3-B4 in Fig. 9 and Fig. 10.

[0051] 11 and 12 , the source terminal 10 has a half-etched region HE that is half-etched in the Z direction from the exposed surface, as in the first embodiment. In the example of Fig. 11 , the half-etched region HE is formed at one end of the source terminal 10 facing the X direction, but the half-etched region HE may be formed at both ends facing the X direction.

[0052] The gate terminal 11 is the same as that described with reference to FIG. 4 in the first embodiment.

[0053] The drain terminal 12 includes a first portion 12a, a second portion 12b, and a third portion 12c. The first portion 12a is a plate-shaped portion extending on the XY plane. The surface of the first portion 12a facing the front surface of the package is exposed from the package surface SF1. The surface of the first portion 12a facing the back surface of the package is a chip bonding surface to which the drain electrode 21d is bonded via a mounting material 31d. One end of the second portion 12b is connected to one end of the first portion 12a in the X direction. The second portion 12b extends in the Z direction. The other end of the second portion 12b is exposed on the package back surface SF2. One end of the third portion 12c is connected to the other end of the first portion 12a in the X direction. The third portion 12c extends in the Z direction. The other end of the third portion 12c is exposed on the package back surface SF2. The third portion 12c faces the second portion 12b in the X direction, with the semiconductor chip 20 sandwiched therebetween.

[0054] The second portion 12b and the third portion 12c of the drain terminal 12 have half-etched regions HE at both ends facing the X direction, which are half-etched in the Z direction from the exposed surface of the package back surface SF2. In the X direction, the two ends of the drain terminal that are not half-etched are exposed from the side surfaces of the package.

[0055] 2.1.3 Planar Configuration of Each Terminal Next, an example of the planar configuration of each terminal will be described. FIG. 13 is a plan view taken along line C3-C4 in FIGS. 11 and 12. FIG. 14 is a plan view taken along line D3-D4 in FIGS. 11 and 12. FIG. 13 shows the shape of the chip bonding surfaces of the source terminal 10 and gate terminal 11, and the portion of the drain terminal 12 that does not include the half-etched region HE. FIG. 14 shows the shape of the exposed surfaces of the source terminal 10, gate terminal 11, and drain terminal 12 on the package back surface SF2. FIGS. 13 and 14 show plan views seen from the package front surface side. The following description focuses on the source terminal 10 and gate terminal 11.

[0056] 13 and 14, the shapes of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 are different from the shape of the exposed surface of the package back surface SF2. The shapes of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 do not correspond to the shapes of the exposed surface. The semiconductor chip 20 is disposed between two drain terminals 12 provided at both ends in the X direction.

[0057] 2.2 Manufacturing Method of Semiconductor Device Next, an example of a manufacturing method of the semiconductor device 1 will be described. FIG. 15 is a diagram showing the flow of the assembly process. Note that, for the sake of simplicity, the example of FIG. 15 shows a cross section of the semiconductor device 1 taken along line A3-A4 in FIGS. 9 and 10, and the gate terminal 11 is omitted. Furthermore, in the example of FIG. 15, the source electrode 21s, gate electrode 21g, drain electrode 21d, passivation film 22, and conductive layers 23s and 23g are omitted.

[0058] As shown in FIG. 15A, similar to the description of the first embodiment using FIG. 8 , a first etching frame is first prepared, on which a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 are provided. A semiconductor chip 20 is mounted on the source terminals 10 and gate terminals 11, respectively, with mounting materials 31s and 31g interposed therebetween, so that the source terminals 10 are connected to the source electrodes 21s and the gate terminals 11 are connected to the gate electrodes 21g (S1). Next, a second etching frame on which a drain terminal 12 is provided is mounted on the drain electrode 21d of the semiconductor chip 20, with the mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. Alternatively, the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame on which the source terminals 10 and gate terminals 11 are provided may be mounted in this order on the second etching frame on which the drain terminals 12 are provided.

[0059] 15B, the plurality of semiconductor devices 1 sharing the first etching frame and the second etching frame are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed.

[0060] 15(c), the mold resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6), thereby dividing the semiconductor device 1 into individual pieces. The cut surfaces of the first etching frame and the second etching frame cut by dicing may be exposed on the side surface of the package.

[0061] The configuration according to this embodiment can provide the same effects as those of the first embodiment.

[0062] In the second embodiment, the case where the exposed surfaces of the drain terminals 12 are provided at both ends in the X direction on the package back surface SF2 has been described, but this is not limiting. For example, the exposed surfaces of the drain terminals 12 may be provided at four ends or four corners of the package back surface SF2.

[0063] 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a configuration of the semiconductor device 1 that is different from those of the first and second embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0064] 3.1 Configuration of Semiconductor Device 3.1.1 Planar Configuration of Semiconductor Device First, an example of the planar configuration of the semiconductor device 1 will be described.

[0065] 16, the semiconductor device 1 of this embodiment further includes a heat sink 40 in addition to the configuration described in the first embodiment. The heat sink 40 is made of a conductive material with excellent thermal conductivity. For example, copper is used for the heat sink 40. For example, the heat sink 40 is provided over the entire surface of the package front surface SF1. Note that the configuration of the exposed surfaces of the source terminal 10, gate terminal 11, and drain terminal 12 on the package back surface SF2 is the same as that described with reference to FIG. 2 in the first embodiment.

[0066] 3.1.2 Cross-sectional Configuration of Semiconductor Device Next, an example of the cross-sectional configuration of the semiconductor device 1 will be described. Fig. 17 is a cross-sectional view taken along line A5-A6 in Fig. 16. Fig. 18 is a cross-sectional view taken along line B5-B6 in Fig. 16.

[0067] As shown in FIGS. 17 and 18, the cross-sectional configurations of the source terminal 10, the gate terminal 11, and the drain terminal 12 are the same as those described with reference to FIGS. 3 and 4 in the first embodiment.

[0068] A heat sink 40 is provided on the package surface SF1 (upper side of the paper in FIGS. 17 and 18 ). A molded resin 13 is provided between the heat sink 40 and the surface of the drain terminal 12 facing the package surface SF1. The heat sink 40 is not in contact with the drain terminal 12 because the molded resin 13 is interposed therebetween. In other words, the heat sink 40 is insulated from the source terminal 10, the gate terminal 11, and the drain terminal 12.

[0069] 3.2 Manufacturing Method of Semiconductor Device Next, an example of a manufacturing method of the semiconductor device 1 will be described. Figure 19 is a diagram showing the flow of the assembly process. Note that, for the sake of simplicity, the example of Figure 19 shows a cross section of the semiconductor device 1 taken along line A5-A6 in Figure 16, with the gate terminal 11 omitted. Furthermore, in the example of Figure 19, the source electrode 21s, gate electrode 21g, drain electrode 21d, passivation film 22, and conductive layers 23s and 23g are omitted.

[0070] As shown in FIG. 19A, similar to the description of the first embodiment using FIG. 8, a first etching frame is first prepared, on which a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 are provided. A semiconductor chip 20 is mounted on the source terminals 10 and gate terminals 11, respectively, with mounting materials 31s and 31g interposed therebetween, so that the source terminals 10 are connected to the source electrodes 21s and the gate terminals 11 are connected to the gate electrodes 21g (S1). Next, a second etching frame on which a drain terminal 12 is provided is mounted on the drain electrodes 21d of the semiconductor chip 20, with the mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. Alternatively, the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame on which the source terminals 10 and gate terminals 11 are provided may be mounted in this order on the second etching frame on which the drain terminals 12 are provided.

[0071] 19(b), after the heat sink 40 is mounted (S11), the plurality of semiconductor devices 1 sharing the first etching frame and the second etching frame are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed.

[0072] 19(c), the heat sink 40, the molded resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6), thereby dividing the semiconductor device 1 into individual pieces. The cut surfaces of the first etching frame, the second etching frame, and the heat sink 40 cut by dicing may be exposed on the side surface of the package.

[0073] The configuration according to this embodiment can improve the mounting capacity of the semiconductor chip 20, similar to the first embodiment.

[0074] Furthermore, with the configuration according to this embodiment, if the drain terminal 12 is not electrically connected on the package surface SF1, a heat sink 40 can be provided on the package surface SF1, thereby improving the heat dissipation performance of the semiconductor device 1.

[0075] The structure of the third embodiment can also be applied to the second embodiment.

[0076] 4. Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a configuration of the semiconductor device 1 that is different from the first to third embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0077] 4.1 Configuration of Semiconductor Device 4.1.1 Planar Configuration of Semiconductor Device First, an example of the planar configuration of the semiconductor device 1 will be described.

[0078] 20 , the semiconductor device 1 of this embodiment further includes an insulating resin 50 in addition to the configuration described in the first embodiment. The insulating resin 50 is made of an insulating material having a higher thermal conductivity than the mold resin 13. The withstand voltage of the insulating resin 50 is preferably equal to or higher than that of the mold resin 13, but may be lower than that of the mold resin 13. The configuration of the exposed surfaces of the source terminal 10, gate terminal 11, and drain terminal 12 on the package back surface SF2 is the same as that described with reference to FIG. 2 of the first embodiment.

[0079] 4.1.2 Cross-sectional Configuration of Semiconductor Device Next, an example of the cross-sectional configuration of the semiconductor device 1 will be described. Fig. 21 is a cross-sectional view taken along line A7-A8 in Fig. 20. Fig. 22 is a cross-sectional view taken along line B7-B8 in Fig. 20.

[0080] As shown in FIGS. 21 and 22, the cross-sectional configurations of the source terminal 10, the gate terminal 11, and the drain terminal 12 are the same as those described with reference to FIGS. 3 and 4 in the first embodiment.

[0081] For example, insulating resin 50 is provided on the entire surface of package surface SF1 (upper side of the paper in FIGS. 21 and 22 ). Insulating resin 50 is in contact with the surface of drain terminal 12 facing package surface SF1. Note that mold resin 13 may be provided between insulating resin 50 and the surface of drain terminal 12 facing package surface SF1.

[0082] 4.2 Manufacturing Method of Semiconductor Device Next, an example of a manufacturing method of the semiconductor device 1 will be described. Figure 23 is a diagram showing the flow of the assembly process. Note that, for the sake of simplicity, the example of Figure 23 shows a cross section of the semiconductor device 1 taken along line A7-A8 in Figure 20, with the gate terminal 11 omitted. Furthermore, in the example of Figure 23, the source electrode 21s, gate electrode 21g, drain electrode 21d, passivation film 22, and conductive layers 23s and 23g are omitted.

[0083] As shown in FIG. 23A, similar to the description of the first embodiment using FIG. 8 , a first etching frame is first prepared, on which a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 are provided. A semiconductor chip 20 is mounted on the source terminals 10 and gate terminals 11, respectively, with mounting materials 31s and 31g interposed therebetween, so that the source terminals 10 are connected to the source electrodes 21s and the gate terminals 11 are connected to the gate electrodes 21g (S1). Next, a second etching frame on which a drain terminal 12 is provided is mounted on the drain electrode 21d of the semiconductor chip 20, with the mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. Alternatively, the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame on which the source terminals 10 and gate terminals 11 are provided may be mounted in this order on the second etching frame on which the drain terminals 12 are provided.

[0084] 23B, after the insulating resin 50 is formed (S21), the plurality of semiconductor devices 1 sharing the etching frame are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed.

[0085] 23(c), the insulating resin 50, the molded resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6), thereby dividing the semiconductor device 1 into individual pieces. The cut surfaces of the first etching frame, the second etching frame, and the insulating resin 50 cut by dicing may be exposed on the side surface of the package.

[0086] The configuration according to this embodiment can improve the mounting capacity of the semiconductor chip 20, similar to the first embodiment.

[0087] Furthermore, with the configuration according to this embodiment, when the drain terminal 12 is not electrically connected on the package surface SF1, the insulating resin 50 having a higher thermal conductivity than the mold resin 13 can be provided on the package surface SF1. This improves the heat dissipation performance of the semiconductor device 1.

[0088] The structure of the fourth embodiment can also be applied to the second embodiment.

[0089] 5. Fifth Embodiment Next, a fifth embodiment will be described. In the fifth embodiment, a power conversion device 100 including a plurality of the semiconductor devices 1 described in the first embodiment will be described. In the following description, a DC-DC converter will be used as an example of the power conversion device 100. The following description will focus on differences from the first embodiment. Note that any of the semiconductor devices 1 described in the second to fourth embodiments may be applied to the power conversion device 100.

[0090] 5.1 Circuit Configuration of the Power Conversion Device First, an example of the circuit configuration of the power conversion device 100 will be described. FIG. 24 is a circuit diagram of the power conversion device 100.

[0091] The power conversion device 100 includes semiconductor devices 1a and 1b, an inductor L1, capacitors C1 and C2, and a gate driver GD. Each of the semiconductor devices 1a and 1b corresponds to the semiconductor device 1 of the first embodiment and includes a MOSFET. The power conversion device 100 also has an input terminal TIN and an output terminal TOUT.

[0092] The input terminal TIN is connected to the drain of the semiconductor device 1a. The input terminal TIN is also connected to a ground voltage node (grounded to ground GND) via a capacitor C1. For example, the ground voltage VSS is supplied to the ground voltage node.

[0093] The source of the semiconductor device 1a is connected to the drain of the semiconductor device 1b and a first end of the inductor L1.

[0094] The gates of the semiconductor devices 1a and 1b are connected to a gate driver GD.

[0095] The source of the semiconductor device 1b is connected to the ground voltage node.

[0096] A second end of the inductor L1 is connected to the output terminal TOUT and to the ground voltage node via the capacitor C2.

[0097] 5.2 Planar Configuration of the Power Conversion Device Next, an example of the planar configuration of the power conversion device 100 will be described. FIG. 25 is a plan view of the power conversion device 100. The example of FIG. 25 is a plan view seen from the top side of the printed circuit board 101. In the following description, the surface on which the inductor L1 and the like are surface-mounted and on which the input terminal TIN and the output terminal TOUT and the like are provided will be referred to as the "upper surface of the printed circuit board." Furthermore, the surface opposite to the mounting surface of the printed circuit board 101 will be referred to as the "lower surface of the printed circuit board." Note that in the example of FIG. 25, capacitors C1 and C2 are omitted to simplify the description.

[0098] As shown in Figure 25, the power conversion device 100 includes semiconductor devices 1a and 1b, a printed circuit board 101, a gate driver GD, an inductor L1, and capacitors C1 and C2. The semiconductor devices 1a and 1b are arranged so that their package back surfaces SF2 face the upper surface of the printed circuit board. In other words, the package front surfaces SF1 of the semiconductor devices 1a and 1b face the lower surface of the printed circuit board. Hereinafter, this arrangement will be referred to as "drain down."

[0099] The drain terminals 12 of the semiconductor device 1a and the semiconductor device 1b are connected to the wiring layer of the printed circuit board 101 on the respective package surfaces SF1.

[0100] 5.3 Cross-sectional Configuration of the Power Converter Next, an example of the cross-sectional configuration of the power converter 100 will be described. Figure 26 is a cross-sectional view of the power converter 100 taken along line X1-X2 in Figure 25. In the example of Figure 26, not only the cross section is shown, but also some of the contact plugs and wiring layers that can be seen through the cross section are indicated by dashed lines. Note that in the example of Figure 26, capacitors C1 and C2 are omitted to simplify the explanation.

[0101] 26 , the power conversion device 100 has a structure in which the semiconductor devices 1a and 1b are embedded in a printed circuit board 101 so as to be drain-down. For example, the gate driver GD and the inductor L1 are surface-mounted on the upper surface of the printed circuit board 101.

[0102] The printed circuit board 101 is a multilayer wiring board having multiple wiring layers, multiple insulating plates (or insulating layers), and a core material. More specifically, the printed circuit board 101 includes a core material (or insulating material) 102, insulating plates (or insulating layers) 103 and 104, contact plugs 110a, 110b, 110c, 110d, and 110e, wiring layers 111a, 111b, 112a, 112b, 112c, 112d, 112f, 113a, 113b, and 113c, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND (i.e., a ground voltage node).

[0103] Each of the insulating plates 103 and 104 has, for example, a sheet shape and is made of an insulating material in which a thermosetting resin is impregnated into carbon fiber. The contact plugs 110a, 110b, 110c, 110d, and 110e and the wiring layers 111a, 111b, 112a, 112b, 112c, 112d, 112f, 113a, 113b, and 113c are made of a conductive material, for example, copper.

[0104] The semiconductor devices 1a and 1b are embedded in a printed circuit board 101. More specifically, the semiconductor devices 1a and 1b are provided between insulating plates 103 and 104 in the Z direction. The semiconductor devices 1a and 1b are also provided between core materials 102 in the X and Y directions. The semiconductor devices 1a and 1b are arranged so that their respective package surfaces SF1 face the insulating plate 103. The exposed surfaces of the source terminals 10 and gate terminals 11 of the semiconductor devices 1a and 1b face the insulating plate 104 (the upper surface of the printed circuit board).

[0105] In other words, the drain-down semiconductor devices 1a and 1b are provided at a distance from each other on an insulating plate 103. An insulating plate 104 is provided on top of the semiconductor devices 1a and 1b (on the back surface side of the package). The sides of the semiconductor devices 1a and 1b contact the core material 102. In other words, the semiconductor devices 1a and 1b are provided in the same layer as the core material 102.

[0106] An input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND are provided on the insulating plate 104 .

[0107] Contact plugs 110a and 110b are provided in the insulating plate 104 and the core material 102. Each of the contact plugs 110a and 110b extends in the Z direction within the insulating plate 104 and the core material 102.

[0108] Contact plugs 110c, 110d, and 110e are provided in the insulating plate 104. The contact plugs 110c, 110d, and 110e extend within the insulating plate 104 in the Z direction.

[0109] A wiring layer 111a is provided between the drain terminal 12 of the semiconductor device 1a and the insulating plate 103. The wiring layer 111a extends on the XY plane. A wiring layer 112a is provided between the gate terminal 11 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112a extends on the XY plane. Wiring layers 112b and 112c are provided between the source terminal 10 of the semiconductor device 1a and the insulating plate 104. The wiring layers 112b and 112c extend on the XY plane.

[0110] A wiring layer 111b is provided between the drain terminal 12 of the semiconductor device 1b and the insulating plate 103. The wiring layer 111b extends on the XY plane. A wiring layer 112d is provided between the gate terminal 11 of the semiconductor device 1b and the insulating plate 104. Wiring layers 112e and 112f are provided between the source terminal 10 of the semiconductor device 1b and the insulating plate 104. The wiring layers 112e and 112f extend on the XY plane.

[0111] Wiring layers 113a, 113b, and 113c are provided on the insulating plate 104. The wiring layers 113a, 113b, and 113c extend on the XY plane.

[0112] The input terminal TIN is connected to a contact plug 110a. The contact plug 110a is connected to a wiring layer 111a. The wiring layer 111a is connected to the drain terminal 12 of the semiconductor device 1a on the package surface SF1 of the semiconductor device 1a (the lower side of the paper in FIG. 26).

[0113] The gate terminal 11 of the semiconductor device 1a is connected to a contact plug 110c via a wiring layer 112a, which is connected to a gate driver terminal TG.

[0114] The source terminal 10 of the semiconductor device 1a is connected to the contact plug 110b via wiring layers 112b and 112c.

[0115] Furthermore, the contact plug 110b is connected to the wiring layer 111b and the wiring layer 113b. The wiring layer 111b is connected to the drain terminal 12 of the semiconductor device 1b on the package surface SF1 (the lower side of the paper in FIG. 26 ) of the semiconductor device 1b. The wiring layer 113b is connected to a first end of the inductor L1. A second end of the inductor L1 is connected to the output terminal TOUT via the wiring layer 113c. The inductor L1 is, for example, surface-mounted on the printed circuit board 101.

[0116] The gate terminal 11 of the semiconductor device 1b is connected to a contact plug 110d via a wiring layer 112d. The contact plug 110d is connected to a gate driver terminal TG via a wiring layer 113a. The gate driver terminal TG is connected to a gate driver GD.

[0117] The source terminal 10 of the semiconductor device 1b is connected to a contact plug 110e via wiring layers 112e and 112f, which is connected to a ground terminal TGND.

[0118] According to the configuration of this embodiment, the semiconductor devices 1a and 1b can be easily embedded in the printed circuit board 101, and the power conversion device 100, for example, a DC-DC converter, can be formed in a small area. Other effects are the same as those of the first embodiment.

[0119] 6. Sixth Embodiment Next, a sixth embodiment will be described. In the sixth embodiment, a configuration of the power conversion device 100 that is different from that of the fifth embodiment will be described. The following description will focus on the differences from the fifth embodiment.

[0120] 6.1 Planar Configuration of the Power Conversion Device First, an example of the planar configuration of the power conversion device 100 will be described. Fig. 27 is a plan view of the power conversion device 100. The example in Fig. 27 is a plan view seen from the top surface side of the printed circuit board 101. Note that in the example in Fig. 27, capacitors C1 and C2 are omitted to simplify the description.

[0121] As shown in Figure 27, the power conversion device 100 includes semiconductor devices 1a and 1b, a printed circuit board 101, a gate driver GD, an inductor L1, and capacitors C1 and C2. The semiconductor device 1a is arranged drain-down. The semiconductor device 1b is arranged so that its package surface SF1 faces the upper surface of the printed circuit board. In other words, the package back surface SF2 of the semiconductor device 1b faces the lower surface of the printed circuit board. That is, the exposed surfaces of the source terminal 10 and the gate terminal 11 face the lower surface of the printed circuit board. Hereinafter, this arrangement will be referred to as "source-down."

[0122] The drain terminals 12 of the semiconductor device 1a and the semiconductor device 1b are connected to the wiring layer of the printed circuit board 101 on the respective package surfaces SF1.

[0123] 6.2 Cross-sectional Configuration of the Power Converter Next, an example of the cross-sectional configuration of the power converter 100 will be described. Figure 28 is a cross-sectional view of the power converter 100 taken along line X3-X4 in Figure 27. In the example of Figure 28, not only the cross section is shown, but also parts of contact plugs and wiring layers that can be seen through the cross section are indicated by dashed lines. Note that in the example of Figure 28, capacitors C1 and C2 are omitted to simplify the explanation.

[0124] As shown in FIG. 28, the printed circuit board 101 includes a core material 102, insulating plates 103 and 104, contact plugs 110a, 110b, 110c, 110d, and 110e, wiring layers 111a, 111b, 111c, 111d, 112a, 112b, 112c, 112d, 112e, 113a, 113b, and 113c, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND.

[0125] The semiconductor devices 1a and 1b are embedded in a printed circuit board 101. In this embodiment, the semiconductor device 1a is disposed so that the package front surface SF1 faces the insulating plate 103. The semiconductor device 1b is disposed so that the package back surface SF2 faces the insulating plate 103. That is, the exposed surfaces of the source terminal 10 and gate terminal 11 of the semiconductor device 1a face the insulating plate 104 (the upper surface of the printed circuit board). The exposed surfaces of the source terminal 10 and gate terminal 11 of the semiconductor device 1b face the insulating plate 103 (the lower surface of the printed circuit board).

[0126] In other words, the drain-down semiconductor device 1a and the source-down semiconductor device 1b are provided separately on an insulating plate 103. An insulating plate 104 is provided on the semiconductor devices 1a and 1b. The sides of the semiconductor devices 1a and 1b are in contact with the core material 102. That is, the semiconductor devices 1a and 1b are provided in the same layer as the core material 102.

[0127] An input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND are provided on the insulating plate 104 .

[0128] Contact plugs 110a, 110d, and 110e are provided in the insulating plate 104 and the core material 102. Each of the contact plugs 110a, 110d, and 110e extends in the insulating plate 104 and the core material 102 in the Z direction.

[0129] Contact plugs 110b and 110c are provided in the insulating plate 104. The contact plugs 110b and 110c extend within the insulating plate 104 in the Z direction.

[0130] A wiring layer 111a is provided between the drain terminal 12 of the semiconductor device 1a and the insulating plate 103. The wiring layer 111a extends on the XY plane. A wiring layer 112a is provided between the gate terminal 11 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112a extends on the XY plane. Wiring layers 112b and 112c are provided between the source terminal 10 of the semiconductor device 1a and the insulating plate 104. The wiring layers 112b and 112c extend on the XY plane.

[0131] Wiring layers 111b and 111c are provided between the gate terminal 11 of the semiconductor device 1b and the insulating plate 103. The wiring layers 111b and 111c extend on the XY plane. A wiring layer 111d is provided between the source terminal 10 of the semiconductor device 1b and the insulating plate 103. Wiring layers 112d and 112e are provided between the drain terminal 12 of the semiconductor device 1b and the insulating plate 104. The wiring layers 112d and 112e extend on the XY plane.

[0132] Wiring layers 113a, 113b, and 113c are provided on the insulating plate 104. The wiring layers 113a, 113b, and 113c extend on the XY plane.

[0133] The input terminal TIN is connected to a contact plug 110a. The contact plug 110a is connected to a wiring layer 111a. The wiring layer 111a is connected to the drain terminal 12 of the semiconductor device 1a on the package surface SF1 of the semiconductor device 1a (the lower side of the paper surface in FIG. 28).

[0134] The gate terminal 11 of the semiconductor device 1a is connected to a contact plug 110c via a wiring layer 112a, which is connected to a gate driver terminal TG.

[0135] The gate driver terminal TG is connected to a contact plug 110d via a wiring layer 113a, and the contact plug 110d is connected to the gate terminal 11 of the semiconductor device 1b via wiring layers 111c and 111b.

[0136] The source terminal 10 of the semiconductor device 1a is connected to the contact plug 110b via wiring layers 112b and 112c.

[0137] Furthermore, contact plug 110b is connected to wiring layer 112e and wiring layer 113b. Wiring layer 112e is connected to wiring layer 112d. Wiring layer 112d is connected to drain terminal 12 of semiconductor device 1b on package surface SF1 (upper side of the paper in FIG. 28) of semiconductor device 1b. Wiring layer 113b is connected to a first end of inductor L1. A second end of inductor L1 is connected to output terminal TOUT via wiring layer 113c.

[0138] The source terminal 10 of the semiconductor device 1b is connected to a contact plug 110e via a wiring layer 111d, which is connected to a ground terminal TGND.

[0139] The configuration according to this embodiment can provide the same effects as those of the fifth embodiment, and other effects are the same as those of the first embodiment.

[0140] 7. Seventh Embodiment Next, a seventh embodiment will be described. In the seventh embodiment, a configuration of the power conversion device 100 that is different from the fifth and sixth embodiments will be described. The following description will focus on the differences from the fifth and sixth embodiments.

[0141] 7.1 Planar Configuration of the Power Conversion Device First, an example of the planar configuration of the power conversion device 100 will be described. Fig. 29 is a plan view of the power conversion device 100. The example in Fig. 29 is a plan view seen from the top surface side of the printed circuit board 101. Note that in the example in Fig. 29, capacitors C1 and C2 are omitted to simplify the description.

[0142] 29, the power conversion device 100 includes semiconductor devices 1a and 1b, a printed circuit board 101, a gate driver GD, an inductor L1, and capacitors C1 and C2. The semiconductor devices 1a and 1b are arranged drain-down, as in the fifth embodiment.

[0143] In this embodiment, the drain terminals 12 of the semiconductor device 1a and the semiconductor device 1b are connected to the wiring layer of the printed circuit board 101 on the rear surface SF2 of each package.

[0144] 7.2 Cross-sectional Configuration of the Power Converter Next, an example of the cross-sectional configuration of the power converter 100 will be described. Figure 30 is a cross-sectional view of the power converter 100 taken along line X5-X6 in Figure 29. In the example of Figure 30, not only the cross section is shown, but also some of the contact plugs and wiring layers that can be seen through the cross section are indicated by dashed lines. Note that in the example of Figure 30, capacitors C1 and C2 are omitted to simplify the explanation.

[0145] As shown in FIG. 30, the printed circuit board 101 includes a core material 102, insulating plates 103 and 104, contact plugs 110a, 110b, 110c, 110d, and 110e, wiring layers 112a, 112b, 112c, 112d, 112e, 112f, 112g, 113a, 113b, and 113c, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND.

[0146] The semiconductor devices 1a and 1b are embedded in a printed circuit board 101. In this embodiment, similar to the fifth embodiment, the semiconductor devices 1a and 1b are arranged so as to be drain-down.

[0147] In other words, the drain-down semiconductor devices 1a and 1b are provided at a distance from each other on an insulating plate 103. An insulating plate 104 is provided on the semiconductor devices 1a and 1b. The sides of the semiconductor devices 1a and 1b are in contact with the core material 102. That is, the semiconductor devices 1a and 1b are provided in the same layer as the core material 102.

[0148] An input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND are provided on the insulating plate 104 .

[0149] Contact plugs 110a, 110b, 110c, 110d, and 110e are provided in the insulating plate 104. The contact plugs 110a, 110b, 110c, 110d, and 110e extend within the insulating plate 104 in the Z direction.

[0150] A wiring layer 112a is provided between the drain terminal 12 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112a extends on the XY plane. A wiring layer 112b is provided between the gate terminal 11 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112b extends on the XY plane. A wiring layer 112c is provided between the source terminal 10 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112c extends on the XY plane.

[0151] A wiring layer 112d is provided between the drain terminal 12 of the semiconductor device 1b and the insulating plate 104. The wiring layer 112d extends on the XY plane. A wiring layer 112e is provided between the gate terminal 11 of the semiconductor device 1b and the insulating plate 104. The wiring layer 112e extends on the XY plane. Wiring layers 112f and 112g are provided between the source terminal 10 of the semiconductor device 1b and the insulating plate 104. The wiring layers 112f and 112g extend on the XY plane.

[0152] Wiring layers 113a, 113b, and 113c are provided on the insulating plate 104. The wiring layers 113a, 113b, and 113c extend on the XY plane.

[0153] The input terminal TIN is connected to a contact plug 110a. The contact plug 110a is connected to a wiring layer 112a. The wiring layer 112a is connected to the drain terminal 12 of the semiconductor device 1a on the rear surface SF2 of the package of the semiconductor device 1a (the upper side of the paper in FIG. 30).

[0154] The gate terminal 11 of the semiconductor device 1a is connected to a contact plug 110c via a wiring layer 112b, which is connected to a gate driver terminal TG.

[0155] The gate driver terminal TG is connected to a contact plug 110d via a wiring layer 113a, and the contact plug 110d is connected to the gate terminal 11 of the semiconductor device 1b via a wiring layer 112e.

[0156] The source terminal 10 of the semiconductor device 1a is connected to the contact plug 110b via the wiring layer 112c.

[0157] Furthermore, the contact plug 110b is connected to the wiring layer 112d and the wiring layer 113b. The wiring layer 112d is connected to the drain terminal 12 of the semiconductor device 1b on the back surface SF2 of the package of the semiconductor device 1b (the upper side of the paper in FIG. 30). The wiring layer 113b is connected to a first end of the inductor L1. A second end of the inductor L1 is connected to the output terminal TOUT via the wiring layer 113c.

[0158] The source terminal 10 of the semiconductor device 1b is connected to a contact plug 110e via wiring layers 112f and 112g, which is connected to a ground terminal TGND.

[0159] The configuration according to this embodiment can provide the same effects as those of the fifth embodiment, and other effects are the same as those of the first embodiment.

[0160] 8. Modifications, etc. In the fifth to seventh embodiments, the semiconductor devices 1a and 1b are embedded in the printed circuit board 101, but the configuration of the power conversion device 100 is not limited thereto. For example, at least one of the semiconductor devices 1a and 1b may be surface-mounted on the printed circuit board 101.

[0161] The semiconductor devices 1a and 1b may be embedded in the printed circuit board 101 so as to be source-down.

[0162] The semiconductor device 1 of the second embodiment may be applied to the fifth to seventh embodiments.

[0163] The semiconductor device 1 of the third or fourth embodiment may be applied to the seventh embodiment.

[0164] In the above embodiment, "connection" also includes a state of being indirectly connected via another conductive material.

[0165] In the above embodiment, "substantially the same" may include manufacturing variations.

[0166] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

Claims

1. A semiconductor device comprising: a semiconductor chip having a source electrode and a gate electrode on a first surface thereof and a drain electrode on a second surface thereof opposite the first surface; a source terminal having a fourth surface exposed from a third surface of a package and a fifth surface connected to the source electrode and having a shape different from that of the fourth surface; a gate terminal having a sixth surface exposed from the third surface of the package and a seventh surface connected to the gate electrode and having a shape different from that of the sixth surface; and a drain terminal connected to the drain electrode and having an eighth surface exposed from the third surface of the package.

2. The semiconductor device according to claim 1, wherein when the semiconductor device is surface-mounted on a printed circuit board, the fourth surface, the sixth surface, and the eighth surface are covered with tin or solder, and when the semiconductor device is vertically mounted on a printed circuit board, the fourth surface, the sixth surface, and the eighth surface are not covered with tin or solder.

3. The semiconductor device according to claim 1, wherein the source terminal, the gate terminal, and the drain terminal are formed of an etching frame.

4. The semiconductor device according to claim 1, wherein each of the source terminal, the gate terminal, and the drain terminal has a first region half-etched in a first direction from the third surface side of the package, and the gate terminal further has a second region half-etched from the seventh surface side.

5. The semiconductor device according to claim 4, wherein the length in the first direction of the first region of the drain terminal is longer than the lengths in the first direction of the first regions of the source terminal and the gate terminal.

6. The semiconductor device according to claim 4, wherein the length of said first region of said source terminal in said first direction is the same as the length of said first region of said gate terminal in said first direction.

7. The semiconductor device according to claim 1, wherein the length of said drain terminal in the first direction is longer than the lengths of said source terminal and said gate terminal in the first direction.

8. The semiconductor device according to claim 1, wherein the drain terminal includes a first portion connected to the drain electrode via a mounting material, and a second portion having one end connected to the first portion, extending in a first direction, and the other end having the eighth surface exposed from the third surface of the package.

9. The semiconductor device according to claim 7, wherein the length of the drain terminal in the first direction is the same as the length of the package in the first direction.

10. The semiconductor device according to claim 8, wherein said first portion of said drain terminal has a tenth surface exposed from a ninth surface opposed to said third surface of said package.

11. The semiconductor device according to claim 8, wherein the drain terminal further includes a third portion having one end connected to the first portion, extending in the first direction, facing the second portion across the semiconductor chip, and having an eleventh surface whose other end is exposed from the third surface of the package.

12. The semiconductor device according to claim 1, further comprising a conductive heat sink exposed from a ninth surface of the package opposite to the third surface, and insulated from the source terminal, the gate terminal, and the drain terminal.

13. The semiconductor device according to claim 1, further comprising an insulating resin exposed from a ninth surface of said package opposite said third surface, in contact with said drain terminal, and having a thermal conductivity higher than that of the molding resin.

14. A method for manufacturing a semiconductor device in which a source terminal, a gate terminal, and a drain terminal are exposed from a first surface of a package, comprising the steps of: mounting a semiconductor chip on the source terminal and the gate terminal provided on a first etching frame via a mounting material so that a source electrode is connected to the source terminal and a gate electrode is connected to the gate terminal; mounting the drain terminal provided on a second etching frame having a thickness different from that of the first etching frame via the mounting material on a drain electrode provided on a surface of the semiconductor chip opposite to the surface on which the source electrode and the gate electrode are provided; sealing the first etching frame, the semiconductor chip, and the second etching frame with molding resin; and cutting the first etching frame, the second etching frame, and the molding resin.

15. The method for manufacturing a semiconductor device according to claim 14, wherein each of the source terminal, the gate terminal, and the drain terminal has a first region that is half-etched in a first direction from the first surface side of the package.

16. The method for manufacturing a semiconductor device according to claim 14, wherein the drain terminal is further exposed from a second surface of the package opposite to the first surface.

17. The method for manufacturing a semiconductor device according to claim 14, wherein the length of the drain terminal in the first direction is the same as the length of the package in the first direction.

18. The method for manufacturing a semiconductor device according to claim 14, further comprising a step of mounting a conductive heat sink exposed from a second surface of the package opposite to the first surface, and insulated from the source terminal, the gate terminal, and the drain terminal.

19. The method for manufacturing a semiconductor device according to claim 14, further comprising the step of forming an insulating resin that is exposed from a second surface of the package opposite to the first surface, that contacts the drain terminal, and that has a higher thermal conductivity than the molding resin.

20. A power conversion device comprising: a first insulating plate; a second insulating plate facing the first insulating plate; a semiconductor device according to any one of claims 1 to 13 provided between the first insulating plate and the second insulating plate; and a core material provided in the same layer as the semiconductor device.

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