Semiconductor device, semiconductor module, and electronic apparatus

Abstract

This semiconductor device comprises a field effect transistor having: a semiconductor; a transition metal element-containing junction body disposed on the semiconductor; and a gate electrode disposed on the semiconductor with the junction body interposed therebetween.

Description

Semiconductor device, semiconductor module and electronic device

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and an electronic device.

[0002] Patent Document 1 discloses a semiconductor device. This semiconductor device includes a field-effect transistor. The field-effect transistor includes a nitride semiconductor layer, an insulating film partially formed on the upper surface of the nitride semiconductor layer, and a gate electrode formed in contact with the upper surface of the nitride semiconductor layer that is exposed and not covered by the insulating film. The insulating film is formed in contact with the side surface of the gate electrode. The insulating film contains a transition metal.

[0003] In a semiconductor device configured as described above, the transition metal mixed in the insulating film forms surface defects and levels at the interface between the nitride semiconductor device and the insulating film and in the insulating film near this interface. These surface defects and levels trap holes or electrons. This reduces the gate leakage current of the field-effect transistor.

[0004] International Publication No. WO2019 / 008658 A1

[0005] However, there has been a demand for a semiconductor device that can effectively suppress characteristic variations such as threshold voltage and drain lag in the on-state and can effectively suppress gate leakage current (off-leakage) in the off-state, as well as a semiconductor module and electronic equipment that include such a semiconductor device.

[0006] A semiconductor device according to a first embodiment of the present disclosure includes a field effect transistor having a semiconductor, a junction body including a transition metal element disposed on the semiconductor, and a gate electrode disposed on the semiconductor with the junction body interposed therebetween.

[0007] A semiconductor device according to a second embodiment of the present disclosure is the semiconductor device according to the first embodiment, further comprising: a main electrode disposed on the semiconductor at a position spaced from the gate electrode in the gate length direction; and a passivation film disposed on the semiconductor between the gate electrode and the main electrode. The passivation film contains a transition metal element. In the semiconductor device according to the second embodiment, the bonded body and the passivation film each contain the same transition metal element. Furthermore, in the semiconductor device according to the second embodiment, the content of the transition metal element contained in the bonded body is lower than the content of the transition metal element contained in the passivation film.

[0008] A semiconductor module according to a third embodiment of the present disclosure includes a semiconductor device, the semiconductor device including a field effect transistor having a semiconductor, a junction body including a transition metal element disposed on the semiconductor, and a gate electrode disposed on the semiconductor with the junction body interposed therebetween.

[0009] An electronic device according to a fourth embodiment of the present disclosure includes a semiconductor device, the semiconductor device including a field effect transistor having a semiconductor, a junction including a transition metal element disposed on the semiconductor, and a gate electrode disposed on the semiconductor with the junction interposed therebetween.

[0010] FIG. 1 is a longitudinal cross-sectional view (a cross-sectional view taken along the line A-A in FIG. 2 ) of a main part of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view of the main part of the semiconductor device shown in FIG. 1 . FIG. 3 is a cross-sectional view corresponding to FIG. 1 at a first step, illustrating each step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view at a second step. FIG. 5 is a cross-sectional view at a third step. FIG. 6 is a cross-sectional view at a fourth step. FIG. 7 is a cross-sectional view at a fifth step. FIG. 8 is a graph showing the relationship between the on / off ratio and the gate voltage for a field-effect transistor mounted on the semiconductor device according to the first embodiment and a field-effect transistor according to a comparative example. FIG. 9 is a graph showing the relationship between the on / off ratio and the thickness of the junction body in the field-effect transistor mounted on the semiconductor device according to the first embodiment. FIG. 10 is a diagram showing the atomic composition ratio of the transition metal element content contained in the junction body to the transition metal element content contained in the passivation film in the field-effect transistor mounted on the semiconductor device according to the first embodiment. Fig. 11 is a longitudinal cross-sectional configuration diagram of a main part of a semiconductor device according to a second embodiment of the present disclosure, corresponding to Fig. 1. Fig. 12 is a perspective view of a semiconductor module according to a third embodiment of the present disclosure. Fig. 13 is a block configuration diagram of an electronic device according to a fourth embodiment of the present disclosure.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First Embodiment The first embodiment is a first example in which the present technology is applied to a field effect transistor mounted on a semiconductor device. Here, the planar configuration, vertical cross-sectional configuration, and manufacturing method of the field effect transistor will be described. 2. Second Embodiment The second embodiment is a second example in which the structure of the gate electrode is changed in the field effect transistor of the semiconductor device according to the first embodiment. 3. Third Embodiment The third embodiment is a third example that describes a semiconductor module in which the semiconductor device according to the first embodiment or the second embodiment is mounted. 4. Fourth Embodiment The fourth embodiment is a fourth example that describes an electronic device in which the semiconductor device according to the first embodiment or the second embodiment is mounted. 5. Other Embodiments

[0012] 1 to 10 , a semiconductor device 1 and a manufacturing method thereof according to a first embodiment of the present disclosure will be described. Here, the arrow X direction shown as appropriate in the figures conveniently represents one planar direction of the semiconductor device 1 placed on a flat surface. The arrow Y direction represents another planar direction perpendicular to the arrow X direction. The arrow Z direction represents an upward direction perpendicular to the arrow X and arrow Y directions. In other words, the arrow X direction, arrow Y direction, and arrow Z direction exactly correspond to the X-axis direction, Y-axis direction, and Z-axis direction, respectively, of a three-dimensional coordinate system. Note that these directions are illustrated to facilitate understanding of the description and do not limit the directions of the present technology.

[0013] [Configuration of Semiconductor Device 1 and Field-Effect Transistor 2] Fig. 1 shows an example of a cross-sectional configuration of a semiconductor device 1 according to the first embodiment and a field-effect transistor 2 mounted thereon. The cross-sectional configuration is a cross-sectional configuration as seen in the direction of arrow Y (hereinafter simply referred to as "in a side view"). Fig. 2 shows an example of a planar configuration of the semiconductor device 1 and the field-effect transistor 2. The planar configuration is a planar configuration as seen in the direction of arrow Z (hereinafter simply referred to as "in a planar view").

[0014] (1) Schematic Overall Configuration of Semiconductor Device 1 and Field-Effect Transistor 2 As shown in FIGS. 1 and 2 , the semiconductor device 1 according to the first embodiment is configured based on a substrate 3. The semiconductor device 1 includes a field-effect transistor 2 on the substrate 3. While a detailed configuration will be described later, in the first embodiment, the field-effect transistor 2 is a Schottky barrier junction type high electron mobility transistor (HEMT). In side and plan views, the field-effect transistor 2 includes a semiconductor 4, a gate electrode 6, and a pair of main electrodes 7 used as a source electrode and a drain electrode. Each component of the field-effect transistor 2 will be described in detail below.

[0015] (2) Structure of the Substrate 3 In the first embodiment, the substrate 3 is made of a semiconductor material. Specifically, for example, semi-insulating single-crystal GaN, which is a III-V group compound semiconductor material, is used as the substrate 3. The lattice constant between the substrate 3 and the channel layer 42 can be controlled by using a buffer layer 41 that constitutes the semiconductor 4, which will be described later. In this case, the substrate 3 can be made of a material having a different lattice constant from that of the channel layer 42, such as SiC, sapphire, or Si. The substrate 3 can also be made of SCAM (ScAlMgO ４ ), Ga ２ O ３ , AlN, diamond, or the like.

[0016] 1, the semiconductor 4 is disposed on the substrate 3. In a side view, the semiconductor 4 is formed by sequentially stacking a buffer layer 41, a channel layer 42, a spacer layer 44, a barrier layer 45, and a cap layer 46 from the surface of the substrate 3 toward the direction of the arrow Z.

[0017] (3-1) Configuration of Buffer Layer 41 The buffer layer 41 is formed of, for example, a compound semiconductor layer. The compound semiconductor layer is formed on the substrate 3 using an epitaxial growth method. When the lattice constants of the substrate 3 and the channel layer 42 are different, the lattice constant can be controlled by the buffer layer 41. This improves the crystal quality of the channel layer 42. Furthermore, in the manufacturing process, warpage of the substrate 3 after the channel layer 42 is formed can be controlled. The warpage of the substrate 3 here corresponds to the warpage of a semiconductor wafer before the dicing step in the manufacturing process.

[0018] In the first embodiment, when the substrate 3 is made of single-crystal Si and the channel layer 42 is made of GaN, the buffer layer 41 may be made of one or more compound semiconductor materials selected from AlN, AlGaN, and GaN. Alternatively, the buffer layer 41 may be formed as a single layer or may be formed by stacking multiple of the above-mentioned compound semiconductor materials. When the buffer layer 41 is made of a ternary compound semiconductor material, the composition ratio may be gradually changed in the deposition direction. Furthermore, the buffer layer 41 may be doped with impurities such as C and Fe as appropriate. Doping with these impurities can reduce buffer leakage and suppress current collapse.

[0019] (3-2) Structure of the Channel Layer 42 The channel layer 42 is formed of, for example, a compound semiconductor layer. The compound semiconductor layer is formed on the buffer layer 41 by epitaxial growth. The channel layer 42 forms part of the current path between the pair of main electrodes 7. More specifically, a two-dimensional electron gas (2DEG) 43 is formed in the channel layer 42 due to the difference in polarization charge between the channel layer 42 and the barrier layer 45 disposed on the channel layer 42, and carriers are accumulated therein. Here, the carriers are electrons.

[0020] The channel layer 42 is formed of a compound semiconductor material, such as GaN. The GaN may be formed of undoped GaN (u-GaN), which does not contain impurities. In this case, impurity scattering of carriers in the channel layer 42 can be suppressed, thereby achieving high carrier mobility.

[0021] (3-3) Configuration of Spacer Layer 44 The spacer layer 44 is formed of, for example, a compound semiconductor layer having a band gap larger than that of the channel layer 42. The compound semiconductor layer is formed on the channel layer 42 by epitaxial growth. The spacer layer 44 is formed of, for example, a nitride semiconductor material containing AlN. This will be explained in detail. In the first embodiment, the spacer layer 44 is formed of, for example, Al ｘ１ In ｙ１ Ga［１－ｘ１－ｙ１］ The spacer layer 44 is formed of a nitride semiconductor material within the composition range of N (0<x1≦1, 0≦y1<1, 0<x1+y1≦1). That is, the spacer layer 44 can be formed using a binary nitride semiconductor material such as AlN, a ternary nitride semiconductor material such as AlGaN, or a quaternary nitride semiconductor material such as AlGaInN.

[0022] In the first embodiment, in the semiconductor 4, AlN, which is a binary compound semiconductor material, is formed as the spacer layer 44 between the channel layer 42 and the barrier layer 45. In the field-effect transistor 2 configured in this manner, the influence of alloy scattering from the barrier layer 45, which is a ternary compound semiconductor material, is small on carriers (two-dimensional electron gas 43) induced at the interface between the spacer layer 44 and the channel layer 42. In other words, high carrier mobility can be achieved in the field-effect transistor 2.

[0023] (3-4) Structure of Barrier Layer 45 The barrier layer 45 is formed of a compound semiconductor layer in which carriers are accumulated in the channel layer 42 due to polarization with the channel layer 42. The compound semiconductor layer is formed on the spacer layer 44 by epitaxial growth. The barrier layer 45 is formed of a nitride semiconductor material whose band gap is larger than that of the channel layer 42. A detailed description will be given below. The barrier layer 45 is made of, for example, Al ｘ In １－ｘ The semiconductor layer is made of nitride semiconductor material where x is a group of N (0≦x<1).

[0024] As a compound semiconductor material used for the barrier layer 45, if the compound semiconductor material allows carriers to be accumulated at the interface between the channel layer 42 and the spacer layer 44 due to the difference in polarization charge amount with the channel layer 42, then for example, Al １－ｘ－ｙ In ｘ Ga ｙ N (0≦x<1, 0≦y<1, x+y≦1) can also be used. １－ｘ－ｙ In ｘ Ga ｙAlternatively, N may be used. In this case, impurity scattering of carriers in the channel layer 42 can be suppressed, thereby achieving high carrier mobility.

[0025] (3-5) Structure of the Cap Layer 46 The cap layer 46 is formed by being laminated on the barrier layer 45. The cap layer 46 is formed, for example, of a single layer of GaN or SiN, or a composite layer in which SiN is laminated on GaN. The cap layer 46 may also be formed, for example, of a single layer, from a material whose composition element concentration changes in the thickness direction. The cap layer 46 may also be formed, for example, from Al １－ｚ－ｗ In ｚ Ga ｗ The epitaxial layer may be formed of a compound semiconductor material of N (0≦z≦1, 0≦w≦1, z+w≦1). In this case, the wafer surface on which the epitaxial layer is formed can be protected from handling and process history.

[0026] It should be noted that the cap layer 46 is not necessarily required from the viewpoint of the final desired device characteristics, mass productivity, and the like.

[0027] (4) Configuration of the Gate Electrode 6 As shown in FIGS. 1 and 2 , a passivation film 5 is disposed on the cap layer 46 of the semiconductor 4, and a gate opening 5H1 is disposed in the passivation film 5, penetrating the passivation film 5 in the film thickness direction (arrow Z direction). The gate electrode 6 is disposed in the cap layer 46 of the semiconductor 4 at least within the gate opening 5H1. A portion of the gate electrode 6 extends around the gate opening 5H1 and onto the passivation film 5. In the first embodiment, the gate electrode 6 is formed of a composite layer in which Ni and Au are sequentially stacked from the semiconductor 4 side toward the arrow Z direction. Note that the gate electrode material of the gate electrode 6 is not limited to this example.

[0028] (5) Configuration of the Main Electrode 7 The main electrode 7 is disposed on the semiconductor 4 through a main electrode opening 5H2 formed in the passivation film 5 at a position spaced apart from the gate electrode 6 in the gate length direction. A pair of main electrodes 7 are disposed on both sides of the gate electrode 6 in the gate length direction, with the gate electrode 6 at the center. The main electrodes 7 are ohmic electrodes that make ohmic contact with the semiconductor 4. That is, the connection between the main electrode 7 and the two-dimensional electron gas 43 has low resistance. The main electrode 7 is formed of a composite layer in which, for example, Ti, Al, Ni, and Au are sequentially stacked from the semiconductor 4 toward the direction of the arrow Z.

[0029] Furthermore, the main electrode 7 is connected to the two-dimensional electron gas 43 via a high impurity density region 9 disposed from the cap layer 46 to the channel layer 42. In plan and side views, the high impurity density region 9 is disposed in a position of the channel layer 42 overlapping with the main electrode 7, and is a semiconductor region having the same conductivity type as the carriers flowing in the channel layer 42 and a higher impurity density than the channel layer 42. As described above, in the first embodiment, electrons flow as carriers in the two-dimensional electron gas 43, and therefore the high impurity density region 9 is formed of an n-type semiconductor region. By providing the high impurity density region 9, the connection between the main electrode 7 and the two-dimensional electron gas 43 has low resistance.

[0030] (6) Configuration of Active Region 10 and Element Isolation Region 11 As shown in FIGS. 1 and 2 , in side view and plan view, the field-effect transistor 2 is disposed in the active region 10, and an element isolation region 11 is disposed around the side of the field-effect transistor 2. The element isolation region 11 is disposed around the side of the active region 10 from at least the cap layer 46 to the channel layer 42, extending deeper toward the substrate 3 than the two-dimensional electron gas (2DEG) 43. In the first embodiment, the element isolation region 11 is a region into which an impurity such as B is introduced to provide insulation. The introduction of the impurity is performed, for example, by ion implantation.

[0031] (7) Configuration of Passivation Film 5 In the first embodiment, the passivation film 5 includes a first passivation film 51 disposed on the semiconductor 4 and a second passivation film 52 disposed on the first passivation film 51. Since the passivation film 5 has a gate opening 5H1 and a main electrode opening 5H2 formed therein, the passivation film 5 is effectively disposed between the gate electrode 6 and the main electrode 7.

[0032] The first passivation film 51 is disposed in contact with the surface of the cap layer 46 of the semiconductor 4. The first passivation film 51 is formed by containing one or more transition metal elements from group III to group XI. In the first embodiment, the first passivation film 51 is formed of HfOx (x=2) containing Hf as a transition metal element. HfO ２ is formed with a stoichiometric composition. The first passivation film 51 configured in this manner has insulating properties. Therefore, the first passivation film 51 is used as an interlayer insulator disposed between electrodes, between an electrode and a wiring, or between wiring. Furthermore, the first passivation film 51 can effectively suppress or prevent the diffusion of elements contained in the second passivation film 52 into the semiconductor 4. The first passivation film 51 is formed to a thickness of, for example, 0.5 nm or more and less than 7.0 nm. Note that the first passivation film 51 does not need to have a completely stoichiometric composition as long as it has insulating properties.

[0033] The second passivation film 52 is laminated on the first passivation film 51. It is used as an interlayer insulator disposed between electrodes, between an electrode and a wiring, or between wirings. The second passivation film 52 is made of, for example, SiN, Al ２ O ３ and SiO ２ The second passivation film 52 may be formed of a single layer or a composite layer of the selected insulating material. The second passivation film 52 may be formed to a thickness of, for example, 10 nm to 200 nm.

[0034] (8) Configuration of Junction 8 In the field-effect transistor 2 configured as above, the gate electrode 6 is disposed in the gate opening 5H1 with the junction 8 interposed between the semiconductor 4. In other words, the junction 8 is disposed between the cap layer 46 of the semiconductor 4 and the gate electrode 6. Here, the present technology includes both a case where the junction 8 is disposed on a part of the interface between the cap layer 46 and the gate electrode 6 and a case where the junction 8 is disposed on the entire interface. Note that a part of the junction 8 may be formed so as to dig into the surface portion of the cap layer 46.

[0035] The bonding body 8 is formed to contain one or more transition metal elements from group III to group XI, similarly to the first passivation film 51. In the first embodiment, the bonding body 8 contains Hf, which is the same transition metal element contained in the first passivation film 51, and HfO ｘ (x≠2). ｘ is formed with a non-stoichiometric composition. That is, the junction body 8 is formed as a conductor rather than an insulator, and is joined to the cap layer 46 of the semiconductor 4 by a Schottky junction. In other words, the gate electrode is joined to the cap layer 46 of the semiconductor 4 by a Schottky junction, with the junction body 8 interposed therebetween. Furthermore, the Schottky junction may be a combination of both of these.

[0036] In the first embodiment, the junction body 8 further contains a transition metal element other than Hf. Here, Ni is contained as the transition metal element. As described above, the junction body 8 side of the gate electrode 6 is made of Ni, and therefore, a portion of this Ni is diffused into the junction body 8. Note that the diffusion of the gate electrode material into the junction body 8 is not necessarily required.

[0037] The junction body 8 is formed to include a pseudomorphic region and an amorphous (or non-crystalline) region at the interface with the cap layer 46 of the semiconductor 4. The pseudomorphic region and the amorphous region are respectively included in the interface direction or the thickness direction of the junction body 8. Here, the pseudomorphic region is used to mean a partial region of the junction body 8 having a lattice constant that matches the lattice constant of the crystal of the cap layer 46 within a range up to the critical film thickness.

[0038] In addition, in the region overlapping the gate electrode 6, the thickness of the junction may be formed to be less uniform than the thickness of the cap layer 46, which is the surface layer on the junction side of the semiconductor 4, or the thickness of the barrier layer 45.

[0039] The thickness of the junction body 8 configured in this manner is, for example, less than 7 nm. Preferably, the thickness of the junction body 8 is 5 nm or less, and more preferably, the thickness of the junction body 8 is 3 nm or less. If the thickness of the junction body 8 is 7 nm or more, fluctuations in the threshold voltage become large during operation of the field-effect transistor 2. When the semiconductor device 1 according to the first embodiment is used, for example, as a power amplifier for a mobile terminal, the fluctuations in the threshold voltage are not suitable for this type of device.

[0040] As described above, the thickness of the junction body 8 may be non-uniform, and therefore, the average thickness of the junction body 8 may be, for example, one atomic layer or more in the region overlapping with the gate electrode 6. Although it depends on the selected transition metal element, the thickness of one atomic layer or more of the junction body 8 is, for example, 0.25 nm or more, as explained using numerical values.

[0041] [Method of Manufacturing the Semiconductor Device 1 and Field Effect Transistor 2] Next, a method of manufacturing the semiconductor device 1 and field effect transistor 2 according to the first embodiment will be described. 3 to 7 show an example of cross sections of the manufacturing method, each illustrating a step.

[0042] First, a substrate 3 is prepared (see FIG. 3). For example, single crystal Si is used for the substrate 3. Although simply referred to as the substrate 3, the substrate 3 is actually a semiconductor wafer having regions for forming a plurality of semiconductor devices 1 before the dicing process.

[0043] 3, a semiconductor 4 is formed on a substrate 3. The semiconductor 4 is formed by sequentially stacking a buffer layer 41, a channel layer 42, a spacer layer 44, a barrier layer 45, and a cap layer 46 from the substrate 3 side in the direction of the arrow Z. Each layer of the semiconductor 4 will be described in detail.

[0044] The buffer layer 41 is formed by epitaxial growth on the substrate 3. The buffer layer 41 is formed of one or more compound semiconductor layers selected from, for example, AlN, AlGaN, and GaN.

[0045] The channel layer 42 is formed by epitaxial growth on the buffer layer 41. The channel layer 42 is formed using, for example, GaN as a compound semiconductor layer.

[0046] The spacer layer 44 is formed by epitaxial growth on the channel layer 42. The spacer layer 44 is formed as a compound semiconductor layer using a nitride semiconductor material containing, for example, AlN.

[0047] The barrier layer 45 is formed by epitaxial growth on the spacer layer 44. The barrier layer 45 is a compound semiconductor layer made of, for example, a nitride semiconductor material.

[0048] The cap layer 46 is formed on the barrier layer 45 by one deposition method selected from epitaxial growth, atomic layer deposition (ALD), and chemical vapor deposition (CVD) depending on the material to be deposited. For example, when the cap layer 46 is formed of GaN as a compound semiconductor layer, the cap layer 46 is formed by epitaxial growth.

[0049] Subsequently, an isolation region 11 is formed in the semiconductor 4 around the active region 10 where the field-effect transistor 2 will be formed (see FIG. 4). As described above, the isolation region 11 is formed by selectively introducing, for example, B or the like into the semiconductor 4 using ion implantation to impart insulating properties. Once the isolation region 11 is formed, the active region 10 is formed into a mesa shape.

[0050] 4, a pair of high impurity concentration regions 9 to be used as a source region or a drain region is formed in the active region 10. The high impurity concentration regions 9 are formed by, for example, a regrowth method. The high impurity concentration regions 9 may be formed after the gate electrode 6 is formed.

[0051] 5, a passivation film 5 is formed over the entire semiconductor 4, including the active region 10 and the element isolation region 11. As described above, the passivation film 5 is formed by sequentially stacking a first passivation film 51 and a second passivation film 52. The first passivation film 51 is formed on the cap layer 46 by using the ALD method or the CVD method. The first passivation film 51 is made of a material containing a transition metal element, for example, HfO ２ The first passivation film 51 is formed to a thickness of, for example, 0.5 nm or more. The second passivation film 52 is formed on the first passivation film 51 using the ALD method or the CVD method. The second passivation film 52 is formed of an insulating material such as SiN, for example, in a single layer or multiple layers.

[0052] 6, in the region where the gate electrode 6 is to be formed, a portion of the gate opening 5H1 is formed in the second passivation film 52 of the passivation film 5. When the portion of the gate opening 5H1 is formed, the surface of the underlying first passivation film 51 is exposed. The gate opening 5H1 is formed by an etching method using a mask 55 formed by, for example, photolithography. As the etching method, an anisotropic dry etching method or a wet etching method is used to effectively suppress the expansion of the opening dimensions.

[0053] Furthermore, the first passivation film 51 is also used as an etching stopper layer because it has an etching selectivity with respect to the second passivation film 52. In other words, the first passivation film 51 can effectively suppress or prevent etching damage to the surface of the semiconductor 4 when forming part of the gate opening 5H1 in the second passivation film 52.

[0054] 7, using the mask 55 and a portion of the gate opening 5H1 as a mask, etching is performed on a portion of the first passivation film 51 in the thickness direction. Dry etching or wet etching is used as the etching method. As the thickness of the first passivation film 51 decreases from its initial thickness and is further affected by the etching history, the insulating properties of the first passivation film 51 are lost, and the first passivation film 51 is formed as a conductive bonded body 8. When the first passivation film 51 is thinner than its initial thickness by, for example, 10% or more, the loss of insulating properties becomes noticeable. As a result, the bonded body 8 is transformed into a conductor containing a transition metal element and having a non-stoichiometric composition.

[0055] Furthermore, a part of the gate opening 5H1 (the second passivation film 52) is used as a mask to form the junction body 8. Therefore, the junction body 8 is formed in a self-aligned manner with respect to the gate opening 5H1. When the junction body 8 is formed, another part of the gate opening 5H1 that is connected to the part of the gate opening 5H1 is formed, thereby completing the gate opening 5H1. After the junction body 8 is formed, the mask 55 is peeled off.

[0056] 1 and 2, the gate electrode 6 is formed. A portion of the gate electrode 6 is electrically connected to and mechanically bonded to the junction body 8 through the gate opening 5H1. The other portion of the gate electrode 6 extends onto the passivation film 5. The gate electrode 6 is formed, for example, by using a mask vapor deposition method. In the first embodiment, the gate electrode 6 is formed by sequentially laminating Ni and Au. Therefore, the junction body 8 already contains Hf as a transition metal element, and further contains Ni of the gate electrode 6 by diffusion. Ni is a transition metal element.

[0057] Subsequently, main electrode openings 5H2 are formed in the passivation film 5 in the high impurity concentration region 9 (see FIG. 1). Thereafter, as shown in FIGS. 1 and 2, a pair of main electrodes 7 to be used as source and drain electrodes are formed. The main electrodes 7 are electrically connected to and mechanically joined to the high impurity concentration region 9 through the main electrode openings 5H2. The main electrodes 7 are formed by sequentially depositing Ti, Al, Ni, and Au using, for example, a mask evaporation method.

[0058] When this series of manufacturing steps is completed, the manufacturing method of the semiconductor device 1 and the field effect transistor 2 according to the first embodiment is completed.

[0059] [Operation and Effect] As described above, the semiconductor device 1 according to the first embodiment includes a field-effect transistor 2. The field-effect transistor 2 includes a semiconductor 4, a junction 8, and a gate electrode 6. The junction 8 is disposed on the semiconductor 4 and contains a transition metal element. The gate electrode 6 is disposed on the semiconductor 4 with the junction 8 interposed therebetween. In other words, the junction 8 is disposed between the semiconductor 4 and the gate electrode 6.

[0060] The junction 8 is configured to protect the surface of the semiconductor 4 with which the gate electrode 6 forms a Schottky contact. More specifically, in the process of forming a portion of the gate opening 5H1 in the passivation film 5 shown in FIGS. 6 and 7 of the manufacturing method, the first passivation film 51, which is later generated as the junction 8, effectively suppresses or prevents the diffusion of elements contained in the second passivation film 52 into the semiconductor 4. In addition, the first passivation film 51 effectively suppresses or prevents etching damage to the semiconductor 4 caused by the etching used to form the portion of the gate opening 5H1. The junction 8 is formed from the first passivation film 51, with the insulating properties of the first passivation film 51 removed, after the portion of the gate opening 5H1 is formed in the second passivation film 52, i.e., after the diffusion of the elements and etching damage are effectively suppressed or prevented.

[0061] In the Schottky junction HEMT according to the comparative example, elements contained in the passivation film and the etching gas are incorporated into the semiconductor during dry etching to form the gate opening. These elements incorporated into the semiconductor cause leakage current during off-state operation. Furthermore, in the Schottky junction HEMT according to the comparative example, the passivation film is completely removed to expose the semiconductor surface to form the gate opening. This means that etching damage occurs on the semiconductor surface, causing the Schottky junction HEMT to exhibit characteristic fluctuations, such as a shift in threshold voltage.

[0062] In the field-effect transistor 2 according to the first embodiment, the gate electrode 6 is disposed on the semiconductor 4 via the junction 8, thereby effectively suppressing off-leakage current. FIG. 8 shows an example of the relationship between the on-off ratio and gate voltage of a field-effect transistor. The horizontal axis represents the gate voltage applied to the gate electrode of the field-effect transistor. The vertical axis represents the on-off ratio of the field-effect transistor. The on-off ratio is the ratio of the minimum current value (off current value) flowing through the two-dimensional electron gas 43 due to gate control to the maximum current value (on current value). The vertical axis is normalized by the maximum current. As is clear from FIG. 8 , the on-off ratio of the field-effect transistor 2 according to the first embodiment, designated by the symbol A, is three to four orders of magnitude smaller than the on-off ratio of the Schottky junction HEMT according to the comparative example, designated by the symbol B.

[0063] 9 shows an example of the relationship between the on / off ratio of the field effect transistor 2 and the thickness of the first passivation film 51 at the time of deposition before being formed into the junction 8. The horizontal axis indicates the thickness of the first passivation film 51 at the time of deposition. The vertical axis indicates the on / off ratio of the field effect transistor 2 after the junction 8 is formed from the first passivation film 51. The on / off ratio here is the current in the off state / the current in the on state. As shown in FIG. 9, when the thickness of the first passivation film 51 at the time of deposition is, for example, 0.5 nm, the on / off ratio of the field effect transistor 2 having the junction 8 formed from the first passivation film 51 is 10 －５ When the thickness of the first passivation film 51 is, for example, 1.0 nm when formed, the on / off ratio of the field effect transistor 2 having the junction 8 formed from the first passivation film 51 is 10 －６ When the thickness of the first passivation film 51 is, for example, 2.0 nm as formed, the on / off ratio of the field effect transistor 2 having the junction 8 formed from the first passivation film 51 is 10 －８ is.

[0064] For example, when the semiconductor device 1 including the field effect transistor 2 is used as a power amplifier for a portable terminal, the power amplifier for the portable terminal has a capacitance of 10. －６ Therefore, in the semiconductor device 1 to be mounted on a device for a portable terminal, if the first passivation film 51 is formed to a thickness of, for example, 1.0 nm, the field effect transistor 2 including the junction 8 formed from the first passivation film 51 can obtain a desired on / off ratio.

[0065] 1, the field effect transistor 2 is constructed as a Schottky junction HEMT. In other words, the junction 8 is not an insulator, and the field effect transistor 2 is not a MIS (Metal Insulator Semiconductor) HEMT. Therefore, the field effect transistor 2 does not suffer from characteristic fluctuations such as threshold voltage fluctuations that occur in MIS HEMTs.

[0066] 1, in the field-effect transistor 2, the thickness of the junction 8 is formed to be less than 7 nm. This makes it possible to effectively suppress or prevent fluctuations in the threshold voltage during operation of the field-effect transistor 2. This makes it possible to construct a semiconductor device 1 suitable for use in devices for mobile terminals.

[0067] 1, in the field-effect transistor 2, the thickness of the junction 8 is less uniform than the thickness of the surface layer of the semiconductor 4 on the junction 8 side, i.e., the thickness of the cap layer 46. Furthermore, in the region overlapping the gate electrode 6, the junction 8 has an average thickness of one atomic layer or more. Therefore, even if the thickness of the junction 8 is less uniform, as long as the junction 8 is formed into one atomic layer or more, it is possible to realize a field-effect transistor 2 that can achieve the above-described effects.

[0068] 1, in the field-effect transistor 2, the junction body 8 contains one or more transition metal elements from group III to group XI. Furthermore, the junction body 8 has a non-stoichiometric composition. In the first embodiment, the junction body 8 contains at least Hf as a transition metal element. The junction body 8 also contains HfOx (x≠2). The field-effect transistor 2 configured in this manner can achieve the above-described effects.

[0069] 1, in the field-effect transistor 2, the gate electrode 6 contains a transition metal element, and the junction body 8 contains the transition metal element contained in the gate electrode 6. In the first embodiment, the gate electrode 6 contains Ni, and the junction body 8 contains Hf and Ni. The field-effect transistor 2 configured in this manner can achieve the above-described effects.

[0070] 1 and 2, the field-effect transistor 2 of the semiconductor device 1 according to the first embodiment includes a main electrode 7. The main electrode 7 is disposed on the semiconductor 4 at a position spaced apart from the gate electrode 6 in the gate length direction. Here, the main electrodes 7 are disposed in pairs. A passivation film 5 is disposed on the semiconductor 4 between the gate electrode 6 and the main electrode 7. In the first embodiment, the passivation film 5 is formed by sequentially stacking a first passivation film 51 and a second passivation film 52. The first passivation film 51 contains a transition metal element. The transition metal element contained in the bonded body 8 and the first passivation film 51 is the same.

[0071] According to the semiconductor device 1 configured in this manner, as shown in FIGS. 5 to 7 of the manufacturing method, the first passivation film 51 is formed as an insulator, but the junction body 8 can be formed using this first passivation film 51. Therefore, a field-effect transistor 2 that exhibits the above-described effects can be constructed with a simple structure. Furthermore, from the perspective of the manufacturing method, since the junction body 8 is formed using the first passivation film 51 that is formed first, the number of manufacturing steps can be reduced compared to when the junction body 8 and the first passivation film 51 are formed separately. Note that the first passivation film 51 corresponds to the "passivation film" according to the present technology.

[0072] Furthermore, in the semiconductor device 1, as shown in FIG. 1, the content (a) of the transition metal element contained in the junction 8 of the field-effect transistor 2 is lower than the content (b) of the transition metal element contained in the first passivation film 51.

[0073] FIG. 10 shows an example of the relationship between the ratio ((b) / (a)) of the transition metal element content (a) in the bonded body 8 to the transition metal element content (b) in the first passivation film 51 and the on-off ratio. The ratio of the transition metal element content based on the Group III element disposed on the surface of the semiconductor 4 is shown here. A scanning transmission electron microscope (STEM) and energy dispersive X-ray spectroscopy (EDX) were used to measure this atomic composition ratio, with the analyzer and analysis software being "Noran System 7" manufactured by Thermo Fisher Scientific. The Group III element is, for example, Ga, which forms the cap layer 46, or Al or In, which forms the barrier layer 45.

[0074] As shown in FIG. 10, for example, when Al, a group III element, is used as a reference, if the atomic composition ratio of the content (a) to the content (b) is 1.60, the on-off ratio is 10 －６On the other hand, when the atomic composition ratio is 2.69, the on-off ratio is 10 －６ In addition, for example, if the atomic composition ratio of the content (a) to the content (b) is 1.84, the on-off ratio will be 10 －６ On the other hand, when the atomic composition ratio is 2.69, the on-off ratio is 10 －６ , and is similarly unsuitable for devices intended for portable terminals. That is, the atomic composition ratio of the content (a) of the transition metal element contained in the bonded body 8 to the content (b) of the transition metal element contained in the first passivation film 51 is set to less than 2.7. With the semiconductor device 1 configured in this manner, a field-effect transistor 2 that exhibits the aforementioned effects can be constructed.

[0075] 1 or the manufacturing method shown in FIGS. 6 and 7 , in the semiconductor device 1, the thickness of the bonded body 8 from the semiconductor 4 is formed to be 10% or more thinner than the thickness of the first passivation film 51 from the semiconductor 4. By reducing the thickness of the first passivation film 51, the insulating properties are lost, and the bonded body 8 can be easily formed from the first passivation film 51.

[0076] 2. Second Embodiment A semiconductor device 1 and a field-effect transistor 2 according to a second embodiment of the present disclosure will be described with reference to Figure 11. In the second embodiment and subsequent descriptions, components that are the same as or substantially the same as components in the first embodiment are denoted by the same reference numerals, and duplicate descriptions will be omitted.

[0077] [Configuration of Semiconductor Device 1 and Field-Effect Transistor 2] FIG. 11 shows an example of a cross-sectional configuration of a semiconductor device 1 according to the second embodiment and a field-effect transistor 2 mounted thereon.

[0078] 11 , the field-effect transistor 2 further includes a junction forming layer 80 between the gate electrode 6 and the junction 8. The junction forming layer 80 occludes some of the elements contained in the first passivation film 51, and forms the junction 8 having a non-stoichiometric composition with the first passivation film 51.

[0079] In the second embodiment, the junction formation layer 80 is made of, for example, Ti. The first passivation film 51 is made of, for example, HfO, similar to the first passivation film 51 in the first embodiment. ２ It is formed by

[0080] 6 of the manufacturing method according to the first embodiment, a gate opening 5H1 is formed, the first passivation film 51 is exposed through the gate opening 5H1, and then a junction generation layer 80 is formed on the first passivation film 51. Subsequently, a gate electrode 6 is formed on the first passivation film 51 with the junction generation layer 80 interposed therebetween. After this, annealing processing and sintering processing are performed.

[0081] When such a manufacturing method is used, the Ti of the junction forming layer 80 absorbs oxygen from the first passivation film 51. Therefore, the first passivation film 51 disposed in the region overlapping the gate opening 5H1 is formed into the junction 8 including a non-stoichiometric composition. That is, the second embodiment does not require the dry etching step of the manufacturing method according to the first embodiment.

[0082] The bonding layer 80 is not limited to Ti as long as it has the same function. For example, Zn, Bi, Co, Cr, Mn, etc. can be used as the bonding layer 80.

[0083] The other components are the same or substantially the same as the components of the semiconductor device 1 and field effect transistor 2 according to the first embodiment, and therefore description thereof will be omitted here.

[0084] [Effects] According to the semiconductor device 1 and field effect transistor 2 of the second embodiment, it is possible to obtain effects similar to those obtained by the semiconductor device 1 and field effect transistor 2 of the first embodiment described above.

[0085] 11 , the field-effect transistor 2 further includes a junction forming layer 80 between the gate electrode 6 and the junction 8. The junction forming layer 80 occludes some of the elements contained in the first passivation film 51, and forms the junction 8 having a non-stoichiometric composition from the first passivation film 51. Therefore, in the method for manufacturing the field-effect transistor 2, the dry etching step can be eliminated, and the manufacturing yield can be improved.

[0086] 3. Third Embodiment A semiconductor module 100 according to a third embodiment of the present disclosure will be described with reference to Fig. 12. Fig. 12 shows a schematic structure of the semiconductor module 100 according to the third embodiment.

[0087] [Configuration of Semiconductor Module 100] The semiconductor module 100 according to the third embodiment is an antenna-integrated module in which, for example, edge antennas 101 arranged in an array and front-end components are mounted as a single module on a substrate 110. The front-end components include a switch 102, a low-noise amplifier 103, a band-pass filter 104, and a power amplifier 105. The semiconductor module 100 can be used, for example, as a transceiver for communications.

[0088] The semiconductor module 100 includes the semiconductor device 1 according to either the first or second embodiment as transistors constituting, for example, a switch 102, a low-noise amplifier 103, or a power amplifier 105.

[0089] [Operation and Effect] The semiconductor module 100 according to the third embodiment includes the semiconductor device 1, and therefore can effectively suppress off-freak in wireless communication.

[0090] 4. Fourth Embodiment A wireless communication device (electronic device) 300 according to a fourth embodiment of the present disclosure will be described with reference to Fig. 13. Fig. 13 shows a schematic block configuration of the wireless communication device 300 according to the fourth embodiment.

[0091] [Configuration of Wireless Communication Device 300] The wireless communication device 300 according to the fourth embodiment includes an antenna ANT, an antenna switch circuit 301, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F. The interface unit I / F includes, for example, a wireless local area network (W-LAN) and Bluetooth (registered trademark). The wireless communication device 300 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection.

[0092] The wireless communication device 300 includes the semiconductor device 1 according to either the first or second embodiment as transistors constituting an antenna switch circuit 301, a high power amplifier HPA, a radio frequency integrated circuit RFIC, or a baseband unit BB.

[0093] [Operation and Effect] The wireless communication device 300 according to the fourth embodiment includes the semiconductor device 1, and therefore can effectively suppress off-leakage in wireless communication.

[0094] 5. Other Embodiments The present technology is not limited to the above-described embodiments and may be modified in various ways without departing from the spirit and scope of the present technology. For example, in the above-described embodiments, the semiconductor is formed of a GaN-based compound semiconductor material. In the present technology, the semiconductor may be formed of a GaAs-based compound semiconductor material.

[0095] As described above, the semiconductor device according to the first embodiment of the present disclosure includes a field-effect transistor having a semiconductor, a junction body including a transition metal element disposed on the semiconductor, and a gate electrode disposed on the semiconductor with the junction body interposed therebetween. With the semiconductor device configured in this manner, off-leakage of the field-effect transistor can be effectively suppressed.

[0096] A semiconductor device according to a second embodiment of the present disclosure is the semiconductor device according to the first embodiment, further comprising: a main electrode disposed on the semiconductor at a position spaced from the gate electrode in the gate length direction; and a passivation film disposed on the semiconductor between the gate electrode and the main electrode. The passivation film contains a transition metal element. In the semiconductor device according to the second embodiment, the transition metal elements contained in the junction and the passivation film are the same. Furthermore, in the semiconductor device according to the second embodiment, the content of the transition metal element contained in the junction is lower than the content of the transition metal element contained in the passivation film. A semiconductor device configured in this manner can easily form the junction and effectively suppress off-leakage of a field-effect transistor.

[0097] A semiconductor module according to a third embodiment of the present disclosure includes a semiconductor device. The semiconductor device includes a field-effect transistor having a semiconductor, a junction including a transition metal element disposed on the semiconductor, and a gate electrode disposed on the semiconductor with the junction interposed therebetween. Therefore, a semiconductor module can be constructed using the field-effect transistor that can effectively suppress off-leakage.

[0098] According to a fourth embodiment of the present disclosure, there is provided an electronic device including a semiconductor device. The semiconductor device includes a field-effect transistor having a semiconductor, a junction including a transition metal element disposed on the semiconductor, and a gate electrode disposed on the semiconductor with the junction interposed therebetween. Therefore, it is possible to construct an electronic device using a field-effect transistor that can effectively suppress off-leakage.

[0099] <Configuration of the Present Technology> The present technology has the following configuration: According to the present technology having the following configuration, it is possible to effectively suppress off-leakage of a field-effect transistor in a semiconductor device, a semiconductor module, and an electronic device.

[0100] (1) A semiconductor device comprising: a semiconductor; a junction structure containing a transition metal element disposed on the semiconductor; and a field effect transistor having a gate electrode disposed on the semiconductor with the junction structure interposed therebetween. (2) The semiconductor device according to (1), wherein the junction structure is joined to the semiconductor by a Schottky junction, or the gate electrode is joined to the semiconductor by a Schottky junction with the junction structure interposed therebetween. (3) The semiconductor device according to (1) or (2), wherein the thickness of the junction structure from the semiconductor is less than 7 nm. (4) The semiconductor device according to (3), wherein the average thickness of the junction structure in the region overlapping the gate electrode is one atomic layer or more. (5) The semiconductor device according to (4), wherein the thickness of the junction structure in the region overlapping the gate electrode is less uniform than the thickness of the surface layer of the semiconductor on the junction structure side. (6) The semiconductor device according to any one of (1) to (5), wherein the junction structure has a non-stoichiometric composition. (7) The semiconductor device according to any one of (1) to (6), wherein the bonded body contains one or more transition metal elements from group III to group XI. (8) The semiconductor device according to any one of (1) to (7), wherein the bonded body contains one or more transition metal elements selected from Hf and Ni as the transition metal element. (9) The semiconductor device according to (8), wherein the bonded body contains HfOx (where x≠2). (10) The semiconductor device according to any one of (1) to (9), wherein the gate electrode contains a transition metal element, and the bonded body contains the transition metal element contained in the gate electrode. (11) The semiconductor device according to any one of (1) to (10), wherein the bonded body contains a region that is pseudomorphic at the interface with the semiconductor and an amorphous region in the interface direction or in the thickness direction of the bonded body. (12) The semiconductor device according to any one of (1) to (11), wherein the semiconductor includes a group III-group V compound semiconductor, and the field effect transistor is a Schottky junction high electron mobility transistor.(13) The semiconductor device according to any one of (1) to (12), further comprising: a main electrode disposed on the semiconductor at a position spaced from the gate electrode in the gate length direction; and a passivation film disposed on the semiconductor between the gate electrode and the main electrode, the passivation film containing a transition metal element. (14) The semiconductor device according to (13), wherein the same transition metal element is contained in the bonded body and the passivation film. (15) The semiconductor device according to (14), wherein the content of the transition metal element contained in the bonded body is lower than the content of the transition metal element contained in the passivation film. (16) The semiconductor device according to (15), wherein the semiconductor comprises a group III element, and wherein the atomic composition ratio of the content of the transition metal element contained in the bonded body to the content of the transition metal element contained in the passivation film is less than 2.7, based on the group III element. (17) The semiconductor device according to any one of (13) to (16), wherein a thickness of the junction from the semiconductor is 10% or more thinner than a thickness of the passivation film from the semiconductor. (18) The semiconductor device according to any one of (1) to (17), further comprising a junction generation layer between the gate electrode and the junction, wherein the junction generation layer occludes some elements contained in the passivation film and forms the junction having a non-stoichiometric composition with the passivation film. (19) A semiconductor module comprising a semiconductor device, the semiconductor device comprising: a semiconductor; a junction disposed on the semiconductor and containing a transition metal element; and a field effect transistor having a gate electrode disposed on the semiconductor with the junction interposed therebetween. (20) An electronic device, the semiconductor device comprising: a semiconductor; a junction disposed on the semiconductor and containing a transition metal element; and a field effect transistor having a gate electrode disposed on the semiconductor with the junction interposed therebetween.

[0101] This application claims priority based on Japanese Patent Application No. 2023-123546, filed on July 28, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0102] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a field effect transistor having a semiconductor; a junction disposed on the semiconductor and containing a transition metal element; and a gate electrode disposed on the semiconductor with the junction interposed therebetween.

2. The semiconductor device according to claim 1, wherein the junction is joined to the semiconductor by a Schottky junction, or the gate electrode is joined to the semiconductor by a Schottky junction with the junction interposed therebetween.

3. The semiconductor device according to claim 1, wherein the thickness of the junction from the semiconductor is less than 7 nm.

4. The semiconductor device according to claim 3, wherein the average thickness of the junction in the region overlapping the gate electrode is equal to or greater than one atomic layer.

5. The semiconductor device according to claim 4, wherein in the region overlapping said gate electrode, the thickness of said junction is non-uniform compared to the thickness of the surface layer of said semiconductor on said junction side.

6. The semiconductor device according to claim 1, wherein the junction has a non-stoichiometric composition.

7. The semiconductor device according to claim 1, wherein the junction contains one or more transition metal elements from Group III to Group XI.

8. The semiconductor device according to claim 1, wherein the bonding body contains at least one transition metal element selected from the group consisting of Hf and Ni.

9. The semiconductor device according to claim 8, wherein the junction contains HfOx (where x≠2).

10. The semiconductor device according to claim 7, wherein the gate electrode contains a transition metal element, and the junction body contains the transition metal element contained in the gate electrode.

11. The semiconductor device according to claim 1, wherein the junction includes a region that is pseudomorphic at the interface with the semiconductor and an amorphous region in the direction of the interface or in the thickness direction of the junction.

12. The semiconductor device according to claim 1, wherein the semiconductor includes a III-V compound semiconductor, and the field effect transistor is a Schottky junction high electron mobility transistor.

13. The semiconductor device according to claim 1, further comprising: a main electrode disposed on the semiconductor at a position spaced apart from the gate electrode in the gate length direction; and a passivation film disposed on the semiconductor between the gate electrode and the main electrode, the passivation film including a transition metal element.

14. The semiconductor device according to claim 13, wherein the junction and the passivation film each contain the same transition metal element.

15. The semiconductor device according to claim 14, wherein the content of the transition metal element contained in the bonded body is lower than the content of the transition metal element contained in the passivation film.

16. The semiconductor device according to claim 15, wherein the semiconductor comprises a group III element, and the atomic composition ratio of the content of the transition metal element contained in the bonded body to the content of the transition metal element contained in the passivation film is less than 2.7, based on the group III element.

17. The semiconductor device according to claim 13, wherein the thickness of the junction from the semiconductor is 10% or more thinner than the thickness of the passivation film from the semiconductor.

18. The semiconductor device according to claim 13, further comprising a junction generation layer between the gate electrode and the junction, the junction generation layer occluding a portion of the elements contained in the passivation film and forming the junction having a non-stoichiometric composition from the passivation film.

19. A semiconductor module comprising a semiconductor device comprising: a field effect transistor having a semiconductor; a junction disposed on the semiconductor and containing a transition metal element; and a gate electrode disposed on the semiconductor with the junction interposed therebetween.

20. An electronic device comprising a semiconductor device, the semiconductor device comprising: a field effect transistor having a semiconductor, a junction disposed on the semiconductor and containing a transition metal element, and a gate electrode disposed on the semiconductor with the junction interposed therebetween.

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