Semiconductor device

Abstract

The present invention suppresses the occurrence of destruction in the vicinity of a wiring region passing through the inside of an active region when an IGBT is turned off. A semiconductor device (1) has a wiring region (4) that passes through the inside of an active region (2) having an IGBT. The wiring region (4) includes: a drift layer (11) of a first conductivity type; a collector layer (16) of a second conductivity type provided on the rear surface side of the drift layer (11); a well layer (17) of the second conductivity type provided on the front surface side of the drift layer (11); a gate runner (5) provided on the front surface side of the well layer (17) to supply a gate potential to the gate electrode (21); and a contact region (third contact region (30)) that electrically connects the well layer (17) and the emitter electrode (22). The gate runner (5) is composed of a single layer (first gate runner (5A)), and has an opening part (5C) larger than the contact region at a position corresponding to the contact region.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] 2. Description of the Related Art An IGBT (Insulated Gate Bipolar Transistor) is known as one type of semiconductor device.

[0003] Fig. 8 is a top view of a conventional semiconductor device. Fig. 9 is an enlarged view of part D in Fig. 8. Fig. 10 is a cross-sectional view taken along the line CC' in Fig. 9. Note that in Figs. 8 and 9, some components are omitted for clarity.

[0004] 8 , conventional semiconductor device 1 has an active region 2 having an IGBT, a termination region 3 surrounding the periphery of active region 2, a wiring region 4 passing through the inside of active region 2, a gate runner 5, and a gate pad 6. Furthermore, conventional semiconductor device 1 has a drift layer 11, a body layer 12, an emitter layer 13, a contact layer 14, a buffer layer 15, a collector layer 16, a well layer 17, a gate electrode 21, an emitter electrode 22, a collector electrode 23, a gate insulating film (not shown), a trench (not shown), an interlayer insulating film 26, an insulating film 27, a first contact region 28, and a second contact region 29, as shown in FIGS.

[0005] 8, a gate runner 5 that supplies a gate potential to a gate electrode 21 of the IGBT is provided between the active region 2 and the termination region 3 and in the wiring region 4. The gate runner 5 is connected to a gate pad 6 that is connected to the outside.

[0006] 9 and 10, the gate runner 5 in the wiring region 4 is composed of two layers: a first gate runner 5A made of polysilicon and a second gate runner 5B made of metal. The first gate runner 5A and the second gate runner 5B are connected by a second contact region 29 that penetrates the interlayer insulating film 26. Because metal has a lower wiring resistance than polysilicon, by configuring the gate runner 5 in two layers, the wiring resistance of the gate runner 5 can be reduced.

[0007] Conventional techniques in which the gate runner 5 in the wiring region 4 is configured in two layers include, for example, FIG. 26 of Patent Document 1 and FIG. 20 of Patent Document 2.

[0008] JP 2019-12840 A JP 2018-200950 A

[0009] 10 , in the conventional semiconductor device 1, when the IGBT is turned off, holes 31 injected from the collector layer 16 at a position overlapping the gate runner 5 in the wiring region 4 enter the well layer 17, pass through the first contact region 28 outside the wiring region 4 that connects the body layer 12 and the emitter electrode 22 via the contact layer 14, and are extracted along a path that leads to the emitter electrode 22. This causes the holes 31 to concentrate at the end of the first contact region 28, resulting in a problem that breakdown may occur at a position indicated by breakdown point 32 near the wiring region 4. This breakdown then causes a problem that the breakdown tolerance of the IGBT in the reverse bias safe operating area (RBSOA) is limited.

[0010] The problem to be solved by the present invention is to provide a semiconductor device that suppresses the occurrence of breakdown in the vicinity of a wiring region that passes through the inside of an active region when an IGBT is turned off.

[0011] In order to achieve the above object, a semiconductor device of the present invention has an active region having an IGBT, a termination region surrounding the periphery of the active region, and a wiring region passing through the inside of the active region, wherein the IGBT has a gate electrode, an emitter electrode provided on the front surface side, and a collector electrode provided on the back surface side, and the wiring region has a drift layer of a first conductivity type, a collector layer of a second conductivity type provided on the back surface side of the drift layer, a well layer of the second conductivity type provided on the front surface side of the drift layer, a gate runner provided on the front surface side of the well layer and supplying a gate potential to the gate electrode, the emitter electrode provided on the front surface side of the gate runner, and a contact region electrically connecting the well layer and the emitter electrode, and the gate runner is composed of a single layer and has an opening larger than the contact region at a position corresponding to the contact region.

[0012] According to the present invention, it is possible to prevent breakdown from occurring near the wiring region that passes through the inside of the active region when the IGBT is turned off.

[0013] 6. A top view of a semiconductor device of an embodiment. An enlarged view of part D in FIG. 1. An AA' cross-sectional view of FIG. 2. A BB' cross-sectional view of FIG. 2. A CC' cross-sectional view of FIG. 2. A top view of a semiconductor device of a comparative example. An enlarged view of part D in FIG. 6. A top view of a conventional semiconductor device. An enlarged view of part D in FIG. 8. A CC' cross-sectional view of FIG. 9.

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0015] FIG. 1 is a top view of a semiconductor device according to an embodiment. FIG. 2 is an enlarged view of part D in FIG. 1. FIG. 3 is a cross-sectional view taken along line A-A' in FIG. 2. FIG. 4 is a cross-sectional view taken along line B-B' in FIG. 2. FIG. 5 is a cross-sectional view taken along line C-C' in FIG. 2. Note that in FIGS. 1 and 2, some components are omitted from the illustration in order to make the drawings easier to understand.

[0016] 1, the semiconductor device 1 of the embodiment has an active region 2 having an IGBT, a termination region 3 surrounding the periphery of the active region 2, and a wiring region 4 passing through the inside of the active region 2. The semiconductor device 1 also has, between the active region 2 and the termination region 3 and in the wiring region 4, a gate runner 5 which is a gate wiring that supplies a gate potential to a gate electrode 21 (see FIG. 2 etc.) of the IGBT, and a gate pad 6 which is connected to the outside and supplies a gate potential to the gate runner 5.

[0017] The gate runner 5 between the active region 2 and the termination region 3 is preferably configured with at least two layers, as in the conventional case. This allows the wiring resistance of the gate runner 5 to be reduced. In this embodiment, an example will be described in which the gate runner 5 is configured with two layers: a first gate runner 5A made of, for example, polysilicon, and a second gate runner 5B made of, for example, a metal such as Al. The first gate runner 5A arranged on the back side and the second gate runner 5B arranged on the front side are connected by a contact region (not shown) that penetrates the interlayer insulating film 26 (see FIGS. 3 to 6 ).

[0018] In contrast, in this embodiment, the gate runner 5 in the wiring region 4 is composed of a single layer of a first gate runner 5A made of, for example, polysilicon. 2 and 5, the semiconductor device 1 of this embodiment has a third contact region 30 in the wiring region 4 that electrically connects the well layer 17 and the emitter electrode 22.

[0019] In this embodiment, in the wiring region 4, the well layer 17 and the emitter electrode 22 are electrically connected via the third contact region 30. Therefore, in the wiring region 4, when the IGBT is turned off, holes 31 injected from the collector layer 16 at a position overlapping the gate runner 5 enter the well layer 17 and can pass directly to the emitter electrode 22 via the third contact region 30. This makes it possible to prevent the holes 31 from concentrating at the end of the first contact region 28 outside the wiring region 4, and to prevent breakdown from occurring near the wiring region 4. As a result, the RBSOA breakdown resistance of the IGBT is not limited by this breakdown, and the RBSOA breakdown resistance can be improved.

[0020] In the wiring region 4, the emitter electrode 22 is provided closer to the surface than the first gate runner 5A. An interlayer insulating film 26 is provided between the emitter electrode 22 and the first gate runner 5A. An insulating film 27 is provided between the first gate runner 5A and the well layer 17. The first gate runner 5A has an opening 5C larger than the third contact region 30 at a position corresponding to the third contact region 30. Therefore, the third contact region 30 has a structure that penetrates the interlayer insulating film 26, the first gate runner 5A, and the insulating film 27. The well layer 17 and the third contact region 30 are preferably connected via a contact layer 14 having a higher impurity concentration than the well layer 17. The emitter electrode 22 is preferably provided in a position that covers the entire gate runner 5 in the lateral direction.

[0021] 2 and 3, the IGBT in the active region 2 has a gate electrode 21, an emitter electrode 22 provided on the front surface side, and a collector electrode 23 provided on the back surface side. In this embodiment, an example will be described in which the IGBT has a trench 25, and the gate electrode 21 and gate insulating film 24 are provided inside the trench 25, but this is not limiting. The emitter electrode 22 and collector electrode 23 are formed of a metal such as Al, and the gate electrode 21 is formed of polysilicon, for example.

[0022] The IGBT also includes a drift layer 11 formed of a semiconductor of a first conductivity type (an n-type example is shown in FIG. 3 ), a body layer 12 formed of a semiconductor of a second conductivity type (a p-type example is shown in FIG. 3 ) and disposed closer to the surface than the drift layer 11, an emitter layer 13 formed of a semiconductor of the first conductivity type and disposed closer to the surface than the body layer 12, an interlayer insulating film 26 provided between the emitter layer 13 and the gate electrode 21 and emitter electrode 22, a buffer layer 15 formed of a semiconductor of the first conductivity type and disposed closer to the back surface than the drift layer 11, and having a higher impurity concentration than the drift layer 11, and a collector layer 16 formed of a semiconductor of the second conductivity type and disposed between the buffer layer 15 and a collector electrode 23. The emitter electrode 22 is connected to the emitter layer 13 at a first contact region 28 and is connected to the body layer 12 via the first contact region 28 and a contact layer 14 formed of a semiconductor of the second conductivity type. The buffer layer 15 is not essential, but is preferably provided.

[0023] The trench 25 has a depth that penetrates the body layer 12 and reaches the drift layer 11. A gate insulating film 24 is provided inside the trench 25 so as to surround the gate electrode 21.

[0024] 2 , 4 , and 5 , the wiring region 4 includes a drift layer 11, a collector layer 16 provided on the back side of the drift layer 11, a second conductivity type well layer 17 provided on the front side of the drift layer 11, a gate runner 5 (first gate runner 5A) provided on the front side of the well layer 17 and supplying a gate potential to a gate electrode 21, an emitter electrode 22 provided on the front side of the gate runner 5, and a contact region (third contact region 30) electrically connecting the well layer 17 and the emitter electrode 22. The gate runner 5 is composed of a single layer (first gate runner 5A) and has an opening 5C larger than the contact region (third contact region 30) at a position corresponding to the contact region (third contact region 30). The wiring region 4 also includes an interlayer insulating film 26, an insulating film 27, a contact layer 14, and a buffer layer 15. The buffer layer 15 is not essential, but is preferably provided.

[0025] As shown in Fig. 4, the well layer 17 has a deeper impurity diffusion depth than the trench 25. The well layer 17 also extends to a part outside the wiring region 4, and as shown in Fig. 5, the well layer 17 becomes shallower midway and is connected to the body layer 12. As shown in Fig. 4, an insulating film 27 is formed between the well layer 17 and the first gate runner 5A, and the insulating film 27 is connected to the gate insulating film 24.

[0026] As shown in FIG. 4, the gate electrode 21 is drawn out to the outside of the trench 25 and connected to the first gate runner 5A.

[0027] Next, the effect of forming the gate runner 5 in the wiring region 4 from a single layer of the first gate runner 5A and electrically connecting the well layer 17 and the emitter electrode 22 by the third contact region 30 within the opening 5C of the first gate runner 5A, as in this embodiment, will be described using comparative examples in FIGS. 6 and 7 .

[0028] 6 is a top view of a semiconductor device of a comparative example, and FIG. 7 is an enlarged view of a portion D in FIG.

[0029] In the comparative example, the gate runner 5 in the wiring region 4 is composed of two layers, a first gate runner 5A and a second gate runner 5B, which are connected to each other via a contact region (not shown), similar to the conventional example shown in FIG. 10 . Furthermore, the emitter electrode 22 and the second gate runner 5B are formed simultaneously from the same material, and are therefore in the same layer, similar to the conventional example shown in FIG. 10 . Therefore, as shown in FIG. 7 , to electrically connect the well layer 17 and the emitter electrode 22 via the third contact region 30 within the opening 5C of the first gate runner 5A, it is necessary to make the width (short-side dimension) of the first gate runner 5A larger than the width of the second gate runner 5B and to provide the third contact region 30 at a position that avoids the second gate runner 5B. As a result, the width of the wiring region 4 increases, and the area of ​​the active region 2 decreases.

[0030] 2, in this embodiment, the width of the wiring region 4 can be made smaller than in the comparative example, thereby ensuring the area of ​​the active region 2. The opening 5C is preferably provided at a position including the center of the gate runner 5 in the lateral direction. It is more preferable that the opening 5C be provided at the center of the gate runner 5 in the lateral direction.

[0031] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this and the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the carriers injected from the collector layer 16 become electrons instead of holes.

[0032] As an example of impurity concentration, the drift layer 11 is shown as a low concentration n-, the emitter layer 13 as a high concentration n+, the contact layer 14 as a high concentration p+, the body layer 12, the collector layer 16, and the well layer 17 as p, and the buffer layer 15 as n. The impurity concentrations are not limited to this, and may be changed as appropriate within a range in which the intended operation of this embodiment is possible.

[0033] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in the embodiments may be combined and applied.

[0034] REFERENCE SIGNS LIST 1...semiconductor device, 2...active region, 3...termination region, 4...wiring region, 5...gate runner, 5A...first gate runner (polysilicon), 5B...second gate runner (metal), 5C...opening, 6...gate pad, 11...drift layer, 12...body layer, 13...emitter layer, 14...contact layer, 15...buffer layer, 16...collector layer, 17...well layer, 21...gate electrode, 22...emitter electrode, 23...collector electrode, 24...gate insulating film, 25...trench, 26...interlayer insulating film, 27...insulating film, 28...first contact region (in IGBT), 29...second contact region (between gate runners), 30...third contact region (wiring region well layer), 31...hole, 32...breakdown location

Claims

1. A semiconductor device comprising: an active region having an IGBT, a termination region surrounding the periphery of the active region, and a wiring region passing through the inside of the active region, wherein the IGBT has a gate electrode, an emitter electrode provided on the front side, and a collector electrode provided on the back side, wherein the wiring region has: a drift layer of a first conductivity type, a collector layer of a second conductivity type provided on the back side of the drift layer, a well layer of a second conductivity type provided on the front side of the drift layer, a gate runner provided on the front side of the well layer and supplying a gate potential to the gate electrode, the emitter electrode provided on the front side of the gate runner, and a contact region electrically connecting the well layer and the emitter electrode, wherein the gate runner is composed of a single layer and has an opening larger than the contact region at a position corresponding to the contact region.

2. The semiconductor device according to claim 1, wherein the opening is provided at a position including the center of the gate runner in the lateral direction.

3. A semiconductor device according to claim 1, wherein the emitter electrode is provided at a position that covers the entire short side of the gate runner.

4. The semiconductor device according to claim 1, wherein the gate runner is made of polysilicon.

5. A semiconductor device according to claim 1, wherein the IGBT has a trench, and the gate electrode is provided inside the trench.

6. A semiconductor device according to claim 1, further comprising a gate runner, which is formed of at least two layers and supplies a gate potential to the gate electrode, between the active region and the termination region.

7. A semiconductor device according to claim 6, characterized in that the gate runner provided in the wiring region is made of polysilicon, and the gate runner, which is composed of at least two layers provided between the active region and the termination region, has a back side made of polysilicon and a front side made of metal.

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