FET, electromechanical instrument, and method for manufacturing fet

Abstract

Provided are an FET that can contribute to securing desired element performance even when miniaturized, an electromechanical instrument, and a method for manufacturing an FET. The FET comprises a diamond semiconductor layer, a gate insulating film disposed on the diamond semiconductor layer, and a gate electrode disposed on the gate insulating film and having a width narrower than the width of the gate insulating film. The width of the gate electrode is less than 100 nm. An end surface of the gate insulating film has, at least in part, a deposition end surface on which an insulating material is deposited.

Description

FET, electrical device, and method for manufacturing FET

[0001] [Description of Related Applications] The present invention is based on Japanese Patent Application No. 2023-127073 (filed on August 3, 2023), the entire contents of which are incorporated herein by reference. The present invention relates to a FET, an electrical device, and a method for manufacturing a FET.

[0002] Recent advances in diamond CVD (Chemical Vapor Deposition) technology have led to the development of increasingly high-purity CVD diamonds, making it possible to obtain single-crystal diamonds with high carrier (electron, hole) mobility. This has raised expectations for their use in diamond FETs (Field Effect Transistors), which offer excellent device performance in terms of electrical properties, high-frequency characteristics, and other factors.

[0003] One method for manufacturing a diamond FET is the following self-alignment method (see, for example, Non-Patent Documents 1 to 3). First, a diamond semiconductor layer (e.g., a hydrogen-terminated diamond layer) is formed on the (001) surface of a diamond single crystal by CVD (Chemical Vapor Deposition), an Au (gold) film is vapor-deposited on the surface of the diamond semiconductor layer, a first resist is formed in the element region on the Au film, and using the first resist as a mask, the Au film is wet-etched until the diamond semiconductor layer is exposed, and the first resist is removed. Next, a second resist having openings for forming a gate electrode and a source electrode / drain electrode is formed, and the Au film exposed from the openings in the second resist is wet-etched to form source electrode / drain electrodes made of an Au film separated widely from the openings. Next, using the second resist as a mask, a gate insulating film is formed on the diamond semiconductor layer exposed from the openings in the second resist by CVD, followed by forming a gate electrode by metal vapor deposition, and then the second resist and the insulating layer and metal layer thereon are lifted off. This completes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) type diamond FET.

[0004] According to the self-alignment method, compared to the non-self-alignment method (see, for example, Patent Document 1 and Non-Patent Document 4) in which the gate electrode and the source electrode / drain electrode are formed using separate resists, the gate insulating film / gate electrode can be positioned accurately relative to the positions of the source electrode / drain electrode. Therefore, even if the channel length or gate length is miniaturized to the order of nm in order to improve high frequency characteristics, there is no alignment error, and diamond FETs can be stably manufactured, which is advantageous in maintaining a high yield.

[0005] JP 2018-078254 A

[0006] Carrier transport properties in diamond and its application to high frequency FETs, Kawarada et al., Applied Physics, 73, 339-345, 2004-03-10, Japan Society of Applied Physics. Gate metal interface of hydrogen-terminated diamond FETs, Kakazu et al., Surface Science, Vol. 29, No. 3, pp. 159-163, 2008. Special feature: "The forefront of diamond surface and interface research" (https: / / www.jstage.jst.go.jp / article / jsssj / 29 / 3 / 29_3_159 / _pdf / -char / ja). "DIAMOND FIELD EFFECT TRANSISTORS", Stephen A. O. Russell et al., (https: / / www.armms.org / media / uploads / 05_armms_apr12_orussell.pdf). "A High Frequency Hydrogen-Terminated Diamond MISFET With fT / fmax of 70 / 80 GHz", X. Yu et al., IEEE Electron Device Letters, vol. 39, no. 9, pp. 1373-1376, Sept. 2018, doi: 10.1109 / LED.2018.2862158.

[0007] The following analysis is provided by the present inventors.

[0008] In the self-alignment method, the gate electrode and the gate insulating film are theoretically formed to have the same width (gate length), but since a space corresponding to the thickness of the source electrode / drain electrode is formed around the bottom of the opening of the second resist after the source electrode / drain electrode is formed by wet etching, the end of the gate electrode may extend outward from the opening of the second resist when the gate electrode is formed, resulting in a longer gate length and making it impossible to obtain desired device characteristics.In the case of MISFET, the end of the gate electrode may protrude from the end of the gate insulating film, and the gate electrode and the diamond semiconductor layer may come too close to each other, resulting in a deterioration in insulation performance or a short circuit (contact), which may cause deterioration in device characteristics.This problem becomes more pronounced as the device is miniaturized to the order of nm.

[0009] A main object of the present invention is to provide an FET, an electrical device, and a method for manufacturing an FET that can contribute to ensuring desired device performance even when miniaturized.

[0010] The FET according to the first aspect comprises a diamond semiconductor layer, a gate insulating film disposed on the diamond semiconductor layer, and a gate electrode disposed on the gate insulating film and having a width narrower than that of the gate insulating film, and the width of the gate electrode is less than 100 nm.

[0011] An electric device according to a second aspect includes the FET according to the first aspect.

[0012] The manufacturing method of the FET according to the third aspect comprises the steps of forming a metal layer on a diamond semiconductor layer, forming a resist having an opening on a part of the metal layer, and using the resist as a mask, wet-etching the metal layer exposed from the opening, thereby forming a source electrode and a drain electrode, using the resist as a mask, forming a gate insulating film on the diamond semiconductor layer through the opening, using the resist as a mask, forming a gate electrode on the gate insulating film through the opening whose opening has been reduced by expanding the resist, and using the resist as a mask, forming a gate electrode on the gate insulating film through the opening whose opening has been reduced.

[0013] The manufacturing method of the FET according to the third aspect of the present invention comprises the steps of forming a metal layer on a diamond semiconductor layer, forming a resist having an opening on a part of the metal layer, and wet-etching the metal layer exposed from the opening using the resist as a mask to form a source electrode and a drain electrode, expanding the resist to reduce the opening of the opening, and using the resist as a mask to form a gate electrode on the diamond semiconductor layer through the opening whose opening has been reduced.

[0014] The first to third aspects can contribute to ensuring the desired device performance even when miniaturized.

[0015] FIG. 1 is a partial cross-sectional view schematically showing an example of the configuration of a diamond FET according to the present disclosure. FIG. 2 is a partial cross-sectional view schematically showing a first modified example of the configuration of a diamond FET according to the present disclosure. FIG. 3 is a process cross-sectional view schematically showing an example of the manufacturing method of a diamond FET according to the present disclosure. FIG. 4 is a process cross-sectional view schematically showing an example of the manufacturing method of a diamond FET according to the present disclosure. FIG. 5 is a process cross-sectional view schematically showing a modified example of the manufacturing method of a diamond FET according to the present disclosure. FIG. 6 is a partial cross-sectional view schematically showing an example of the configuration of a FET according to the present disclosure.

[0016] The following description of the embodiments will be made with reference to the drawings. Note that, when reference numerals are used in this application, they are intended solely to aid understanding and are not intended to limit the present invention to the illustrated embodiments. Furthermore, the following embodiments are merely examples and do not limit the present invention.

[0017] [Form 1] The diamond FET according to form 1 will be explained using the drawings. Figure 1 is a partial cross-sectional view showing an example of the configuration of the diamond FET according to the present disclosure. Figure 2 is a partial cross-sectional view showing a first modified example of the configuration of the diamond FET according to the present disclosure. Note that form 1 will be explained using the diamond FET as an example.

[0018] The diamond FET1 is a FET (Field Effect Transistor) having a source electrode 12a, a drain electrode 12b, and a gate electrode 14a in an element region 2 on a diamond semiconductor layer 11 (a hydrogen termination portion 11a in FIG. 1) (see FIG. 1). In the diamond FET1, the source electrode 12a and the drain electrode 12b are disposed on the diamond semiconductor layer 11 with a gap therebetween, and a gate electrode 14a is disposed between the source electrode 12a and the drain electrode 12b on the diamond semiconductor layer 11 with a gap therebetween via a gate insulating film 13a. The width of the gate electrode 14a (gate length L Ｇ ) is the width L of the gate insulating film 13a ＩThe gate insulating film 13a extends outward beyond both sides of the side end faces of the gate electrode 14a. The diamond FET1 can be incorporated into electrical machinery and equipment such as semiconductor devices, power electronics devices, high frequency devices, communication equipment, sensing equipment, automobiles, power transmission and distribution equipment, devices for harsh environments, equipment for high temperature environments, equipment for radiation environments, space equipment, and nuclear reactor equipment. Note that the diamond FET1 is merely an example, and form 1 may also be applied to FETs that do not use diamond.

[0019] When the diamond FET 1 is applied to a MISFET as shown in FIG. 1, it can have the following configuration.

[0020] In the diamond FET 1 of FIG. 1, a diamond semiconductor layer 11 is formed on a diamond substrate 10, with the upper surface (for example, the (001) plane, the (111) plane, or the like) being a hydrogen termination 11a. In FIG. 1, the hydrogen termination 11a is configured to be present in the device region 2, but not outside the device region 2. A source electrode 12a and a drain electrode 12b are disposed on the hydrogen termination 11a, spaced apart from each other and in ohmic contact with the hydrogen termination 11a. A gate electrode 14a is disposed between the source electrode 12a and the drain electrode 12b on the hydrogen termination 11a. The gate electrode 14a is disposed at intervals from each of the source electrode 12a and the drain electrode 12b. The gate electrode 14a is disposed on the hydrogen termination 11a via a gate insulating film 13a. The width (gate length L Ｇ ) is the width L of the gate insulating film 13a Ｉ The gate insulating film 13a extends outward from both sides of the sidewall surfaces of the gate electrode 14a.

[0021] The diamond substrate 10 is a substrate made of a diamond single crystal (see FIG. 1). The diamond substrate 10 may also be a substrate made of diamond polycrystal. For example, a high-temperature, high-pressure synthetic diamond single crystal substrate can be used as the diamond substrate 10. It is preferable to use a diamond substrate 10 with a surface roughness (in accordance with ISO 4287) of 10 nm or less. If the surface roughness of the diamond substrate 10 exceeds 10 nm, it is preferable to polish the diamond substrate 10 so that the surface roughness is 10 nm or less. This has the advantage of reducing the surface roughness of the diamond semiconductor layer 11 synthesized on the diamond substrate 10 and improving the contact between the diamond semiconductor layer 11 and metals or insulating films.

[0022] The diamond semiconductor layer 11 is a layer that includes diamond and has a portion that functions as a semiconductor (see FIG. 1). The thickness of the diamond semiconductor layer 11 can be, for example, several μm or several tens of μm, but is not limited thereto. The diamond semiconductor layer 11 can be formed, for example, by chemical vapor deposition of diamond crystals (epitaxial diamond crystals) on the diamond substrate 10 using hydrogen and methane gas as raw materials using a microwave plasma CVD apparatus. The diamond semiconductor layer 11 thus formed has a hydrogen termination portion 11a on the (001) plane (upper surface). The hydrogen termination portion 11a has a hole channel formed therein and exhibits p-type conduction. By subjecting the region of the hydrogen termination portion 11a other than the element region 2 to ozone treatment to remove hydrogen, it is possible to configure the hydrogen termination portion 11a to be present in the element region 2, but not to be present in the region other than the element region 2. In addition, the diamond semiconductor layer 11 is not limited to the one that has hydrogen termination portion 11a, but may have the part that contains (is doped, is injected into) impurities (for example, boron, phosphorus, etc.) in diamond.In addition, instead of having the diamond semiconductor layer 11 on the diamond substrate 10, for example, it may be the diamond freestanding film that is obtained by using a microwave plasma CVD device, using hydrogen and methane gas as raw material, growing diamond crystal on a seed substrate through chemical vapor deposition, and then removing this seed substrate.

[0023] The source electrode 12a and the drain electrode 12b are electrodes made of a predetermined metal (see FIG. 1). For example, Au can be used for the source electrode 12a and the drain electrode 12b. The source electrode 12a and the drain electrode 12b are formed on the diamond semiconductor layer 11. In order to ensure adhesion with the diamond semiconductor layer 11, the source electrode 12a and the drain electrode 12b are preferably formed on the diamond semiconductor layer 11 in a state that has not been exposed to an etching agent, a resist stripper, or oxygen plasma for resist ashing. The source electrode 12a and the drain electrode 12b are arranged so as to be in direct contact (ohmic contact) with the hydrogen termination portion 11a of the diamond semiconductor layer 11. The source electrode 12a and the drain electrode 12b can be formed, for example, by forming a metal layer on the diamond semiconductor layer 11 (for example, by vapor deposition or sputtering), forming a resist for forming the source electrode / drain electrode on the metal layer, performing wet etching using the resist as a mask, and then removing the resist.

[0024] The source-drain distance, which is the distance between the source electrode 12a and the drain electrode 12b, can be less than 200 nm, and is preferably less than 100 nm when considering operation in a high frequency band (for example, a cutoff frequency of 50 to 100 GHz). The lower limit of the source-drain distance is the limit distance at which the device functions as an FET. The source-drain distance can be changed depending on the wet etching time.

[0025] The thickness of each of the source electrode 12 a and the drain electrode 12 b is preferably less than 100 nm in consideration of operation in a high frequency band, preferably less than 50 nm in consideration of obtaining desired RF (Radio Frequency) characteristics, and preferably less than 25 nm in consideration of operation in an even higher frequency band (for example, a cutoff frequency of more than 100 GHz). The lower limit of the thickness of the source electrode 12 a and the drain electrode 12 b is the critical film thickness (the same applies to other thicknesses for which no lower limit is specified).

[0026] The source electrode 12a and the drain electrode 12b may be in direct contact with the hydrogen termination portion 11a of the diamond semiconductor layer 11 as shown in Fig. 1, or may be disposed on the hydrogen termination portion 11a via contact layers 15a, 15b as shown in Fig. 2. For example, P-type B (boron) doped diamond or the like may be used for the contact layers 15a, 15b. For example, P+ diamond doped with B (boron) or the like may be used for the contact layers 15a, 15b. For example, the contact layers 15a, 15b may be formed on the diamond semiconductor layer 11 by hot filament CVD, microwave plasma CVD, or the like. In the case of B-doped diamond, for example, B may be doped at 5 x 10 １９ ~1 x 10 ２２ / cm ３ The thickness of the contact layers 15a and 15b can be set to, for example, 20 to 300 nm.

[0027] Here, as a method for improving high frequency performance, ＳＤ Reducing the distance between the source electrode 12a and the drain electrode 12b and thinning the source electrode 12a and the drain electrode 12b are also effective methods. When wet etching the metal layer (corresponding to 12 in FIG. 3B) for the source electrode 12a and the drain electrode 12b, the metal layer 12 is actually side-etched, resulting in L ＳＤ This effect naturally becomes greater as the thickness of the metal layer 12 increases. ＳＤ For a FET that operates in a high frequency region such as a cutoff frequency of 100 GHz, L ＳＤ In this case, by making the thickness of the source electrode 12a and the drain electrode 12b less than 100 nm, desired characteristics (for example, RF characteristics) can be easily obtained. ＳＤ It has been experimentally confirmed that making the thickness less than 50 nm is effective for fabricating elements for higher frequencies. Ｔ is generally expressed as the transconductance (g ｍ ) and the actually observed g ｍ Is LＧ However, as miniaturization progresses, the intrinsic transconductance becomes smaller. ｍ０ When the source-gate resistance R Ｓ According to the relationship (Equation 1 below), R Ｓ Therefore, in order to manufacture high-performance transistors that operate in the high-frequency range, the influence of R Ｓ It is important to keep the L ＳＤ In order to prevent an increase in the thickness, it is desirable to make the thickness of the source electrode 12a and the drain electrode 12b less than 50 nm.

[0028] [Formula 1]

[0029] The gate insulating film 13a is made of, for example, Al ２ O ３ , SiO ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , CaF ２ , LaF ３ , and MgF ２ In order to improve the carrier mobility (60 to 3800 cm / Vs), an insulating film having a single layer structure or a laminated structure of any combination of the above can be used. ２ , LaF ３ , MgF ２ The use of an insulating film having a single layer structure of any of the above or a laminated structure of any combination thereof may be useful depending on the application of the device utilizing the present invention. The thickness of the gate insulating film 13a may be, for example, 1 nm to 100 nm. If it is thinner than 1 nm, sufficient insulating performance cannot be obtained. The thickness of the gate insulating film 13a is preferably less than 50 nm. The width L of the gate insulating film 13a Ｉ is, for example, the width of the gate electrode 14a (gate length L Ｇ ) and can be 50 to 100 nm.

[0030] The end surface (sidewall surface) of the gate insulating film 13a is at least partially a deposition end surface on which a material (insulating material) is deposited without molding (molding by openings in the resist). The end surface of the gate insulating film 13a may have, on its upper portion, a molded end surface molded by openings in the resist. The end surface of the gate insulating film 13a may be entirely a deposition end surface. The end surface of the gate insulating film 13a is an unetched end surface. The end surface of the gate insulating film 13a is not an end surface molded by openings in the resist.

[0031] The gate electrode 14a may be a metal film having a single layer structure of any of Al, Au, Ti, Mo, Cr, Ru, Cu, Pb, Zn, and Pt, or a laminated structure of any combination thereof. The thickness of the gate electrode 14a may be 10 nm to 500 nm, and the gate length L Ｇ The resist for forming the gate electrode also serves as a resist for forming the source electrode / drain electrode, and after the source electrode 12a and the drain electrode 12b are formed using this resist, the gate insulating film 13a and the gate electrode 14a can be formed by a self-alignment method using this resist. Ｇ is the width L of the gate insulating film 13a ＩSince it is shorter than, when forming gate electrode 14a and when forming gate insulating film 13a, the size of the opening of the resist for forming gate electrode is changed.For example, gate electrode 14a can be formed by using a resist having an opening for forming gate electrode as a mask on diamond semiconductor layer 11, by CVD method using a predetermined raw material gas, forming an insulating layer for gate insulating film 13a through this opening, then heating to a predetermined temperature to thermally expand the resist for forming gate electrode, making the opening of this resist smaller, and forming a metal film for gate electrode 14a through this reduced opening (for example, evaporation, sputtering, CVD, etc.), and then lifting off the resist and the insulating layer and metal layer thereon.In addition, the method for changing the size of the opening of the resist for forming gate electrode can utilize the thermal expansion of the material of the resist, and not only can change the size of the opening by changing from a non-heated state to a heated state, but also can change the size of the opening by changing from a cooled state to a non-cooled state.

[0032] The end face (side wall face) of the gate electrode 14a may have a deposition end face at the bottom where a metal material is deposited without molding (molding by openings in the resist) and a molded end face at the top where a molded end face is molded by openings in the resist. The end face of the gate electrode 14a may be a deposition end face entirely. The end face of the gate electrode 14a is an unetched end face.

[0033] Width of the gate electrode 14a (gate length) L Ｇ is preferably less than 100 nm in order to improve frequency characteristics (shorten the transit time of carriers traveling through the channel), and is preferably less than 60 nm in consideration of operation in a higher frequency band (for example, a cutoff frequency of more than 100 GHz), and is preferably less than 50 nm in consideration of obtaining desired RF (Radio Frequency) characteristics. Ｇ The lower limit of is the limit length at which the element functions as an FET.

[0034] Width L of the gate insulating film 13a Ｉ The width (gate length) of the gate electrode 14a Ｇ Fraction of (LＧ / L Ｉ ) is preferably 0.2 to 0.8, more preferably 0.4 to 0.7, in consideration of high frequency characteristics and yield. Ｇ and the source-drain distance L ＳＤ On the other hand, if the ratio exceeds 0.8, the device characteristics deteriorate due to an increase in surface leakage current and a decrease in insulation, leading to a decrease in yield.

[0035] Gate length L Ｇ As miniaturization progresses, the contact between the gate electrode 14a and the diamond semiconductor layer 11 via the gate insulating film 13a decreases, and resistance components are likely to be generated or the element is likely to be destroyed by fracture. Ｇ When the thickness of the gate insulating film 13a is less than 100 nm, it is desirable to cover the gate electrode 14a including the gate insulating film 13a with a passivation film (not shown). The passivation film can be made of the same insulating material as the gate insulating film 13a, for example, Al. ２ O ３ , SiO ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , CaF ２ , LaF ３ , and MgF ２ In consideration of the improvement of carrier mobility and processability, an insulating film having a single layer structure or a laminated structure of any combination thereof can be used. Insulating materials containing F (fluorine), such as CaF ２ , LaF ３ , MgF ２The thickness of the passivation film is preferably 100 nm or more, in consideration of ensuring the contact between the gate electrode 14a and the diamond semiconductor layer 11 via the gate insulating film 13a, and the contact between the source electrode 12a and the drain electrode 12b and the diamond semiconductor layer 11, and is preferably 300 nm or more, in consideration of the flatness or flat processability of the upper surface of the passivation film 15.

[0036] Next, a method for manufacturing a diamond FET according to embodiment 1 will be described with reference to the drawings. Figures 3 to 5 are cross-sectional views illustrating steps in an example of a method for manufacturing a diamond FET according to the present disclosure.

[0037] First, a diamond semiconductor layer 11 is formed on a diamond substrate 10 (see Fig. 3(A)). The diamond semiconductor layer 11 can be formed by chemical vapor deposition of diamond crystal on the diamond substrate 10 using, for example, a microwave plasma CVD device, with hydrogen and methane gas without added impurities as raw materials (volume ratio of methane to hydrogen is 0.5%). The diamond semiconductor layer 11 thus formed is hydrogen-terminated diamond with hydrogen-terminated part 11a on the (001) plane (upper surface).

[0038] Next, the metal layer 12 is formed on the diamond semiconductor layer 11 (see FIG. 3(B)). The metal layer 12 can be formed by depositing a predetermined metal (for example, gold) on the diamond semiconductor layer 11 by, for example, RF sputtering.

[0039] Next, a resist 20 is formed to cover the element region 2 on the metal layer 12, and the metal layer 12 is etched using the resist 20 as a mask until the diamond semiconductor layer 11 is exposed (see FIG. 3(C)). The resist 20 can be formed by, for example, lithography. For example, an EB (electron beam) resist can be used as the resist 20. The metal layer 12 can be etched using, for example, a wet etching agent.

[0040] Next, using the resist 20 as a mask, ozone treatment is performed to selectively eliminate the hydrogen termination 11a in the region other than the element region 2 in the diamond semiconductor layer 11 (see FIG. 3(D)). As a result, the region other than the element region 2 in the diamond semiconductor layer 11 (the region that has become the oxygen termination) becomes highly resistive, and the elements can be electrically insulated from each other.

[0041] Next, the resist (20 in FIG. 3D) on the metal layer 12 is removed (see FIG. 4A). The resist 20 can be removed, for example, with a resist remover or by ashing. After the resist 20 is removed, cleaning is performed.

[0042] Next, a resist 21 having openings 21a for forming a gate electrode and a source electrode / drain electrode is formed on the diamond semiconductor layer 11 including the metal layer 12 (see FIG. 4(B)). The resist 21 can be formed by, for example, lithography. For example, an EB resist can be used for the resist 21, and a PMMA (Polymethylmethacrylate)-based resist can be used, but is not limited to this. The resist 21 may have a structure in which multiple resists are stacked, or may have a structure in which a sacrificial layer or a hard mask is sandwiched between them. The thickness of the resist 21 can be, for example, 300 to 1000 nm, and is preferably 100 nm or more.

[0043] Next, using the resist 21 as a mask, the metal layer (12 in FIG. 4B) exposed from the opening 21a is etched, and the metal layer 12 is separated into the source electrode 12a and the drain electrode 12b by under-etching, and then the distance between the end faces of the source electrode 12a and the drain electrode 12b is made wider than the width of the opening 21a by side-etching (see FIG. 4C). The etching of the metal layer 12 can be performed using, for example, a wet etching agent.

[0044] Next, the insulating layer 13 and the gate insulating film 13a are formed on the diamond semiconductor layer 11 including the resist 21 (see FIG. 5(A)). The insulating layer 13 and the gate insulating film 13a can be formed by, for example, the CVD method using a predetermined raw material gas. The gate insulating film 13a is formed on the diamond semiconductor layer 11 through the opening 21a of the resist 21 by the CVD method.

[0045] Next, the resist 21 is heated to a predetermined temperature (e.g., 50 to 100°C) to expand it, thereby reducing the opening (21a in FIG. 5A) to form a smaller opening 21b (see FIG. 5B). Heating can be performed using a resistance heating evaporation device. The size of the opening 21b can be controlled by temperature depending on the combination of the material of the resist 21 and its size at room temperature. For example, an opening 70 nm wide at room temperature (corresponding to 21a in FIG. 5A) can be made into an opening 21b with a width of 50 nm by raising the temperature to 100°C.

[0046] Next, a metal layer 14 and a gate electrode 14a are formed on the insulating layer 13 and the gate insulating film 13a (see FIG. 5C). The metal layer 14 and the gate electrode 14a can be formed by, for example, a vapor deposition method using a resistance heating vapor deposition apparatus. The gate electrode 14a is formed on the gate insulating film 13a through the opening 21b, which has a smaller opening, by the vapor deposition method.

[0047] Next, the resist (21 in FIG. 5C), as well as the insulating layer (13 in FIG. 5C) and the metal layer (14 in FIG. 5C) thereon are removed (see FIG. 1). The resist 21, as well as the insulating layer 13 and the metal layer 14 thereon, can be removed by lifting them off using, for example, a resist remover. After removing the resist 21, cleaning is performed. Thereafter, depending on the size of the diamond FET 1, a passivation film (not shown) is formed, holes are drilled in the passivation film to form plugs or pads, and a multilayer wiring structure is formed as necessary.

[0048] According to the first embodiment, the gate insulating film 13a and the gate electrode 14a can be formed so as to be controlled in the gate length direction and the gate thickness direction, which contributes to ensuring the desired element performance even when miniaturized.

[0049] According to the first aspect, a structure can be formed with high precision that ensures insulation of the gate insulating film 13a from the gate electrode 14a, so that both high voltage resistance and high frequency performance can be achieved.

[0050] In order to realize a high-performance FET that operates in the millimeter wave band, not only the gate length must be reduced but also the source-gate resistance R Ｓ The reduction of the source-gate distance L by the self-alignment method is a major issue. ＳＧ To improve the frequency characteristics, it is necessary to reduce the gate length L Ｇ The main factor is the miniaturization of the gate length L Ｇ By miniaturizing the transconductance g ｍ As the value of the source-gate distance L increases, ＳＧ However, it is very difficult to align the resist for forming the gate electrode and the resist for forming the source and drain electrodes on the order of nm, and it is even more difficult to reduce the source-gate distance L ＳＧ On the other hand, according to the self-alignment method as in the first embodiment, the resist 21 used for forming the source electrode 12a and the drain electrode 12b can be directly used for forming the gate electrode 14a, so that the resist overlapping process is unnecessary, and it is easy to form a fine structure, and the source-gate distance L ＳＧ Since the source-gate resistance R ｓ It is easy to reduce.

[0051] Furthermore, in the self-alignment method, if the gate insulating film and gate electrode are deposited successively through the same resist opening, their lengths are the same, limiting yield and insulating performance. In other words, when attempting to form extremely fine structures, the mask accuracy during deposition becomes insufficient, and pressure is applied to the gate electrode during electrode contact, causing the gate electrode to shift laterally or be pushed out, resulting in a deterioration in insulating properties. The smaller the structure, the more likely this deterioration in insulating properties occurs. On the other hand, by using a technique for processing the width of the gate electrode 14a smaller than the width of the gate insulating film 13a, as in Example 1, it is possible to improve yield and fabricate practical devices.

[0052] The insulating performance of the surface differs from that of the bulk, and can sometimes be degraded by surface leakage currents due to factors such as surface leakage currents generated through low-quality portions of the surface during insulating film formation and leakage currents due to contamination on the insulating film surface. Therefore, to improve device reliability, a method for controlling the surface area of ​​the gate insulating film not covered by the gate electrode is required. Diamond FETs using hydrogen-terminated diamond tend to avoid high-temperature processes to protect the conductive film, so the insulating film deposition process can also be performed at relatively low temperatures. This inherently reduces insulating performance. These issues have led to hesitation in designing devices with MISFET structures and the use of metals for Schottky contacts in the gate electrode, limiting the freedom of device design. This is one of the hidden challenges for the practical application of diamond FETs, even though it is not directly visible. In this regard, according to the first aspect, MISFETs with structures that were previously impossible can be realized using a self-alignment method.

[0053] [Embodiment 2] A diamond FET according to embodiment 2 will be described with reference to the drawings. Fig. 6 is a process cross-sectional view schematically showing a modified example of the method for manufacturing a diamond FET according to the present disclosure.

[0054] The second embodiment is a modification of the first embodiment, in which the method for manufacturing a MISFET-type diamond FET according to the first embodiment is applied to a method for manufacturing a MESFET (Metal Semiconductor Field Effect Transistor)-type diamond FET.

[0055] After the source electrode 12a and the drain electrode 12b are formed by the steps shown in FIGS. 3A to 4C, the insulating layer (13 in FIG. 5A) and the gate insulating film (13a in FIG. 5A) are not formed, and the resist 21 is expanded by heating to a predetermined temperature (for example, 50 to 100° C.), thereby reducing the opening (21a in FIG. 5A) to form an opening 21b (see FIG. 6A).

[0056] Next, a metal layer 14 and a gate electrode 14a are formed on the diamond semiconductor layer 11 including the resist 21 (see FIG. 6(B)). The metal layer 14 and the gate electrode 14a can be formed by, for example, a vapor deposition method using a resistance heating vapor deposition device. The gate electrode 14a is formed on the diamond semiconductor layer 11 by the vapor deposition method through the opening 21b whose opening has been reduced.

[0057] Next, the resist (21 in FIG. 6(B)) and the metal layer thereon (14 in FIG. 6(B)) are removed (see FIG. 6(C)). The resist 21 and the metal layer thereon 14 can be removed by lifting off using a resist remover, for example. After removing the resist 21, cleaning is performed. This completes a MESFET-type diamond FET with a miniaturized gate length.

[0058] The other configurations are the same as those of the first embodiment.

[0059] According to the second embodiment, it is possible to form the gate electrode 14a that is controlled in the gate length direction and gate thickness direction, so that it can contribute to ensuring the desired device performance even when miniaturized.In particular, it is useful for forming the device that has a gate length of less than 50 nm, which is required in the ultra-high frequency region.In other words, in the current diamond semiconductor manufacturing technology, it is not possible to realize a gate length of less than 50 nm, which is the limit of exposure technology and deposition technology, but according to the second embodiment, it is possible to control beyond the limit of exposure technology and deposition technology, and it has been confirmed that it is possible to actually form the gate electrode 14a with a gate length of 40 nm.

[0060] [Mode 3] A FET according to Mode 3 will be described with reference to the drawings. Fig. 7 is a partial cross-sectional view schematically showing an example of the configuration of a FET according to the present disclosure.

[0061] The FET 30 includes a diamond semiconductor layer 31, a gate insulating film 32, and a gate electrode 33. The gate insulating film 32 is disposed on the diamond semiconductor layer 31. The gate electrode 33 is disposed on the gate insulating film 32. The gate electrode 33 has a width L Ｉ Narrower width than L Ｇ The width of the gate electrode 33 is less than 100 nm.

[0062] According to the third aspect, the gate electrode 33 can be prevented from protruding from the edge of the gate insulating film 32, which contributes to ensuring the desired device performance even when miniaturized.

[0063] Some or all of the above embodiments may be described as, but are not limited to, the following supplementary notes.

[0064] [Appendix 1] A FET comprising: a diamond semiconductor layer; a gate insulating film disposed on the diamond semiconductor layer; and a gate electrode disposed on the gate insulating film and having a width narrower than that of the gate insulating film, wherein the width of the gate electrode is less than 100 nm. [Appendix 2] The FET according to Appendices 1, wherein an end face of the gate insulating film at least partially has a deposition end face on which an insulating material is deposited. [Appendix 3] The FET according to Appendices 1 or 2, wherein the end face of the gate electrode at least partially has a deposition end face on which a metal material is deposited without molding. [Appendix 4] The FET according to any one of Appendices 1 to 3, wherein the ratio of the width of the gate electrode to the width of the gate insulating film is 0.2 to 0.8. [Appendix 5] The FET according to any one of Appendices 1 to 4, wherein the thickness of the gate insulating film is 1 nm to 100 nm. [Appendix 6] The FET according to any one of Appendices 1 to 5, wherein the thickness of the gate electrode is 10 nm to 500 nm. [Appendix 7] A FET according to any one of Appendices 1 to 6, wherein the width of the gate insulating film is wider than the width of the gate electrode and is 50 to 100 nm. [Appendix 8] A FET according to any one of Appendices 1 to 7, comprising a source electrode and a drain electrode disposed on the diamond semiconductor layer and disposed on both outer sides of the gate insulating film and the gate electrode with a gap therebetween. [Appendix 9] A FET according to Appendices 8, wherein the thickness of each of the source electrode and the drain electrode is less than 100 nm. [Appendix 10] A FET according to Appendices 8 or 9, wherein the distance between the source electrode and the drain electrode is less than 200 nm. [Appendix 11] A FET according to any one of Appendices 8 to 10, wherein each end face of the source electrode and the drain electrode is a surface formed by wet etching. [Appendix 12] The gate insulating film is made of Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３, LaF ３ , and MgF ２ a step of forming a gate insulating film on the diamond semiconductor layer through the opening by using the resist as a mask, a step of expanding the resist to reduce the size of the opening, and a step of forming a gate electrode on the gate insulating film through the reduced opening by using the resist as a mask. [Appendix 15] A method for manufacturing a FET, comprising the steps of: forming a metal layer on a diamond semiconductor layer; forming a resist having an opening in a part of the metal layer, and wet-etching the metal layer exposed from the opening using the resist as a mask, thereby forming a source electrode and a drain electrode; expanding the resist to reduce the size of the opening; and using the resist as a mask, forming a gate electrode on the diamond semiconductor layer through the reduced opening.

[0065] The disclosures of the above-mentioned patent and non-patent documents are incorporated herein by reference and may be used as the basis or part of the present invention, as necessary. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure of the present invention (including the claims and drawings), and further based on the basic technical concepts thereof. Furthermore, various combinations and selections (or non-selections, as necessary) of the various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible within the scope of the entire disclosure of the present invention. In other words, the present invention naturally includes various modifications and alterations that would be possible by a person skilled in the art in accordance with the entire disclosure and technical concepts, including the claims and drawings. Furthermore, with regard to the numerical values ​​and numerical ranges described in this application, any intermediate values, lower values, and smaller ranges are deemed to be included, even if not explicitly stated. Furthermore, the disclosures of the above-cited documents, when used in part or in whole in combination with the disclosures herein as part of the disclosure of the present invention, are also deemed to be included in (belong to) the disclosures of this application, in accordance with the spirit of the present invention.

[0066] REFERENCE SIGNS LIST 1 Diamond FET (FET) 2 Element region 10 Diamond substrate 11 Diamond semiconductor layer 11a Hydrogen termination 12 Metal layer 12a Source electrode 12b Drain electrode 13 Insulating layer 13a Gate insulating film 14 Metal layer 14a Gate electrode 15a, 15b Contact layer 20, 21 Resist 21a Opening 21b Opening 30 FET 31 Diamond semiconductor layer 32 Gate insulating film 33 Gate electrode

Claims

1. A FET comprising: a diamond semiconductor layer; a gate insulating film disposed on the diamond semiconductor layer; and a gate electrode disposed on the gate insulating film and having a width narrower than that of the gate insulating film, wherein the width of the gate electrode is less than 100 nm.

2. The FET according to claim 1, wherein an end surface of the gate insulating film at least partially has a deposition end surface on which an insulating material is deposited.

3. The FET according to claim 1 or 2, wherein an end face of the gate electrode at least partially has a deposition end face on which a metal material is deposited.

4. The FET according to claim 1, wherein the ratio of the width of said gate electrode to the width of said gate insulating film is 0.2 to 0.

8.

5. The FET according to any one of claims 1 to 4, wherein the gate insulating film has a thickness of 1 nm to 100 nm.

6. The FET according to any one of claims 1 to 5, wherein the thickness of the gate electrode is 10 nm to 500 nm.

7. The FET according to claim 1, wherein the width of said gate insulating film is wider than the width of said gate electrode and is in the range of 50 to 100 nm.

8. The FET according to any one of claims 1 to 7, further comprising a source electrode and a drain electrode disposed on said diamond semiconductor layer and spaced apart from each other on both outer sides of said gate insulating film and said gate electrode.

9. The FET of claim 8, wherein the source electrode and the drain electrode each have a thickness less than 100 nm.

10. The FET according to claim 8 or 9, wherein the distance between the source electrode and the drain electrode is less than 200 nm.

11. The FET according to any one of claims 8 to 10, wherein end faces of the source electrode and the drain electrode are surfaces formed by wet etching.

12. The gate insulating film is made of Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , LaF ３ , and MgF ２ 12. The FET according to claim 1, which has a single layer structure of any one of the above or a laminate structure of any combination thereof.

13. An electrical device comprising a FET according to any one of claims 1 to 12.

14. A method for manufacturing a FET, comprising the steps of: forming a metal layer on a diamond semiconductor layer; forming a resist having an opening in a portion of the metal layer, and using the resist as a mask to wet-etch the metal layer exposed from the opening, thereby forming a source electrode and a drain electrode; forming a gate insulating film on the diamond semiconductor layer through the opening, using the resist as a mask; expanding the resist to reduce the size of the opening; and forming a gate electrode on the gate insulating film through the reduced opening, using the resist as a mask.

15. A method for manufacturing a FET, comprising the steps of: forming a metal layer on a diamond semiconductor layer; forming a resist having an opening on a portion of the metal layer, and wet-etching the metal layer exposed from the opening using the resist as a mask to form a source electrode and a drain electrode; expanding the resist to reduce the size of the opening; and using the resist as a mask to form a gate electrode on the diamond semiconductor layer through the reduced opening.

Images