Inverter circuit, chip, and electronic device

Abstract

Disclosed are an inverter circuit, a chip, and an electronic device, relating to the technical field of electronic devices. An inverter circuit (400) comprises a voltage boost circuit (401), an inverter (402), and a reference voltage generation circuit (404). An input terminal of the voltage boost circuit (401) is used for coupling a power supply. A first input terminal of the inverter (402) is coupled to an output terminal of the voltage boost circuit (401), and an output terminal of the inverter (402) is used for coupling a load. An input terminal of the reference voltage generation circuit (404) is coupled to the output terminal of the voltage boost circuit (401), and an output terminal of the reference voltage generation circuit (404) is coupled to a second input terminal of the inverter (402). The reference voltage generation circuit (404) is used for receiving a voltage signal (Uboost) output by the output terminal of the voltage boost circuit (401). The reference voltage generation circuit (404) is further used for sampling the voltage signal (Uboost), and generating a reference voltage (Uref) and outputting same to the second input terminal of the inverter (402), wherein the reference voltage (Uref) comprises a voltage generated on the basis of a minimum sampling voltage. The solution can acquire high-fidelity high-voltage sinusoidal driving signals by means of the inverter circuit.

Description

Inverter circuits, chips and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on August 7, 2023, with application number 202310993565.3 and application name “Inverter Circuit, Chip and Electronic Device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of electronic equipment, and in particular to inverter circuits, chips and electronic equipment. Background Art

[0003] As electronic devices such as mobile phones, smart wearable products, and personal computers (PCs) gradually develop towards being lighter and smaller, higher requirements are placed on the performance and volume of the heat dissipation modules of electronic devices. Since liquid cooling has a better heat dissipation effect, liquid cooling can usually be used to dissipate heat from electronic devices. The liquid cooling module may include: a pump and a working fluid. The working substance can be understood as a carrier that realizes the mutual conversion of thermal energy and mechanical energy. The pump can serve as a power source for the working fluid and provide power for the flow of the working fluid. During the flow process, the working fluid can serve as a carrier for heat transfer, so that the liquid cooling module can achieve the effect of heat dissipation.

[0004] A typical liquid cooling module uses a piezoelectric liquid pump as the power source of the working fluid. However, the piezoelectric liquid pump requires a high-voltage sinusoidal drive. Therefore, how to obtain a high-fidelity high-voltage sinusoidal drive signal becomes a problem that needs to be solved.

[0005] Summary of the Invention

[0006] The present application discloses an inverter circuit, a chip, and an electronic device, which can obtain a high-fidelity high-voltage sinusoidal drive signal through the inverter circuit.

[0007] In a first aspect, an inverter circuit is provided. The inverter circuit includes: a boost circuit, an inverter, and a reference voltage generation circuit; the input end of the boost circuit is coupled to a power supply; the first input end of the inverter is coupled to the output end of the boost circuit, and the output end of the inverter is coupled to a load; the input end of the reference voltage generation circuit is coupled to the output end of the boost circuit, and the output end of the reference voltage generation circuit is coupled to the second input end of the inverter; the reference voltage generation circuit is configured to receive a voltage signal output from the output end of the boost circuit, and the reference voltage generation circuit is further configured to sample the voltage signal and generate a reference voltage to output to the second input end of the inverter, wherein the reference voltage is a voltage generated based on a minimum sampled voltage of the voltage signal. Since the input end of the boost circuit is used to couple the power supply; the first input end of the inverter is coupled to the output end of the boost circuit, the DC voltage Uin of the power supply input can be boosted by the boost circuit to obtain a voltage signal Uboost (a steamed bun wave with a DC bias voltage Uoffset), and the voltage signal Uboost is output to the inverter, thereby achieving an amplitude of the inverter output voltage Uo greater than the input DC voltage Uin; in addition, the reference voltage generation circuit can sample the voltage signal Uboost and output the generated reference voltage Uref to the inverter. Since the reference voltage Uref is a voltage generated according to the minimum sampling voltage of the voltage signal Uboost, the lowest point of Uboost can be used as the reference voltage Uref (corresponding to the minimum sampling voltage, that is, the DC bias voltage Uoffset of the steamed bun wave Uboost). When the reference voltage Uref is used as the reference ground of the H-bridge inverter to flip Uboost, the DC bias voltage Uoffset carried by Uboost can be eliminated, and a faithful high-voltage sinusoidal drive signal, namely Uo, can be obtained. In addition, since the inverter circuit does not involve a filter circuit, it occupies a smaller volume or area, which is more conducive to the miniaturization of the equipment.

[0008] In one possible implementation, the reference voltage generation circuit includes: a voltage tracking circuit coupled between an input terminal and an output terminal of the reference voltage generation circuit; the voltage tracking circuit includes: an analog-to-digital converter, a first memory, a second memory, a comparator, an AND gate circuit, and a digital-to-analog converter; the analog-to-digital converter is coupled between the input terminal of the reference voltage generation circuit and the first memory, the first memory is coupled to the first input terminal of the comparator and the first input terminal of the AND gate circuit; the second memory is coupled to the output terminal of the AND gate circuit, the digital-to-analog converter, and the second input terminal of the comparator; the output terminal of the comparator is coupled to the second input terminal of the AND gate circuit; and the output terminal of the digital-to-analog converter is coupled to the output terminal of the reference voltage generation circuit.

[0009] In one possible implementation, an analog-to-digital converter is configured to convert a second sampled voltage of a voltage signal into a second digital signal; a first memory is configured to store the second digital signal; a second memory is configured to store a first digital signal, wherein the first digital signal is a digital signal corresponding to the first sampled voltage of the voltage signal; a comparator is configured to compare the first digital signal and the second digital signal to generate a comparison result; an AND gate circuit is configured to perform an AND operation on the first digital signal and the comparison result and output an operation result, wherein a first operation result is generated when the voltage corresponding to the first digital signal is greater than the voltage corresponding to the second digital signal; or a second operation result is generated when the voltage corresponding to the first digital signal is less than the voltage corresponding to the second digital signal; the second memory is configured to store the second digital signal based on the first operation result or to maintain storage of the first digital signal based on the second operation result; and a digital-to-analog converter is configured to convert the first digital signal or the second digital signal into an analog voltage, wherein the reference voltage generation circuit generates the reference voltage based on the analog voltage. In some examples, the first memory may be a first-in-first-out (FIFO) memory, and the second memory may be a register. Exemplarily, the analog-to-digital converter ADC performs analog-to-digital (AD) conversion on the sampled voltage of the voltage signal Uboost to obtain a digital signal B, which is stored in the FIFO memory; wherein the value in the register is recorded as digital signal A, and digital signal A can be a digital signal obtained by sampling the voltage signal Uboost for the first time before obtaining the digital signal B, or it can also be a default initial value set in the register based on experience; then, the register sends digital signal A to the comparator, and the FIFO memory sends digital signal B to the comparator, and the comparator compares digital signal A and digital signal B to generate a comparison result; the FIFO memory sends digital signal B to the AND gate circuit, and the comparator sends the comparison result to the AND gate circuit, and the AND gate circuit performs an AND operation on digital signal B and the comparison result, and outputs the operation result; wherein, when the voltage corresponding to digital signal A is greater than the voltage corresponding to digital signal B, a first operation result is generated; or when the voltage corresponding to digital signal A is less than the voltage corresponding to digital signal B, a second operation result is generated. The register stores digital signal B according to the first operation result, or stores digital signal A according to the second operation result. Afterwards, the digital-to-analog converter DAC converts the digital signal (A or B) stored in the register into an analog voltage; finally, the reference voltage generating circuit 404 generates a reference voltage Uref based on the analog voltage; after sampling the voltage signal Uboost for one or more cycles, the digital signal stored in the register is updated to a digital signal corresponding to the minimum sampling voltage.

[0010] In one possible implementation, the reference voltage generation circuit further includes: a selection switch; a common terminal of the selection switch coupled to the output terminal of the analog-to-digital converter; a first selection terminal of the selection switch coupled to the first memory; and a second selection terminal of the selection switch coupled to the second memory. Thus, when it is determined that the voltage signal Uboost is sampled for the first time, the common terminal of the selection switch can be controlled to be conductively connected to the second selection terminal to transmit the resulting digital signal A to the register; thereafter, the common terminal of the selection switch is conductively connected to the first selection terminal, and the generated digital signals are sequentially transmitted to the FIFO memory during subsequent voltage sampling processes.

[0011] In one possible implementation, the system further includes: a voltage sampling circuit and a voltage amplification circuit; the voltage sampling circuit is coupled between the input of the reference voltage generation circuit and the voltage tracking circuit; and the voltage amplification circuit is coupled between the voltage tracking circuit and the output of the reference voltage generation circuit; the voltage sampling circuit has a first sampling ratio, and the voltage amplification circuit has a first amplification ratio, where the product of the first amplification ratio and the first sampling ratio is 1. The voltage sampling circuit can sample the voltage signal Uboost output by the boost circuit at a sampling ratio k1. Since Uboost is sampled by the voltage sampling circuit, the sampling ratio k1 of the voltage sampling circuit causes a certain reduction in the voltage amplitude of Uboost. Therefore, the reduction caused by the voltage sampling circuit needs to be compensated by the voltage amplification circuit at a certain amplification ratio k2 in the form of gain. Therefore, the sampling ratio k1 and the amplification ratio k2 have the following relationship: k1*k2=1.

[0012] In one possible implementation, the system further includes an impedance matching circuit coupled between the voltage amplifier circuit and the output terminal of the reference voltage generation circuit. The impedance matching circuit is primarily used to match the impedance of the resistor between the voltage amplifier circuit and the impedance of the inverter to ensure impedance matching of the system lines and normal voltage transmission. In some examples, the impedance matching circuit can be implemented as a voltage follower.

[0013] In one possible implementation, a voltage sampling circuit includes: a first resistor and a second resistor; a first end of the first resistor coupled to an input end of a reference voltage generating circuit; a second end of the first resistor coupled to a first end of a second resistor, and the second end of the first resistor further coupled to a voltage tracking circuit; and a second end of the second resistor coupled to ground. The sampling ratio k1 is defined as: first resistor R1 / second resistor R2.

[0014] In a possible implementation, the amplifier circuit includes a positive feedback amplifier circuit or a negative feedback amplifier circuit.

[0015] In a possible implementation, the boost circuit includes: a boost circuit.

[0016] In a possible implementation, the inverter includes: an H-bridge inverter.

[0017] In a second aspect, a chip is provided, including a substrate and an inverter circuit arranged on the substrate, wherein the inverter circuit includes the inverter circuit provided in the first aspect and possible implementations thereof.

[0018] In a third aspect, an electronic device is provided, comprising a pump and an inverter circuit as described in the first aspect and its possible implementations; the inverter circuit is connected to the pump.

[0019] In a possible implementation, the electronic device includes a liquid cooling module, the liquid cooling module includes the pump and a cavity, and the pump is used to drive the working medium to flow in the cavity.

[0020] In a possible implementation, the cavity is provided in a housing of the electronic device.

[0021] Among them, the technical problems solved by the second to third aspects and their possible implementation methods and the technical effects achieved can be referred to the description of the first aspect and its possible implementation methods, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0023] FIG2 is a schematic diagram of a driving method of a piezoelectric liquid pump provided in an embodiment of the present application;

[0024] FIG3 is a schematic structural diagram of an inverter circuit provided in an embodiment of the present application;

[0025] FIG4 is a schematic structural diagram of an inverter circuit provided by another embodiment of the present application;

[0026] FIG5 is a waveform diagram of Uboost provided in an embodiment of the present application;

[0027] FIG6 is a schematic structural diagram of an inverter circuit provided in yet another embodiment of the present application;

[0028] FIG7 is a schematic diagram of the duty cycle of Q1 and Q2 provided in an embodiment of the present application;

[0029] FIG8 is a schematic diagram of the conduction state of Q3-Q6 provided in an embodiment of the present application;

[0030] FIG9 is a schematic diagram of the structure of a voltage tracking circuit provided in an embodiment of the present application;

[0031] FIG10 is a schematic diagram of the structure of a voltage tracking circuit provided by another embodiment of the present application;

[0032] FIG11 is a schematic structural diagram of a voltage tracking circuit provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0034] In this document, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "multiple" means two or more. In addition, in this document, directional terms such as "upper" and "lower" are defined relative to the orientation of the structure schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for description and clarification relative to each other, and they may change accordingly according to changes in the orientation of the structure.

[0035] When used to describe a three-port switch (also known as a switching device, such as a switch tube or a switching transistor), the "first end" and the "second end" may refer to the connection ends of the switch, respectively, and the "control end" may refer to the control end of the switch. For example, for a MOS (metal-oxide-semiconductor) tube, the control end may refer to the gate of the MOS tube, the first end may refer to the source of the MOS tube, and the second end may refer to the drain of the MOS tube, or the first end may refer to the drain of the MOS tube and the second end may refer to the source of the MOS tube. In the embodiments of the present application, each switch may include a switching transistor. However, in order to minimize the increase in internal resistance caused by the switches connected in series on the line, each switch may also include two or more switching transistors connected in parallel.

[0036] The technical solution in this application will be described below with reference to the accompanying drawings.

[0037] The electronic devices involved in the embodiments of the present application may include, but are not limited to: mobile phones, tablet computers, laptops, ultra-mobile personal computers (UMPCs), handheld computers, netbooks, personal digital assistants (PDAs), wearable electronic devices, virtual reality devices, and other electronic devices that require battery charging.

[0038] 1 , a schematic structural diagram of an electronic device 10 is provided. Taking a mobile phone as an example, it can be seen that the electronic device 10 includes: a housing 100 and an electronic functional component (not shown in the figure) located in the housing 100. In the embodiment of the present application, the mobile phone may be a folding device or a straight-board device. The electronic functional components of the electronic device 10 include, but are not limited to: a processor, an internal memory, a charging management module, a power management module, a battery, an antenna, a communication module, a camera, an audio module, a speaker, a receiver, a microphone, a sensor module, a motor, and an indicator, etc. Among them, the electronic device 10 may have more or fewer electronic functional components than described above. Various electronic functional components can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0039] Electronic functional components release heat when they are in working state. When the temperature inside the electronic device 10 is too high, it will affect the working efficiency of the electronic functional components and the service life of the electronic device 10. Therefore, a liquid cooling module 200 needs to be provided to control the temperature rise of the electronic functional components. Based on the above considerations, in some feasible implementations, the liquid cooling module 200 is located between the housing 100 and the electronic functional components to achieve temperature control of the electronic functional components. Exemplarily, the liquid cooling module 200 can be located on the side of the housing 100 adjacent to the electronic functional components. The liquid cooling module 200 can achieve temperature control of the electronic functional components. In some feasible implementations, the liquid cooling module 200 can also be used as part of the electronic functional component package to achieve temperature control of the electronic functional components. Exemplarily, the liquid cooling module can be packaged in the battery as part of the battery to achieve temperature control of the battery.

[0040] The structure of the liquid cooling module 200 is described as follows:

[0041] 1 , the liquid cooling module 200 may include: a cavity 201, a pump 202 and a working fluid (not shown in the figure). The working fluid is filled in the cavity 201. The pump 202 is connected to the cavity 201, and the pump 202 can serve as a power source for the working fluid in the cavity 201, providing power for the flow of the working fluid. During the flow process, the working fluid can serve as a carrier for heat transfer, taking heat away from the electronic functional components, thereby achieving temperature control of the electronic functional components. In the embodiment of the present application, the cavity 201 provides a flow track / place for the flow of the working fluid, and the cavity 201 can be set in the housing 100 of the electronic device. The embodiment of the present application does not specifically limit the type of pump 202. In some feasible implementation methods, the pump 202 can adopt a micro piezoelectric liquid pump, which has an amplitude of ≤50um, is ultra-thin, small in size, simple in structure, has high pressure and low flow, no electromagnetic interference, and low working noise. It can achieve precise fluid delivery and control, and is particularly suitable for electronic devices such as mobile phones, watches, and accessories.

[0042] Typically, piezoelectric fluid pumps require high-voltage alternating current (AC). To reduce noise generated by piezoelectric fluid pumps, high-voltage sinusoidal AC is often used. As shown in FIG2 , since the power supply 300 of the electronic device 10 typically only provides a direct current (DC) voltage of 3-5V, an inverter circuit 400 is required to convert the DC voltage output by the power supply 300 into high-voltage sinusoidal AC (as shown in FIG2 , the peak-to-peak value of the high-voltage sinusoidal AC in the example is 200Vpp) to drive the piezoelectric fluid pump 202.

[0043] 3 , a specific circuit structure of an inverter circuit 400 is provided. The inverter circuit 400 includes a boost circuit 401, an inverter 402, and a filter circuit 403. The input voltage Uin provided by the power supply is a DC voltage. A boost circuit 401 (for example, a boost circuit is used in FIG3 ) can be used to boost the input voltage Uin to obtain a first-level high-voltage DC voltage Uboost. This high-voltage DC voltage Uboost serves as the input of an inverter 402 (an H-bridge inverter is used in FIG3 ). The inverter 402 uses a sinusoidal pulse width modulation (SPWM) strategy to output an SPWM wave, which then passes through a filter circuit 403 (an LC filter circuit is used in FIG3 ) to obtain a high-voltage sinusoidal AC current to drive a load (a piezoelectric fluid pump). Specifically, as shown in FIG3 , a boost circuit 401 includes an inductor L1, a switch Q1, and a switch Q2. The first end of the inductor L1 is coupled to the positive electrode (+) of the power supply, the second end of the inductor L1 is coupled to the first end of the switch Q1, the second end of the switch Q1 is coupled to the negative electrode (-) of the power supply, and the negative electrode (-) of the power supply is coupled to ground (GND). The second end of the switch Q2 is coupled to the first end of the switch Q1. The first end of the switch Q2 serves as the output end of the boost circuit. Switches Q1 and Q2 are controlled to turn on or off at a constant switching frequency through pulse width modulation (PWM). A stable Uboost output is achieved by adjusting the duty cycle of the pulse width modulation signal. To ensure the stability of the output voltage of the boost circuit, a capacitor C1 is typically coupled between the first end of the switch Q2 and ground (GND). Inverter 402 includes an H-bridge inverter consisting of switch Q3, switch Q4, switch Q5, and switch Q6; wherein a first end of switch Q3 is coupled to the output end of boost circuit 401, a second end of switch Q3 is coupled to the first end of switch Q4, a second end of switch Q4 is coupled to ground GND, a first end of switch Q5 is coupled to the output end of boost circuit 401, a second end of switch Q5 is coupled to the first end of switch Q6, and a second end of switch Q6 is coupled to ground GND; inverter 402 adopts a sinusoidal pulse width SPWM modulation strategy to control the on-duty cycle of switches Q3, Q4, Q5, and Q6, and outputs an SPWM wave (wherein the SPWM wave is a rectangular wave) between the second end of switch Q3 and the second end of switch Q5. Filter circuit 403 includes an inductor L2, an inductor L3, a capacitor C2, and a capacitor C3. The first end of inductor L2 is coupled to the second end of switch Q3, and the second end of inductor L2 is coupled to the first end of the load. The first end of inductor L3 is coupled to the second end of switch Q5, and the second end of inductor L3 is coupled to the second end of the load. Capacitor C2 is coupled between the second end of inductor L2 and ground GND, and capacitor C3 is coupled between the second end of inductor L3 and ground GND. Thus, the filtering function of filter circuit 403 filters the SPWM wave into a high-voltage sinusoidal AC power Uo.Among them, since the inverter circuit 400 shown in Figure 3 includes a filter circuit 403, and the filter circuit 403 is mainly composed of an inductor and a capacitor, it occupies a large volume or area, which is not conducive to the miniaturization of electronic equipment; in addition, the six switches of the boost circuit and the H-bridge inverter all operate in a high-frequency switching state throughout the process, resulting in large switching losses and low efficiency.

[0044] In another example, as shown in FIG4 , a specific circuit structure of an inverter circuit 400 is provided. The inverter circuit 400 includes a boost circuit 401 and an inverter 402. Among them, the boost circuit 401 adopts the boost circuit in FIG3 , and its specific connection relationship can be referred to the description of FIG3 and will not be repeated; the inverter 402 adopts an H-bridge inverter, and its specific connection relationship can be referred to the description of FIG3 and will not be repeated. The difference from the inverter circuit shown in FIG3 is that the second ends of the switch Q4 and the switch Q6 are both coupled to the positive electrode (+) of the power supply Uin, and the capacitor C1 is coupled between the first end of the switch Q2 and the second end of the switch Q4, and the second ends of the switch Q4 and the switch Q6 are directly coupled to the two ends of the load. In this way, the input voltage Uin provided by the power supply is a DC voltage. A boost circuit 401 (for example, a boost circuit is used in FIG4 ) can be used to boost the input voltage Uin to generate a sine wave Uboost with a DC bias voltage Uoffset (see FIG5 ). This sine wave Uboost serves as the input of the inverter 402 (an H-bridge inverter is used in FIG3 ). The function of the H-bridge inverter is to flip the sine wave Uboost and convert it into a sine wave. Therefore, using Uin as the reference ground of the H-bridge inverter can approximately eliminate the DC bias of the sine wave Uboost and obtain a high-voltage sinusoidal drive signal. Compared with the solution shown in FIG3 , since the inverter circuit shown in FIG4 no longer requires a filter circuit, it occupies a smaller volume and area. In addition, since the H-bridge inverter is only used to flip the sine wave Uboost, it can reduce the switching frequency of Q3-Q6 relative to the SPWM strategy control, thereby reducing switching losses. However, it is understandable that device L1, switch Q1, and switch Q2 in a boost circuit typically have on-resistance. Therefore, the DC bias voltage Uoffset is typically not equal to Uin. In some examples, as shown in Figure 5, Uin may be greater than the DC bias voltage Uoffset. When using Uin as the reference ground for the H-bridge inverter to flip the steamed bun wave Uboost, significant distortion occurs near the zero crossing, making it impossible to generate a standard sine wave. Therefore, obtaining a high-fidelity, high-voltage sinusoidal drive signal through the inverter circuit becomes a problem that needs to be solved.

[0045] To solve the above problems, an embodiment of the present application provides an inverter circuit 400 , as shown in FIG6 , including: a boost circuit 401 , an inverter 402 , and a reference voltage generating circuit 404 .

[0046] The input end of the boost circuit 401 is used to couple with a power supply; the first input end of the inverter 402 is coupled with the output end of the boost circuit 401, and the output end of the inverter 402 is used to couple with a load; the input end of the reference voltage generating circuit 404 is coupled with the output end of the boost circuit 401, and the output end of the reference voltage generating circuit 404 is coupled with the second input end of the inverter 402; the reference voltage generating circuit 404 is used to receive a voltage signal output from the output end of the boost circuit 401, and the reference voltage generating circuit 404 is also used to sample the voltage signal to generate a reference voltage Uref and output it to the second input end of the inverter 402, wherein the reference voltage Uref includes a voltage generated based on the minimum sampling voltage.

[0047] For example, as shown in FIG6 , the boost circuit 401 can be a boost circuit. The specific structure of the boost circuit can be found in FIG3 and will not be described in detail here. The inverter 402 can be an H-bridge inverter. The specific structure can be found in FIG3 and will not be described in detail here. The difference from FIG4 is that in FIG6 , the first terminal of the reference voltage generation circuit 404 is coupled to the first terminal of the switch Q2, and the second terminal of the reference voltage generation circuit 404 is coupled to the second terminals of the switch Q4 and the switch Q6.

[0048] Thus, the boost circuit 401 is the main module that ensures that the output voltage amplitude of the inverter 402 is greater than the input DC voltage Uin. Its main function is to boost the input DC voltage Uin under the action of the controller to generate a steamed wave Uboost with a DC offset voltage (Uoffset), where the DC offset voltage is recorded as Voffset. Referring to the structure of the boost circuit 401 shown in Figure 6, the expression for the output voltage of the boost circuit 401 is:

[0049] U offset is the DC bias voltage, U m For U boost The maximum value max.

[0050] The switches Q1 and Q2 of the boost circuit 401 are alternately turned on and complementarily turned on. The relationship between the output voltage Uboost and the duty cycle D of the switch Q1 is:

[0051] The controller dynamically changes the size of Uboost by adjusting the duty cycle D. The modulation strategy (SPWM) and the output voltage Uboost of the boost circuit 401 are shown in FIG7 . Uboost is a steamed bun wave with a DC bias voltage Uoffset.

[0052] The function of the reference voltage generating circuit is to sample the voltage signal Uboost. After processing, the lowest point of Uboost is obtained as the reference voltage Uref (corresponding to the minimum sampling voltage), that is, the DC bias voltage Uoffset of the steamed bun wave. Using the reference voltage Uref as the reference ground of the H-bridge inverter to flip Uboost can eliminate the DC bias voltage Uoffset carried by Uboost and obtain a high-fidelity high-voltage sinusoidal drive signal Uo. Specifically, as shown in Figure 8, the operating frequency of the H-bridge inverter is set to the same as the frequency of Uo, Q3 and Q6 are in the same conduction state (on or off), Q4 and Q5 are in the same conduction state, and Q3 and Q4 are alternately complementary. Since the reference ground of the H-bridge inverter is the reference voltage Uref, the value of the reference voltage Uref is equal to Uoffset, so Uboost can be flipped to become a sinusoidal wave output after the DC bias voltage Uoffset is eliminated.

[0053] 9 and 10 , a specific structure of a reference voltage generation circuit 404 is provided. Reference voltage generation circuit 404 includes a voltage tracking circuit 4042 coupled between the input and output of reference voltage generation circuit 404. Voltage tracking circuit 4042 includes an analog-to-digital converter (ADC), a first memory S1, a second memory S2, a comparator OA1, an AND gate circuit &, and a digital-to-analog converter (DAC). The ADC is coupled between the input of reference voltage generation circuit 404 and the first memory S1. The first memory S1 is coupled to the first input of comparator OA1 and the first input of AND gate circuit &. The second memory S2 is coupled to the output of AND gate &, the DAC, and the second input of comparator OA1. The output of comparator OA1 is coupled to the second input of AND gate &. The output of the DAC is coupled to the output of reference voltage generation circuit 404. In some examples, the first memory S1 may be a first in first out (FIFO) memory, and the second memory S2 may be a register.

[0054] In addition, referring to Figures 9 and 10, the reference voltage generating circuit 404 further includes: a voltage sampling circuit 4041 and a voltage amplifying circuit 4043; the voltage sampling circuit 4041 is coupled between the input end of the reference voltage generating circuit 404 and the voltage tracking circuit 4042; the voltage amplifying circuit 4043 is arranged between the voltage tracking circuit 4042 and the output end of the reference voltage generating circuit 404; the voltage sampling circuit 4041 has a first sampling ratio, the voltage amplifying circuit 4043 has a first amplification ratio, and the product of the first amplification ratio and the first sampling ratio is 1.

[0055] As shown in FIG10 , the voltage sampling circuit 4041 includes: a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is coupled to the input end of the reference voltage generating circuit 404 for receiving the voltage Uboost output by the boost circuit 401. The second end of the first resistor R1 is coupled to the first end of the second resistor R2, which is also coupled to the voltage tracking circuit 4042; the second end of the second resistor R2 is coupled to the ground GND. The voltage amplifier circuit 4043 includes a positive feedback amplifier circuit or a negative feedback amplifier circuit. As shown in FIG10 , a negative feedback amplifier circuit is provided, which includes an operational amplifier OA2, the positive terminal (+) of the operational amplifier OA2 being coupled to the voltage tracking circuit 4042 via a resistor R3; the negative terminal (-) of the operational amplifier OA2 being coupled to the ground GND via a resistor R4; and the output terminal of the operational amplifier OA2 being coupled to the negative terminal (-) of the operational amplifier OA2 via a resistor R5. Since Uboost is sampled by the voltage sampling circuit 4041, the sampling ratio of the voltage sampling circuit 4041 (i.e., R1 / R2) causes a certain reduction in the voltage amplitude of Uboost. Therefore, it is necessary to use the voltage amplifier circuit 4043 to compensate for the reduction caused by the voltage sampling circuit in the form of gain at a certain amplification ratio.

[0056] 9 and 10 , the reference voltage generation circuit 404 further includes an impedance matching circuit 4044 disposed between the voltage amplifier circuit 4043 and the output of the reference voltage generation circuit 404. Impedance matching circuit 4044 is primarily used to match the impedance of the resistor between the voltage amplifier circuit 4043 and the impedance of the H-bridge inverter to ensure system line impedance matching and normal voltage transmission. In some examples, impedance matching circuit 4044 may utilize a voltage follower OA3. Voltage follower OA3 includes a positive terminal (+) and a negative terminal (-). The positive terminal (+) of the voltage follower is coupled to the output of operational amplifier OA2, and the output of the voltage follower is coupled to the negative terminal (-) of voltage follower OA3.

[0057] Based on the reference voltage generating circuit 404 shown in FIG9 and FIG10 , its functions are described in detail as follows:

[0058] First, the voltage sampling circuit 4041 samples the voltage signal Uboost output by the boost circuit 401 . For example, the sampling ratio of the voltage sampling circuit 4041 is k1 (ie, R1 / R2 = k1 ).

[0059] Then, the ADC performs analog-to-digital (AD) conversion on the sampled voltage to obtain a digital signal B, which is stored in the FIFO memory S1; wherein the value in the register S2 is recorded as the digital signal A, wherein the digital signal A can be the digital signal obtained by the first voltage sampling before the voltage signal Uboost is sampled to obtain the digital signal B, or it can also be a default initial value set in the register S2 based on experience. It should be noted that, as shown in Figure 11, the voltage tracking circuit 4042 can include: a selection switch K1; the common end of the selection switch K1 is coupled to the output end of the analog-to-digital converter ADC, the first selection end of the selection switch K1 is coupled to the first memory S1; and the second selection end of the selection switch K1 is coupled to the second memory S2. In this way, when it is determined that the voltage signal Uboost is sampled for the first time, the common end of the selection switch K1 can be controlled to be conductive with the second selection end to transmit the obtained digital signal A to the register S2; then the common end of the selection switch K1 is connected to the first selection end, and the digital signals generated in the subsequent voltage sampling process are sequentially transmitted to the FIFO memory S1.

[0060] Afterwards, register S2 sends digital signal A to comparator OA1, and FIFO memory S1 sends digital signal B to comparator OA1. Comparator OA1 compares digital signal A and digital signal B to generate a comparison result. FIFO memory S1 sends digital signal B to AND gate &, and comparator OA1 sends the comparison result to AND gate &. AND gate & performs an AND operation on digital signal B and the comparison result, outputting the operation result. When the voltage corresponding to digital signal A is greater than the voltage corresponding to digital signal B, the comparison result can be logic "1," and AND gate & performs an AND operation on digital signal B with logic "1," generating a first operation result, which includes digital signal B. Alternatively, when the voltage corresponding to digital signal A is less than the voltage corresponding to digital signal B, the comparison result can be logic "0," and AND gate & performs an AND operation on digital signal B with logic "0," generating a second operation result, which can include logic "0." Register S2 stores digital signal B based on the first operation result, or maintains storage of digital signal A based on the second operation result. Afterwards, the digital-to-analog converter DAC converts the digital signal (A or B) stored in register S2 into an analog voltage; finally, the reference voltage generation circuit 404 generates a reference voltage Uref based on the analog voltage; after sampling the voltage signal Uboost for one or more cycles, the digital signal stored in the register is updated to a digital signal corresponding to the minimum sampled voltage. The process in which the reference voltage generation circuit 404 generates the reference voltage Uref based on the analog voltage includes: the analog voltage is amplified by the voltage amplifier circuit 4043, and the amplification ratio of the voltage amplifier circuit 4043 is k2, with the following relationship: k1*k2=1; the amplified analog signal is impedance matched by the impedance matching circuit 4044 to generate the reference voltage Uref, which is output as the reference ground of the H-bridge inverter.

[0061] Optionally, an embodiment of the present application further provides a chip, comprising a substrate and an inverter circuit fabricated on the substrate.

[0062] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An inverter circuit, characterized in that: include: A boost circuit, wherein an input end of the boost circuit is used for coupling a power supply; An inverter, wherein a first input end of the inverter is coupled to an output end of the boost circuit, and an output end of the inverter is used to couple to a load; a reference voltage generating circuit, wherein an input end of the reference voltage generating circuit is coupled to an output end of the boost circuit, and an output end of the reference voltage generating circuit is coupled to a second input end of the inverter; The reference voltage generating circuit is used to receive the voltage signal output by the output end of the boost circuit; The reference voltage generating circuit is further used for sampling the voltage signal to generate a reference voltage to be output to the second input terminal of the inverter, wherein the reference voltage is a voltage generated according to a minimum sampling voltage of the voltage signal.

2. The inverter circuit according to claim 1, characterized in that: The reference voltage generating circuit comprises: a voltage tracking circuit coupled between an input terminal and an output terminal of the reference voltage generating circuit; The voltage tracking circuit comprises: an analog-to-digital converter, a first memory, a second memory, a comparator, an AND gate circuit and a digital-to-analog converter; The analog-to-digital converter is coupled between the input end of the reference voltage generating circuit and the first memory, the first memory is coupled to the first input end of the comparator and the first input end of the AND gate circuit; the second memory is coupled to the output end of the AND gate circuit, the digital-to-analog converter and the second input end of the comparator; the output end of the comparator is coupled to the second input end of the AND gate circuit; the output end of the digital-to-analog converter is coupled to the output end of the reference voltage generating circuit.

3. The inverter circuit according to claim 2, characterized in that: The analog-to-digital converter is used to convert the second sampled voltage of the voltage signal into a second digital signal; The first memory is used to store the second digital signal; The second memory is used to store a first digital signal, where the first digital signal is a digital signal corresponding to a first sampling voltage of the voltage signal; The comparator is used to compare the first digital signal and the second digital signal to generate a comparison result; The AND gate circuit is used to perform an AND operation on the first digital signal and the comparison result, and output an operation result, wherein when the voltage corresponding to the first digital signal is greater than the voltage corresponding to the second digital signal, a first operation result is generated; or when the voltage corresponding to the first digital signal is less than the voltage corresponding to the second digital signal, a second operation result is generated; The second memory is used to store the second digital signal according to the first operation result, or to keep storing the first digital signal according to the second operation result; The digital-to-analog converter is used to convert the first digital signal or the second digital signal into an analog voltage, wherein the reference voltage generating circuit generates the reference voltage according to the analog voltage.

4. The inverter circuit according to claim 3, characterized in that: The reference voltage generating circuit further includes: a selection switch; The common end of the selection switch is coupled to the output end of the analog-to-digital converter, the first selection end of the selection switch is coupled to the first memory, and the second selection end of the selection switch is coupled to the second memory.

5. The inverter circuit according to any one of claims 2 to 4, characterized in that: Also includes: Voltage sampling circuit and voltage amplifying circuit; The voltage sampling circuit is coupled between the input terminal of the reference voltage generating circuit and the voltage tracking circuit; The voltage amplifying circuit is coupled between the voltage tracking circuit and the output end of the reference voltage generating circuit; The voltage sampling circuit has a first sampling ratio, the voltage amplifying circuit has a first amplifying ratio, and the product of the first amplifying ratio and the first sampling ratio is 1.

6. The inverter circuit according to claim 5, characterized in that: Also includes: The impedance matching circuit is coupled between the voltage amplifying circuit and the output end of the reference voltage generating circuit.

7. The inverter circuit according to claim 5, characterized in that: The voltage sampling circuit comprises: a first resistor and a second resistor; The first end of the first resistor is coupled to the input end of the reference voltage generating circuit. The second end of the first resistor is coupled to the first end of the second resistor, and the second end of the first resistor is also coupled to the voltage tracking circuit; the second end of the second resistor is coupled to the ground.

8. The inverter circuit according to claim 5, characterized in that: The voltage amplifier circuit includes a positive feedback amplifier circuit or a negative feedback amplifier circuit.

9. The inverter circuit according to claim 6, characterized in that: The impedance matching circuit includes a voltage follower.

10. The inverter circuit according to any one of claims 1 to 9, characterized in that: The voltage boost circuit includes: a boost circuit.

11. The inverter circuit according to any one of claims 1 to 10, characterized in that: The inverter includes: an H-bridge inverter.

12. A chip, characterized in that: It comprises a substrate, and an inverter circuit as claimed in any one of claims 1 to 11 arranged on the substrate.

13. An electronic device, characterized in that: It comprises a pump and an inverter circuit as described in any one of claims 1 to 11; the inverter circuit is connected to the pump.

14. The electronic device according to claim 13, characterized in that: The electronic device comprises a liquid cooling module, the liquid cooling module comprises the pump and a cavity, and the pump is used to drive the working medium to flow in the cavity.

15. The electronic device according to claim 14, characterized in that: The cavity is arranged in the housing of the electronic device.

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