Storage unit, manufacturing method therefor, memory, and electronic device

Abstract

The present application provides a storage unit, a manufacturing method therefor, a memory, and an electronic device. When the Helmholtz free energy of a metal element in an introduced first doped layer is lower than the Helmholtz free energy of a metal element in a ferroelectric layer, a dielectric layer can show the ferroelectric performance by means of the introduction of the first doped layer; and when the Helmholtz free energy of a metal element in an introduced second doped layer is not lower than the Helmholtz free energy of the metal element in the ferroelectric layer, captured and accumulated electrons can be conducted by means of the introduction of the second doped layer, thereby avoiding aggregation and accumulation of electrons in the dielectric layer, preventing the dielectric layer from being broken down due to electron aggregation and accumulation, improving the reliability of the dielectric layer and even the storage unit when a ferroelectric storage unit is obtained.

Description

Storage unit, manufacturing method thereof, memory and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on August 16, 2023, with application number 202311038185.0 and application name “A storage unit, its manufacturing method, memory and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of storage technology, and in particular to a storage unit, a manufacturing method thereof, a memory, and an electronic device. Background Art

[0004] Ferroelectric memories offer advantages such as low read and write voltages, low power consumption, small device size, high read and write speeds, excellent cycling performance, strong radiation resistance, and non-volatility, making them promising candidates for building a new generation of non-volatile memories. Compared to traditional ferroelectric materials, hafnium-based ferroelectrics not only offer superior scaling properties but also overcome technical challenges and bottlenecks such as incompatibility with complementary metal oxide semiconductor (CMOS) processes, difficulties in scaling, and difficulty achieving high-density integration. Therefore, hafnium-based ferroelectric devices are expected to become the core unit of future new ferroelectric memories.

[0005] However, in the storage layer of hafnium-based ferroelectric memory, in order to enable the hafnium oxide material to exhibit ferroelectricity, oxygen vacancies can generally be introduced into the hafnium oxide. If there are a large number of oxygen vacancies, the oxygen vacancies can capture and accumulate electrons, introduce a built-in electric field, produce a pinning effect on the electric domain in a certain polarization direction, and may even cause the storage layer to be broken down, resulting in poor reliability of the hafnium-based ferroelectric memory.

[0006] Summary of the Invention

[0007] The present application provides a memory cell, a manufacturing method thereof, a memory, and an electronic device, which are used to improve the reliability and performance of a hafnium-based ferroelectric memory.

[0008] In a first aspect, embodiments of the present application provide a memory cell, which may include: a first conductive layer, a functional layer, and a dielectric layer disposed between the first conductive layer and the functional layer; the dielectric layer may include: a stacked ferroelectric layer, a first doped layer, and a second doped layer. The ferroelectric layer may be made of, but is not limited to, a hafnium oxide material. Pure hafnium oxide rarely exhibits ferroelectricity. When a first doped layer is introduced, and the Helmholtz free energy of the metal element in the first doped layer is lower than the Helmholtz free energy of the metal element in the ferroelectric layer, the metal in the first doped layer requires less energy to move, making it more likely to generate defects in the dielectric layer, thereby generating more oxygen vacancies. The oxygen vacancies can promote the hafnium oxide to exhibit ferroelectricity, thereby forming a ferroelectric layer. However, due to the deep defect energy levels of oxygen vacancies, a large number of oxygen vacancies can capture and accumulate electrons, introduce a built-in electric field, produce a pinning effect on the electric domain of a certain polarization direction, and even cause the dielectric layer to breakdown. Therefore, when a second doped layer is introduced, and the Helmholtz free energy of the metal element in the second doped layer is not lower than the Helmholtz free energy of the metal element in the ferroelectric layer, it means that the metal in the second doped layer requires higher energy to move, and fewer defects are generated in the dielectric layer with shallower defect energy levels. These shallower defects can guide the captured and accumulated electrons, preventing electron aggregation and accumulation in the dielectric layer, and thus avoiding the problem of dielectric layer breakdown caused by electron aggregation and accumulation. Therefore, by introducing a first doped layer and a second doped layer with different functions, not only can a ferroelectric layer be obtained, but the reliability of the dielectric layer and even the storage unit can also be improved.

[0009] It should be understood that the ferroelectric layer can be made of materials other than hafnium oxide, and may also include other materials with similar properties to hafnium oxide, without limitation. The hafnium oxide material characteristic refers to the fact that hafnium oxide alone is difficult to exhibit ferroelectricity, but the introduction of oxygen vacancies or a first doping layer can make hafnium oxide exhibit ferroelectricity.

[0010] For the introduced first doping layer and the second doping layer: the first doping layer can be provided with multiple layers, and a ferroelectric layer is provided between two adjacent first doping layers, the second doping layer can also be provided with multiple layers, and a ferroelectric layer is also provided between two adjacent second doping layers, and a ferroelectric layer is provided between the first doping layer and the second doping layer, so that the first doping layer and the second doping layer can be separated by the ferroelectric layer, and each first doping layer and each second doping layer can also be separated by the ferroelectric layer to achieve uniform ferroelectric distribution in the dielectric layer. When the ferroelectric layer also has multiple layers, the ferroelectric layer, the first doping layer and the second doping layer can be stacked alternately or non-alternatingly, as long as a ferroelectric layer is provided between different first doping layers, between different second doping layers, and between the first doping layer and the second doping layer. The specific stacking method of the ferroelectric layer, the first doping layer and the second doping layer can be designed according to actual needs and is not limited here.

[0011] For example, in addition to meeting the Helmholtz free energy requirement, the metal element in the first doping layer may also meet the following requirements: the difference in atomic radius between the metal element in the first doping layer and the metal element in the ferroelectric layer is not less than a threshold value, that is, the difference in atomic radius between the metal element in the first doping layer and the metal element in the ferroelectric layer is large. This allows the introduction of the metal in the first doping layer to cause significant lattice distortion in the ferroelectric layer, significantly impacting the crystallization of the ferroelectric layer, and thus more conducive to the formation of the ferroelectric layer. Alternatively, the valence of the metal element in the first doping layer is lower than that of the metal element in the ferroelectric layer. This allows the metal in the first doping layer to have a lower stability in oxygen bonding, thereby more easily introducing more oxygen vacancies, similarly impacting the crystallization of the ferroelectric layer, and thus more conducive to the formation of the ferroelectric layer. Alternatively, the difference in atomic radius between the metal element in the first doping layer and the metal element in the ferroelectric layer is not less than a threshold value, and the valence of the metal element in the first doping layer is lower than that of the metal element in the ferroelectric layer. This can promote the formation of the ferroelectric layer from both the perspectives of causing lattice distortion in the ferroelectric layer and introducing oxygen vacancies. In this case, the metal element in the first doping layer may include, but is not limited to, at least one of lanthanum, cerium, molybdenum, zirconium, silicon, gadolinium, and yttrium. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is lower than the valence state of the metal element in the ferroelectric layer, the metal can be considered to meet the requirement of having a valence state lower than the valence state of the metal element in the ferroelectric layer.

[0012] Furthermore, taking the example of hafnium oxide, a material used to make the ferroelectric layer, as an example, hafnium oxide has multiple phase structures, the most common of which are T-phase, O-phase, and M-phase. The ferroelectric phase is a type of O-phase. During heat treatment, hafnium oxide can form the T-phase as the temperature rises, and then transform into the O-phase or M-phase during cooling. When the first doping layer includes a metal element, the metal element can stabilize the hafnium oxide in the O-phase, causing it to exhibit ferroelectricity and form a ferroelectric layer. Alternatively, when the first doped layer includes multiple metal elements, some of these metal elements (referred to as Class A metal elements) are used to stabilize hafnium oxide in the O phase and exhibit ferroelectricity to form a ferroelectric layer. Therefore, the role of the Class A metal elements includes promoting the formation of the ferroelectric layer. Another portion of these metal elements (referred to as Class B metal elements) is used to promote the formation of the T phase of hafnium oxide, thereby reducing the heat treatment temperature and the thermal budget required for crystallization. Therefore, the role of the Class B metal elements includes reducing the heat treatment temperature required during the formation of the ferroelectric layer, thereby obtaining the ferroelectric layer and improving the reliability of the dielectric layer while also reducing the thermal budget during the formation of the ferroelectric layer. Among them, the Class A metal elements may include, but are not limited to, at least one of lanthanum, cerium, and molybdenum, and the Class B metal elements may include, but are not limited to, at least one of zirconium, silicon, gadolinium, and yttrium.

[0013] Similarly, in addition to meeting the Helmholtz free energy requirement, the metal element in the second doping layer may also meet the following requirements: the difference in atomic radius between the metal element in the second doping layer and the metal element in the ferroelectric layer is less than a threshold value, i.e., the atomic radius of the metal element in the second doping layer is close to that of the metal element in the ferroelectric layer. This allows the introduction of the metal into the second doping layer to cause minimal lattice distortion in the ferroelectric layer, minimally affecting the crystallization of the ferroelectric layer, and to produce shallow defect energy levels, thereby channeling accumulated electrons and preventing electron aggregation. Alternatively, the valence state of the metal element in the second doping layer is not lower than that of the metal element in the ferroelectric layer. This allows the metal in the second doping layer to bond with oxygen to be relatively stable, making it difficult to introduce oxygen vacancies or introducing fewer oxygen vacancies, and to produce shallow defect energy levels, thereby channeling accumulated electrons and preventing electron aggregation. Alternatively, the difference in atomic radius between the metal element in the second doping layer and the metal element in the ferroelectric layer is less than a threshold value, and the valence state of the metal element in the second doping layer is not lower than that of the metal element in the ferroelectric layer. In this case, the metal element in the second doped layer may include, but is not limited to, at least one of titanium and niobium. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is not lower than the valence state of the metal element in the ferroelectric layer, the metal can be considered to meet the requirement of having a valence state not lower than the valence state of the metal element in the ferroelectric layer.

[0014] The threshold value can be set based on factors such as the storage window and reliability requirements of the memory cell. For example, the threshold value can be set to 10 μm, but this is not a limitation. It should be understood that within the storage window of the memory cell, the ferroelectric polarization state is strong and remains unchanged, while outside the storage window, the polarization state is weak or flipped. Therefore, within the storage window of the memory cell, the memory cell has a high storage capacity, can stably record information, and achieve data storage.

[0015] The memory cell may include a transistor and a storage capacitor. When the dielectric layer is applied to the storage capacitor, the functional layer can serve as a second conductive layer in the storage capacitor. The first conductive layer and the second conductive layer are disposed on either side of the dielectric layer, thereby forming a storage capacitor. The storage window of the dielectric layer in the storage capacitor affects the storage performance of the storage capacitor, and thus the performance of the memory cell. By introducing the first doped layer, a ferroelectric layer can be obtained, thereby obtaining a sufficient storage window to enable data storage. Furthermore, by introducing the second doped layer, the reliability of the dielectric layer can be improved, thereby improving the reliability of the dielectric layer without compromising the storage window.

[0016] When the dielectric layer is applied to a transistor, the functional layer can serve as the channel of the transistor, and correspondingly, the first conductive layer can serve as the gate of the transistor. The dielectric layer serves as the gate insulating layer of the transistor to isolate the channel and the gate to avoid short circuit between the channel and the gate. Therefore, when the dielectric layer has better reliability, the reliability and performance of the transistor will also be improved.

[0017] Moreover, taking the storage capacitor as an example, when the storage capacitor is arranged on the substrate, the first conductive layer, the dielectric layer and the functional layer can be stacked in a direction perpendicular to the substrate surface, and the dielectric layer is arranged between the first conductive layer and the functional layer. In this case, the storage capacitor can be regarded as a storage capacitor with a two-dimensional structure. Alternatively, the functional layer and the insulating layer can be alternately stacked in a direction perpendicular to the substrate surface to form a stacked structure, and then a through hole is dug in the stacked structure, and the through hole penetrates the stacked structure along the stacking direction. Thereafter, the dielectric layer and the first conductive layer are sequentially filled in the through hole, and the dielectric layer is arranged between the stacked structure and the first conductive layer. In this case, the stacking direction of the ferroelectric layer, the first doped layer and the second doped layer is perpendicular to the extension direction of the through hole. In this case, the storage capacitor formed can be regarded as a storage capacitor with a three-dimensional structure. For transistors, similar to storage capacitors, transistors with a two-dimensional structure or a transistor with a three-dimensional structure can also be made, which will not be described in detail here.

[0018] Exemplarily, the material of the first conductive layer may include any material having a conductive function, such as, but not limited to, metals, metal oxides, and conductive organic materials, and the material can be selected based on actual needs and is not limited here. When the functional layer serves as the second conductive layer, the material of the functional layer can be the same as or different from the material of the first conductive layer, and the material can be selected based on actual needs and is not limited here. When the functional layer serves as the communication of the transistor, it can be made of a semiconductor material, and the material can be selected based on actual needs and is not limited here.

[0019] Of course, the first conductive layer and the functional layer serving as the second conductive layer can both be referred to as conductive film layers. For example, a film layer with auxiliary functions can be provided between the conductive film layer and the dielectric layer, such as, but not limited to, an adhesion layer or an interface passivation layer. When an adhesion layer is provided, the adhesion layer can increase the adhesion between the dielectric layer and the conductive film layer, thereby avoiding the conductive film layer and the dielectric layer from falling off and separating during the use of the storage unit, thereby further improving the reliability of the storage unit. The adhesion layer can be made of a material selected based on the material of the conductive film layer. As long as the material can play an adhesion role, the adhesion layer can be made. When an interface passivation layer is provided, the interface passivation layer can suppress the diffusion of elements between the dielectric layer and the conductive film layer, thereby avoiding the functional degradation of the conductive film layer and the dielectric layer, thereby improving the ferroelectricity of the dielectric layer and improving the reliability of the storage unit. The interface passivation layer can also be made of a material selected based on the material of the conductive film layer. As long as the material can play an interface passivation role, the interface passivation layer can be made.

[0020] In a second aspect, embodiments of the present application further provide a method for fabricating a memory cell. The memory cell fabricated by the fabrication method may be the memory cell described in the first aspect and any possible embodiment of the first aspect. The fabrication method may include: forming a functional layer; stacking a ferroelectric layer, a first doped layer, and a second doped layer on the functional layer, such that the ferroelectric layer, the first doped layer, and the second doped layer constitute a dielectric layer, the Helmholtz free energy of the metal elements in the first doped layer is lower than the Helmholtz free energy of the metal elements in the ferroelectric layer; and the Helmholtz free energy of the metal elements in the second doped layer is not lower than the Helmholtz free energy of the metal elements in the ferroelectric layer; and forming a first conductive layer on the dielectric layer. Thus, the introduction of the first doped layer can facilitate the dielectric layer to exhibit ferroelectric properties, and the introduction of the second doped layer can guide trapped and accumulated electrons, preventing electron aggregation and accumulation in the dielectric layer, thereby avoiding the problem of dielectric layer breakdown caused by electron aggregation and accumulation, thereby improving the reliability of the dielectric layer and even the memory cell when the ferroelectric memory cell is obtained.

[0021] Exemplarily, stacking a ferroelectric layer, a first doped layer, and a second doped layer on the functional layer may include: stacking an initial film layer, a first doped layer, and a second doped layer on the functional layer, and then heat-treating the initial film layer, the first doped layer, and the second doped layer so that the initial film layer is converted into a ferroelectric layer, thereby forming a dielectric layer on the functional layer. In other words, when forming the dielectric layer, physical vapor deposition or chemical vapor deposition can be used to form a stacked initial film layer, a first doped layer, and a second doped layer; and heat-treating the initial film layer, the first doped layer, and the second doped layer so that the initial film layer is converted into a ferroelectric layer. Taking atomic layer deposition as an example, since the thickness of the film layer obtained by each deposition of atomic layer deposition is limited, multiple depositions may be performed continuously to obtain a film layer of the target thickness. For example, when depositing the initial film layer using atomic layer deposition, taking hafnium oxide as an example, multiple hafnium oxide layers may be deposited continuously until the thickness of the hafnium oxide layers deposited multiple times reaches the target thickness, thereby obtaining the initial film layer. Furthermore, the first and second doped layers are used to facilitate the formation of the ferroelectric layer and improve its reliability. Therefore, the first and second doped layers do not need to be thicker; they can be deposited once using atomic layer deposition. By stacking multiple ferroelectric layers, first and second doped layers, a dielectric layer of the target thickness can be obtained.

[0022] Taking the initial film layer made of hafnium oxide as an example, the heat treatment process may include: first heating the initial film layer, the first doped layer, and the second doped layer to a first preset temperature, so that the hafnium oxide forms a T phase during the heating process; then cooling the initial film layer, the first doped layer, and the second doped layer to a second preset temperature, so that the hafnium oxide transforms from the T phase to the O phase during the cooling process and stabilizes in the O phase, thereby causing the hafnium oxide to exhibit ferroelectricity. The heat-treated initial film layer can be transformed into a ferroelectric layer. It should be understood that the first preset temperature is higher than the second preset temperature, and the selection of the first preset temperature and the second preset temperature can be set based on factors such as the formation temperature of the T phase and the O phase, and is not limited here.

[0023] Of course, the heat treatment process is not limited to being performed before forming the first conductive layer, but can also be performed after forming the first conductive layer. In this case, the method for manufacturing the memory cell can specifically include: forming a functional layer; forming an initial dielectric layer in contact with the functional layer, the initial dielectric layer comprising: a stacked initial film layer, a first doped layer, and a second doped layer; forming the first conductive layer on the initial dielectric layer; and performing a heat treatment to convert the initial film layer into a ferroelectric layer, thereby forming the dielectric layer. The heat treatment process can be referred to in the heat treatment process described above and will not be described in detail here.

[0024] For example, when the dielectric layer is applied to a storage capacitor and the storage capacitor has a three-dimensional structure, forming the functional layer may include forming alternating functional layers and insulating layers. The insulating layer may be made of any material that can provide insulation, and is not limited herein.

[0025] Among them, since the principle of solving the problem of the storage unit manufactured by this manufacturing method is similar to the principle of solving the problem of the aforementioned storage unit, the technical effects of this manufacturing method can refer to the embodiments and technical effects of the aforementioned storage unit, and the repeated parts will not be repeated.

[0026] On the third aspect, an embodiment of the present application further provides a memory, which may include: a storage array and a controller coupled to the storage array, the storage array including a plurality of storage units as described in the first aspect and any possible embodiment of the first aspect, the plurality of storage units being deployed in an array manner; a storage array for storing data; a controller for writing data to the storage array or reading data from the storage array. In this way, on the basis of improving the reliability of the storage unit, the reliability of the memory is also improved, thereby improving the performance of the memory. Since the principle of solving the problem by the memory is similar to the principle of solving the problem by the aforementioned storage unit, the embodiments and technical effects of the memory can refer to the embodiments and technical effects of the aforementioned storage unit, and the repeated parts will not be repeated.

[0027] Exemplarily, when a memory cell includes a transistor and at least one storage capacitor, the memory may further include: a word line, a bit line, and at least one control line. When the memory cells in the memory array are arranged in an array manner, memory cells in the same row can be connected to the same word line, while memory cells in different rows are connected to different word lines, so that different word lines can control the on and off of transistors in memory cells in different rows. Memory cells in the same column can be connected to the same bit line, while memory cells in different columns are connected to different bit lines, so that different bit lines can provide voltages to memory cells in different rows. Each control line is respectively connected to the second end of each storage capacitor in each memory cell. In other words, each memory cell is connected to a control line. The number of control lines provided is the same as the number of storage capacitors in the memory cell, and they are provided in a one-to-one correspondence. Thus, through the word lines and bit lines, each memory cell can be precisely controlled, and the voltages provided by the control lines enable precise writing and reading of data.

[0028] In a fourth aspect, an embodiment of the present application further provides an electronic device, which may include: a circuit board, and a memory as described in the second aspect and any possible implementation of the second aspect, wherein the memory is disposed on the circuit board. In this way, based on the improved reliability of the memory, the reliability of the electronic device is also improved, thereby improving the performance of the electronic device. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the aforementioned memory, the embodiments and technical effects of the electronic device can refer to the embodiments and technical effects of the aforementioned memory, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0030] FIG2 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0031] FIG3 is a schematic diagram of the structure of a storage capacitor in a storage unit provided in an embodiment of the present application;

[0032] FIG4 is a schematic diagram of the structure of a storage capacitor in another storage unit provided in an embodiment of the present application;

[0033] FIG5 is a schematic diagram of the principle provided by an embodiment of the present application;

[0034] FIG6 is a schematic diagram of the structure of a transistor in a memory cell provided in an embodiment of the present application;

[0035] FIG7 is a schematic diagram of the structure of a storage capacitor in another memory cell provided in an embodiment of the present application;

[0036] FIG8 is a flowchart of manufacturing a storage unit provided in an embodiment of the present application;

[0037] FIG9 is a flowchart of manufacturing another storage unit provided in an embodiment of the present application;

[0038] FIG10 is a flowchart of manufacturing another storage unit provided in an embodiment of the present application;

[0039] FIG11 is a flowchart of manufacturing another storage unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0041] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrating relative positional relationships and do not represent true proportions.

[0042] In order to facilitate understanding of the technical solution provided by the embodiments of the present application, its application scenario is first explained below.

[0043] The storage unit can be widely used in devices with storage functions, for example, it can be applied to storage devices with only storage functions, such as memories, and can also be applied to electronic devices with storage functions and other functions (such as read and write functions). The electronic device can be a portable electronic device that includes functions such as a personal digital assistant and / or a music player, such as a mobile phone, a tablet computer, a wearable device with wireless communication functions (such as a smart watch), or a car-mounted device. Exemplary embodiments of portable electronic devices include but are not limited to devices equipped with Or a portable electronic device with other operating systems. The portable electronic device may also be a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of the present application, the electronic device may also be a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0044] FIG1 exemplarily shows a schematic diagram of the structure of a memory when it is used in an electronic device. Referring to FIG1 , the electronic device includes a housing 300 and a circuit board 200 disposed in the housing 300, and the memory 100 is disposed on the circuit board 200. The memory 100 may be a non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. It should be noted that the memory described in this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0045] FIG2 exemplarily illustrates a schematic diagram of the internal structure of a memory 100 applicable to embodiments of the present application. It should be understood that the illustrated memory 100 is merely an example, and that the memory 100 may have more or fewer components than shown, may combine two or more components, or may have a different component configuration. The various components shown in the figure may be implemented in hardware, including one or more signal processing and / or application-specific integrated circuits, software, or a combination of hardware and software.

[0046] As shown in FIG2 , the memory 100 may include a storage array 110 and a controller 120. The storage array 110 is used to store data and is a matrix array composed of multiple storage cells arranged in rows and columns. Each storage cell can be used to store one or more bits of binary data, such as "0" and / or "1." The multiple storage cells may be located on different tracks of the same disk or on different disks, without specific limitation. The controller 120 is used to read or write data in the storage array 110 and is a device with control capabilities. The controller 120 can be connected to the storage array 110, for example, by a bus connection. The controller 120 may include multiple functional components, such as, but not limited to, driver circuits, decoding circuits, and amplifier circuits. These functional components may be provided as separate devices, implemented in a single device, or provided in at least two devices in any combination, without specific limitation.

[0047] Continuing with reference to FIG2 , the controller 120 can also be connected to an external device 400, which can be, for example, a read / write device or a processor. When reading / writing data, the external device 400 can send a read / write request to the controller 120, which carries the row address information and column address information of the target storage unit to be read / written. The controller 120 decodes the row address information in the read / write request to determine the row where the target storage unit is located, and turns on all storage units corresponding to the row where the target storage unit is located by decoding the selection signal. It then decodes the column address information in the read / write request to obtain the column where the target storage unit is located, and then reads the data stored in the target storage unit at the column and sends it to the external device 400, or writes the data to be written sent by the external device 400 into the target storage unit at the column.

[0048] Although not shown in FIG. 2 , the memory 100 may further include other components, such as a main memory data register (MDR) and a main memory address register (MAR), which are not described in detail here.

[0049] Ferroelectric memory is gaining popularity as a new type of memory that combines high-speed read / write speeds with non-volatility. Its core structure is a metal-ferroelectric layer-metal device. The ferroelectric layer serves as the storage medium, leveraging the two states of ferroelectric polarization to write and read "0" and "1," which remain unchanged even after the electric field is removed. The ferroelectric layer can be made of hafnium oxide, a material with multiple phases, the most common of which are T, O, and M. The ferroelectric phase is a type of O phase. The storage window of a ferroelectric memory is determined by the O-phase ratio and the polar axis orientation. The O-phase ratio is positively correlated with the storage window, as is the proximity of the polar axis to the C-axis. Therefore, the storage window can be adjusted by adjusting the O-phase ratio and the polar axis orientation. Pure hafnium oxide material itself is extremely difficult to stabilize in the O phase, so pure hafnium oxide material itself is difficult to show ferroelectric phase. Element doping can affect the crystallization and crystal phase formation of hafnium oxide, so through element doping, hafnium oxide can show ferroelectric phase, thereby obtaining hafnium oxide-based ferroelectric material.

[0050] When hafnium oxide-based ferroelectric materials are used as dielectric layers in memory, their reliability also needs to be considered. When hafnium oxide-based ferroelectric materials are used as storage layers (also known as dielectric layers) in storage capacitors, if there are a large number of oxygen vacancies, these oxygen vacancies can capture and accumulate electrons, introduce a built-in electric field, produce a pinning effect on the electric domain of a certain polarization direction, and even cause the storage medium to break down, resulting in a decrease in the reliability of the hafnium oxide-based ferroelectric memory. When hafnium oxide-based ferroelectric materials are used as gate insulators in transistors, if there are a large number of oxygen vacancies, this can also cause the gate insulator to break down, resulting in a decrease in the reliability of the hafnium oxide-based ferroelectric memory.

[0051] Therefore, the embodiments of the present application provide a memory cell, a manufacturing method thereof, a memory, and an electronic device to improve the reliability of hafnium oxide-based ferroelectric memory and improve the performance of the ferroelectric memory.

[0052] First embodiment: Figures 3 and 4 are schematic structural diagrams of a memory cell according to an embodiment of the present application. As shown in Figures 3 and 4, the memory cell may include: a first conductive layer 10, a functional layer 20, and a dielectric layer 30 disposed between the first conductive layer 10 and the functional layer 20. The dielectric layer 30 may include: a stacked ferroelectric layer 30a, a first doped layer 30b, and a second doped layer 30c. As shown in Figure 3, when the first doped layer 30b is provided in multiple layers, a ferroelectric layer 30a is provided between two adjacent first doped layers 30b. As shown in Figure 4, when the second doped layer 30c is provided in multiple layers, a ferroelectric layer 30a is also provided between two adjacent second doped layers 30c, and a ferroelectric layer 30a is provided between the first doped layer 30b and the second doped layer 30c. In this way, the first doped layer 30b and the second doped layer 30c can be separated by the ferroelectric layer 30a, and each first doped layer 30b and each second doped layer 30c can also be separated by the ferroelectric layer 30a, thereby achieving uniform ferroelectric distribution in the dielectric layer 30. When the ferroelectric layer 30a also has multiple layers, the ferroelectric layer 30a, the first doping layer 30b and the second doping layer 30c can be stacked alternately (as shown in Figure 4) or non-alternatingly (as shown in Figure 3), as long as the ferroelectric layer 30a is provided between different first doping layers 30b, between different second doping layers 30c, and between the first doping layer 30b and the second doping layer 30c. The specific stacking method of the ferroelectric layer 30a, the first doping layer 30b and the second doping layer 30c can be designed according to actual needs and is not limited here.

[0053] In conjunction with the schematic diagram shown in FIG5 and Table 1 below, the material used to make the ferroelectric layer 30a can include, but is not limited to, hafnium oxide. Hafnium oxide alone is unlikely to exhibit ferroelectricity. As shown in a1 in FIG5 , when the dielectric layer 30 includes only a hafnium oxide layer and a first doped layer 30b, if the Helmholtz free energy of the metal element in the first doped layer 30b (as shown by y1 in FIG5 a1) is lower than the Helmholtz free energy of the hafnium metal (as shown by y0 in FIG5 a1), this indicates that the metal element y1 in the first doped layer 30b requires less energy to move. This makes it easier to generate defects in the dielectric layer 30, thereby generating more oxygen vacancies (as shown by y3 in FIG5 a1). Oxygen vacancies y3 can cause the hafnium oxide layer to exhibit ferroelectricity, thereby forming the ferroelectric layer 30a. However, due to the deep defect energy levels of oxygen vacancies y3, a large number of oxygen vacancies y3 can trap and accumulate electrons (as shown by b1 in FIG5 ), introduce a built-in electric field, produce a pinning effect on the electric domain of a certain polarization direction, and even cause the dielectric layer 30 to break down, resulting in low reliability of the dielectric layer 30. It should be understood that in b1 in FIG5 , n1 represents the energy level of the metal forming the first conductive layer, and n2 represents the energy level of the metal forming the functional layer.

[0054] Table 1

[0055] As shown in a2 in FIG. 5 , when the dielectric layer 30 only includes a hafnium oxide layer and a second doping layer 30 c, if the Helmholtz free energy of the metal element in the second doping layer 30 c (as shown in y2 in a2 in FIG. 5 ) is not lower than the Helmholtz free energy of the metal hafnium element y0, it means that the metal element y2 in the second doping layer 30 c requires higher energy when moving, and fewer defects are generated in the dielectric layer 30 and the defect energy level is shallow, making it difficult to capture accumulated electrons (as shown in b2 in FIG. 5 ). In addition, the hafnium oxide layer is less likely to exhibit ferroelectricity, so it is more difficult to form the ferroelectric layer 30 a.

[0056] As shown in a3 in FIG5 , when dielectric layer 30 includes a hafnium oxide layer, a first doped layer 30b, and a second doped layer 30c, defects are more likely to form in dielectric layer 30 because the Helmholtz free energy of metal element y1 in first doped layer 30b is lower than that of metal hafnium element y0. This results in a higher number of oxygen vacancies y3. Oxygen vacancies y3 enable the hafnium oxide layer to exhibit ferroelectricity, thereby forming ferroelectric layer 30a. Furthermore, because the Helmholtz free energy of metal element y2 in second doped layer 30c is not lower than that of metal element y0 in ferroelectric layer 30a, fewer defects are generated in dielectric layer 30, and their energy levels are relatively shallow. These shallow defects can channel trapped and accumulated electrons (as shown in b3 in FIG5 ), preventing electron aggregation and accumulation in dielectric layer 30, and thus preventing breakdown of dielectric layer 30 due to electron aggregation and accumulation. Therefore, by introducing the first doping layer 30b and the second doping layer 30c having different functions, not only the ferroelectric layer 30a can be obtained, but also the reliability of the dielectric layer 30 and even the memory cell can be improved.

[0057] It should be understood that the ferroelectric layer 30a may be made of materials other than hafnium oxide, and may also include other materials with similar properties to hafnium oxide, without limitation. The hafnium oxide material characteristic refers to the fact that hafnium oxide alone is difficult to exhibit ferroelectricity. However, the introduction of oxygen vacancies or the introduction of the first doping layer 30b can make hafnium oxide exhibit ferroelectricity.

[0058] For example, in addition to meeting the Helmholtz free energy requirement, the metal elements in the first doping layer 30b may also meet the following requirements: the difference in atomic radius between the metal elements in the first doping layer 30b and the metal elements in the ferroelectric layer 30a is not less than a threshold value, that is, the difference in atomic radius between the metal elements in the first doping layer 30b and the metal elements in the ferroelectric layer 30a is large. In this way, when the metal in the first doping layer 30b is introduced, the lattice distortion of the material in the ferroelectric layer 30a is large, which has a greater impact on the crystallization of the material in the ferroelectric layer 30a, thereby being more conducive to the formation of the ferroelectric layer 30a. Alternatively, the valence state of the metal elements in the first doping layer 30b is lower than the valence state of the metal elements in the ferroelectric layer 30a. In this way, the stability of the metal-oxygen combination in the first doping layer 30b is lower, and it is easier to introduce more oxygen vacancies, which also has a greater impact on the crystallization of the material in the ferroelectric layer 30a, thereby being more conducive to the formation of the ferroelectric layer 30a. Alternatively, the difference in atomic radius between the metal element in the first doping layer 30b and the metal element in the ferroelectric layer 30a is not less than a threshold, and the valence of the metal element in the first doping layer 30b is lower than the valence of the metal element in the ferroelectric layer 30a. This can promote the formation of the ferroelectric layer 30a from two perspectives: causing lattice distortion in the material in the ferroelectric layer 30a and introducing oxygen vacancies. In this case, the metal element in the first doping layer 30b may include, but is not limited to, at least one of lanthanum, cerium, molybdenum, zirconium, silicon, gadolinium, yttrium, etc. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is lower than the valence state of the metal element in the ferroelectric layer 30a, the metal can be considered to meet the requirement of having a valence state lower than the valence state of the metal element in the ferroelectric layer 30a.

[0059] Furthermore, taking the example of hafnium oxide as the material of the ferroelectric layer 30a, hafnium oxide has multiple phase structures, the most common of which are T phase, O phase, and M phase. The ferroelectric phase is a type of O phase. During heat treatment, hafnium oxide can form the T phase as the temperature rises, and then transform into the O phase or M phase during cooling. In this case, the first doped layer 30b can include a metal element that can stabilize the hafnium oxide in the O phase, thereby exhibiting ferroelectricity and forming the ferroelectric layer 30a. Alternatively, as shown in Table 2 below, the first doped layer 30b may include multiple metal elements. Some of these metal elements (referred to as Class A metal elements) are used to stabilize hafnium oxide in the O phase, thereby exhibiting ferroelectricity and forming the ferroelectric layer 30a. Therefore, the Class A metal elements promote the formation of the ferroelectric layer 30a. Other metal elements (referred to as Class B metal elements) promote the formation of the T phase in the hafnium oxide, resulting in a mixture of the O and T phases. This can lower the heat treatment temperature and the thermal budget required for crystallization. Therefore, the Class B metal elements lower the heat treatment temperature required during the formation of the ferroelectric layer 30a, thereby obtaining the ferroelectric layer 30a and improving the reliability of the dielectric layer 30 while also reducing the thermal budget required for forming the ferroelectric layer 30a. The Class A metal elements may include, but are not limited to, at least one of lanthanum, cerium, and molybdenum, and the Class B metal elements may include, but are not limited to, at least one of zirconium, silicon, gadolinium, and yttrium.

[0060] Table 2

[0061] Similarly, in addition to meeting the Helmholtz free energy requirement, the metal elements in the second doping layer 30c may also meet the following requirements: the difference in atomic radius between the metal elements in the second doping layer 30c and the metal elements in the ferroelectric layer 30a is less than a threshold value, that is, the atomic radius of the metal elements in the second doping layer 30c is close to that of the metal elements in the ferroelectric layer 30a. In this way, when the metal in the second doping layer 30c is introduced, the lattice distortion of the material in the ferroelectric layer 30a is small, the crystallization of the material in the ferroelectric layer 30a is small, and the defect energy level generated is shallow, which can guide the accumulated electrons and prevent electron aggregation. Alternatively, the valence state of the metal elements in the second doping layer 30c is not lower than the valence state of the metal elements in the ferroelectric layer 30a. In this way, the metal in the second doping layer 30c is relatively stable in combination with oxygen, making it difficult to introduce oxygen vacancies or introducing fewer oxygen vacancies, and the defect energy level generated is shallow, which can guide the accumulated electrons and prevent electron aggregation. Alternatively, the difference in atomic radius between the metal element in the second doping layer 30c and the metal element in the ferroelectric layer 30a is less than a threshold value, and the valence state of the metal element in the second doping layer 30c is not lower than the valence state of the metal element in the ferroelectric layer 30a. In this case, the metal element in the second doping layer 30c may include, but is not limited to, at least one of titanium and niobium. It should be understood that a metal may have multiple valence states, but as long as one of the valence states is not lower than the valence state of the metal element in the ferroelectric layer 30a, the metal can be considered to meet the requirement that the valence state is not lower than the valence state of the metal element in the ferroelectric layer 30a.

[0062] The threshold value can be set based on factors such as the storage window and reliability requirements of the memory cell. For example, the threshold value can be set to 10 μm, but this is not a limitation. It should be understood that within the storage window of the memory cell, the ferroelectric polarization state is strong and remains unchanged, while outside the storage window, the polarization state is weak or flipped. Therefore, within the storage window of the memory cell, the memory cell has a high storage capacity, can stably record information, and achieve data storage.

[0063] For example, taking the metal elements in the first doping layer as lanthanum and zirconium and the metal element in the second doping layer as titanium, refer to Table 3 below, where La:HfO2 represents lanthanum-doped hafnium oxide, Zr:HfO2 represents zirconium-doped hafnium oxide, Ti:HfO2 represents titanium-doped hafnium oxide, La:Ti:HfO2 represents lanthanum and titanium-doped hafnium oxide, and La:Zr:Ti:HfO2 represents lanthanum, zirconium and titanium-doped hafnium oxide.

[0064] Table 3

[0065] From the results shown in Table 3: for lanthanum-doped hafnium oxide, although the proportion of the O phase can be increased to make the hafnium oxide exhibit ferroelectricity with the O phase as the main phase, the required heat treatment temperature is high, resulting in a high thermal budget and poor reliability; for zirconium-doped hafnium oxide, since the crystal phase is a mixture of O phase and T phase, the proportion of the O phase can be reduced, so the hafnium oxide can exhibit ferroelectricity and the thermal budget can be reduced; for titanium-doped hafnium oxide, it is difficult to form the O phase or the T phase, so it is difficult to make the hafnium oxide exhibit ferroelectricity; for lanthanum and titanium-doped hafnium oxide, the effects of lanthanum and titanium can make the hafnium oxide exhibit ferroelectricity and improve reliability, but the thermal budget is high due to the effect of lanthanum; for lanthanum, zirconium and titanium-doped hafnium oxide, the effects of lanthanum, zirconium and titanium can make the hafnium oxide exhibit ferroelectricity and improve reliability, and the thermal budget can be reduced due to the effect of zirconium. Furthermore, zirconium-doped hafnium oxide easily forms polycrystalline due to the mixing of O and T phases. This makes it difficult to maintain phase consistency between different memory cells when device area is scaled, resulting in poor device scaling. However, for lanthanum-, zirconium-, and titanium-doped hafnium oxide, the lanthanum and titanium elements can compensate for the poor scaling caused by zirconium doping alone, thereby improving device scaling performance. Therefore, in practical applications, the choice of doping element can be based on thermal budget requirements, reliability requirements, and scalability.

[0066] The memory cell may include a storage capacitor. When the dielectric layer 30 is applied to the storage capacitor, the functional layer 20 may serve as the second conductive layer in the storage capacitor. The first conductive layer 10 and the second conductive layer are disposed on either side of the dielectric layer 30, thereby forming a storage capacitor. The storage window of the dielectric layer 30 in the storage capacitor affects the storage performance of the storage capacitor, and thus the performance of the memory cell. By introducing the first doped layer 30b, a ferroelectric layer 30a can be obtained, thereby obtaining a sufficient storage window to enable data storage. Furthermore, by introducing the second doped layer 30c, the reliability of the dielectric layer 30 can be improved, thereby improving the reliability of the dielectric layer 30 without compromising the storage window.

[0067] Moreover, in the storage capacitor, when the storage capacitor is arranged on a substrate (not shown in Figures 3 and 4), the first conductive layer 10, the dielectric layer 30 and the functional layer 20 can be stacked along a direction perpendicular to the substrate surface (i.e., the z direction shown in Figures 3 and 4), and the dielectric layer 30 is arranged between the first conductive layer 10 and the functional layer 20. In this case, the storage capacitor can be regarded as a storage capacitor with a two-dimensional structure.

[0068] For example, the material of the first conductive layer 10 may include any conductive material, such as, but not limited to, metals, metal oxides, and conductive organic compounds. The material can be selected based on actual needs and is not limited here. When the functional layer 20 serves as the second conductive layer, the material of the functional layer 20 may be the same as or different from the material of the first conductive layer 10. The material can be selected based on actual needs and is not limited here.

[0069] The first conductive layer 10 and the functional layer 20 as the second conductive layer can both be referred to as conductive film layers. For example, as shown in FIG4 , a film layer with auxiliary functions can be provided between the conductive film layer and the dielectric layer 30, such as, but not limited to, an adhesion layer 40 or an interface passivation layer (not shown in FIG4 ). When the adhesion layer 40 is provided, the adhesion layer 40 can increase the adhesion between the dielectric layer 30 and the conductive film layer, thereby avoiding the conductive film layer and the dielectric layer 30 from falling off and separating during the use of the memory cell, thereby further improving the reliability of the memory cell. The adhesion layer 40 can be made of a material selected based on the material of the conductive film layer. As long as the material can play an adhesion role, the adhesion layer 40 can be made. When the interface passivation layer is provided, the interface passivation layer can inhibit the diffusion of elements between the dielectric layer and the conductive film layer, avoiding the degradation of the functions of the conductive film layer and the dielectric layer, thereby improving the ferroelectricity of the dielectric layer and improving the reliability of the memory cell. The interface passivation layer can also be made of a material selected based on the material of the conductive film layer. As long as the material can play an interface passivation role, the interface passivation layer can be made.

[0070] Second embodiment: FIG6 is a schematic diagram of the structure of a memory cell in an embodiment of the present application, as shown in FIG6 , the structure of the memory cell in the second embodiment is basically similar to that of the memory cell in the first embodiment, except that the application scenario of the dielectric layer 30 is different. For example, when the memory cell includes a transistor, the dielectric layer 30 can be applied to the transistor. In this case, the functional layer 20 can serve as the channel of the transistor, the first conductive layer 10 can serve as the gate of the transistor, and the dielectric layer 30 serves as a gate insulating layer to isolate the gate and the channel in the transistor to avoid short circuit between the channel and the gate. Thus, when the dielectric layer 30 has good reliability, the reliability and performance of the transistor will also be improved. Moreover, when the functional layer 20 serves as the communication of the transistor, it can be made of semiconductor material, which can be selected according to actual needs and is not limited here. Wherein, S in FIG6 represents the source of the transistor, and D represents the drain of the transistor.

[0071] It should be understood that the similarities between the structures of the storage unit in the second embodiment and the storage unit in the first embodiment can be found in the first embodiment, and the repeated parts will not be repeated.

[0072] Third embodiment: FIG7 is a schematic diagram of the structure of a memory cell according to an embodiment of the present application. The structure of the memory cell in this third embodiment is substantially similar to that of the memory cell in the first embodiment, except that the storage capacitor has a three-dimensional structure. Referring to FIG7 , the functional layer 20 and the insulating layer 50 can be alternately stacked in a direction perpendicular to the surface of the substrate (not shown in FIG7 ) (i.e., the z-direction) to form a stacked structure m1. A through hole m2 is then dug in the stacked structure m1. The through hole m2 extends through the stacked structure m1 along the stacking direction (i.e., the z-direction). The through hole m2 is then filled with a dielectric layer 30 and a first conductive layer 10 in sequence. The dielectric layer 30 is disposed between the stacked structure m1 and the first conductive layer 10. In this case, the stacking direction (i.e., the x-direction) of the ferroelectric layer 30a, the first doped layer 30b, and the second doped layer 30c is perpendicular to the extension direction (i.e., the z-direction) of the through hole m2. The storage capacitor formed in this case can be considered a three-dimensional storage capacitor. This allows the memory cell to have both a two-dimensional and a three-dimensional structure, expanding the application range of the memory cell. Furthermore, the dielectric layer 30, the first conductive layer 10, and the filling layer 60 can completely fill the through hole m2, and the filling layer 60 is disposed on the side of the first conductive layer 10 facing away from the dielectric layer 30 (such as the left side in the cross-sectional view of FIG7). The filling layer 60 can be made of an insulating material, which can reduce the material used to make the first conductive layer 10. When the cost of the material used to make the first conductive layer 10 is high, while the cost of the material used to make the filling layer 60 is low, the manufacturing cost of the memory cell can be effectively reduced. Alternatively, the dielectric layer 30 and the first conductive layer 10 can completely fill the through hole m2, that is, the first conductive layer 10 fills the space in the through hole m2 not occupied by the dielectric layer 30. This can simplify the manufacturing steps and process of the memory cell and improve manufacturing efficiency.

[0073] It should be understood that the similarities between the structures of the storage unit in the third embodiment and the storage unit in the aforementioned first embodiment can be found in the aforementioned first embodiment, and the repeated parts will not be repeated.

[0074] Fourth embodiment: FIG8 is a schematic diagram exemplarily illustrating a method for manufacturing a memory cell in an embodiment of the present application. Referring to FIG8 , taking the dielectric layer applied to a storage capacitor, using hafnium oxide to manufacture an initial film layer, using lanthanum oxide to manufacture a first doping layer, and using titanium oxide to manufacture a second doping layer as an example, the specific manufacturing process of the memory cell may include:

[0075] S1. As shown in FIG8 (a), a W film layer is formed on the substrate by physical vapor deposition as a functional layer. The functional layer can be regarded as a second conductive layer.

[0076] S2. As shown in (b) of FIG8 , an atomic layer deposition method is used to stack 10 hafnium oxide layers, 1 lanthanum oxide layer, 10 hafnium oxide layers, 1 titanium oxide layer, and 20 hafnium oxide layers on the functional layer; wherein the 10 hafnium oxide layers or the 20 hafnium oxide layers are used as the initial film layer, the lanthanum oxide layer is used as the first doping layer, and the titanium oxide layer is used as the second doping layer. The initial film layer, the first doping layer, and the second doping layer form an initial dielectric layer;

[0077] For example, the deposition rate of the hafnium oxide layer may be, but is not limited to, 1.07 angstroms per pass; the deposition rate of the lanthanum oxide layer may be, but is not limited to, 0.46 angstroms per pass; and the deposition rate of the titanium oxide layer may be, but is not limited to, 0.50 angstroms per pass. Furthermore, the total thickness of the initial film layer, the first doped layer, and the second doped layer stacked in step S2 may be, but is not limited to, 80 angstroms.

[0078] Furthermore, by making the topmost initial film layer in the initial dielectric layer slightly thicker, the doping elements in the first doping layer or the second doping layer can be mainly retained inside the initial dielectric layer, preventing the doping elements from approaching the surface of the initial dielectric layer, thereby avoiding the introduction of additional interface effects and improving the reliability of the storage unit.

[0079] It should be understood that the multilayer hafnium oxide included in the initial film layer is produced continuously, so as to ensure that the initial film layer has a certain thickness, and the number of hafnium oxide layers included in the initial film layer is not limited to 10 or 20 layers. This is just an example, and the specific setting can be made according to actual conditions and is not limited here.

[0080] S3, heating the initial dielectric layer, cooling it when the temperature reaches a first preset temperature, and ending the heat treatment process when the temperature reaches a second preset temperature, so that the initial film layer is transformed into a ferroelectric layer to obtain a dielectric layer;

[0081] S4. As shown in FIG8(c), a TiN film is formed on the dielectric layer as a first conductive layer by using physical vapor deposition.

[0082] In this way, the introduction of the first doped layer can help the dielectric layer exhibit ferroelectric properties, and the introduction of the second doped layer can guide the captured and accumulated electrons, preventing the electrons from gathering and accumulating in the dielectric layer, thereby preventing the dielectric layer from being punctured due to electron gathering and accumulation, thereby improving the reliability of the dielectric layer and even the memory unit when obtaining a ferroelectric memory unit.

[0083] It should be understood that this embodiment only illustrates the method of manufacturing a memory cell using the example shown in Figure 8. The stacking order of the initial film layer, the first doping layer, and the second doping layer is not limited to the one shown in Figure 8. It can also be other stacking orders, which are not shown in this embodiment. As long as the stacking order of ferroelectric layers is provided between different first doping layers, between different second doping layers, and between the first doping layer and the second doping layer, it is applicable to the embodiments of the present application.

[0084] Fifth embodiment: FIG9 is a schematic diagram illustrating an exemplary method for fabricating a memory cell according to an embodiment of the present application. Referring to FIG9 , the fabrication method in the fifth embodiment is substantially similar to the fabrication method in the aforementioned fourth embodiment, except that different doping elements are introduced. For example, in the fifth embodiment, taking hafnium oxide as the initial film layer, lanthanum oxide and zirconium oxide as the first doping layer, and titanium oxide as the second doping layer as an example, S2 in the aforementioned fourth embodiment can be adjusted as follows: Referring to FIG9 (b), atomic layer deposition is used to stack five hafnium oxide and zirconium oxide composite film layers, one lanthanum oxide layer, five composite film layers, one titanium oxide layer, and ten composite film layers on top of the functional layer; wherein the hafnium oxide in the composite film layer serves as the initial film layer, the lanthanum oxide and zirconium oxide in the composite film layer serve as the first doping layer, and titanium oxide serves as the second doping layer. The initial film layer, the first doping layer, and the second doping layer form an initial dielectric layer; in this case, it can be understood that zirconium oxide is doped into the initial film layer, and the lanthanum oxide layer and the titanium oxide layer are doped outside the initial film layer. Alternatively, atomic layer deposition is used to stack five layers of hafnium oxide, one layer of zirconium oxide, five layers of hafnium oxide, one layer of lanthanum oxide, five layers of hafnium oxide, one layer of titanium oxide, and ten layers of hafnium oxide on top of the functional layer. The hafnium oxide serves as the initial film layer, the lanthanum oxide and zirconium oxide serve as the first doping layer, and the titanium oxide serves as the second doping layer. The initial film layer, the first doping layer, and the second doping layer form the initial dielectric layer. In this case, it can be understood that the zirconium oxide, lanthanum oxide, and titanium oxide layers are all doped outside the initial film layer. The deposition rate of the zirconium oxide layer can be, but is not limited to, 0.93 angstroms per deposition. The deposition rates of the hafnium oxide, lanthanum oxide, and titanium oxide layers can refer to the fourth embodiment above, and any repetitions are not repeated here.

[0085] It should be understood that, referring to (a) in FIG9 , S1 in the fifth embodiment is the same as S1 in the aforementioned fourth embodiment; S3 in the fifth embodiment is the same as S3 in the aforementioned fourth embodiment; referring to (c) in FIG9 , S4 in the fifth embodiment is the same as S4 in the aforementioned fourth embodiment; therefore, for the similarities between the manufacturing method in the fifth embodiment and the manufacturing method in the aforementioned fourth embodiment, please refer to the aforementioned fourth embodiment for details, and the repeated parts will not be repeated.

[0086] Sixth embodiment: FIG10 is a schematic diagram illustrating a method for manufacturing a memory cell according to an embodiment of the present application. As shown in FIG10 , the manufacturing method in the sixth embodiment is substantially similar to the manufacturing method in the aforementioned fourth embodiment, with the following differences:

[0087] (1) Step k1 is added between S1 and S2 in the aforementioned fourth embodiment. Step k1 may specifically include: as shown in FIG10( b ), forming an auxiliary layer having auxiliary functions on the functional layer. The auxiliary functions of the film layer may include, but are not limited to, adhesion and interface passivation;

[0088] (2) Step k2 is added between S3 and S4 in the aforementioned fourth embodiment. Step k2 may specifically include: as shown in (d) in Figure 10, an auxiliary layer with auxiliary functions is formed on the dielectric layer. The auxiliary functions of the film layer may include but are not limited to adhesion and interface passivation.

[0089] In this way, the reliability of the memory cell can be further improved by using the film layer with auxiliary functions.

[0090] It should be understood that, referring to (a) in FIG10 , S1 in the sixth embodiment is the same as S1 in the aforementioned fourth embodiment; referring to (c) in FIG10 , S2 in the sixth embodiment is the same as S2 in the aforementioned fourth embodiment; S3 in the sixth embodiment is the same as S3 in the aforementioned fourth embodiment; referring to (e) in FIG10 , S4 in the sixth embodiment is the same as S4 in the aforementioned fourth embodiment; therefore, for the similarities between the manufacturing method in the sixth embodiment and the manufacturing method in the aforementioned fourth embodiment, please refer to the aforementioned fourth embodiment for details, and the repeated parts will not be repeated.

[0091] Seventh embodiment: FIG11 is a schematic diagram exemplarily illustrating a method for manufacturing a memory cell according to an embodiment of the present application. As shown in FIG11 , the manufacturing method in the seventh embodiment is substantially similar to the manufacturing method in the aforementioned fourth embodiment, with the following differences:

[0092] (1) Adjusting the above S1 to: as shown in FIG11(a), using chemical vapor deposition, alternately depositing metal W film layers and insulating layers on the substrate to obtain a stacked structure m1, with the metal W film layers serving as functional layers; wherein the stacked structure m1 includes multiple functional layers and multiple insulating layers;

[0093] (2) adding step k3 between S1 and S2 above, step k3 may include: as shown in FIG11(b), opening the stacked structure m1 by photolithography and high-aspect-ratio dry etching to obtain a columnar through-hole T with a diameter of about 50 nm, the through-hole T penetrating the stacked structure m1 along the stacking direction;

[0094] (3) Each film layer formed in the above steps S2 to S4 is fabricated in the through hole T, as shown in (c) and (d) of FIG11 ;

[0095] (4) If the TiN film layer formed in the above S4 does not fill the remaining space in the through hole T, it is necessary to continue to form a filling layer after the TiN film layer is formed, and fill the unoccupied space in the through hole T with the filling layer, which is not shown in the figure; the manufacturing process of the filling layer includes: using chemical vapor deposition method, using insulating material, and depositing an insulating layer on the TiN film layer to fill the through hole T; wherein the insulating material and the manufacturing material of the insulating layer can be the same or different.

[0096] In this way, the storage capacitor obtained is a three-dimensional structure, which expands the application range of ferroelectric memory cells.

[0097] It should be understood that the process of forming each film layer in the initial dielectric layer in the seventh embodiment is the same as S2 in the aforementioned fourth embodiment, the process of processing the initial dielectric layer to obtain the dielectric layer in the seventh embodiment is the same as S3 in the aforementioned fourth embodiment, and the process of manufacturing the TiN film layer in the seventh embodiment is the same as S4 in the aforementioned fourth embodiment. Therefore, the similarities between the manufacturing method in the seventh embodiment and the manufacturing method in the aforementioned fourth embodiment can be specifically referred to the aforementioned fourth embodiment, and the repeated parts will not be repeated.

[0098] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A storage unit, characterized in that: include: A first conductive layer, a functional layer, and a dielectric layer disposed between the first conductive layer and the functional layer, wherein the dielectric layer comprises: a ferroelectric layer, a first doped layer, and a second doped layer that are stacked; The Helmholtz free energy of the metal elements in the first doping layer is lower than the Helmholtz free energy of the metal elements in the ferroelectric layer, and the Helmholtz free energy of the metal elements in the second doping layer is not lower than the Helmholtz free energy of the metal elements in the ferroelectric layer.

2. The storage unit according to claim 1, characterized in that The difference between the atomic radius of the metal element in the second doping layer and the metal element in the ferroelectric layer is smaller than a threshold value, and / or the valence state of the metal element in the second doping layer is not lower than the valence state of the metal element in the ferroelectric layer.

3. The storage unit according to claim 1 or 2, characterized in that: The second doped layer is provided with multiple layers, and the ferroelectric layer is provided between two adjacent second doped layers.

4. The storage unit according to any one of claims 1 to 3, characterized in that: The second doping layer includes at least one of titanium and niobium.

5. The storage unit according to any one of claims 1 to 4, characterized in that: The difference in atomic radius between the metal element in the first doping layer and the metal element in the ferroelectric layer is not less than the threshold, and / or the valence state of the metal element in the first doping layer is lower than the valence state of the metal element in the ferroelectric layer.

6. The storage unit according to any one of claims 1 to 5, characterized in that: The first doped layer is provided with multiple layers, and the ferroelectric layer is provided between two adjacent first doped layers.

7. The storage unit according to any one of claims 1 to 6, characterized in that: The first doping layer includes at least one of lanthanum, cerium, molybdenum, zirconium, silicon, gadolinium, and yttrium.

8. The storage unit according to any one of claims 1 to 7, characterized in that: The ferroelectric layer is disposed between the first doping layer and the second doping layer.

9. The storage unit according to any one of claims 1 to 8, characterized in that: The storage unit includes a storage capacitor, and the functional layer is a second conductive layer.

10. The storage unit according to any one of claims 1 to 8, characterized in that: The memory cell includes a transistor, the functional layer is a channel in the transistor, and the first conductive layer is a gate in the transistor.

11. The storage unit according to any one of claims 1 to 10, characterized in that: The ferroelectric layer is made of a material including hafnium oxide.

12. A method for manufacturing a storage unit according to any one of claims 1 to 11, characterized in that: include: Forming a functional layer; A ferroelectric layer, a first doped layer and a second doped layer are stacked on the functional layer, the ferroelectric layer, the first doped layer and the second doped layer constitute a dielectric layer, the Helmholtz free energy of the metal element in the first doped layer is lower than the Helmholtz free energy of the metal element in the ferroelectric layer; the Helmholtz free energy of the metal element in the second doped layer is not lower than the Helmholtz free energy of the metal element in the ferroelectric layer; A first conductive layer is formed on the dielectric layer.

13. The method according to claim 12, characterized in that A ferroelectric layer, a first doping layer and a second doping layer are stacked on the functional layer, comprising: stacking an initial film layer, the first doping layer and the second doping layer on the functional layer; The initial film layer, the first doping layer and the second doping layer are thermally treated so that the initial film layer is transformed into the ferroelectric layer.

14. A memory, characterized in that: include: A storage array and a controller coupled to the storage array, wherein the storage array comprises a plurality of storage units according to any one of claims 1 to 11, and the plurality of storage units are deployed in an array manner; The storage array is used to store data; The controller is used to write data into the storage array or read data from the storage array.

15. An electronic device, characterized in that: include: A circuit board and a memory as claimed in claim 14, wherein the memory is arranged on the circuit board.

Images