Spacer for wafer

Abstract

The invention relates to a method for producing a coupled wafer (100) having a spacer wafer (150) for protecting metal contacts (120) of a functional wafer (110), the method comprising the steps: providing the functional wafer (110), which has a functional layer (140), a passivation layer (130) and the metal contacts (120), wherein the passivation layer and the metal contacts are arranged on the functional layer; providing the spacer wafer (150), which has a silicon layer (160) having trenches (166) and has an oxide layer (170), a second oxide layer (190) and a carrier substrate, wherein the second oxide layer has recesses which are each enclosed by one of the trenches and are arranged and designed in such a way that there is correspondence between the recesses and the metal contacts (120) and all of the metal contacts can be covered by the associated recesses; producing a coupled wafer (100) by connecting the passivation layer to the second oxide layer in such a way that each of the metal contacts is covered by the associated recess; and removing the carrier substrate and forming recesses in the spacer wafer (150) in such a way that the metal contacts are in contact with the external surroundings (105).

Description

[0001] Wafer spacers

[0002] The present invention relates to the field of wafer processing and concerns a method for producing a coupled wafer with a spacer wafer for protecting metal contacts. Furthermore, it concerns a corresponding coupled wafer.

[0003] State of the art

[0004] US 2008 / 0303129 A1 discloses a method for preventing damage to sensitive surfaces in MEMS manufacturing. For this purpose, the use of a chuck with a structured contact surface is proposed. A cover wafer is described in detail, which is to be connected to an interposer wafer during a manufacturing process. The cover wafer is positioned on the chuck, and the structuring ensures that mechanical damage is avoided. DE 10 2015 206 996 A1 discloses the so-called EPyC process (EPyC: epitaxial polysilicon cycle) for manufacturing microelectromechanical structures with large vertical dimensions. This process uses epitaxial polysilicon as the functional and sacrificial material and builds a layer structure of epitaxial polysilicon layers (EpiPoly layers) using repeated cycles.

[0005] Disclosure of the invention

[0006] According to the invention, a method for producing a coupled wafer with a spacer wafer for protecting metal contacts of a functional wafer and a corresponding coupled wafer are proposed.

[0007] According to a first aspect of the invention, a method for producing a coupled wafer with a spacer wafer for protecting metal contacts of a functional wafer is proposed. The method comprises providing the functional wafer, for example, a MEMS wafer (MEMS: microelectromechanical system), with a functional layer (which implements the actual functions of a MEMS component), for example, comprising silicon or consisting of silicon, a passivation layer, and the metal contacts, wherein the passivation layer and the metal contacts are arranged on a surface of the functional layer. The metal contacts can, for example, be designed to establish electrical connections between the functional wafer and other components.

[0008] The metal contacts, which can represent metal pads, can, for example, consist of an aluminum-copper alloy (AlCu), copper (Cu), and / or gold (Au), or can comprise AlCu, Cu, and / or Au. The passivation layer can preferably consist of silicon dioxide (SiO2) and / or a silicon nitride (for example, stoichiometric silicon nitride, i.e., SiAlXk, and / or a non-stoichiometric silicon nitride, i.e., a silicon nitride with a non-stoichiometric composition), or can comprise silicon dioxide and / or silicon nitride. In particular, it is conceivable for the passivation layer to consist of a silicon nitride layer and a silicon dioxide layer, or to comprise these layers. It is conceivable for the silicon dioxide layer or the silicon nitride layer to be applied first to the functional layer.The use of a double layer as a passivation layer comprising a layer of stoichiometric silicon nitride and a layer of non-stoichiometric silicon nitride is also possible. The passivation layer preferably serves as an etch stop layer for a subsequent silicon sacrificial layer etching, wherein sulfur hexafluoride (SF6) and / or xenon difluoride (XeF2) can be used as etching gases for this purpose.

[0009] Furthermore, a spacer wafer is provided. The spacer wafer comprises a silicon layer having trenches filled with a passivation material. The passivation material can be, for example, silicon dioxide, silicon nitride, and / or silicon oxynitride. The spacer wafer further comprises a first oxide layer on a first surface of the silicon layer, a second oxide layer on a second surface of the silicon layer opposite the first surface, and a carrier substrate arranged on the first oxide layer, preferably comprising silicon or consisting of silicon. For the purposes of this invention, oxide layers are understood to mean layers that comprise silicon dioxide (SiCh) or consist of SiCh.

[0010] The silicon layer can, in particular, be an epi-polycrystalline silicon layer (EpiPoly layer). Epi-polycrystalline silicon layers are polycrystalline silicon layers that have been grown epitaxially, i.e., under epitaxial growth conditions. Such epi-polycrystalline silicon layers typically have thicknesses of more than 5 pm, frequently even several tens of pm. In this case, the silicon layer preferably has a thickness of 10-20 pm. The thickness of the silicon layer defines the distance between the metal contacts and a support surface, for example, a chuck. The trenches can, for example, have been deposited thermally and / or by means of low-pressure chemical vapor deposition (LPCVD).A trench preferably connects the first surface to the second surface of the silicon layer, i.e. it preferably extends through the entire thickness of the silicon layer defined by the distance between the first and second surfaces.

[0011] The second oxide layer on the silicon layer further comprises one or more recesses, each of which is enclosed by one or more of the trenches in the silicon layer. A recess is referred to as being enclosed by a trench in the silicon layer if the trench extends in such a way that, when the recess is imaginarily continued perpendicular to the second surface of the silicon layer into the silicon layer, the recess is enclosed laterally by the trench, i.e., parallel to the second surface in all directions. If a trench connects the first surface to the second surface of the silicon layer, it thus also encloses a region of the silicon layer and separates this region from the rest of the silicon layer. A trench within the meaning of the invention can only ever enclose a region of the silicon layer.If a trench structure encloses several regions of the silicon layer that are separated from one another due to the trench structure, the trench structure constitutes multiple trenches within the meaning of the invention. An example would be two trenches that both enclose different regions in the silicon layer, but are connected to each other by another trench or part of another trench. This trench structure constitutes multiple trenches because it encloses several regions.

[0012] Here, the one or more recesses are arranged and configured such that an association is established between the one or more recesses and the metal contacts, and all metal contacts can be simultaneously covered by the respective recess assigned to them. Coverability of a metal contact by a recess within the meaning of the invention means that a base area of ​​the recess can be placed in a base area of ​​the metal contact such that this base area of ​​the recess encloses the base area of ​​the metal contact.

[0013] The one or more recesses in the second oxide layer are thus arranged according to the arrangement of the metal contacts, thereby establishing an association between the recesses and the metal contacts. In this case, multiple metal contacts can also be associated with a single recess. For example, two, three, four, or five metal contacts can be associated with a single recess. All metal contacts can also be associated with a single recess. Preferably, the number of recesses is identical to the number of metal contacts. In this case, the recesses are arranged in an identical pattern to the metal contacts; the positions of the recesses in the second oxide layer therefore correspond to the positions of the metal contacts on the functional layer.

[0014] The recesses are preferably dimensioned with a margin so that the metal contacts are reliably accessible even with existing process tolerances, such as an alignment offset during subsequent wafer bonding. The same applies to creating the trenches in the silicon layer of the spacer wafer.

[0015] In general, a wide variety of arrangements of the metal contacts are conceivable, for example a grid-like arrangement or an asymmetric arrangement. Likewise, a wide variety of shapes are possible for the recesses in the second oxide layer; for example, one of the one or more recesses can have a rectangular, circular, or hexagonal base area. The shape of a recess can also be adapted to a shape of the covered metal contact. The shapes of the recesses can also vary between the individual recesses within a spacer wafer, or all recesses can have the same shape, for example rectangular, circular, or hexagonal. One recess can cover a plurality of metal contacts, for example two, three, four, five, or more. One recess can also cover all metal contacts.In particular, the recesses can also be designed such that, after subsequent singulation, a spacer structure, for example in the form of a frame and / or individual support structures, for example in corners of the chips or MEMS components, remains for each chip formed or MEMS component formed from the spacer wafer. This ensures continued protection of the singulated chips or MEMS components even after singulation. Preferably, the geometry of a recess in the second oxide layer is continued with a corresponding recess in the remainder of the spacer wafer; this further recess therefore has at least a similar base area and at least similar cross-sections parallel to the second oxide layer as the recess in the second oxide layer.

[0016] The provision of the spacer wafer can accordingly comprise, for example, the following steps: providing a silicon wafer comprising the carrier substrate, partially oxidizing the silicon wafer, preferably thermally, to produce the first oxide layer on a surface of the carrier substrate, growing the silicon layer, preferably as an EpiPoly layer, on the first oxide layer, wherein the layer thickness is preferably 10-20 μm, producing the trenches in the silicon layer, for example by means of reactive ion etching (RIE) and / or deep reactive ion etching (DRIE) and / or, in particular in the case of relatively thin silicon layers, by means of a plasma etching process, producing the second oxide layer on the second surface of the silicon layer and filling the trenches with the passivation material, both, for example, thermally and / or by means of LPCVD,and finally, a partial removal of the second oxide layer to create the one or more recesses in the second oxide layer. The thickness of the first oxide layer is preferably selected such that it can function as a selective etch stop layer for the subsequent removal of the carrier substrate. Furthermore, the creation of the trenches and the removal of the second oxide layer are carried out such that the one or more recesses are each enclosed by one of the trenches, and the one or more recesses are arranged and configured such that an association is formed between the one or more recesses and the metal contacts, and all metal contacts can be simultaneously covered by the respective associated recess. In this procedure, the growth of an EpiPoly layer on the first oxide layer may involve the prior application of a polysilicon starter layer.for example, by means of CVD polysilicon deposition (CVD: chemical vapor deposition), onto the oxide layer, since polysilicon (polycrystalline silicon) typically cannot be epitaxially grown directly onto the oxide layer.

[0017] When providing the spacer wafer in this way, the carrier substrate, the first oxide layer on a surface of the carrier substrate and the silicon layer on the first oxide layer can also be provided directly in the form of a raw wafer such as an SOI wafer (SOI: Silicon-on-Insulator) and the further method steps for providing the spacer wafer can be carried out starting from this SOI wafer.

[0018] A coupled wafer comprising the functional wafer and the spacer wafer is produced by bonding the passivation layer of the functional wafer to the second oxide layer of the spacer wafer. This is done in such a way that each of the metal contacts is covered by the associated recess. Therefore, prior to this bonding, the metal contacts are preferably adjusted with regard to their positioning relative to the recesses. The bonding can be achieved, for example, using a direct bonding process, such as SiO2-SiO2 direct bonding. All process steps from this direct bonding process onward should preferably be carried out at a temperature below the limit typically permitted in the back-end-of-line (BEOL), for example, 450°C.

[0019] The carrier substrate of the spacer wafer is then removed, preferably by grinding and subsequent chemical-mechanical polishing (CMP). This procedure allows the carrier substrate to be removed with high precision. Alternatively, the removal can also be performed by a plasma-free or plasma-assisted silicon etching process, for example, using an SFβ etching gas, or by a combination of grinding, polishing, in particular CMP, and / or etching, for example, using SFe.

[0020] Finally, recesses are created in the spacer wafer such that the metal contacts are in contact with an external environment of the coupled wafer via the one or more recesses in the second oxide layer and the recesses now created in the spacer wafer. Access to the metal contacts is thus exposed. Creating the recesses in the spacer wafer preferably comprises partially removing the first oxide layer of the spacer wafer, for example by gas-phase etching, plasma etching, and / or wet etching, and subsequently etching the silicon layer, for example by etching with sulfur hexafluoride (SFe). In this case, the filled trenches preferably serve as an etch stop. Certain materials for the metal contacts, such as AlCu, Cu, and / or Au, are particularly advantageous when etched using SFe, since they are not attacked by SFe etching.As mentioned above, the shape of these recesses in the spacer wafer can continue the geometry of the recesses in the second oxide layer.

[0021] The trenches that provide access to the metal contacts can, for example, have inner walls that run parallel to one another and perpendicular to the second surface of the silicon layer. An inner wall of a trench refers to a lateral surface of the trench that faces inwards, i.e., into an inner region. Since the filled trenches in the silicon layer each enclose the recesses in the oxide layer and thus also a region of the silicon layer, they each have an inner region. It is also conceivable for the trenches to have inner walls that are not parallel to one another and run obliquely to the second surface of the silicon layer, with the distance between the inner walls increasing or decreasing with increasing distance from the second surface.This second, angled variant results in recesses in the spacer wafer that open or close outward and can be particularly advantageous for edge coverage of deposited layers, such as when applying over-pad metallization to the metal contacts. It can also have a positive effect on the performance of a soldering process for soldering the metal contacts.

[0022] The coupled wafer created in this way enables access to the metal contacts, enabling further processing steps within a manufacturing process. At the same time, the coupled wafer can be placed with the spacer wafer facing down on a support surface, such as a chuck, without the risk of damaging the metal contacts or any layers applied to the metal contacts. The spacer wafer processed according to the described method can therefore serve as a spacer in the subsequent manufacturing process and thus protect the functional wafer.

[0023] After the recesses have been created in the spacer wafer, an over-pad metallization (OPM) can be applied to the metal contacts. The OPM can, for example, be an ENEPIG coating (ENEPIG: electroless nickel, electroless palladium, immersion gold). Areas of the coupled wafer provided with silicon dioxide are not coated. Such a coating is typically applied with the metal contacts oriented upwards (i.e., against the direction of gravity). The metal contacts can be conditioned before application. Conditioning means cleaning and / or roughening the surface of the metal contacts in preparation for the application of the OPM, which may also result in the metal contacts being removed. Conditioning can, for example, be carried out by or include cleaning with an O^2 Ar plasma and / or back-sputtering (removing material using a sputtering process).During back sputtering, the second silicon dioxide layer can be removed.

[0024] After the OPM has been applied, a passivation layer, preferably a silicon dioxide layer, can be applied to the over-pad metallization. This can serve as additional protection to counteract potential chuck and / or environmental contamination, for example in a production facility. In the case of a silicon dioxide layer, this can later be removed without leaving any residue, for example by means of HF gas phase etching, plasma etching and / or wet chemical etching. Thereafter, if necessary after rotating the coupled wafer, for example about a longitudinal axis of the wafer, the coupled wafer can be placed on a support surface, for example a chuck, in such a way that only the spacer wafer is in contact with the support surface. The coupled wafer can then be further processed; for example, ME MS structures present in the functional wafer can be exposed.Such MEMS structures can, for example, be the structures for one or more MEMS components such as MEMS sensors and MEMS actuators, for example, MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors, and / or MEMS resonators. MEMS structures can be exposed in the functional layer using plasma-free and / or plasma-assisted etching. Such etching is preferably carried out using sulfur hexafluoride (SFe), xenon difluoride (XeF2), chlorine trifluoride (ClF3), and / or nitrogen trifluoride (NF3).

[0025] Finally, after exposing the MEMS structures, at least one or more oxide layers, for example the first oxide layer, can be at least partially removed from the spacer wafer, for example using an RF gas-phase etching, a plasma etching, and / or a wet-chemical etching. In this process step, any passivation layers applied to the OPM, for example silicon dioxide layers, and / or the passivation material of the filled trenches can also be removed. For example, a silicon dioxide layer used as a passivation layer on the OPM of the metal contacts is removed without residue using an RF gas-phase etching, a plasma etching, and / or a wet-chemical etching. If desired, specific areas can be protected from an RF gas-phase etching by applying non-stoichiometric silicon nitride.

[0026] Furthermore, it is conceivable that the metal contacts are connected to one or more components, for example, electronic components such as ASICs (ASIC: application-specific integrated circuit) and / or MEMS components, or a component wafer such as an ASIC wafer or a MEMS wafer, preferably to establish electrical connections. Such a step can be performed, for example, before the coupled wafer is singulated into individual chips or MEMS components and is preferably carried out after any MEMS structures have been exposed. Alternatively, however, such a connection can also be performed after the coupled wafer has been singulated.

[0027] The silicon layer preferably contains one or more further trenches filled with an insulating material, wherein the insulating material can be, for example, silicon dioxide, silicon nitride, and / or silicon oxynitride. These one or more further trenches extend such that each of the further trenches encloses a trench surrounding a recess in the oxide layer. The insulating material can be identical to the passivation material of the trenches surrounding the recesses in the oxide layer. The further trenches improve the electrical insulation of the metal contacts in the coupled wafer and exist in addition to the trenches filled with the insulating material, which enclose the recesses in the oxide layer and serve as an etch stop during the creation of the recess in the spacer wafer.Any geometries and arrangements are conceivable for the one or more additional trenches, for example, that an additional trench encloses several recesses in the oxide layer.

[0028] Finally, the coupled wafer can be singulated, optionally including a component wafer already connected to the coupled wafer, in order to obtain, for example, individual MEMS components or chips. It is particularly advantageous if, in this case, the recesses in the second oxide layer are formed in such a way that, after this singulation, a spacer structure, for example in the form of a frame and / or individual support structures, for example in corners of the MEMS components or chips, remains on the spacer wafer for each chip or MEMS component formed. This can ensure at least partial protection of the chips or MEMS components even after singulation, in particular if the metal contacts are still exposed, i.e., have not yet been used to connect components or a component wafer.

[0029] According to a second aspect of the invention, a coupled wafer is proposed, preferably produced by a method as described above, wherein the coupled wafer comprises a functional wafer, for example a MEMS wafer, with a functional layer, a passivation layer and metal contacts, wherein the passivation layer and the metal contacts are arranged on a surface of the functional layer.The coupled wafer further comprises a spacer wafer, wherein the spacer wafer comprises a silicon layer having trenches filled with a passivation material, a first oxide layer on a first surface of the silicon layer, a second oxide layer on a second surface of the silicon layer opposite the first surface, and a carrier substrate arranged on the first oxide layer, wherein the second oxide layer has one or more recesses, each of which is enclosed by one of the trenches, wherein the recesses are arranged and configured such that an association is formed between the one or more recesses and the metal contacts, and all metal contacts are simultaneously covered by the respective recess assigned to them. In this case, the filled trenches can be filled, for example, with silicon dioxide, silicon nitride, and / or silicon oxynitride as a passivation material.

[0030] The passivation layer of the functional wafer is connected to the second oxide layer of the spacer wafer in such a way that each of the metal contacts is covered by the associated recess, and further recesses exist in the spacer wafer in such a way that the metal contacts are in contact with an external environment of the coupled wafer via the one or more recesses of the second oxide layer and the recesses in the spacer wafer.

[0031] Advantages of the invention

[0032] The advantages of the invention are manifold. The invention discloses a method for producing a defined spacer wafer made of silicon and its integration and further processing within the scope of chip or MEMS component production. The spacer wafer processed according to the invention, which serves as a spacer, makes it possible to protect metal contacts extending from the functional wafer while still allowing them to be further processed through appropriate openings, in particular enabling electrical coupling to other components such as an ASIC or a corresponding component wafer. Even after the coupled wafer has been singulated, spacer structures can be provided for the individual chips or MEMS components based on the spacer wafer.

[0033] The method's approach allows for a high degree of flexibility for adaptation to the precise conditions of the manufacturing process in which the invention is to be used. For example, the height of the spacer wafer can be selected to ensure safe handling of the coupled wafer. The coupled wafer can, for example, be placed with the spacer wafer facing down and thus be further processed in manufacturing systems lying on a chuck without risking chuck or system contamination. Applying an OPM to the metal contacts is also easily achieved thanks to the openings in the form of recesses in the spacer wafer, and the height of the spacer wafer can be adapted to the height of the OPM layer.

[0034] The method according to the invention and a coupled wafer according to the invention further offer a large number of advantageous variants with which they can be adapted to the respective required conditions:

[0035] For example, the metal contacts can be provided with a silicon dioxide layer for protection during further processing, which can be removed later along with other oxide layers, for example by means of HF gas phase etching.

[0036] In the spacer wafer, additional trenches filled with an insulating material can be integrated into the silicon layer between the created recesses for better electrical insulation of the metal contacts.

[0037] The walls created by the recesses in the silicon layer of the spacer wafer serve as a solder stop during the subsequent soldering process. This prevents uncontrolled flow of the solder.

[0038] The invention can be used for virtually any arrangement of metal contacts. Furthermore, different geometries can be created for the recesses in the second oxide layer and generally in the spacer wafer, which can be varied as desired within an arrangement of metal contacts.

[0039] Short description of the drawings

[0040] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0041] They show:

[0042] Figures 1 A to 1 J are schematic representations of cross sections of

[0043] Wafers for explaining a method according to the invention for producing a coupled wafer according to the invention;

[0044] Figures 2A, 2B are schematic representations of cross sections of coupled wafers according to the invention when using an OPM with a passivation layer;

[0045] Figures 3A to 3C are schematic representations of coupled wafers according to the invention for explaining a method according to the invention when using additional trenches for electrical insulation;

[0046] Figure 4 shows schematic representations of cross sections of exemplary embodiments of metal contacts and the walls surrounding them in a coupled wafer according to the invention;

[0047] Figure 5 shows schematic representations of exemplary variants of the arrangement of metal contacts in a coupled wafer according to the invention;

[0048] Figure 6 shows schematic representations of exemplary possible configurations of recesses for metal contacts in a coupled wafer according to the invention; and Figure 7 shows, in schematic form as a flow chart, an exemplary method according to the invention for producing a coupled wafer according to the invention.

[0049] Embodiments of the invention

[0050] In the following description of the embodiments of the invention, identical or similar elements are designated by identical reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only depict the subject matter of the invention schematically. Furthermore, for the sake of clarity, the individual elements shown in Figures 1A to 6, such as layers, trenches, and regions, are provided with reference numerals purely by way of example.

[0051] Figures 1 A to 1 J show schematic cross-sectional views to explain an exemplary method according to the invention for producing a coupled wafer according to the invention as well as such a coupled wafer in cross-sectional views.

[0052] In detail, Figure 1A shows a schematic representation of a cross-section through a functional wafer 110, which has a functional layer 140 and a passivation layer 130 on a surface 142 of the functional layer 140. The functional wafer 110 also comprises metal contacts 120, which are also arranged on the surface 142 and are laterally enclosed by the passivation layer 130. The metal contacts 120 are thus arranged in recesses of the passivation layer 130. The passivation layer 130 can, for example, consist of silicon dioxide and / or silicon nitride or comprise these materials. The functional layer 140 can have MEMS structures. For better clarity, it is only partially shown with these MEMS structures in this and the following figures; instead, the functional layer 140 is shown in most figures only limited to the area near the passivation layer 130.This reduced representation is symbolized by a wave-shaped boundary of the drawn functional layer 140.

[0053] Figure 1B shows a schematic representation in the upper part of Figure S of a cross-section through a spacer wafer 150 having a carrier substrate 180, for example made of silicon. The spacer wafer 150 further comprises a first oxide layer 170, for example comprising or consisting of silicon dioxide and / or silicon nitride, which is applied to a surface 184 of the carrier substrate 180. On this first oxide layer 170, in turn, is a silicon layer 160, preferably an EpiPoly layer, which is in contact with the first oxide layer 170 by a first surface 162. Trenches 166 exist in the silicon layer 160, which are filled with a passivation material such as silicon dioxide, silicon nitride and / or silicon oxynitride and laterally enclose certain regions 161 of the silicon layer 160, thus separating them from the rest of the silicon layer 160.This is illustrated in the lower sub-figure T, which shows a section through the silicon layer 160 and the trenches 166, the course of which is marked in the upper sub-figure S by a dashed line T. As can be seen in the lower sub-figure T, the trenches 166 each form frames for the regions 161 of the silicon layer 160. For the sake of clarity, exemplary corresponding points in the two sub-figures S and T are connected to one another by dashed lines 168. Furthermore, a dashed line S is drawn in sub-figure T, which clarifies the position of the cross-section shown in sub-figure S.

[0054] A second oxide layer 190 with recesses 192 is applied to the second surface 164 opposite the first surface 162 of the silicon layer 160. The trenches 166 run through the entire thickness of the silicon layer 160, i.e., from the first surface 162 to the second surface 164, and thus connect the first oxide layer 170 to the second oxide layer 190. The recesses 192 are positioned such that they are each enclosed by one of the trenches 166. As can be seen, the recesses 192 are further arranged and configured such that an association is formed between the recesses 192 and the metal contacts 120 of the functional wafer 110, and all metal contacts 120 can be simultaneously covered by the respective recess 192 assigned to them.

[0055] Figure 1C now shows a coupled wafer 100, which was produced by connecting the functional wafer 110 and the spacer wafer 150 from Figures 1A and 1B. For this purpose, connections were made between the passivation layer 130 of the functional wafer 110 and the second oxide layer 190 of the spacer wafer 150. Each of the metal contacts 120 is covered by its associated recess 192 in the second oxide layer 190. Cavities 132 are defined by the recesses in the passivation layer 130 and the recesses 192 in the second oxide layer 190. The coupled wafer 100 is located in an external environment 105.

[0056] After the coupled wafer 100 has been produced, it is further processed, as shown in Figure 1D, by removing the carrier substrate, for example, by grinding and subsequent CMP. Recesses 152 can then be specifically created in the spacer wafer 150 using etching processes as shown in Figures 1E and 1F. In detail, this takes place in two steps: First, as shown in Figure 1E, recesses are created in the first oxide layer 170, for example, by gas-phase etching, plasma etching, and / or wet etching. Then, as shown in Figure 1F, recesses are created in the silicon layer 160, for example, by SFβ etching.

[0057] In the example shown, this is done directly above the metal contacts 120 by removing the regions 161 enclosed by the trenches 166, whereby the metal contacts 120 are brought into contact with an external environment 105 of the coupled wafer 100 via the recesses 192 of the second oxide layer 190 and the recesses 152 in the spacer wafer 150. The filled trenches 166 serve as an etch stop during the removal of the regions 161.

[0058] The metal contacts 120 are preferably provided with an OPM coating. For this purpose, the metal contacts 120 can be conditioned beforehand. After such conditioning, if necessary, the OPM 122, for example ENEPIG, can be applied to the conditioned metal contacts 120, as shown in Figure 1G. The coupled wafer 100 can then be rotated about a longitudinal axis, represented in Figure 1G by an arrow 101, as shown in Figure 1H, and placed on a support surface 102, for example, a chuck 103, with the now protected rear side, i.e., with the metal contacts 120 facing downward.

[0059] Finally, structures, for example MEMS structures 144, can now be exposed in the functional layer 140. For this purpose, as shown in Figure 11, silicon is removed from the functional layer 140, for example using SFe, XeF2, ClF3 and / or NF3, thereby exposing any MEMS structures 144 that may be present. To graphically illustrate such a removal of silicon in the MEMS structures 144, different hatching was used for the MEMS structures 144 in Figures 1H and 11. The previously remaining parts of the first oxide layer 170 and the passivation material of the trenches 166 can then be removed, for example by means of an RF gas-phase etching. The upper part of Figure 1J shows the result of such an etching process. To prevent unwanted areas of oxide layers from being attacked, these can be provided with a silicon nitride and thus passivated against RF.In the example shown, such a procedure is dispensed with, as a result of which parts 131 of the layers 130, 190 around the metal contacts 120 are removed by the RF gas phase etching, wherein for the illustration in the figures it is assumed that in addition to the second oxide layer 190, the passivation layer 130 and the passivation material of the filled trenches 166 also consist at least partially of silicon dioxide and are attacked by the RF gas phase etching.

[0060] The coupled wafer 100 processed in this way can finally be connected to further components such as ASICs or even to wafers for such components. Figure 1J shows how the coupled wafer 100, with metal contacts 120 provided with OPM 122, is brought into contact with electrical contacts 126 of a component wafer 104, for example, an ASIC wafer, in order to establish electrical connections between the functional wafer 110 and the component wafer 104. Such a connection of the metal contacts 120 to the electrical contacts 126 can be achieved, for example, by means of a soldering process. The remaining parts of the silicon layer 160 serve as solder stop.

[0061] Figures 2A and 2B show, by means of schematic representations of cross sections, a variant of the method according to the invention from Figures 1A to 1J and a corresponding coupled wafer 100 according to the invention with an OPM (over-pad metallization) 122. In this variant, as shown in Figure 2A, a passivation layer 124, for example a silicon dioxide layer, is applied to the over-pad metallization 122. Such a passivation layer 124 counteracts chuck and / or environmental contamination by the over-pad metallization 122, as illustrated by Figure 2B, in which the coupled wafer 100 was placed on a support surface 102 of a chuck 103. In the case of a silicon dioxide layer, such a passivation layer 124 can later be removed without residue, for example by means of HF gas-phase etching.

[0062] Figures 3A to 3C show a further possible variant of the method according to the invention and of coupled wafers 100 according to the invention from Figures 1A to 1J in a schematic representation. In this variant, additional trenches 166 filled with an insulating material are used to provide electrical insulation. As for the passivation material of the filled trenches 166, silicon dioxide, silicon nitride, and / or silicon oxynitride, for example, can be used as the insulating material. Figure 3A shows, for illustration, in a schematic plan view of a portion of a coupled wafer 100, the general concept of the placement of these additional trenches 167 in relation to the metal contacts 120, the OPM 122, and the recesses 192 in the second oxide layer 190. For better comprehensibility, the elements relevant to understanding the concept have been drawn in, even if they would not actually be visible in a plan view.As can be seen, in this example, the additional trenches 167 are each arranged centrally between the metal contacts 120 in the form of a grid. However, this does not have to be the case; any geometries and arrangements of the additional trenches are conceivable, including the possibility of an additional trench enclosing several recesses 192 in the second oxide layer 190. Figures 3B and 3C show cross-sectional views of the coupled wafer 100 constructed according to this concept, once in Figure 3B with the metal contacts 120 oriented upwards and provided with an OPM 122, and once when applied to an ASIC wafer 104 in Figure 3C. It can be seen that the additional trenches 67 extend through the entire thickness of the silicon layer 160. In the coupled wafer 100 shown in Figure 3C, the first oxide layer 170 and the passivation material of the trenches 166 have been removed compared to the coupled wafer 100 in Figure 3B.However, the further trenches 167 in the silicon layer 160 remain filled to ensure electrical insulation.

[0063] Figure 4 shows, by way of example in sub-figures A and B as cross-sections, two variants for configurations of trenches 466a, 466b, which, within the scope of a method according to the invention and a coupled wafer according to the invention, serve to create access to metal contacts 420a, 420b of a

[0064] REVISED SHEET (RULE 91) ISA / EP functional wafers 410a, 410b. The coupled wafer comprising a functional wafer 410a, 410b and a spacer wafer 450a, 450b is shown only partially in the area around a metal contact 420a, 420b in both partial figures A and B. The illustrated metal contacts 420a, 420b are provided with an OPM 422a, 422b. Furthermore, as in the previous figures, as part of a coupled wafer according to the invention comprising the functional wafer 410a, 410b and a passivation layer 430a, 430b and a functional layer 440a, 440b of the functional wafer 410a and a spacer wafer 450a, 450b with a silicon layer 460a, 460b, trenches 466a, 466b in the silicon layer 460a, 460b, a first oxidation layer 470a, 470b and a second oxidation layer 490a, 490b with the recesses 492a, 492b.

[0065] As shown in sub-figure A of Figure 4, a spacer wafer 450a may have walls 467a extending parallel to each other and perpendicular to the second surface 464a of the silicon layer 460a, which walls are defined by the trenches 466a. Sub-figure B, however, shows trenches 466b extending obliquely with respect to the second surface 464b of the silicon layer 460b. The distance between the walls increases with increasing distance from the second surface 464b. Both variants thus result in different recesses 452a, 452b in the respective spacer wafer 450a, 450b, which together with the recesses 492a, 492b in the second oxidation layer 490a, 490b function as access points to the metal contacts 420a, 420b, wherein the variant of sub-figure B with the obliquely extending trenches 466b can be particularly advantageous when applying the OPM 422a, 422b and when carrying out a soldering process.

[0066] Figure 5 shows, in sub-figures A and B, in purely schematic form, exemplary variants of the arrangement of Meta II contacts 520a, 520b and the recesses 592a, 592b associated with them in a coupled wafer 500a, 500b according to the invention. In detail, the illustrations each show a section of a coupled wafer 500a, 500b in plan view, with only the components required for illustration, namely the respective second oxide layer 590a, 590b, the metal contacts 520a, 520b, the OPM 522a, 522b, and the recesses 592a, 592b in the second oxide layer 590a, 590b, being schematically illustrated. Here, sub-figure A of Figure 5 shows an arrangement of the metal contacts 520a in a grid and sub-figure B shows a completely free, asymmetrical arrangement of the metal contacts 520b.Furthermore, Figure 5 shows exemplary cases in which several metal contacts 520b, namely two metal contacts 520b and four metal contacts 520b, are each assigned to a common recess 592b and are covered by this.

[0067] Figure 6 shows schematic representations of four exemplary configurations A to D of recesses for metal contacts 620a, 620b, 620c, 620d in a coupled wafer according to the invention. As in Figure 5, these representations are limited to a simplified and partial top view. Each schematically depicts the respective second oxide layer 690a, 690b, 690c, 690d, the metal contacts 620a, 620b, 620c, 620d, the OPM 622a, 622b, 622c, 622d, and the recesses 692a, 692b, 692c, 692d in the second oxide layer 690a, 690b, 690c, 690d. Shown are various shapes for the recesses 692a, 692b, 692c, 692d, more specifically a recess 692a with a rectangular base, a recess 692b with a circular base, a recess 692c with a hexagonal base and a recess 692d with a hexagonal base covering two metal contacts 620d.The shapes of the recesses can be varied as desired within an arrangement of electrical contacts.

[0068] Finally, Figure 7 shows, in schematic form as a flowchart, an exemplary method according to the invention for producing a coupled wafer with MEMS structures in a functional wafer. In step 710, the functional wafer is provided with a functional layer comprising the MEMS structures, a passivation layer, and metal contacts, wherein the passivation layer and the metal contacts are arranged on a surface of the functional layer. Furthermore, a spacer wafer is provided 715, wherein the spacer wafer comprises a silicon layer having trenches filled with a passivation material, a first oxide layer on a first surface of the silicon layer, a second oxide layer on a second surface of the silicon layer opposite the first surface, and a carrier substrate arranged on the first oxide layer.In this case, the second oxide layer has recesses which are each enclosed by one of the trenches, wherein the recesses are arranged and designed such that an association between the recesses and the metal contacts is formed and all metal contacts can be covered at the same time by the respective recess assigned to them.

[0069] In step 720, a coupled wafer comprising the functional wafer and the spacer wafer is produced by bonding the passivation layer of the functional wafer to the second oxide layer of the spacer wafer. This is done in such a way that each of the metal contacts is covered by the associated recess. This is followed by removal 725 of the carrier substrate and creation 730 of recesses in the spacer wafer such that the metal contacts are in contact with an external environment of the coupled wafer via the recesses of the second oxide layer and the recesses in the spacer wafer.

[0070] To improve the electrical contact with components to be connected, conditioning 735 of the Meta II contacts can be carried out by back-sputtering and subsequent application 740 of an over-pad metallization onto the conditioned metal contacts.

[0071] Finally, for exposing MEMS structures 750 in the functional layer of the functional wafer, the coupled wafer can be placed 745 on a support surface such that only the spacer wafer is in contact with the support surface. This exposing MEMS structures 750 can be followed by at least partial removal 755 of oxide layers no longer required from the spacer wafer, preferably by means of RF gas-phase etching. Silicon nitride passivation for RF protection is conceivable here. Subsequently, in step 760, the exposed coupled wafer can be connected to a component wafer, such as an ASIC wafer, or to individual components, such as ASICs. Dicing can then take place to obtain the individual MEMS components, each of which has been created from the spacer wafer with a spacer structure.Instead of connecting to a component wafer or individual components before singulation, singulation can also be performed before connecting to individual components.

[0072] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of one skilled in the art.

Claims

Claims 1 . Method for producing a coupled wafer (100, 500a, 500b) with a spacer wafer (150, 450a, 450b) for protecting metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) of a functional wafer (110, 410a, 410b), comprising the following steps: a. Providing (710) the functional wafer (110, 410a, 410b) with a functional layer (140, 440a, 440b), a passivation layer (130, 430a, 430b) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d), wherein the passivation layer (130, 430a, 430b) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) are arranged on a surface (142) of the functional layer (140, 440a, 440b); b. Providing (715) the spacer wafer (150, 450a, 450b), wherein the spacer wafer (150, 450a, 450b) • a silicon layer (160, 460a, 460b) having trenches (166, 466a, 466b) filled with a passivation material; • a first oxide layer (170, 470a, 470b) on a first surface (162) of the silicon layer (160, 460a, 460b); • a second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) on a second surface (164, 464a, 464b) of the silicon layer (160, 460a, 460b) opposite the first surface (162); and • a carrier substrate (180) arranged on the first oxide layer (170, 470a, 470b), wherein the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) has one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d), which are each enclosed by one of the trenches (166, 466a, 466b) and are arranged and designed such that an assignment between the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) and all metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) can simultaneously be covered by the respective recess (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) assigned to them; c. Producing (720) a coupled wafer (100, 500a, 500b) comprising the functional wafer (110, 410a, 410b) and the spacer wafer (150, 450a, 450b) by connecting the passivation layer (130, 430a, 430b) of the functional wafer (110, 410a, 410b) to the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) of the spacer wafer (150, 450a, 450b) such that each of the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) is covered by the associated recess (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d); d. removing (725) the carrier substrate (180); and e.Creating (730) recesses (152, 452a, 452b) in the spacer wafer (150, 450a, 450b) such that the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) extend over the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) of the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) and the recesses (152, 452a, 452b) in the spacer wafer (150, 450a, 450b) are in contact with an external environment (105) of the coupled wafer (100, 500a, 500b).

2. The method according to claim 1, wherein after the creation (730) of the recesses (152, 452a, 452b) in the spacer wafer (150, 450a, 450b) an application (740) of an over-pad metallization (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d) is carried out on the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d), wherein before the application (740) of the over-pad metallization (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d) preferably a conditioning of the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) takes place.

3. The method according to claim 2, wherein after the application (740) of the over-pad metallization (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d) an application of a passivation layer (124), preferably a silicon dioxide layer onto which over-pad metallization (122, 422a, 422b, 522a, 522b, 622a, 622b, 622c, 622d) is applied 4. Method according to one of the preceding claims with the following further steps: • Placing (745) the coupled wafer (100, 500a, 500b) on a support surface (102) such that only the spacer wafer (150, 450a, 450b) is in contact with the support surface (102); and / or • Exposing (750) MEMS structures (144) in the functional layer (140, 440a, 440b), preferably by means of plasma-free and / or plasma-assisted etching and / or using SF6, XeF2, ClF3 and / or NF3.

5. The method according to claim 4, wherein after the exposing (750) of the MEMS structures (144), an at least partial removal (755) of one or more oxide layers (170, 470a, 470b) from the spacer wafer (150, 450a, 450b) is preferably carried out by means of HF gas phase etching.

6. The method according to any one of the preceding claims, wherein a connection (760) of the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) to one or more components and / or a component wafer (104) is carried out.

7. The method according to any one of the preceding claims, wherein the silicon layer (160, 460a, 460b) comprises one or more further trenches (167) filled with a second insulation material, wherein each of the one or more further trenches (167) encloses a trench (166, 466a, 466b) enclosing a recess (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) in the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d).

8. Method according to one of the preceding claims, wherein the trenches (166, 466a, 466b) • have inner walls (467a) extending parallel to one another and perpendicular to the second surface (164, 464a) of the silicon layer (160, 460a); or • have inner walls (467b) that are not parallel to one another and that extend obliquely to the second surface (464b) of the silicon layer (460b), wherein a distance between the inner walls (467b) increases or decreases with increasing distance from the second surface (464b).

9. Method according to one of the preceding claims, wherein at least one, preferably each of the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) in the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) has a rectangular base area, a circular base area or a hexagonal base area.

10. The method according to any one of the preceding claims, wherein providing (715) the spacer wafer (150, 450a, 450b) comprises the following steps: • Providing a silicon wafer comprising the carrier substrate (180), partially oxidizing the silicon wafer to produce the first oxide layer (170, 470a, 470b) on a surface (184) of the carrier substrate (180) and growing the silicon layer (160, 460a, 460b), preferably as an EpiPoly layer, on the first oxide layer (170, 470a, 470b); or Providing a raw wafer comprising the carrier substrate (180), the first oxide layer (170, 470a, 470b) on a surface (184) of the carrier substrate (180) and the silicon layer (160, 460a, 460b) on the first oxide layer (170, 470a, 470b); • Creating the trenches (166, 466a, 466b) in the silicon layer (160, 460a, 460b); • Producing the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) on the second surface (164, 464a, 464b) of the silicon layer (160, 460a, 460b) and filling the trenches (166, 466a, 466b) with the passivation material; and • partially removing the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) to produce the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) in the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d), wherein the creation of the trenches (166, 466a, 466b) and the removal of the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) are carried out in such a way that the one or more recesses (190, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) are each formed by one of the trenches (166, 466a, 466b) enclosed and the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) are arranged and designed such that an association between the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) is formed and all metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) can simultaneously be covered by the respective recess (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) assigned to them.

11. Coupled wafer (100, 500a, 500b), preferably produced by a method according to one of claims 1 to 10, comprising • a functional wafer (110, 410a, 410b) having a functional layer (140, 440a, 440b), a passivation layer (130, 430a, 430b) and metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d), wherein the passivation layer (130, 430a, 430b) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) are arranged on a surface (142) of the functional layer (140, 440a, 440b); and • a spacer wafer (150, 450a, 450b), wherein the spacer wafer (150, 450a, 450b) comprises a silicon layer (160, 460a, 460b) having trenches (166, 466a, 466b) filled with a passivation material, a first oxide layer (170, 470a, 470b) on a first surface (162) of the silicon layer (160, 460a, 460b), a second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) on a second surface (164, 464a, 464b) of the silicon layer opposite the first surface (162) (160, 460a, 460b) and a carrier substrate (180) arranged on the first oxide layer (170, 470a, 470b), wherein the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) has one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d), which are each enclosed by one of the trenches (166, 466a, 466b) and are arranged and designed such that an association between the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) and the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) is formed and all metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) are simultaneously covered by the respective recess (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) assigned to them, wherein the passivation layer (130, 430a, 430b) of the functional wafer (110, 410a, 410b) is connected to the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) of the spacer wafer (150, 450a, 450b) is that each of the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) is formed by the associated recess (192, 492a, 492b,592a, 592b, 692a, 692b, 692c, 692d), and further recesses (152, 452a, 452b) in the spacer wafer (150, 450a, 450b) exist such that the metal contacts (120, 420a, 420b, 520a, 520b, 620a, 620b, 620c, 620d) are connected via the one or more recesses (192, 492a, 492b, 592a, 592b, 692a, 692b, 692c, 692d) of the second oxide layer (190, 490a, 490b, 590a, 590b, 690a, 690b, 60c, 80d) and the recesses (152, 452a, 452b) in the spacer wafer (150, 450a, 450b) are in contact with an external environment (105) of the coupled wafer (100, 500a, 500b).

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