Semiconductor wafer providing method and semiconductor wafer providing system

Abstract

Disclosed is a semiconductor wafer providing method performed by a first entity, the semiconductor wafer providing method including: an acquisition step for acquiring a remaining wafer from a second entity; a processing step for processing a sliced surface of the remaining wafer; a growth step for growing a semiconductor crystal layer on the processed surface of the remaining wafer; and a wafer providing step for providing a new semiconductor wafer, which has at least a part of the semiconductor crystal layer grown on the processed surface of the remaining wafer, to a second entity that is the same as or different from the acquisition source of the remaining wafer.

Description

Semiconductor wafer providing method and semiconductor wafer providing system

[0001] The present invention relates generally to providing semiconductor wafers.

[0002] Generally, in the process of cutting out a plurality of semiconductor chips from a semiconductor wafer, devices (e.g., electrodes and wiring patterns) are formed on the front surface of the semiconductor wafer, and the back surface of the semiconductor wafer is ground to thin the semiconductor wafer (e.g., Patent Document 1).

[0003] JP 2022-66988 A

[0004] Grinding the backside of the semiconductor wafer produces grinding debris, which is discarded.

[0005] Generally, semiconductor wafers are thinned to less than half of their original thickness, so more than half of the semiconductor wafer becomes grinding waste (for example, when a semiconductor wafer is thinned from 350 μm to 100 μm, more than 70% becomes grinding waste).

[0006] A semiconductor wafer providing method is performed by a first entity. The semiconductor wafer providing method includes an obtaining step, a processing step, a growth step, and a wafer providing step. In the obtaining step, a remaining wafer is obtained from a second entity, the remaining wafer being a semiconductor wafer portion having a second main surface, the remaining wafer being sliced ​​from a semiconductor wafer having a device on the first main surface out of a first main surface and a second main surface. In the processing step, the sliced ​​surface of the remaining wafer is processed. In the growth step, a semiconductor crystal layer is grown on the processed surface of the remaining wafer. In the wafer providing step, a new semiconductor wafer having at least a portion of the semiconductor crystal layer grown on the processed surface of the remaining wafer is provided to the second entity, which may be the same as or different from the entity from which the remaining wafer was obtained.

[0007] A main wafer, which is a semiconductor wafer portion having a first main surface, is used by the second entity, but the remaining wafer other than the main wafer among the semiconductor wafers is not discarded as grinding waste, but can be reclaimed by the first entity into a new semiconductor wafer and provided to the second entity.

[0008] 1 shows an example of the overall configuration of a system according to a first embodiment of the present invention; FIG. 2 shows the transition of the state of a slice surface; FIG. 3 shows a schematic diagram of a thermal etching process in a first example of a processing step according to a second embodiment of the present invention; FIG. 4 shows a schematic diagram of a surface oxidation process in a second example of a processing step according to a second embodiment of the present invention; and FIG. 5 shows a schematic diagram of a plasma etching process in a third example of a processing step according to a second embodiment of the present invention.

[0009] In the following description, an "interface apparatus" may be one or more interface devices. The one or more interface devices may be at least one of the following: - One or more I / O (Input / Output) interface devices. The I / O (Input / Output) interface device is an interface device for at least one of an I / O device and a remote display computer. The I / O interface device for the display computer may be a communication interface device. The at least one I / O device may be a user interface device, for example, either an input device such as a keyboard and a pointing device, or an output device such as a display device. - One or more communication interface devices. The one or more communication interface devices may be one or more homogeneous communication interface devices (e.g., one or more NICs (Network Interface Cards)) or two or more heterogeneous communication interface devices (e.g., a NIC and an HBA (Host Bus Adapter)).

[0010] In the following description, the term "memory" refers to one or more memory devices, which are an example of one or more storage devices, and may typically be a primary storage device. At least one memory device in the memory may be a volatile memory device or a non-volatile memory device.

[0011] In the following description, a "persistent storage device" may refer to one or more persistent storage devices, which are an example of one or more storage devices. A persistent storage device may typically be a non-volatile storage device (e.g., an auxiliary storage device), and more specifically, may be, for example, a hard disk drive (HDD), a solid state drive (SSD), a non-volatile memory express (NVME) drive, or a storage class memory (SCM).

[0012] In the following description, the term "storage device" may refer to at least one of memory and persistent storage device.

[0013] In the following description, a "processor" may refer to one or more processor devices. The at least one processor device may typically be a microprocessor device such as a CPU (Central Processing Unit), but may also be another type of processor device such as a GPU (Graphics Processing Unit). The at least one processor device may be a single-core or multi-core device. The at least one processor device may also be a processor core. At least one processor device may be a processor device in a broad sense, such as a circuit that is a collection of gate arrays written in a hardware description language that performs part or all of the processing (for example, an FPGA (Field-Programmable Gate Array), a CPLD (Complex Programmable Logic Device), or an ASIC (Application Specific Integrated Circuit)).

[0014] Furthermore, in the following description, functions may be described using the expression "yyy unit." However, the functions may be realized by one or more computer programs executed by a processor, by one or more hardware circuits (e.g., FPGAs or ASICs), or by a combination thereof. When a function is realized by a program executed by a processor, the specified processing is performed using a storage device and / or an interface device, etc., as appropriate, and therefore the function may be considered to be at least a part of the processor. Processing described using a function as the subject may be processing performed by a processor or a device having the processor. A program may be installed from a program source. The program source may be, for example, a program distribution computer or a computer-readable recording medium (e.g., a non-transitory recording medium). The description of each function is an example, and multiple functions may be combined into one function, or one function may be divided into multiple functions.

[0015] Hereinafter, several embodiments of the present invention will be described with reference to the drawings. In the following description, the semiconductor wafer is a SiC (silicon carbide) wafer, but the present invention can also be applied to semiconductor wafers other than SiC wafers. Examples of semiconductor wafers other than SiC wafers include GaN (gallium nitride), AlN (aluminum nitride) wafers, and diamond wafers. [First embodiment]

[0016] FIG. 1 shows an example of the overall configuration of a system according to a first embodiment of the present invention.

[0017] The surface device step and the laser slicing step are performed in a second entity. The second entity may be a device manufacturer that extracts SiC chips from the SiC wafer 40 and provides SiC chips or devices having SiC chips. The SiC wafer 40 is roughly divided into a layer serving as a base SiC crystal and a layer serving as a grown SiC crystal (oriented SiC crystal). The grown SiC crystal has a lower density of BPDs (basal plane dislocations) than the base SiC crystal.

[0018] In the surface device step, devices are formed on the first main surface (front surface) of the SiC wafer 40. The devices may include electrodes and wiring patterns.

[0019] In the laser slicing step, the SiC wafer 40 having the device is sliced ​​along the surface direction (a direction perpendicular to the thickness direction, in other words, a direction parallel to the first main surface) using a laser device. Specifically, for example, the laser device irradiates the interior of the SiC wafer 40 with a laser (e.g., a pulsed laser) from the second main surface (rear surface) side of the SiC wafer 40. As a result, a modified layer is formed inside the SiC wafer 40 along the surface direction. Starting from the modified layer, the SiC wafer 40 is divided into a main wafer 111, which is the SiC wafer portion having the first main surface, and a remaining wafer 112, which is the SiC wafer portion having the second main surface. The main wafer 111 includes a grown SiC crystal but does not include an underlying SiC crystal. The remaining wafer 112 includes an underlying SiC crystal and may also include some grown SiC crystal.

[0020] The acquisition step, processing step, growth step, and wafer providing step are performed in a first entity different from the second entity (in this embodiment, an inspection step is also performed between the acquisition step and the processing step, as will be described later). The first entity is a company that provides a new service, that is, a company that performs a service of acquiring (recovering) a remaining wafer 112 of a SiC wafer 40 from the second entity, growing a SiC crystal on the remaining wafer 112 to reclaim the SiC wafer 40, and providing the reclaimed SiC wafer 40 to the same or a different second entity. One or more second entities exist for one first entity.

[0021] In the acquisition step, the remaining wafer 112 is acquired from a second entity. In the processing step, the sliced ​​surface of the remaining wafer 112 is processed. In the growth step, a grown SiC crystal (an example of a semiconductor crystal layer) is grown on the processed surface of the remaining wafer 112. In the wafer provision step, a new SiC wafer 40 having at least a portion of the grown SiC crystal grown on the processed surface of the remaining wafer 112 is provided to the second entity, which may be the same as or different from the entity from which the remaining wafer 112 was acquired.

[0022] The remaining wafer 112 can be reclaimed by the first entity into a new semiconductor wafer and provided to the second entity, rather than being discarded as grinding waste.

[0023] The processing step may be performed by a processing device 172, and the growth step may be performed by a growth device 173 (the inspection step described below may be performed by an inspection device 171). Furthermore, the first entity may use a first entity terminal 174, which is an information processing terminal such as a personal computer or a smartphone.

[0024] A wafer provision support system 180 is provided that communicates with at least one of the inspection apparatus 171, the processing apparatus 172, the growth apparatus 173, and the first entity terminal 174, for example, via a communication network. The wafer provision support system 180 supports the provision of SiC wafers 40. In this embodiment, the wafer provision support system 180 is a physical computer system (one or more physical computers), but may also be a logical computer system (for example, a system on a cloud platform) based on a physical computer system (for example, a cloud platform). The wafer provision support system 180 includes an interface device 181, a storage device 182, and a processor 183 connected thereto.

[0025] Through the interface device 181, communication is performed with at least one of the inspection device 171, the processing device 172, the growth device 173, and the first entity terminal 174.

[0026] The storage device 182 stores management information 191. The management information 191 is information for managing at least a part of the process from the acquisition step to the wafer provision step, and includes, for example, at least a part of the information input through the interface device 181, and also includes information output to the processing device 172, the growth device 173, or the first entity terminal 174, and information on which that information is based. The storage device 182 also stores a computer program to be executed by the processor 183.

[0027] The processor 183 reads and executes a computer program from the storage device 182, thereby realizing functions such as a support unit 192 for supporting the provision of SiC wafers 40.

[0028] Hereinafter, among the steps in the first entity, the acquisition step, processing step, growth step, and wafer provision step will be described first, and then the inspection step will be described.

[0029] In the acquisition step, remaining wafers 112 are acquired from one or more second entities. Any number of remaining wafers 112 may be sent to the first entity at any timing from the second entity. Alternatively, an acquisition schedule including the number and acquisition time of remaining wafers 112 to be acquired from each of the one or more second entities may be shared between the second entity and the first entity, and the remaining wafers 112 may be acquired from the second entity according to the acquisition schedule. Information representing the acquisition schedule of each second entity may be included in the management information 191. For example, the support unit 192 may accept an input of the acquisition schedule from a second entity system (not shown) or the first entity terminal 174 via the interface device 181 and store information representing the acquisition schedule in the storage device 182. Similar to the wafer provision support system 180, the second entity system may be either a physical computer system or a logical computer system, and may include, for example, an information processing terminal such as a personal computer in the second entity. <Processing Step>

[0030] The processing in the processing step includes cutting (typically grinding and / or polishing) the sliced ​​surface and removing the process-affected layer including the cut sliced ​​surface. The processing device 172 may include, for example, a device (e.g., a grinder) for grinding and / or polishing the sliced ​​surface and a device for removing the process-affected layer, or these devices may be integrated (i.e., cutting and removal may be performed by a single device). For example, the processing device 172 may be a device for grinding and polishing, such as a CMP (Chemical Mechanical Polishing) method. <Growth Step>

[0031] In the processing step, the remaining wafer 112 is processed to obtain a seed crystal 113. The seed crystal 113 may be composed of only a base SiC crystal, or may be composed of a base SiC crystal and a portion of oriented SiC crystal. In a growth device 173, a grown SiC crystal (oriented SiC crystal) 114 is grown on the seed crystal 113 (the processed remaining wafer). This crystal growth may be performed by sublimation or CVD (Chemical Vapor Deposition), or by other methods. <Wafer Providing Step>

[0032] A new SiC wafer 40 composed of the seed crystal 113 (processed remainder wafer) and the grown SiC crystal 114 is provided to a second entity that may be the same as or different from the source of the remainder wafer on which the SiC wafer is based. In this way, the acquired remainder wafer 112 is regenerated into such a new SiC wafer 40 and provided to the second entity, so that the second entity can obtain a main wafer from the SiC wafer 40. Note that in the wafer providing step, the support unit 192 may select a packaging material for the new SiC wafer 40, and a worker may place the new SiC wafer 40 in the packaging material selected by the support unit 192 and provide the new SiC wafer 40. This reduces the risk of cracks or breakage occurring in the new SiC wafer 40 during delivery of the new SiC wafer 40 to the second entity.

[0033] The above is a description of the obtaining step, processing step, growing step, and wafer providing step.

[0034] In this embodiment, an inspection step for inspecting the sliced ​​surface of the acquired remaining wafer 112 is provided between the acquisition step and the processing step. The inspection step is, for example, as follows:

[0035] The inspection in the inspection step includes measuring at least one of the height difference of the sliced ​​surface and the thickness of the process-affected layer having the sliced ​​surface. In this embodiment, both are measured. The height difference of the sliced ​​surface is the height difference caused by the uneven shape of the surface (represented by the jagged shape in FIG. 2 described later) that occurs due to the laser irradiation in the laser slicing step or the division into the main wafer 111 and the remaining wafer 112.

[0036] The inspection step is performed by an inspection device 171. The inspection device 171 may include a laser microscope and a Raman spectrometer. The laser microscope may be used to measure the height difference of the sliced ​​surface. The Raman spectrometer may be used to measure the thickness of the processing-affected layer. The measurement methods for both the height difference of the sliced ​​surface and the thickness of the processing-affected layer are not limited to this example. For example, the height difference of the sliced ​​surface may be measured by a white light interferometer or a contact-type shape measuring machine.

[0037] The support unit 192 receives information representing the measured height difference of the slice plane from the inspection device 171 or the first entity terminal 174, and stores the information in the storage device 182 as part of the management information 191. The support unit 192 also receives information representing the measured thickness of the processing-affected layer from the inspection device 171 or the first entity terminal 174, and stores the information in the storage device 182 as part of the management information 191.

[0038] At least one of the following (x) and (y) may be performed. The processing in the (x) processing step includes determining the amount of removal of the sliced ​​surfaces based on at least one of the measured height difference of the sliced ​​surfaces of the remaining wafer 112 and the measured thickness of the processed-affected layer, and removing the sliced ​​surfaces according to the determined removal amount. This allows appropriate (neither excessive nor insufficient) sliced ​​surface processing to be performed according to the acquired quality (state) of the remaining wafer 112. Specifically, for example, the support unit 192 determines the amount of removal of the sliced ​​surfaces based on information (information in the management information 191) representing at least one of the measured height difference of the sliced ​​surfaces and the measured thickness of the processed-affected layer, and stores information representing the determined removal amount in the storage device 182 as part of the management information 191. For example, if the PV value (maximum valley depth) is measured as an example of the height difference of the sliced ​​surfaces and the processed-affected layer depth is measured as an example of the thickness of the processed-affected layer, the removal amount may be calculated as PV value + (processing-affected layer depth × N). N may be any value greater than 0 (e.g., any natural number). The support unit 192 may output information representing the cutting amount to the first entity terminal 174, and the processing device 172 may process the sliced ​​surface according to the cutting amount in response to an operation from an operator who has viewed the cutting amount. Alternatively, the support unit 192 may input a processing command associated with the information representing the cutting amount to the processing device 172 (or a control device of the processing device 172), and the processing device 172 may thereby process the sliced ​​surface according to the cutting amount. The "cutting amount" may be defined by parameter values ​​for one or more parameter items. For example, the parameter items may include the length of time for processing by the processing device 172 and the processing power (e.g., temperature, pressure, etc.). In the (y) growth step, the thickness of the grown SiC crystal is determined based on at least one of the measured height difference of the sliced ​​surface of the remaining wafer 112 and the measured thickness of the processing-affected layer, and the grown SiC crystal is grown to the determined thickness. This allows for appropriate (just enough) crystal growth to be performed according to the quality (condition) of the obtained remaining wafer 112.Specifically, for example, the support unit 192 determines the thickness of the grown SiC crystal based on information (information in the management information 191) representing at least one of the measured height difference of the slice surface and the measured thickness of the process-affected layer, and stores information representing the determined thickness (how thick the grown SiC crystal should be grown) in the storage device 182 as part of the management information 191. For example, the grown thickness may be determined based on at least one of X, Y, Z, and α. Specifically, for example, the grown thickness may be X-Y+Z+α. X may be the thickness required at the start of the surface device step or the laser slicing step in the second entity (the thickness required by the second entity). Y may be the thickness of the grown SiC crystal at the time of receipt by the first entity. Z may be the amount of removal determined in (x) above. α may be any value (e.g., approximately 50 μm) determined as a processing allowance (processing margin) for removing irregularities and flattening the grown SiC crystal. The support unit 192 may output information representing the thickness to the first entity terminal 174, and in response to an operation by an operator who views the thickness, the growth device 173 may grow a grown SiC crystal of that thickness on the seed crystal. Alternatively, the support unit 192 may input a crystal growth command associated with information representing the thickness to the growth device 173 (or a control device for the growth device 173), which causes the growth device 173 to grow a grown SiC crystal of that thickness on the seed crystal. [Second Embodiment]

[0039] The second embodiment will be described, focusing mainly on the differences from the first embodiment, and explanations of the commonalities with the first embodiment will be omitted or simplified.

[0040] In the second embodiment, crystal growth in the growth step is performed using a method disclosed in a prior application WO 2023 / 067736 filed by the same applicant as the present application (hereinafter, for convenience, this method will be referred to as the "NGK method" based on the applicant's notation). That is, in the growth step, a SiC single crystal serving as a seed crystal and a SiC powder layer are placed in a container while in contact with each other, and the container is placed in a firing furnace and heat-treated, thereby growing a SiC single crystal on the seed crystal. The NGK method can produce a SiC single crystal (grown SiC crystal) with a lower BPD density than that obtained by sublimation deposition and a similar BPD density to that obtained by CVD. The second embodiment can incorporate all or part of the technology disclosed in WO 2023 / 067736.

[0041] When crystal growth is performed by the NGK method, the surface after processing may have a lower flatness than when crystal growth is performed by sublimation or CVD, and the surface after processing does not need to be completely flat, as shown in Figure 2. Specifically, for example, it is as follows.

[0042] When homoepitaxial growth is performed on a seed crystal by sublimation or CVD, it is usually essential that the growth surface be atomically flat and that there be no process-affected layer, because this can cause unevenness on the epitaxial growth surface and defects such as dislocations to appear in the crystal.

[0043] On the other hand, SiC wafers are hard and stable against heat and chemicals, so planarizing the surface or removing processing damage by CMP after slicing or grinding takes a very long time and also results in significant consumption of polishing slurry, polishing pads, etc.

[0044] Therefore, in this embodiment, the removal of the damaged layer in the processing step is performed by a thermal etching process, a surface oxidation process, or a plasma etching process (i.e., any process that results in lower flatness after etching than etching by CMP). Examples of each process related to the removal of the damaged layer in the processing step according to the second embodiment will be described below. Note that in this embodiment, etching other than the thermal etching process, surface oxidation process, and plasma etching process, such as etching by CMP, or other etching processes (e.g., hydrogen etching) may also be performed.

[0045] FIG. 3 shows a schematic diagram of the thermal etching process.

[0046] The processing device 172 may include a device that removes the damaged layer by a thermal etching process. Such a device is illustrated in Fig. 3. In the thermal etching process, the surface of the remaining wafer (including the damaged layer) that has been heated and processed in an electric furnace 302 is sublimated to a thickness of about several microns.

[0047] For example, a gas (e.g., an inert gas such as nitrogen or argon) is introduced through a gas pipe 305 into an electric furnace 302 made of a heat insulating material and provided with a heater 301, creating an inert gas atmosphere inside the electric furnace 302. The inside of the electric furnace 302 may also be a vacuum atmosphere.

[0048] Heating is performed by the heater 301, and the maximum heat treatment temperature is within a certain temperature range (for example, 1000 to 2000°C) and may be set taking into account the required etching amount (for example, 1800°C). The maximum temperature is maintained for a certain time range (for example, 1 minute to 5 hours) and may be set taking into account the required etching amount (for example, 1 hour). The "required etching amount," "maximum heat treatment temperature," and "maximum temperature maintenance time" may each be an example of at least one element of the removal amount, and may be determined by the support unit 192 based on the measured thickness of the work-affected layer.

[0049] The remaining wafer 112 (e.g., the remaining wafer 112 whose surface has been ground) may be placed on a setter 303 (e.g., graphite) on a spacer 304 (e.g., graphite), or may be placed using a sheath or the like made of a heat-resistant material.

[0050] If the surface of the remaining wafer 112 is carbonized after this thermal etching process, the carbonized layer on the surface may be removed by separate annealing in an atmospheric furnace or the like, or by processing such as polishing. To prevent carbonization of the surface, a carbon getter material such as Ta may be placed in the electric furnace 302.

[0051] FIG. 4 shows a schematic diagram of the surface oxidation process.

[0052] The processing device 172 may include a device that removes a process-affected layer by a surface oxidation process. An example of such a device is shown in FIG. 4 . In the surface oxidation process, the surface (including the process-affected layer) of the remaining wafer that has been heated and processed in an oxidizing atmosphere (including the air atmosphere) in the electric furnace 402 is oxidized to a thickness of about several μm. The oxide film may be removed by processing such as polishing, or may be volatilized or melted (by reaction with the raw material powder) during crystal growth.

[0053] For example, in an electric furnace 402 made of insulating material and equipped with a heater 401, the maximum heat treatment temperature may be set within a certain temperature range (e.g., 800 to 2000°C) taking into account the required etching amount (e.g., 1400°C). Furthermore, the maximum temperature holding time may be set within a certain time range (e.g., 5 minutes to 50 hours) taking into account the required etching amount (e.g., 1 hour). The "required etching amount," "maximum heat treatment temperature," and "maximum temperature holding time" may each be an example of at least one element of the removal amount, and may be determined by the support unit 192 based on the measured thickness of the work-affected layer.

[0054] The remaining wafer 112 (for example, the remaining wafer 112 with its surface ground) may be placed on a setter 403 (for example, alumina) on a spacer 404 (for example, alumina).

[0055] FIG. 5 shows a schematic diagram of the plasma etching process.

[0056] The processing device 172 may include a device that removes the damaged layer by a plasma etching process. An example of such a device is shown in Fig. 5. In the plasma etching process, the surface of the processed remaining wafer (including the damaged layer) is etched to a depth of several micrometers.

[0057] Plasma etching includes reactive ion etching (RIE), electron cyclotron resonance (ECR), inductively coupled plasma (ICP), capacitively coupled plasma (CCP), etc., but is not particularly limited, and for example, RIE can be applied.

[0058] The substrate temperature, gas type, processing time, and apparatus configuration may be appropriately set depending on the desired etching rate and surface condition. The remaining wafer surface may be previously cleaned of surface deposits by ashing or the like.

[0059] An upper electrode 501 and a lower electrode 503 are disposed in a chamber 502, gas is introduced through a gas inlet pipe 505 and exhausted through a gas exhaust pipe 504, and plasma is generated between the electrodes 501 and 503 by a high frequency power supply 509s.

[0060] The above is a description of examples of each process related to removal of the damaged layer in the processing step according to the second embodiment. Note that there are also differences regarding crystal growth between the sublimation method, the CVD method, and the NGK method, for example, as follows.

[0061] That is, while the sublimation method and the CVD method require precision cleaning after CMP polishing and before forming the epitaxial layer, the NGK method does not require such cleaning.

[0062] Furthermore, in the sublimation and CVD methods, the temperature rise rate is fast, so warping of the seed crystal increases the possibility of seed crystal breakage. Furthermore, in the sublimation and CVD methods, multiple seed crystals can be placed in the chamber of the growth device, but even if one seed crystal breaks, it will affect the other seed crystals. On the other hand, in the NGK method, the temperature rise rate is slower than in the sublimation and CVD methods, so even if the seed crystal is slightly warped, the possibility of breakage due to the warping is low. Furthermore, in the NGK method, one seed crystal is stored in one container, so even if one seed crystal breaks, it will not affect the other seed crystals.

[0063] In both the second and first embodiments, the diameter of the remaining wafer 112 acquired in the acquisition step may be 6 inches or more, for example, the diameter of the remaining wafer may be 8 inches or more (e.g., the second embodiment). For example, whether the diameter is 6 inches or 8 inches, the thickness of the main wafer 111 may be approximately 100 μm, but when the diameter is 6 inches, the thickness of the remaining wafer 112 may be approximately 250 μm, and when the diameter is 8 inches, the thickness of the remaining wafer 112 may be approximately 400 μm. [Third Embodiment]

[0064] The third embodiment will be described below, focusing mainly on the differences from the first and second embodiments, and explanations of the commonalities with the first and second embodiments will be omitted or simplified.

[0065] A schedule determination step is performed. In the schedule determination step, a growth schedule for growing SiC crystals on the processed surfaces of the remnant wafers 112 is determined, for example, by the support unit 192, based on the acquisition schedule for each of the one or more second entities. The growth step is performed based on the growth schedule. This is expected to efficiently reclaim and provide SiC wafers. For example, if the acquisition schedule from the first second entity is "acquire 100 remnant wafers with a diameter of 6 inches in period X," and the acquisition schedule from the second second entity is "acquire 200 remnant wafers with a diameter of 8 inches from the second second entity in period X," a growth schedule for a total of 300 remnant wafers 112 may be determined based on these acquisition schedules. In other words, the determination of the growth schedule may be based on a combination of the acquisition time indicated by the acquisition schedule of each second entity, the number of remnant wafers 112 to be acquired, and the diameter of the remnant wafers 112 to be acquired. Additionally, the growth schedule may be determined based on the acquisition schedule of each second entity as well as the geographical distance between the second entity and the first entity and / or other factors.

[0066] Specifically, for example, the growth schedule may be determined based on at least one of the following (1) to (3): (1) A required growth thickness based on information about the remaining wafer 112 (e.g., the thickness determined in (y) above); (2) Information about a second entity from which the remaining wafer 112 is obtained and / or provided (e.g., information representing at least one of the name of the second entity, information about the SiC wafer used or to be used by the second entity (e.g., wafer manufacturer, grade, shape parameters (e.g., warpage), quality (e.g., defect density)), and specifications required by the second entity); (3) Processing conditions in the processing step (e.g., conditions according to the required processing thickness and surface condition identified based on the obtained information about the remaining wafer 112).

[0067] Specifically, for example, the growth schedule may be determined in the following manner. That is, the support unit 129 identifies the maximum required growth thickness obtained in (1) for all remaining wafers on which crystal growth is to be performed. Based on this information (maximum required growth thickness), the support unit 129 determines the maximum temperature and holding time during crystal growth (at the same time, the support unit 129 may determine the removal date and time, processing date and time, etc.). Furthermore, the support unit 129 determines the target quality (e.g., warpage, crystal defects, surface irregularities, etc.) for each remaining wafer based on (2) and (3) above, and determines parameters for controlling the crystal quality (e.g., temperature increase rate, temperature decrease rate, sheath arrangement, etc.) for each remaining wafer based on the determined target quality for that remaining wafer. Based on the information thus identified or determined, the support unit 129 calculates a growth schedule that can optimize the crystal growth thickness and quality (warpage, crystal defects, surface irregularities, etc.). [Fourth Embodiment]

[0068] The fourth embodiment will be described below, focusing mainly on the differences from the first to third embodiments, and explanations of the commonalities with the first to third embodiments will be omitted or simplified.

[0069] A classification step is performed. In the classification step, for each of the acquired remaining wafers 112, the support unit 192, for example, assigns a group ID to the remaining wafer 112 based on wafer information including information indicating at least one of the second entity from which the remaining wafer 112 was acquired (e.g., the name or address of the second entity) and the quality of the remaining wafer 112 (e.g., the quality identified in the inspection step and / or the quality after the processing step). For each group ID, one or more remaining wafers assigned the group ID are a collection of remaining wafers having the same or similar characteristics in the wafer information. Each remaining wafer 112 is subjected to a processing step and / or a step subsequent to the processing step based on the group ID assigned to the remaining wafer 112. For example, the remaining wafers 112 may be stored in a location corresponding to the assigned group ID. The wafer information may also include at least one of the name of the second entity, the manufacturer of the seed crystal, the quality level of the seed crystal, the thickness of the wafer or grown SiC crystal before or after processing, and the required amount of removal. The support unit 192 may use the wafer information of each remaining wafer 112 to schedule which wafers should be grouped together for efficient processing and growth, and then proceed with subsequent processing on a group-by-group basis. This is expected to minimize variations in processing and growth among wafers, and optimize processing and growth times. Among the wafer information, information indicating the shape, geometry, and thickness of the wafer may be used as the basis for classification (grouping), and classification may also be performed based on information related to the second entity (e.g., the name and address of the second entity). [Fifth Embodiment]

[0070] The fifth embodiment will be described below, focusing mainly on the differences from the first to fourth embodiments, and explanations of the commonalities with the first to fourth embodiments will be omitted or simplified.

[0071] An information providing step is performed. In the information providing step, the support unit 192, for example, provides information to each of one or more second entities (for example, to a second entity system (for example, a second entity terminal) of the second entity). The provided information includes information representing at least one of the following (1) to (3): (1) progress in the process from the remaining wafer 112 to the provision of a new SiC wafer 40 to the second entity; (2) if a defect is detected in the process, an identified or estimated cause of the defect; and (3) at least a second inspection result out of a first inspection result on the quality of the remaining wafer 112 and a second inspection result on the quality of the new SiC wafer 40 obtained from the remaining wafer 112 and provided to the second entity.

[0072] This allows the second entity to determine when it will receive new SiC wafers 40, the quality of the received SiC wafers 40, and the control of laser slicing. Furthermore, by sharing the acquired information on the depth of the process-affected layer (including, for example, crack depth) of the remaining wafer 112, the amount of chipping and scratches caused by slicing, and crystal defects and their variations, the second entity can improve the slicing conditions, which is expected to improve the processing time, growth time, and yield at the first entity. Furthermore, information on the yield at the first entity may be provided to the second entity, and the contract or other agreement between the first and second entities may be adjusted based on this information. [Sixth Embodiment]

[0073] The sixth embodiment will be described below, focusing mainly on the differences from the first to fifth embodiments, and explanations of the commonalities with the first to fifth embodiments will be omitted or simplified.

[0074] The provided SiC wafer 40 may be a wafer serving as a grown SiC crystal portion sliced ​​from a grown SiC crystal grown on the processed surface of the remaining wafer 112, instead of the SiC wafer 40 having the grown SiC crystal 114 and the seed crystal 113. In other words, a wafer may be provided that essentially serves as a substrate for the main wafer.

[0075] Furthermore, after the wafer providing step, another growth step may be performed. In the other growth step, a grown SiC crystal may be grown on a portion of the wafer other than the sliced ​​grown SiC crystal portion (an example of a semiconductor crystal layer portion) (for example, a wafer composed of at least the seed crystal out of the remainder of the grown SiC crystal and the seed crystal). The other growth step may be performed by growth apparatus 173.

[0076] Although one embodiment has been described above, this is merely an example for explaining the present invention, and the scope of the present invention is not limited to this embodiment. The present invention can be implemented in various other forms. For example, any two or more of the above-described embodiments may be combined.

[0077] 171... inspection device, 172... processing device, 173... growth device, 174... first entity terminal, 180... wafer provision support system

Claims

1. A semiconductor wafer providing method performed by a first entity, comprising: an acquiring step of acquiring from a second entity a remaining wafer, the remaining wafer being a semiconductor wafer portion having the second main surface and sliced ​​from a semiconductor wafer having a device on the first main surface out of a first main surface and a second main surface; a processing step of processing the sliced ​​surface of the remaining wafer; a growing step of growing a semiconductor crystal layer on the processed surface of the remaining wafer; and a wafer providing step of providing a new semiconductor wafer having at least a portion of the semiconductor crystal layer grown on the processed surface of the remaining wafer to the same or different second entity from which the remaining wafer was acquired.

2. A method for providing a semiconductor wafer as described in claim 1, further comprising an inspection step for inspecting the sliced ​​surfaces between the acquisition step and the processing step, the inspection in the inspection step including measuring at least one of a height difference of the sliced ​​surfaces and a thickness of a processing-damaged layer having the sliced ​​surfaces, and the processing in the processing step including determining an amount of removal of the sliced ​​surfaces based on at least one of the measured height difference of the sliced ​​surfaces and the measured thickness of the processing-damaged layer, and removing the sliced ​​surfaces in accordance with the determined amount of removal.

3. The method for providing a semiconductor wafer according to claim 2, wherein the determined amount of removal is a value obtained by adding the measured height difference of the sliced ​​surface to the product of the measured thickness of the process-affected layer and an arbitrary value.

4. A method for providing a semiconductor wafer as described in claim 1, further comprising an inspection step of inspecting the sliced ​​surfaces between the acquisition step and the processing step, the inspection in the inspection step including measuring at least one of a height difference of the sliced ​​surfaces and a thickness of a process-damaged layer having the sliced ​​surfaces, and the growth step determining a thickness to be grown of a semiconductor crystal layer based on at least one of the measured height difference of the sliced ​​surfaces and the measured thickness of the process-damaged layer, and growing the semiconductor crystal layer by the determined thickness.

5. The method for providing a semiconductor wafer as described in claim 4, wherein the processing in the processing step includes determining an amount of cutting of the sliced ​​surfaces based on at least one of a measured height difference of the sliced ​​surfaces and a measured thickness of the processed-altered layer, and cutting the sliced ​​surfaces in accordance with the determined amount of cutting, and the determined thickness is a thickness obtained by subtracting from the thickness required by the second entity the sum of the thickness of the semiconductor crystal layer at the time of receipt by the first entity, the determined amount of cutting, and an arbitrary value.

6. A method for providing a semiconductor wafer as described in claim 4, comprising a schedule determination step including the following processes: (a) identifying the determined maximum growth thickness value among all remaining wafers on which a semiconductor crystal layer is grown; (b) determining a maximum temperature and holding time during crystal growth based on the identified maximum growth thickness value; (c) determining a target quality for each remaining wafer based on information representing the warp and / or quality of the wafer used or to be used by the second entity from which the remaining wafer is obtained and / or to which the remaining wafer is provided, and information representing the processing conditions in the processing step; (d) determining parameters for controlling the crystal quality for each remaining wafer based on the determined target quality of the remaining wafer; and (e) calculating a growth schedule, which is a schedule for optimizing crystal growth thickness and quality and is a schedule for growing semiconductor crystals on the processed surface of the remaining wafer, from the information identified or determined in (a) to (d).

7. A method for providing a semiconductor wafer as described in claim 1, further comprising a schedule determination step of determining a growth schedule for a semiconductor crystal on the processed surface of the remaining wafer based on an acquisition schedule including the number and acquisition time of remaining wafers to be acquired from each of one or more second entities, and performing the growth step based on the determined growth schedule.

8. A semiconductor wafer providing method as described in claim 1, further comprising: a classification step of assigning a group ID to each of the acquired remaining wafers based on wafer information including information representing at least one of the second entity from which the remaining wafer was acquired and the quality of the remaining wafer; wherein for each group ID, one or more remaining wafers assigned with the group ID are a collection of remaining wafers having identical or similar characteristics of the wafer information; and each remaining wafer undergoes the processing step and / or a step subsequent to the processing step based on the group ID assigned to the remaining wafer.

9. The semiconductor wafer providing method according to claim 1, wherein in said wafer providing step, a packaging material for said new semiconductor wafer is selected, and said new semiconductor wafer is provided by placing said new semiconductor wafer in the selected packaging material.

10. A method for providing a semiconductor wafer as described in claim 1, comprising: an information providing step of providing information to each of one or more second entities, the information including information representing at least one of the following: - progress in the process from the remaining wafer to the provision of a new semiconductor wafer to the second entity; - if a defect is detected in the process, an identified or estimated cause of the defect; - at least a second inspection result out of a first inspection result on the quality of the remaining wafer and a second inspection result on the quality of the new semiconductor wafer obtained from the remaining wafer and provided to the second entity.

11. The method for providing a semiconductor wafer according to claim 1, wherein the semiconductor wafer is a SiC wafer, and in the growing step, a SiC single crystal as a seed crystal and a SiC powder layer are placed in a container while being in contact with each other, and the container is placed in a firing furnace for heat treatment, thereby growing a SiC single crystal on the seed crystal.

12. The method for providing a semiconductor wafer according to claim 1, wherein the new semiconductor wafer has the processed remaining wafer and a semiconductor crystal layer including a semiconductor crystal layer grown on the processed surface of the remaining wafer.

13. The method for providing a semiconductor wafer according to claim 1, wherein the new semiconductor wafer is a wafer as a semiconductor crystal layer portion sliced ​​from a semiconductor crystal layer grown on the processed surface of the remaining wafer.

14. The method for providing a semiconductor wafer according to claim 13, further comprising, after said wafer providing step, a further growing step of growing a semiconductor crystal layer on the wafer other than the sliced ​​semiconductor crystal layer portions.

15. The method of claim 1, wherein the remaining wafer obtained in the obtaining step has a diameter of 6 inches or more.

16. The semiconductor wafer providing method according to claim 15, wherein the remaining wafer obtained in the obtaining step has a diameter of 8 inches or more.

17. The method for providing a semiconductor wafer according to claim 11, wherein the processing in the processing step includes removing by any process that results in a lower flatness after etching than etching according to a CMP (Chemical Mechanical Polishing) method.

18. A semiconductor wafer providing system comprising: a processing device that processes a sliced ​​surface of a remaining wafer acquired by a first entity from a second entity; and a growth device that grows a semiconductor crystal layer on the processed surface of the remaining wafer, wherein the remaining wafer is a semiconductor wafer portion having the second main surface sliced ​​from a semiconductor wafer having a device on the first main surface out of a first main surface and a second main surface, and a new semiconductor wafer having at least a portion of the semiconductor crystal layer grown on the processed surface of the remaining wafer is provided to a second entity that is the same as or different from the entity from which the remaining wafer was acquired.

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