Field effect transistor and manufacturing method therefor

Abstract

Provided in the present invention are a field effect transistor and a manufacturing method therefor. A lateral etching process is used to directly form a cantilever beam on a silicon substrate, a space below the cantilever beam is filled with a dielectric layer to form a silicon-on-insulator (SOI) structure, and at least a portion of a drain electrode and / or a channel is formed on the cantilever beam. In the manufacturing method, the introduction of an additional substrate is not required, and the use of expensive SOI formation techniques such as oxygen ion implantation and separation and silicon bonding is avoided; moreover, a field effect transistor manufactured by means of the manufacturing method has a high integration level, low power consumption and good heat dissipation performance.

Description

Field effect transistor and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on August 28, 2023, with application number 202311096265.1 and invention name “A Field Effect Transistor and Its Manufacturing Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor devices, and in particular to a field effect transistor and a manufacturing method thereof. Background Art

[0003] With the advancement of Moore's Law, transistor size continues to shrink, aiming to achieve higher performance and higher density. As transistor size continues to shrink, the challenges facing transistors become increasingly severe. As transistor channel lengths continue to shrink, the short-channel effect leads to increasing leakage, necessitating an increase in the channel doping concentration, particularly the concentration of pocket ion implantation (Halo implantation). However, this leads to two disadvantages. First, the increased Halo implantation concentration increases the electric field at the PN junction formed by the drain and channel. Such a high electric field can easily lead to gate-induced drain leakage. Second, the increased doping concentration reduces the uniformity of transistor threshold voltage, which is caused by random fluctuations in the implanted dopants. To address this, the industry has proposed the use of fully depleted or partially depleted active silicon on insulator (FD-SOI) technologies. These technologies result in partial or complete channel depletion. This reduces leakage current and significantly reduces the doping concentration of the channel, reducing the impact of random fluctuations in dopants caused by ion implantation.

[0004] The difference between FD-SOI and PD-SOI is the depth of the channel, that is, the thickness of the silicon. Generally speaking, the thickness of PD-SOI is greater than 0.15um. However, whether it is FD-SOI or PD-SOI, a substrate material such as SOI is required to prepare the corresponding transistors. Therefore, the SOI substrate is the biggest challenge of this technology. The industry already has mature technologies, mainly oxygen ion implantation separation (SIMOX, separation by implantation of oxygen) technology and silicon bonding technology (Bond silicon), but both technologies are expensive and have a narrow range of applications. It is difficult to ensure that field-effect transistors such as FD-SOI or PD-SOI can meet basic requirements such as low power consumption while also taking into account low-cost requirements.

[0005] Summary of the Invention

[0006] Based on the above-described problems, the present invention proposes a field-effect transistor and a method for manufacturing the same. A lateral etching process is used to directly form a cantilever on a silicon substrate. A dielectric layer is filled in the space below the cantilever to form a silicon-on-insulator (SOI) structure, and at least a portion of the drain and / or channel is formed on the cantilever. This manufacturing method does not require the introduction of an additional substrate, avoids the use of expensive silicon-on-insulator (SOI) formation technologies such as oxygen ion implantation segmentation and silicon bonding, and facilitates compatibility between the manufacturing process of the field-effect transistor and other device processes during chip fabrication, saving manufacturing costs in many ways. Furthermore, the field-effect transistor manufactured using this manufacturing method can have a high degree of integration, low power consumption, and good heat dissipation performance.

[0007] In a first aspect, an embodiment of the present invention provides a method for manufacturing a field effect transistor, the method comprising the steps of:

[0008] S1: providing a silicon wafer as a substrate;

[0009] S2: forming a cantilever beam in the substrate using a lateral etching process;

[0010] S3: filling a first dielectric layer in the space below the cantilever beam, wherein the first dielectric layer and the cantilever beam form a silicon-on-insulator structure;

[0011] S4: At least a portion of the drain and / or at least a portion of the channel of the field effect transistor are formed on the cantilever.

[0012] In a specific embodiment, the field effect transistor includes a gate, a source, and a drain, and the gate, source, and drain are all formed on the cantilever beam.

[0013] In a specific embodiment, only the drain and / or a portion of the channel of the field effect transistor are formed on the cantilever beam.

[0014] In a specific embodiment, the cantilever beam is completely suspended relative to the substrate, and the cantilever beam is supported by the first dielectric layer.

[0015] In a specific embodiment, the cantilever beam is partially suspended relative to the substrate, and the cantilever beam is supported by the connecting portion and / or the first dielectric layer. The connecting portion can also be used for heat dissipation and carrier transport.

[0016] In a specific embodiment, the field effect transistor includes a source electrode, and the connecting portion is located in a region corresponding to a projection of the source electrode.

[0017] In a specific embodiment, the connecting portion is located at two end portions of the cantilever beam, and the directions of the two end portions are located in the length direction of the channel of the field effect transistor.

[0018] In a specific embodiment, the transistor includes a gate, which is formed on the cantilever, and the gate is formed to be located only at the top of the cantilever; or the gate is formed to be located not only at the top of the cantilever but also at both sides of the cantilever; or the gate is formed to be located not only at the top of the cantilever but also at both sides and the bottom outer side of the cantilever.

[0019] In a specific embodiment, the step S2 further includes the following steps:

[0020] S21: preparing a hard mask plate including a first through hole and a second through hole on the substrate by using a trench forming mask;

[0021] S22: Etching downward according to the positions of the first through hole and the second through hole, increasing the lateral etching component to form the cantilever beam.

[0022] In a specific embodiment, the step S2 further includes the following steps:

[0023] S23: performing epitaxial growth on the outer side of the cantilever beam to form an epitaxial growth layer;

[0024] S24: performing self-aligned etching on the epitaxial growth layer using the hard mask template, and etching the remaining epitaxial growth layer to form a part of the cantilever beam.

[0025] In a specific embodiment, the step S2 further includes the following steps:

[0026] S21: pre-forming a first trench and a second trench on the substrate;

[0027] S22: performing lateral etching so that the lower portion of the portion between the first groove and the second groove is at least partially etched away so that the upper portion is suspended to form a cantilever beam.

[0028] In a specific embodiment, the first trench and the second trench are arranged in a channel width direction or a length direction of the field effect transistor.

[0029] In a specific embodiment, the lateral etching is bidirectional etching performed simultaneously in the first trench and the second trench.

[0030] In a specific embodiment, the step 21 further includes the following steps:

[0031] S211: forming a hard mask on the substrate using a trench forming mask;

[0032] S212: Etching the substrate using the hard mask to form the first trench and the second trench of a certain depth.

[0033] In a specific embodiment, after step 21 and before step 22, the following steps are further included:

[0034] S2-1: Depositing a second dielectric layer in the first trench and the second trench on the substrate;

[0035] S2-2: Carve the second dielectric layer corresponding to the bottom of the first trench and the second trench, and continue etching downward to a certain depth to reserve sufficient side etching space.

[0036] In a specific embodiment, the step S2 further includes the following steps:

[0037] S23: baking the cantilever beam in a high-temperature hydrogen atmosphere.

[0038] In a specific embodiment, the step S4 further includes the step of forming a planar gate on the cantilever beam:

[0039] S41: growing a gate oxide layer in a partial area of ​​the cantilever beam;

[0040] S42: Covering the polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

[0041] In a specific embodiment, the step S4 further includes the step of forming a three-dimensional gate on the cantilever beam:

[0042] S41: using a transistor formation region definition mask and using the hard mask for self-aligned etching to open the first dielectric layer on both sides of the active region;

[0043] S42: growing a gate oxide layer in a partial area of ​​the cantilever beam;

[0044] S43: Filling polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

[0045] In a specific embodiment, the step S4 further includes the steps of:

[0046] S44: performing a spacer process on the polysilicon gate;

[0047] S45: performing source-drain ion doping on the two side regions of the gate to form the source and drain.

[0048] In a specific embodiment, fully depleted and / or partially depleted field effect transistors are formed by varying the thickness of the cantilever beam.

[0049] In a second aspect, the present invention further provides a field effect transistor formed by the method for forming a field effect transistor described in any of the above embodiments.

[0050] The field effect transistor and the method for forming the same according to the embodiment of the present invention have the following advantages compared with the prior art:

[0051] (1) A lateral etching process is used to directly form a cantilever on a silicon substrate. A silicon-on-insulator (SOI) structure is formed by filling a dielectric layer in the space below the cantilever. This manufacturing method does not require the introduction of an additional substrate, avoids the use of expensive technologies such as oxygen ion implantation and silicon bonding, and reduces the manufacturing cost of field-effect transistors. In addition, this manufacturing method facilitates the compatibility of the manufacturing process of field-effect transistors with other device processes on the chip, which can simplify the chip manufacturing process. The simplified manufacturing process can also further reduce costs. In addition, the provision of a dielectric layer filled below the cantilever can greatly reduce or even avoid the parasitic capacitance generated by the device above the cantilever, thereby greatly reducing power consumption.

[0052] (2) In some application scenarios, the gate of the embodiment of the present invention is preferably a three-dimensional field effect transistor in the form of a three-dimensional gate structure. The three-dimensional gate structure can provide a channel size that meets sufficient performance requirements, which is beneficial to circuit integration. It is also beneficial to the implementation of the process of "forming a cantilever directly on a silicon substrate by a lateral etching process, and forming a silicon-on-insulator (SOI) structure by filling a dielectric layer in the space below the cantilever" in the present invention. Because, in order to ensure process accuracy, the depth of the lateral etching process cannot be unlimited, and the area size of the channel of the three-dimensional gate can be made much smaller than that of the horizontal gate, which can ensure the controllability of the lateral etching process and improve the yield of the manufactured field effect transistor.

[0053] (3) In some application scenarios, since the drain or channel is most likely to generate parasitic capacitance, the embodiments of the present invention form at least a portion of the drain and / or channel on the cantilever. The dielectric layer filled under the cantilever can avoid the large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption.

[0054] (4) In some application scenarios, the cantilever is completely suspended, and the source, drain, gate and other structures are all located on the cantilever. The parasitic capacitance generated by the source, drain and gate can be reduced or avoided. By using a mask etching compatible with other processes to make a fully suspended cantilever, the cantilever is completely isolated and supported by the dielectric layer from the silicon substrate. The parasitic capacitance of the field effect transistor can be further reduced without increasing the production cost, thereby reducing the power consumption of the field effect transistor.

[0055] (5) In some application scenarios, the side surfaces of the source and / or drain on the cantilever are exposed to the shallow trench isolation, which can increase the contact area between the source and / or drain and the dielectric layer, further reduce the parasitic capacitance of the field effect transistor, and thus reduce the power consumption of the field effect transistor.

[0056] (6) In some application scenarios, the cantilever is partially suspended. Since the drain or channel areas are most likely to generate parasitic capacitance, and the heat generated by the field effect transistor cannot be ignored, the embodiment of the present invention partially suspends the cantilever. For example, in one embodiment of the present invention, a portion of the drain and / or channel is formed on the cantilever, and the other portion is not arranged on the cantilever. The dielectric layer filled under the cantilever can avoid the large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption. At the same time, at least the portion corresponding to the source is connected to the silicon substrate body. Since the heat dissipation performance of the silicon substrate material is better than that of the dielectric layer, the large amount of heat generated by the field effect transistor on the cantilever can be easily diffused through the portion connected to the silicon substrate, taking into account the heat dissipation requirements of the field effect transistor and greatly reducing the probability of thermal damage to the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The accompanying drawings constitute a part of this specification and are used to further understand the present invention. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principle of the present invention.

[0058] FIG. 1 shows a process flow diagram of a field effect transistor structure according to an embodiment.

[0059] FIG2-4b is a schematic diagram of a three-dimensional structure of a field effect transistor according to different embodiments.

[0060] 5 a - 5 c are schematic cross-sectional views taken along line BB′ of different embodiments of field effect transistors.

[0061] FIG. 6 is a process flow chart of a field effect transistor structure according to an embodiment.

[0062] FIG. 7 is a process flow chart of a field effect transistor structure according to another embodiment. DETAILED DESCRIPTION

[0063] The following detailed description is illustrative and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0064] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention.

[0065] In a first aspect, an embodiment of the present invention provides a method for manufacturing a field effect transistor. As shown in FIG1 , a process flow of a method for manufacturing a field effect transistor provided by an embodiment of the present invention is provided. The process flow includes a method for manufacturing a cantilever structure. The method for manufacturing a cantilever structure includes the following steps:

[0066] S1: providing a silicon wafer as a substrate;

[0067] S2: forming a cantilever beam in the substrate using a lateral etching process.

[0068] S3: Filling the space below the cantilever with a first dielectric layer, so that the first dielectric layer and the cantilever form a silicon-on-insulator structure;

[0069] S4: At least a portion of the drain and / or at least a portion of the channel of the field effect transistor are formed on the cantilever.

[0070] As shown in FIG2 , an example of the three-dimensional structure of a field effect transistor manufactured by the method for manufacturing a field effect transistor according to the aforementioned embodiment is shown. The field effect transistor includes a gate, a source, and a drain. At least a portion of the drain and / or at least a portion of the channel are formed on the cantilever. It can be that only the drain and / or a portion of the channel of the field effect transistor are formed on the cantilever. Alternatively, as shown in FIG2 , the gate, source, and drain are all formed on the cantilever. As shown in FIG2 , the field effect transistor is arranged on a silicon substrate 1 and includes a cantilever 1′. The cantilever manufacturing method of the cantilever 1′ is to directly perform lateral etching on a silicon wafer. Depending on the thickness of the cantilever, a fully depleted and / or partially depleted field effect transistor can be formed. The field effect transistor also includes a source 3, a drain 4, a gate 2, and a gate oxide layer 6. A channel (not shown) is formed in the area between the source 3 and the drain 4, and a first dielectric layer 5 is filled under the cantilever 1′.

[0071] In the embodiment shown in FIG2 , the source 3, drain 4 and gate 2 are all formed on the cantilever beam, and the cantilever beam 1′ is completely suspended above the substrate 1, that is, the cantilever beam 1′ is completely supported and insulated by the first dielectric layer 5. The source 3, drain 4 and gate 2 can all greatly reduce or avoid the generation of parasitic capacitance by filling the first dielectric layer 5, thereby greatly reducing the power consumption of the field effect transistor. The completely suspended cantilever beam 1′ can make the parasitic capacitance of the source, drain, channel and other regions all be set on the cantilever beam 1′, so that the parasitic capacitance of these regions can be reduced or even avoided, so that the field effect transistor can be more suitable for high-speed and low-power circuits.

[0072] FIG2 also illustrates that gate 2 is formed as an "n"-type solid gate, i.e., the field-effect transistor is formed as a fin field-effect transistor. In FIG2 , the solid gate can cover the top surface of the cantilever 1' and the two side surfaces of the cantilever 1' in the channel width direction. However, the solid gate is not limited to that shown in FIG2 . The solid gate can also be a ring gate, i.e., arranged circumferentially around the cantilever 1' in the channel width direction (i.e., the A-A' direction), formed to be located not only at the top of the cantilever but also at the two side surfaces and the bottom outer surface of the cantilever. Gate 2 is not limited to a solid gate and can also be a horizontal gate, i.e., the gate only includes the position above the top of the cantilever.

[0073] Compared to horizontal gates, the preferred embodiment is a 3D gate. Because the 3D gate occupies a much smaller plane, when fabricated as a 3D gate to form a field-effect transistor, the requirements for the cantilever beam 1' are also lower, requiring smaller width and length dimensions. The smaller cantilever beam size means that the lateral etching process can be more precise, with smaller errors, which is more conducive to reducing the risk of etching damage, thus making it easier to directly perform a lateral etching process on the silicon wafer to form the cantilever beam without performing epitaxial growth on the silicon wafer.

[0074] In a specific embodiment, the cantilever beam 1' is not limited to being fully suspended as shown in FIG2, but may also be partially suspended. For example, as shown in FIG3, the cantilever beam 1' and the substrate 1 are integrated, and the two end portions of the cantilever beam 1' are connected to the substrate 1 as a whole through a connecting portion 1". Alternatively, one of the end portions may be connected to the substrate 1 as a whole through a connecting portion 1". The cantilever beam can be supported by the connecting portion and / or the first dielectric layer. In addition to providing support, the connecting portion can also be used for heat dissipation and carrier transport of semiconductor devices such as field-effect transistors on the cantilever beam.

[0075] Among them, to form a completely suspended cantilever beam 1', it is necessary to reserve a cantilever beam connecting portion 1" in the lateral etching process step. After the first dielectric layer 5 is filled into the space below the cantilever beam, the connecting portion 1" of the cantilever beam 1' can be removed through an additional etching step or a synchronous process with other structures to form a completely suspended cantilever beam 1'.

[0076] In a specific embodiment, at least the end of the drain electrode passes through the end of the cantilever beam 1', as shown in Figures 4a-4b, which are schematic diagrams of the ends of the source and drain electrodes passing through the ends of the cantilever beam. The drain electrode 4 and / or the source electrode 3 are formed by passing through the end portion of the cantilever beam 1'. In actual integrated circuit manufacturing, the advantage of such a formation is that the outer end region of the drain electrode 4 and / or the source electrode 3 can contact the insulating dielectric layer filled in the shallow trench isolation, that is, the drain electrode 4 and / or the source electrode 3 are completely isolated by the insulating dielectric, thereby further reducing the parasitic capacitance. Specifically, as shown in FIG5a, which is a schematic cross-sectional view along the BB' direction in FIG4a, in actual integrated circuit manufacturing, the area on the end side of the drain 4 and / or source 3 also includes an STI (shallow trench isolation) region 7. In this embodiment, by exposing the end of the drain 4 and / or source 3 to the shallow trench isolation trench, the end of the drain 4 and / or source 3 can be covered and contacted via the insulating medium subsequently filled in the shallow trench isolation trench, so that the parasitic capacitance can be further reduced, thereby reducing the power consumption of the field effect transistor. The situation where the drain 4 and / or source 3 passes through the end of the cantilever 1' is not limited to a completely suspended cantilever, but can also be applied to a cantilever partially suspended in any form. For example, as shown in FIG4b, the cantilever 1' and the substrate 1 are integrated into a structure through a connecting portion 1". The position of the connecting portion 1" relative to the cantilever 1' in FIG4b is only an example, and this embodiment is not limited to this.

[0077] In a specific embodiment, only part of the drain and / or channel is located on the cantilever and it also falls within the scope of the present invention. Due to the problem of heat dissipation in SOI devices, based on this, this embodiment considers that the gate (or channel), drain, source, etc. do not have to be all located on the cantilever 1'. For example, optionally, part or all of the drain is located on the cantilever 1', part or all of the channel is located on the cantilever 1', part or all of the source is located on the cantilever 1', part or all of the gate is located on the cantilever 1', etc., taking into account both reducing parasitic capacitance and alleviating heating conditions. The inventors found that the parasitic capacitance generated in the drain region of the field effect transistor is relatively significant, and the parasitic capacitance generated in the channel region is often not negligible. Based on this, a preferred embodiment is to set the drain and / or part of the channel on the cantilever, and the other part is not set on the cantilever. Then, the drain and / or part of the channel located above the cantilever can be reduced by the first dielectric layer 5 set below the cantilever 1'. In this way, the need to significantly reduce parasitic capacitance and alleviate the heating condition of SOI can be taken into account.

[0078] In one specific embodiment, to form only a portion or all of the drain and / or channel on the cantilever beam, the cantilever beam 1' may not be completely suspended above the substrate 1. Figure 5b shows a schematic diagram of a drain and channel formed on the cantilever beam. The cantilever beam 1' is not completely suspended relative to the substrate 1. The cantilever beam 1' is connected to the substrate 1 via a connecting portion 1' to form an integrated structure. The cantilever beam 1' is supported by the first dielectric layer 5 and / or the connecting portion 1'. As shown in Figure 5b, the source region is located above the connecting portion 1', while the drain and gate (channel) regions are located above the cantilever beam 1'.

[0079] The provision of the connecting portion 1″ prevents the cantilever beam from collapsing when it is formed by lateral etching. Compared to the process of fully suspended cantilever beam 1′, retaining the connecting portion allows for greater process selectivity in the implementation of partially suspended cantilever beam 1′. The appropriate etching direction can be selected based on actual process accuracy, cost, and other requirements. It can also be determined whether to etch away the connecting portion retained by lateral etching in subsequent processes based on process compatibility requirements, without being restricted by the filling order of the first dielectric layer 5. Compared to the process of fully suspended cantilever beam 1′, which requires first filling the first dielectric layer 5 before removing the connecting portion, the partial suspension process is more cost-effective.

[0080] Furthermore, it is worth noting that the suspension beam 1' is not completely suspended above the substrate 1, which is particularly beneficial for heat dissipation during the operation of the field-effect transistor. This is because the heat dissipation efficiency of the insulating medium is far lower than that of the silicon substrate material. By partially suspending the suspension beam 1' with the connecting portion 1", the heat generated during the operation of the field-effect transistor is quickly dissipated through the suspension beam 1', the connecting portion 1", and the substrate 1, thereby improving the heat dissipation performance of the field-effect transistor. The connecting portion 1" is also more conducive to carrier transport. At the same time, by positioning the connecting portion 1" below the source region and filling the drain and / or channel with the first dielectric layer, the parasitic capacitance of regions such as the drain and / or channel, which are more prone to parasitic capacitance, can be reduced. Heat from the suspension beam can also be dissipated through the connecting portion. Furthermore, since only part or all of the drain and / or channel need to be positioned on the suspension beam, the required suspension beam size can be reduced, thereby reducing the length of the extended portion of the suspension beam. When the extended portion is not too long, the suspension beam is less likely to collapse, thereby reducing the difficulty of the suspension beam manufacturing process.

[0081] In a specific embodiment, in order to further ensure the heat dissipation performance of the field effect transistor and the controllability requirements of the lateral etching process, as shown in Figures 3, 4b, and 5c, another example of partial suspension of the cantilever beam 1' is shown. The cantilever beam 1' is arranged in a bridge-like manner across the first dielectric layer 5. Along the channel direction, the ends of the cantilever beam 1' are integrated with the substrate 1 through two connecting portions 1", and the formed field effect transistor cantilever beam 1' is supported by the first dielectric layer 5 and the connecting portions 1" at both ends, which makes it more stable. The two connecting portions 1" prevent the cantilever beam 1' formed by lateral etching from collapsing due to various uncontrollable errors during the manufacturing process before the first dielectric layer 5 is filled, thereby greatly reducing the difficulty of the process. Figures 4b and 5c illustrate that the source and drain are only partially located on the cantilever beam 1', while Figures 2-3 illustrate that the source, drain, gate, channel, etc. are all formed on the cantilever beam. However, the embodiments of the present invention are not limited to this. In actual settings, the proportion of the source, drain, and gate on the cantilever beam can be reasonably arranged by designing the filling depth of the first dielectric layer to balance various process and performance requirements.

[0082] In a specific embodiment, when the silicon wafer is laterally etched to form a cantilever 1', lateral etching can be performed in the width direction of the channel (the A-A' direction in FIG2). Since the size of the cantilever in the width direction of the channel is much smaller than the size in the length direction, it is preferred to perform lateral etching in the width direction of the channel to control the controllability of the lateral etching process. On this basis, bidirectional simultaneous etching during lateral etching can further increase the accuracy of lateral etching. In addition, for a partially suspended cantilever, etching can also be performed in the length direction of the channel (BB' in FIG2) to form a cantilever. Since it is not necessary to etch through the entire area, it is beneficial to etch a space of a depth toward the length direction of the channel only through shallow trench isolation on one side while ensuring the controllable requirements of the lateral etching process. In addition, the grooves or through holes used for lateral etching to form the cantilever can be arranged in the width direction or the length direction of the channel.

[0083] The following describes in detail the manufacturing process details of the field effect transistor provided by the present invention with reference to the accompanying drawings.

[0084] FIG6 is a process flow chart of one embodiment of the method for manufacturing a field effect transistor provided by the present invention. It is a schematic diagram of the A-A' cross section based on the gate position. Among them, Figures (1) to (5) of FIG6 illustrate part of the process of step S2, which includes the following steps:

[0085] S21: A hard mask plate including a first through hole and a second through hole is prepared on the substrate using a groove forming mask. Specifically, as shown in FIG6 (1), a hard mask plate L2 is pre-formed on the substrate 1, and a groove forming mask L1 is formed on the hard mask plate L2. As shown in FIG6 (2), a first through hole H1 and a second through hole H2 are formed on the hard mask plate L2 using the groove forming mask L1, and the surface of the silicon wafer is exposed through the first through hole H1 and the second through hole H2.

[0086] S22: Based on the positions of the first through hole and the second through hole, when etching downward, the lateral etching component is increased to form the cantilever beam. Specifically, referring to Figure (3) in FIG6 , in the first through hole H1 and the second through hole H2, when etching downward, the exposed silicon wafer surface is tilted at a certain angle, that is, the lateral etching component is increased to form a cantilever beam 1' on the silicon wafer. The etching directions applied in the first through hole H1 and the second through hole H2 have an intersection below the cantilever beam 1'. Therefore, the bottom of the cantilever beam 1' can be directly hollowed out by lateral etching.

[0087] In order to further improve the yield of the cantilever beam 1', the preferred step S2 specifically further includes the following steps:

[0088] S23: epitaxial growth is performed on the outer side of the cantilever beam to form an epitaxial growth layer. Specifically, as shown in FIG. 6 (4), an epitaxial growth layer 11 is grown in the hollowed space using epitaxial growth technology.

[0089] S24: The epitaxial growth layer is self-aligned and etched using a hard mask template. The remaining epitaxial growth layer on the cantilever is used to form a portion of the cantilever. Specifically, the pattern of the hard mask template L2 can be used to remove the irregular portions around the epitaxial growth layer 11. The remaining portion of the epitaxial growth layer 11 is used to form the cantilever 1', as shown in Figure (5) of Figure 6. A regular cantilever 1' is formed. This method makes it easy to control the size and shape of the cantilever. The regular cantilever 1' can improve the yield of semiconductor devices such as field effect transistors that are subsequently formed.

[0090] Figures (6) to (9) of FIG. 6 illustrate some of the process steps for forming a field-effect transistor in combination with a cantilever beam. Specifically, Figure (6) of FIG. 6 illustrates step S3, in which a first dielectric layer 5 is filled in the space below the cantilever beam 1'. The first dielectric layer 5 and the cantilever beam 1' form a silicon-on-insulator structure. In order to complete step S4 to form a field-effect transistor, step S4 preferably also includes the step of forming a three-dimensional gate on the cantilever beam 1':

[0091] S41: Using a mask to define the transistor formation area, and using a hard mask for self-aligned etching, the first dielectric layer on both sides of the active area is etched away. As shown in FIG. 6 (7), the first dielectric layer 5 is etched away to expose the cantilever beam 1'.

[0092] S42: A gate oxide layer is grown on a portion of the suspension beam. As shown in FIG6 (8), a gate oxide layer 6 is formed on the left and right sides and the top side of the suspension beam 1'. In order to form a three-dimensional gate, the gate oxide layer 6 is formed not only on the top side of the suspension beam, but also on the left and right side surfaces. FIG6 (8) of FIG6 illustrates the required coverage position of the n-type gate. In addition, the three-dimensional gate can also be a ring gate, that is, the gate oxide layer 6 needs to surround the suspension beam 1' in the circumferential direction of the suspension beam 1', or the gate oxide layer 6 is formed not only on the top side of the suspension beam, but also on the left and right side surfaces and the bottom side surface.

[0093] S43: Fill the polysilicon layer, use the gate to form a mask, and form a polysilicon gate on the gate oxide layer. As shown in Figure (9) of Figure 6, an n-shaped three-dimensional gate 2 is formed on the gate oxide layer 6, that is, the gate 2 is formed not only on the top side of the cantilever beam, but also on the left and right side surfaces. When setting up the ring gate, it is also necessary to wrap the bottom side of the cantilever beam (not shown in the figure).

[0094] In a specific embodiment, the gate formed in step S4 may also be a planar gate. The steps of forming the planar gate on the cantilever beam are as follows:

[0095] S41: growing a gate oxide layer on a portion of the cantilever beam. Specifically, the hard mask L2 on the cantilever beam 1' is removed, and a gate oxide layer 6 is grown on the top side of the cantilever beam. The gate oxide layer 6 is only located on the top surface of the cantilever beam 1' (not shown in the drawings).

[0096] S42: Cover the polysilicon, use the gate to form a mask, and form a polysilicon gate on the gate oxide layer. Specifically, grow the gate 2 on the gate oxide layer 6 on the top side of the suspension beam. The gate 2 is only located on the top surface of the suspension beam 1' (not shown in the figure).

[0097] FIG7 is a process flow chart of another embodiment of the method for manufacturing a field effect transistor provided by the present invention. FIG7 (1) to (5) of FIG7 illustrate a portion of the process of step S2, which is different from the corresponding process in FIG6 and includes the following steps:

[0098] S21: A first trench and a second trench are pre-formed on the substrate. Specifically, a hard mask L2 is pre-formed on the substrate 1, and a trench forming mask L1 is formed on the hard mask L2. Referring to FIG. 7 (1), the trench forming mask L1 is used to etch a first through hole H1 and a second through hole H2 in a substantially vertical direction on the hard mask L2. The etching is further carried out into the silicon wafer, and the first trench and the second trench are formed in the substrate at the positions corresponding to the first through hole H1 and the second through hole H2.

[0099] S22: Lateral etching is performed to at least partially remove the lower portion of the portion between the first trench and the second trench, thereby leaving the upper portion suspended to form a cantilever beam. Referring to Figures (3) and (4) in FIG7 , the substrate is laterally etched downward at a certain angle according to the positions of the first trench and the second trench to form a cantilever beam 1′.

[0100] In a specific embodiment, after step 21 and before step 22, the process further includes the following steps:

[0101] S2-1: Depositing a second dielectric layer in the first trench and the second trench on the substrate; as shown in Figure (2) in FIG. 7 , the first trench and the second trench are deposited with the second dielectric layer L3.

[0102] S2-2: The second dielectric layer corresponding to the bottoms of the first and second trenches is carved, and the etching is continued downward to a certain depth to reserve sufficient space for side etching. Lateral etching is performed at a certain angle to hollow out the portion below the cantilever beam 1'. During the lateral etching, the portion of the cantilever beam covered by the second dielectric layer L3 is protected from etching, thereby forming a cantilever beam 1' of sufficient depth.

[0103] In a specific embodiment, step S2 further includes the following steps:

[0104] S23: The cantilever beam is baked in a high-temperature hydrogen atmosphere. Specifically, as shown in FIG. 7 (4), the etched surface of the cantilever beam 1' formed by lateral etching is irregular. In order to improve the yield of the device and form a regular cantilever beam 1', the cantilever beam is baked in a high-temperature hydrogen atmosphere (H2Bake), which can improve the tip of the cantilever beam 1'. As shown in FIG. 7 (5), after the high-temperature hydrogen atmosphere baking, the bottom of the cantilever beam 1' becomes smooth and regular, which is conducive to improving the yield of semiconductor devices such as field effect transistors formed subsequently thereon.

[0105] In a specific embodiment, Figures (6)-(9) of Figure 7 illustrate some process steps for forming a field effect transistor in combination with a cantilever beam, and the process is similar to Figures (6)-(9) of Figure 6, and will not be repeated here.

[0106] In a specific embodiment, the field effect transistor further includes a sidewall. In order to complete step S4 to form the field effect transistor, preferably, step S4 further includes the steps of:

[0107] S44: performing a sidewall spacer process on the polysilicon gate; the sidewall spacer of this embodiment can be manufactured by any conventional sidewall spacer process, and this embodiment is not limited thereto.

[0108] S45: Doping the source and drain ions on both sides of the gate to form the source and drain. The source and drain of this embodiment can be made using any conventional source and drain manufacturing process, and this embodiment is not limited thereto.

[0109] In a specific embodiment, a fully depleted and / or partially depleted field effect transistor can be formed by controlling the thickness of the cantilever beam of any of the aforementioned embodiments.

[0110] In a second aspect, the present invention further provides a field effect transistor formed by the method for forming a field effect transistor described in any of the above embodiments.

[0111] The field effect transistor and the method for forming the same according to the embodiment of the present invention have the following advantages compared with the prior art:

[0112] (1) A lateral etching process is used to directly form a cantilever on a silicon substrate. A silicon-on-insulator (SOI) structure is formed by filling a dielectric layer in the space below the cantilever. This manufacturing method does not require the introduction of an additional substrate, avoids the use of expensive technologies such as oxygen ion implantation and silicon bonding, and reduces the manufacturing cost of field-effect transistors. In addition, this manufacturing method facilitates the compatibility of the manufacturing process of field-effect transistors with other device processes on the chip, which can simplify the chip manufacturing process. The simplified manufacturing process can also further reduce costs. In addition, the provision of a dielectric layer filled below the cantilever can greatly reduce or even avoid the parasitic capacitance generated by the device above the cantilever, thereby greatly reducing power consumption.

[0113] (2) In some application scenarios, the gate of the embodiment of the present invention is preferably a three-dimensional field effect transistor in the form of a three-dimensional gate structure. The three-dimensional gate structure can provide a channel size that meets sufficient performance requirements, which is beneficial to circuit integration. It is also beneficial to the implementation of the process of "forming a cantilever directly on a silicon substrate by a lateral etching process, and forming a silicon-on-insulator (SOI) structure by filling a dielectric layer in the space below the cantilever" in the present invention. Because, in order to ensure process accuracy, the depth of the lateral etching process cannot be unlimited, and the area size of the channel of the three-dimensional gate can be made much smaller than that of the horizontal gate, which can ensure the controllability of the lateral etching process and improve the yield of the manufactured field effect transistor.

[0114] (3) In some application scenarios, since the drain or channel is most likely to generate parasitic capacitance, the embodiments of the present invention form at least a portion of the drain and / or channel on the cantilever. The dielectric layer filled under the cantilever can avoid the large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption.

[0115] (4) In some application scenarios, the cantilever is completely suspended, and the source, drain, gate and other structures are all located on the cantilever. The parasitic capacitance generated by the source, drain and gate can be reduced or avoided. By using a mask etching compatible with other processes to make a fully suspended cantilever, the cantilever is completely isolated and supported by the dielectric layer from the silicon substrate. The parasitic capacitance of the field effect transistor can be further reduced without increasing the production cost, thereby reducing the power consumption of the field effect transistor.

[0116] (5) In some application scenarios, the side surfaces of the source and / or drain on the cantilever are exposed to the shallow trench isolation, which can increase the contact area between the source and / or drain and the dielectric layer, further reduce the parasitic capacitance of the field effect transistor, and thus reduce the power consumption of the field effect transistor.

[0117] (6) In some application scenarios, the cantilever is partially suspended. Since the drain or channel areas are most likely to generate parasitic capacitance, and the heat generated by the field effect transistor cannot be ignored, the embodiment of the present invention partially suspends the cantilever. For example, in one embodiment of the present invention, a portion of the drain and / or channel is formed on the cantilever, and the other portion is not arranged on the cantilever. The dielectric layer filled under the cantilever can avoid the large amount of parasitic capacitance generated by the drain and / or channel, thereby greatly reducing power consumption. At the same time, at least the portion corresponding to the source is connected to the silicon substrate body. Since the heat dissipation performance of the silicon substrate material is better than that of the dielectric layer, the large amount of heat generated by the field effect transistor on the cantilever can be easily diffused through the portion connected to the silicon substrate, taking into account the heat dissipation requirements of the field effect transistor and greatly reducing the probability of thermal damage to the field effect transistor.

[0118] While the basic concepts have been described above, it will be apparent to those skilled in the art that the detailed disclosure is merely illustrative and does not limit the present invention. Although not explicitly described herein, those skilled in the art may make various modifications, improvements, and revisions to the present invention. Such modifications, improvements, and revisions are suggested in the present invention and remain within the spirit and scope of the exemplary embodiments of the present invention.

[0119] It should be understood that the embodiments described herein are intended only to illustrate the principles of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly described and illustrated herein.

Claims

1. A method for manufacturing a field effect transistor, the method comprising the steps of: S1: providing a silicon wafer as a substrate; S2: forming a cantilever beam in the substrate by using a lateral etching process; S3: filling a first dielectric layer in the space below the cantilever beam, wherein the first dielectric layer and the cantilever beam form a silicon-on-insulator structure; S4: At least a portion of the drain and / or at least a portion of the channel of the field effect transistor are formed on the cantilever beam.

2. The method according to claim 1, characterized in that The field effect transistor includes a gate, a source, and a drain, and the gate, the source, and the drain are all formed on the suspension beam.

3. The method according to claim 1, characterized in that Only a drain and / or a portion of a channel of the field effect transistor is formed on the cantilever beam.

4. The method according to any one of claims 1 to 3, characterized in that: The cantilever beam is completely suspended relative to the substrate, and the cantilever beam is supported by the first dielectric layer.

5. The method according to any one of claims 1 to 3, characterized in that: The cantilever beam is partially suspended relative to the substrate, and the cantilever beam is supported by the connecting portion and / or the first dielectric layer. The connecting portion can also be used for heat dissipation and carrier transport.

6. The method according to claim 5, characterized in that The field effect transistor comprises a source electrode, and the connecting portion is located in a region corresponding to a projection of the source electrode.

7. The method according to claim 5, characterized in that The connecting parts are located at two end portions of the cantilever beam, and directions of the two end portions are located in the length direction of the channel of the field effect transistor.

8. The method according to claim 1, characterized in that The transistor includes a gate, which is formed on the cantilever beam. The gate is formed to be located only at the top of the cantilever beam; or the gate is formed to be located not only at the top of the cantilever beam but also at both side surfaces of the cantilever beam; or the gate is formed to be located not only at the top of the cantilever beam but also at both side surfaces and the bottom outer surface of the cantilever beam.

9. The method according to claim 1, characterized in that: The step S2 specifically further comprises the steps of: S21: preparing a hard mask template including a first through hole and a second through hole on the substrate by using a groove forming mask; S22: Etching downwards according to the positions of the first through hole and the second through hole, and increasing the lateral etching component to form the cantilever beam.

10. According to the method of claim 9, the step S2 specifically further comprises the steps of: S23: performing epitaxial growth on the outer side of the cantilever beam to form an epitaxial growth layer; S24: performing self-aligned etching on the epitaxial growth layer using the hard mask template, and etching the remaining epitaxial growth layer to form a part of the cantilever beam.

11. The method according to claim 1, characterized in that: The step S2 specifically further comprises the steps of: S21: pre-forming a first groove and a second groove on the substrate; S22: Perform lateral etching so that the lower portion of the portion between the first groove and the second groove is at least partially etched away so that the upper portion is suspended to form a cantilever beam.

12. The method according to claim 11, characterized in that The first trench and the second trench are arranged in a channel width direction or a length direction of the field effect transistor.

13. The method according to claim 11, characterized in that The lateral etching is bidirectional etching performed simultaneously in the first trench and the second trench.

14. The method according to claim 11, characterized in that The step 21 specifically further includes the steps of: S211: forming a hard mask on the substrate by using a groove forming mask; S212: Etching the substrate using the hard mask to form the first trench and the second trench of a certain depth.

15. The method according to claim 11, characterized in that After step 21 and before step 22, the method further includes the following steps: S2-1: depositing a second dielectric layer in the first trench and the second trench on the substrate; S2-2: Carve the second dielectric layer corresponding to the bottom of the first groove and the second groove, and continue etching downward to a certain depth to reserve sufficient side etching space.

16. The method for forming a field effect transistor according to claim 9, characterized in that: The step S2 specifically further comprises the steps of: S23: baking the cantilever beam in a high-temperature hydrogen atmosphere.

17. The method according to claim 1, characterized in that The step S4 further comprises the step of forming a planar gate on the cantilever beam: S41: growing a gate oxide layer in a partial area of ​​the cantilever beam; S42: Covering the polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

18. The method according to claim 1, characterized in that The step S4 further comprises the step of forming a three-dimensional gate on the suspension beam: S41: using a transistor forming region definition mask and using a hard mask template for self-aligned etching to open the first dielectric layer on both sides of the active region; S42: growing a gate oxide layer in a partial area of ​​the cantilever beam; S43: filling polysilicon, using the gate to form a mask, and forming a polysilicon gate on the gate oxide layer.

19. The method according to claim 17 or 18, characterized in that The step S4 further comprises the steps of: S44: performing a sidewall process on the polysilicon gate; S45: performing source-drain ion doping on the two side regions of the gate to form a source electrode and a drain electrode.

20. The method according to any one of claims 1, characterized in that: Fully depleted and / or partially depleted field effect transistors are formed by different thicknesses of the cantilever beams.

21. A field effect transistor, characterized in that: It is formed by the method according to any one of claims 1 to 20.

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