Sequencing unit, and chip and preparation method therefor

Abstract

The present invention belongs to the technical field of biological testing. Disclosed are a sequencing unit, and a chip and a preparation method therefor. The sequencing unit comprises a substrate, wherein a sample flow channel is formed above the substrate, and a buffer solution flow channel is formed below the substrate; a single-hole liquid storage cavity is formed between the sample flow channel and the substrate; an electrode is provided on the substrate, and one end of the electrode is connected to the single-hole liquid storage cavity; a substrate through-hole is further formed in the substrate and is in communication with the buffer solution flow channel; and the substrate through-hole is in communication with the single-hole liquid storage cavity via a liquid resistance flow channel. The sequencing unit is manufactured by mature processing technology and is not limited by the thickness of the substrate, such that the requirement on the depth-to-width ratio of the substrate through-hole is greatly reduced.

Description

Sequencing unit, chip, and preparation method Technical Field

[0001] The present invention belongs to the field of biological detection technology, and particularly relates to a sequencing unit, a chip and a preparation method. Background Art

[0002] A nanopore sequencing device determines the base pair sequence of a DNA molecule by detecting changes in the electrical signal generated when the DNA molecule passes through a nanometer-sized hole. This type of device generally consists of a thin film that can separate two liquid storage chambers and a nanopore embedded in the film. This nanopore can use a protein molecule with a pore structure that exists naturally or is artificially compiled (nanopore protein), or it can be opened in the film through physical processing methods such as ion beams. When the device performs DNA sequencing, the liquid storage chambers on both sides of the film are at different potentials to drive the DNA molecule through the nanopore. When the sequencing target DNA passes through the nanopore, the electrical signal between the two liquid storage chambers is recorded simultaneously. By analyzing these signals, the sequencing of the DNA structure can be completed.

[0003] Current nanopore devices primarily monitor changes in the ionic current flowing between two reservoirs, calculating the base pair sequence of the target DNA. Stretched DNA molecules are long, requiring time to pass through the nanopore. During this time, only a small portion of the DNA molecule's base sequence remains within the nanopore. Because each base has a different effect on the magnitude of the ionic current, the magnitude of the ionic current varies with changes in the sequence of the small portion of bases within the nanopore. Therefore, by analyzing the changes in the ionic current throughout the passage of the DNA through the nanopore, algorithms can be used to calculate the base pair sequence of the target DNA.

[0004] Because their sequencing method is based on ionic current, this type of nanopore device has high requirements for ionic current detection accuracy. The nanopore protein used in current biological nanopore sequencing devices has a resistance of approximately 1 gigaohm in the sequencing environment, resulting in an ionic current of approximately 100 picoamperes during sequencing. Therefore, changes in the device structure and the test environment can significantly affect the accuracy of ionic current measurement, placing high demands on the amplification performance and stability of the device circuit. Furthermore, the measurement of ionic current is affected by the size of the electrode area, which limits the total number of nanopore devices per unit area, thereby limiting the throughput of commercial nanopore devices.

[0005] Given the limitations of ion current sequencing, voltage sequencing methods based on a voltage divider have been proposed in recent years. This method creates a voltage divider by adding a buffer channel connected by a liquid resistance channel to the reservoir on one side of a membrane embedded with a nanopore. This allows the device to detect changes in the electrical potential of the reservoir on one side of the membrane to determine changes in the resistance within the nanopore, and then calculate the base sequence of the target DNA using a corresponding algorithm.

[0006] In the currently disclosed patents, most of the liquid resistance flow channels and buffer flow channels are realized by making substrate through-holes. The commonly used through-hole production methods in the field of micro-nano processing have certain requirements for the thickness of the material and the geometry of the through-hole. Since most of the nanopore sequencing devices are currently made based on silicon wafers, their thickness is mostly hundreds of microns, and the hole diameter required for this structure is often in the range of several microns. The current more mature high aspect ratio micro-nano processing technology can only effectively complete deep hole etching with a maximum aspect ratio of 15:1 in actual production due to factors such as load effect and mask layer area. Therefore, how to effectively produce this type of substrate through-hole structure has become an important technical issue in the current realization of voltage sequencing principle chip production and mass production.

[0007] Summary of the Invention

[0008] In order to solve the above technical problems existing in the prior art, the present invention provides a sequencing unit, a chip and a preparation method.

[0009] To achieve the above object, the technical solution of the present invention is as follows:

[0010] A sequencing unit comprises a substrate, a sample flow channel is provided above the substrate, and a buffer flow channel is provided below the substrate; a single-pore liquid storage cavity is provided between the sample flow channel and the substrate, an electrode is provided on the substrate, and one end of the electrode is connected to the single-pore liquid storage cavity;

[0011] A substrate through-hole is also provided on the substrate, and the substrate through-hole is connected to the buffer flow channel; the substrate through-hole is connected to the single-hole liquid storage cavity through a liquid resistance flow channel.

[0012] Furthermore, a first structural layer is provided above the substrate, and a single-hole liquid storage cavity is provided in the first structural layer.

[0013] Furthermore, a second structural layer is provided above the first structural layer, a sample flow channel is provided in the second structural layer, and the sample flow channel is communicated with the single-hole liquid storage cavity.

[0014] Furthermore, a third structural layer is provided below the substrate, a buffer flow channel is provided in the third structural layer, and the buffer flow channel is connected to the substrate perforation.

[0015] Furthermore, the liquid resistance flow channel is arranged on the lower surface of the first structural layer.

[0016] Furthermore, the liquid resistance flow channel is arranged on the upper surface of the substrate.

[0017] Furthermore, the liquid resistance flow channel is a straight extension structure, an arc structure or a folded line structure.

[0018] Furthermore, the resistance value of the substrate through-hole is smaller than the resistance value of the liquid resistance flow channel.

[0019] The present invention also provides a sequencing chip, comprising at least one row of sequencing units, each row of sequencing units comprising the above-mentioned sequencing units.

[0020] Furthermore, each row of sequencing units includes multiple sequencing units, and the sample flow channels of the multiple sequencing units are interconnected to form a common sample flow channel; the buffer flow channels of the multiple sequencing units are interconnected to form a common buffer flow channel.

[0021] Furthermore, one end of the common sample flow channels of different rows converges and is provided with a sample inlet, and the other end of the common sample flow channels of different rows converges and is provided with a sample outlet;

[0022] One end of the common buffer flow channels of different rows converges and is provided with a buffer inlet, and the other end of the common buffer flow channels of different rows converges and is provided with a buffer outlet.

[0023] Furthermore, the common sample flow channels in different rows are isolated from each other or connected to form a whole flow channel; the common buffer flow channels in different rows are isolated from each other or connected to form a whole flow channel.

[0024] Furthermore, the sequencing chip further comprises an upper cover, which covers all common sample flow channels; a first interface is provided in the upper cover, which is in communication with the common sample flow channels.

[0025] Furthermore, the sequencing chip further comprises a lower cover, which covers all common buffer flow channels; a second interface is provided in the lower cover, which is connected to the common buffer flow channels.

[0026] The present invention also provides a sequencing chip, comprising a substrate, a sample flow channel disposed above the substrate, and a buffer flow channel disposed below the substrate, characterized in that at least two rows of single-pore liquid storage cavities communicating with the sample flow channel are disposed between the sample flow channel and the substrate; an electrode is disposed on the substrate, and one end of the electrode is connected to the single-pore liquid storage cavity;

[0027] At least one common low-resistance flow channel is also arranged above the substrate, and the common low-resistance flow channel is connected to the single-hole liquid storage cavity through a liquid resistance flow channel; a first substrate perforation connected to one end of the common low-resistance flow channel is provided on the substrate, and the first substrate perforation is connected to the buffer flow channel.

[0028] Furthermore, a first structural layer is provided above the substrate, and a single-hole liquid storage cavity and the common low-resistance flow channel are provided in the first structural layer.

[0029] Furthermore, a second structural layer is provided on the first structural layer, and at least one row of sample flow channels is provided in the second structural layer, and one row of sample flow channels corresponds to and is connected to at least one row of single-hole liquid storage cavities.

[0030] Furthermore, a third structural layer is provided below the substrate, and a buffer flow channel is provided in the third structural layer.

[0031] Furthermore, a membrane layer is provided in the single-hole liquid storage cavity, and nanopores for molecules to pass through are provided on the membrane layer.

[0032] Furthermore, the membrane layer is arranged at the interface between the sample flow channel and the single-hole liquid storage cavity.

[0033] Furthermore, the liquid resistance flow channel is arranged on the lower surface of the first structural layer, and / or the liquid resistance flow channel is arranged on the upper surface of the substrate.

[0034] Furthermore, the liquid resistance flow channel is a straight extension structure, an arc structure or a folded line structure.

[0035] Furthermore, a second substrate through-hole is provided on the substrate, and the second substrate through-hole is connected to the other end of the first substrate through-hole provided in the common low-resistance flow channel; the second substrate through-hole is connected to the buffer flow channel.

[0036] Furthermore, a first substrate perforation is provided at one end of each common low-resistance flow channel, and a second substrate perforation is provided at the other end of each common low-resistance flow channel, and neither the first substrate perforation nor the second substrate perforation is located between two adjacent rows of single-hole liquid storage cavities.

[0037] Furthermore, the sample flow channels connected to a row of single-hole liquid storage chambers are connected to each other to form a common sample flow channel; one end of the common sample flow channels in different rows converge and a sample inlet is set, and the other end of the common sample flow channels in different rows converge and a sample outlet is set; a column of buffer flow channels located on one side of the first substrate perforation is a common buffer flow channel connected to multiple first substrate perforations, and a column of buffer flow channels located on one side of the second substrate perforation is a common buffer flow channel connected to multiple second substrate perforations.

[0038] Furthermore, the common sample flow channels in different rows are isolated from each other or connected to form a whole flow channel.

[0039] Furthermore, the plurality of common low-resistance flow channels converge at two ends, and the first substrate through-hole and the second substrate through-hole are arranged at the convergence of the two ends of the plurality of common low-resistance flow channels.

[0040] Furthermore, the sequencing chip further comprises an upper cover, which covers all common sample flow channels; a first interface is provided in the upper cover, which is in communication with the common sample flow channels.

[0041] Furthermore, the sequencing chip further includes a lower cover, which covers all common buffer flow channels; a second interface is provided in the lower cover, and the second interface is connected to the common buffer flow channel.

[0042] The present invention also provides a method for preparing a sequencing chip, which is used to prepare the above-mentioned sequencing chip, comprising:

[0043] S1. preparing a substrate and a third structural layer, and forming an electrode on the substrate;

[0044] S2, forming a sacrificial structure of a liquid resistance flow channel on the substrate;

[0045] S3, forming a first structural layer covering the sacrificial structure of the liquid resistance flow channel on the substrate, and forming a single-hole liquid storage cavity in the first structural layer;

[0046] S4, forming a second structural layer above the first structural layer, and forming a sample flow channel in the second structural layer;

[0047] S5, forming a buffer flow channel in the third structural layer;

[0048] S6, forming a substrate through-hole in communication with the buffer flow channel on the substrate until a portion of the sacrificial structure of the liquid resistance flow channel is exposed;

[0049] S7, removing the sacrificial structure of the liquid resistance flow channel to achieve communication between the single-hole liquid storage cavity and the buffer flow channel;

[0050] S8. Construct a membrane layer in the single-hole liquid storage cavity.

[0051] The present invention also provides another method for preparing a sequencing chip, which is used to prepare the above-mentioned sequencing chip, comprising:

[0052] S1. preparing a substrate and a third structural layer, and forming an electrode on the substrate;

[0053] S2, forming a sacrificial structure of a liquid resistance flow channel on the substrate;

[0054] S3, forming a first structural layer covering the liquid resistance flow channel sacrificial structure above the substrate, and forming a single-hole liquid storage cavity and a common low-resistance flow channel in the first structural layer;

[0055] S4, forming a buffer flow channel on the third structural layer;

[0056] S5, forming a first substrate through-hole and a second substrate through-hole in communication with the buffer flow channel on the substrate;

[0057] S6. forming a second structural layer on the temporary substrate;

[0058] S7, forming a sample flow channel on the second structural layer;

[0059] S8, bonding the second structural layer with the temporary substrate to the first structural layer;

[0060] S9, removing the temporary base;

[0061] S10. Remove the sacrificial structure of the liquid resistance flow channel.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] The sequencing unit provided by the present invention features a perforated substrate, connecting a single-pore liquid reservoir and a buffer flow channel via a liquid resistance channel. This overall structure can be fabricated using established processing techniques and is not limited by substrate thickness, significantly relaxing the required depth-to-width ratio of the substrate perforation. Furthermore, the present invention positions the sample and buffer flow channels on either side of the substrate, further reducing the vertical footprint of a single nanopore device. Consequently, compared to the device density of 3,000 nanopores per square centimeter in conventional nanopore devices, the nanopore device provided by the present invention can achieve a density of 100,000 nanopores per square centimeter.

[0064] The sequencing chip provided by the present invention provides a common low-resistance flow channel on the substrate, thereby reducing the number of substrate perforations and lowering the substrate processing cost. In addition, there is no need for one detection unit to correspond to one substrate perforation, and a common low-resistance flow channel with a smaller width can be used, thereby increasing the arrangement density of the sequencing units and improving the sequencing throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG1 is a top view of the sequencing unit provided by the present invention.

[0066] FIG2 is a cross-sectional view taken along line AA in FIG1 .

[0067] FIG3 is a bottom view of the sequencing unit provided by the present invention.

[0068] FIG4 is a top view of the first embodiment of the sequencing chip.

[0069] FIG5 is a BB cross-sectional view in FIG4 .

[0070] FIG6 is a cross-sectional structural diagram of a second embodiment of a sequencing chip.

[0071] FIG7 is a cross-sectional structural diagram of the sequencing chip after adding a membrane layer and voltage to Example 2.

[0072] FIG8 is a schematic diagram of the working principle of the second embodiment of the sequencing chip.

[0073] FIG9 is a top view of the third embodiment of the sequencing chip.

[0074] FIG10 is a cross-sectional view taken along line CC in FIG9 .

[0075] FIG11 is a bottom view of the third embodiment of the sequencing chip.

[0076] FIG12 is a DD cross-sectional view in FIG11 .

[0077] FIG13 is a top view of a fourth embodiment of a sequencing chip.

[0078] FIG14 is a cross-sectional view taken along line EE in FIG13 .

[0079] FIG15 is a bottom view of the fourth embodiment of the sequencing chip.

[0080] FIG16 is a cross-sectional view taken along line FF in FIG15 .

[0081] FIG17 is a top view of the fifth embodiment of the sequencing chip.

[0082] FIG18 is a cross-sectional view of GG in FIG17 .

[0083] FIG19 is a top view of Example 6 of a sequencing chip.

[0084] FIG20 is a cross-sectional view taken along line HH in FIG19 .

[0085] FIG21 is a schematic diagram of the first embodiment of the seventh process for preparing a sequencing chip provided by the present invention.

[0086] FIG22 is a second schematic diagram of Example 7 of the preparation process of the sequencing chip provided by the present invention.

[0087] FIG23 is a third schematic diagram of Example 7 of the preparation process of the sequencing chip provided by the present invention.

[0088] FIG24 is a fourth schematic diagram of Example 7 of the preparation process of the sequencing chip provided by the present invention.

[0089] FIG25 is a fifth schematic diagram of Example 7 of the preparation process of the sequencing chip provided by the present invention.

[0090] FIG26 is a sixth schematic diagram of Example 7 of the preparation process of the sequencing chip provided by the present invention.

[0091] FIG27 is a seventh schematic diagram of Example 7 of the preparation process of the sequencing chip provided by the present invention.

[0092] FIG28 is a schematic diagram eight of Example 7 of the preparation process of the sequencing chip provided by the present invention.

[0093] FIG29 is a schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0094] FIG30 is a second schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0095] FIG31 is a third schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0096] FIG32 is a fourth schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0097] FIG33 is a fifth schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0098] FIG34 is a sixth schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0099] FIG35 is a seventh schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0100] FIG36 is a schematic diagram eight of Example eight of the preparation process of the sequencing chip provided by the present invention.

[0101] FIG37 is a seventh schematic diagram of Example 8 of the preparation process of the sequencing chip provided by the present invention.

[0102] FIG38 is a schematic diagram eight of Example eight of the preparation process of the sequencing chip provided by the present invention.

[0103] Description of reference numerals:

[0104] 101. Substrate, 102. First structural layer, 103. Second structural layer, 104. Third structural layer, 105. Electrode, 106. Sacrificial structure of liquid resistance flow channel, 107. Upper cover, 108. Lower cover, 201. Sample flow channel, 202. Buffer flow channel, 203. Single-hole liquid storage chamber, 204. Liquid resistance flow channel, 205. Substrate perforation, 211. Sample inlet, 211', Sample outlet, 212. Buffer inlet, 212', Buffer outlet, 221. First interface, 222. Second interface, 301. Membrane layer, 302. DNA molecule, 214. Common low-resistance flow channel, 215. First substrate perforation, 215', second substrate perforation, 401. Temporary substrate, 93. Amplifying circuit, 94. Computer. DETAILED DESCRIPTION

[0105] The technical solution of the present invention will be clearly described below in conjunction with the accompanying drawings. Obviously, the described embodiments are not all embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0106] It should be further explained that the structures shown in the accompanying drawings are merely conceptual diagrams and are not drawn strictly according to geometric proportions.

[0107] Sequencing unit

[0108] The present invention provides a sequencing unit, as shown in Figures 1 and 2, comprising a substrate 101, a sample flow channel 201 disposed above the substrate 101, and a buffer flow channel 202 disposed below the substrate 101; a single-pore liquid storage chamber 203 is disposed between the sample flow channel 201 and the substrate, wherein a membrane layer may be disposed within the single-pore liquid storage chamber 203, and a nanopore for molecules to pass through the membrane layer is disposed on the membrane layer; a sensing electrode 105 is disposed on the substrate 101, and one end of the electrode 105 is connected to the single-pore liquid storage chamber 203;

[0109] The substrate 101 is further provided with a substrate through-hole 205 , which connects the buffer flow channel below the substrate 101 to the top of the substrate 101 ; the substrate through-hole 205 is connected to the single-hole liquid storage cavity 203 via a liquid resistance flow channel 204 .

[0110] The liquid resistor flow channel 204 is a channel with a small height and width and a long length. Its main purpose is to achieve a liquid resistor of a given size by adjusting its length and cross-sectional area. However, considering the processing accuracy and the requirements in actual use, the length of the liquid resistor flow channel 204 is mostly from a dozen to several dozen microns, the width is mostly from 500 nanometers to one micron, and the height is mostly several hundred nanometers. Since the substrate perforation 205 is designed to penetrate the substrate, its length can be designed to be 50um to 500um, which is about ten times that of the liquid resistor flow channel 204; in order to make the resistance of the substrate perforation 205 much smaller than that of the liquid resistor flow channel 204, the cross-sectional area of ​​the substrate perforation 205 will be much larger than that of the liquid resistor flow channel. The resistance value of the substrate perforation 205 can be adjusted by setting the substrate thickness and the cross-sectional area of ​​the substrate perforation.

[0111] For example, the liquid resistance channel 204 has a length of 50 μm, a width of 1 μm, and a height of 0.1 μm. The cross-sectional area of ​​the substrate through-hole 205 is 10 μm × 10 μm, and the length is 500 μm. Therefore, the calculated resistance of the liquid resistance channel 204 is 100 times the resistance of the substrate through-hole 205.

[0112] When in working state, the sample flow channel 201, the substrate perforation 205, the buffer flow channel 202 and the liquid resistance flow channel 204 are all filled with electrolyte solution. Corresponding voltages are introduced on both sides of the sample flow channel 201 and the buffer flow channel 202 to encourage DNA molecules to pass through the nanopores in the membrane layer. The base sequence of the DNA molecule is identified by the change in resistance value in the nanopore reflected by the change in potential detected by the sensing electrode 105.

[0113] In addition, as shown in FIG2 , a first structural layer 102 is disposed above the substrate 101, and a single-pore liquid storage cavity 203 is disposed within the first structural layer 102. A second structural layer 103 is disposed above the first structural layer 102, and a sample flow channel 201 is disposed within the second structural layer 103. The sample flow channel 201 is connected to the single-pore liquid storage cavity 203. Although FIG18 shows that the single-pore liquid storage cavity 203 and the common low-resistance flow channel 214 are disposed in different structural layers from the sample flow channel 201, it is conceivable that the single-pore liquid storage cavity 203 and the common low-resistance flow channel 214 can also be disposed in the same structural layer as the sample flow channel 201 by methods such as embossing or 3D printing.

[0114] The membrane layer 301 (see FIG7 ) is disposed at the interface between the sample flow channel 201 and the single-hole liquid storage chamber 203. The membrane layer 301 may be a bilayer film composed of amphiphilic molecules, or a solid film composed of materials such as silicon nitride and graphene.

[0115] As shown in FIG3 , the buffer flow channel 202 is defined by the third structural layer 104 . The third structural layer 104 is disposed below the substrate 101 . The buffer flow channel 202 is disposed in the third structural layer 104 . The buffer flow channel 202 is connected to the substrate through-hole 205 .

[0116] The liquid resistance flow channel 204 is disposed on the lower surface of the first structural layer 102. Aside from the liquid resistance flow channel 204, there is no communication between the single-hole liquid storage cavity 203 and the substrate through-hole 205. That is, the single-hole liquid storage cavity 203 and the substrate through-hole 205 are connected only through the liquid resistance flow channel 204. The liquid resistance flow channel 204 can be in the form of a straight line, or an arc, for example, encircling the single-hole liquid storage cavity before connecting to the substrate through-hole; or in the form of a folded line, for example, connecting to the single-hole liquid storage cavity and then connecting to the substrate through-hole using a rectangular, circuitous folded line structure.

[0117] In other embodiments, the liquid resistance flow channel 204 may also be provided on the upper surface of the substrate 101. The liquid resistance flow channel structure in this embodiment may also be in the form of a straight line, an arc line, or a folded line.

[0118] Example 1, sequencing chip:

[0119] As shown in Figure 4 , the sequencing chip provided in this embodiment includes a row of sequencing units, each row containing multiple sequencing units. The sample flow channels 201 of the multiple sequencing units are interconnected to form a common sample flow channel. The area enclosed by the dotted line in Figure 4 is a buffer flow channel 202, which is interconnected to form a common buffer flow channel. The common sample flow channel has a sample inlet 211 at one end and a sample outlet 211' at the other. The common buffer flow channel has a buffer inlet 212 at one end and a buffer outlet 212' at the other.

[0120] Figure 5 shows a cross-sectional view of the sequencing chip. The sample solution flowing in from the sample inlet 211 passes through the common sample flow channel and flows into the sample flow channel of each sequencing unit. Each sample flow channel 201 is connected to a corresponding single-pore liquid reservoir 203. The single-pore liquid reservoir 203 is connected to the buffer flow channel 202 via a liquid resistance flow channel 204 and a substrate through-hole 205.

[0121] Example 2, sequencing chip:

[0122] This embodiment differs from the first embodiment in that, as shown in FIG6 , an upper cover 107 is further provided above the second structural layer 103. The upper cover 107 covers and bonds the second structural layer 103. A first interface 221 communicating with the common sample flow channel is provided on the upper cover 107. The first interface 221 allows liquid to enter and electrodes to be connected. A lower cover 108 is provided below the third structural layer 104. The lower cover 108 covers and bonds the third structural layer 104. A second interface 222 communicating with the common buffer flow channel is provided on the lower cover 108. The second interface 222 allows liquid to enter and electrodes to be connected.

[0123] After the chip is assembled, a bilayer embedded with porins is constructed between the single-pore liquid storage cavity 203 and the sample flow channel 201 through a certain film-forming pore-embedding method. As shown in FIG7 , the brief process of the film-forming pore-embedding method is as follows: First, a buffer solution (a polar solution containing the required electrolyte) is injected into the sample flow channel 201 and the buffer flow channel 202 through the first interface 221 and the second interface 222. The buffer solution fills the sample flow channel 201, the single-pore liquid storage cavity 203, the buffer flow channel 202, the substrate perforation 205, and the liquid resistor flow channel 204. Then, a non-polar solution containing bipolar molecules is injected from the first interface 221. Due to the laminar flow characteristics of the liquid in the microchannel, the non-polar solution will only remove the buffer in the sample flow channel 201, but not the buffer in the single-pore liquid storage cavity 203. Moreover, due to the different polarities of the two liquids, the bipolar molecules will form a bipolar molecular film at the liquid interface of the single-pore liquid storage cavity 203 at the opening of the sample flow channel 201. Finally, the buffer solution is injected into the sample channel 201 through the first interface 221 to replace the non-polar solution. Similarly, due to the different polarities of the two liquids, the bipolar molecules will form a bimolecular membrane layer at the opening of the single-pore liquid storage chamber 203 located in the sample channel 201, a bilayer film composed of two layers of bipolar molecules. After the bilayer film is formed, it begins to embed. First, an embedding solution containing porins is injected into the sample channel 201 through the first interface 221 to replace the buffer solution originally present in the sample channel 201. A voltage is applied to the sample channel 201 and the buffer channel 202 through the first interface 221 and the second interface 222, thereby forming an electric potential difference on both sides of the bilayer. This potential difference will change the permeability of the bilayer, thereby forming nano-sized micropores on the surface of the bilayer. At the same time, the porins in the embedding solution will move toward the micropores under the action of the electric field due to their electrical properties, and will eventually be embedded in the micropores. Finally, a buffer solution is injected into the sample flow channel 201 through the first interface 221 to replace the embedded well solution for subsequent storage.

[0124] In the sequencing state, the sample solution enters the sample flow channel 201 from the sample inlet 211, thereby replacing the original buffer. As shown in Figure 7, the voltage V3 is applied to one side of the sample flow channel 201 of the bilayer through the first interface 221, while the voltage V2 is applied to the side of the buffer flow channel 202 through the second interface 222, and passes through the liquid resistance flow channel 204, and finally applied to the side of the single-pore liquid storage chamber 203. Due to the presence of the liquid resistance flow channel 204, the voltage V1 detected by the sensing electrode of the single-pore liquid storage chamber 203 will be less than the voltage V2. When the DNA molecule 302 passes through the bilayer (membrane layer 301) embedded with pore proteins, the resistance ratio between the nanopore protein embedded in the bilayer and the liquid resistance flow channel 204 will change. According to the change pattern of the voltage V1 detected by the sensing electrode, the base arrangement of the DNA molecule can be identified.

[0125] Figure 8 shows a schematic diagram of the circuit after the sequencing chip is connected to the corresponding sequencing system, in which the resistance between the fixed voltage V2 and V3 is mainly composed of the resistance R1 of the porin and the resistance R2 of the liquid resistance flow channel. The voltage V1 will be collected and amplified by an amplifier circuit 93 and transmitted and recorded in the electrical signal database of the sequencing system (computer 94). Since the DNA molecule 302 passes through the porin during the sequencing process, and the DNA base combination passing through the porin at different times varies, the overall resistance R1 of the porin will change over time, that is, the resistance R1 of the porin can be regarded as a variable resistor. Therefore, the voltage V1 at a given time can be used to determine the total resistance of the porin and the base combination currently passing through the pore. Then, using a deep learning algorithm, the base sequence of the DNA molecule passing through the porin can be calculated. At the same time, due to the separation between the sample flow channel and the buffer flow channel in this embodiment, cross-contamination and leakage between samples are reduced, and the signal-to-noise ratio of the signal is improved.

[0126] Example 3, sequencing chip:

[0127] The sequencing chip provided in this embodiment includes multiple rows of sequencing units (only three rows of sequencing units are shown in Figure 9, but the specific number of rows can be set by those skilled in the art as needed and is not limited to the number shown in the figure). Each row of sequencing units contains multiple sequencing units, and the sample flow channels 201 of the sequencing units in the same row are interconnected to form a common sample flow channel, and the buffer flow channels 202 of the sequencing units in the same row are interconnected to form a common buffer flow channel.

[0128] As shown in FIG9 , there are three common sample flow channels, and one end of the three common sample flow channels converges to form a sample inlet 211, and the other end of the three common sample flow channels converges to form a sample outlet 211′. As shown in FIG11 , there are three common buffer flow channels, and one end of the three common buffer flow channels converges to form a buffer inlet 212, and the other end of the three buffer flow channels converges to form a buffer outlet 212′.

[0129] Figures 10 and 12 show cross-sectional views of the internal structure of the sequencing chip, in which the liquid resistance channel 204 is connected to the single-hole liquid storage chamber 203. The liquid resistance channel 204 then circles the single-hole liquid storage chamber 203 and connects to the substrate perforation 205. Because the sample channel 201 and buffer channel 202 of the sequencing chip converge at both ends, liquid and voltage can be directly supplied to the microfluidic systems on the upper and lower sides of the substrate 101 through the first interface 221 and second interface 222 of the upper cover 107 and lower cover 108. If the liquid resistance of the sample channel 201 and buffer channel 202 is low, the electrodes on the two interfaces can be used alone to provide voltage to the two separation channel systems.

[0130] Example 4: Sequencing Chip

[0131] As shown in FIG13 , the difference between this embodiment and the third embodiment is that the three common sample flow channels are connected to form an integral common sample flow channel, and a sample inlet 211 is provided at one end of the integral common sample flow channel, and a sample outlet 211' is provided at the other end; similarly, as shown in FIG15 , the three common buffer flow channels are connected to form an integral common buffer flow channel, and a buffer inlet 212 is provided at one end of the integral buffer flow channel, and a buffer outlet 212' is provided at the other end.

[0132] Figures 14 and 16 are cross-sectional views of the internal structure of the sequencing chip. The internal structure, which is identical to that of Example 3, is not described here. The difference from Example 3 is that the common sample flow channel formed in the second structural layer 103 covers the single-well liquid reservoir cavities 203 of the multiple rows of molecular detection units, and the common buffer flow channel formed in the third structural layer 104 covers the base through-holes 205 of the multiple rows of molecular detection units.

[0133] Example 5, sequencing chip:

[0134] The sequencing chip provided in this embodiment differs from that in the third embodiment in that, as shown in Figures 17 and 18, at least one common low-resistance flow channel 214 is further provided in the first structural layer 102. In this embodiment, two common low-resistance flow channels 214 are provided, and the common low-resistance flow channels 214 are flow channels whose openings are located on the lower surface of the first structural layer 102; a common low-resistance flow channel 214 is provided between every two rows of single-hole liquid storage chambers 203, and one common low-resistance flow channel can be shared by multiple molecular detection units in two adjacent rows of molecular detection units.

[0135] A first substrate through-hole 215 and a second substrate through-hole 215' are provided on substrate 101. First substrate through-hole 215 is located at one end of a common low-resistance flow channel 214, while second substrate through-hole 215' is located at the other end of the common low-resistance flow channel 214. Both first and second substrate through-holes 215' communicate with the buffer flow channel. As can be seen in Figure 17, first and second substrate through-holes 215, 215' are located at opposite ends of the common low-resistance flow channel 214, not between adjacent rows of detection units.

[0136] Although FIG17 shows that the common low-resistance flow channel 214 is provided with a first substrate through-hole 215 and a second substrate through-hole 215' at both ends, it is conceivable that a substrate through-hole may be provided at only one end of the common low-resistance flow channel 214. For example, each common low-resistance flow channel 214 may be provided with a first substrate through-hole 215 only at the left end in the figure, or with a second substrate through-hole 215' only at the right end in the figure. Furthermore, it is conceivable that the substrate through-holes may be provided at different ends of each common low-resistance flow channel 214. For example, the upper common low-resistance flow channel 214 in FIG17 may be provided with a first substrate through-hole 215 only at the left end in the figure, while the lower common low-resistance flow channel 214 may be provided with a second substrate through-hole 215' only at the right end in the figure.

[0137] The sample channel is defined by the second structural layer 103, which is arranged above the first structural layer 102; at least one row of sample flow channels 201 is arranged in the second structural layer 103, and the sample flow channels 201 correspond to and are connected to the single-hole liquid storage cavity 203 one by one. In this embodiment, three rows of sample flow channels 201 are provided, the middle sample flow channel covers the two adjacent rows of single-hole liquid storage cavities 203, and the three rows of sample flow channels 201 converge at both ends; the three rows of sample flow channels 201 converge at one end and connect to the sample inlet 211, and converge at the other end and connect to the sample outlet 211'. Although Figure 2 shows that the single-hole liquid storage cavity 203 and the sample flow channel 201 are respectively arranged in different structural layers, it is conceivable that the single-hole liquid storage cavity 203 and the sample flow channel 201 can also be arranged in the same structural layer by methods such as stamping, 3D printing, etc.

[0138] The buffer flow channel 202 is defined by the third structural layer 104 , which is disposed below the substrate 101 . A plurality of buffer flow channels 202 are disposed within the third structural layer 104 . The buffer flow channel 202 can be multiple as shown in FIG. 11 or single as shown in FIG. 15 .

[0139] The buffer flow channels 202 are connected to the first substrate through-holes 215 and the second substrate through-holes 215'. The buffer flow channels 202 arranged on one side of the first substrate through-holes 215 serve as common buffer flow channels connected to the plurality of first substrate through-holes 215, while the buffer flow channels 202 arranged on one side of the second substrate through-holes 215' serve as common buffer flow channels connected to the plurality of second substrate through-holes 215'.

[0140] In this embodiment, every two rows of sequencing units share a common low-resistance flow channel 214. Simply providing one or two through-substrate vias at either end of the common low-resistance flow channel 214 suffices. This reduces the number of through-substrate vias, eliminating the need for a dedicated through-substrate via for each sequencing unit. Specifically, the first through-substrate via 215 and the second through-substrate via 215' can be common through-substrate vias shared by both rows of sequencing units.

[0141] Due to the high resistance characteristics of the liquid resistance flow channel 204 itself, the total resistance value of the common low resistance flow channel 214 and the substrate perforation should be smaller than the resistance value of the liquid resistance flow channel 204, so there is a certain minimum requirement for its cross-sectional area. For example, the cross-sectional area of ​​the common low resistance flow channel 214 can be designed to be 10um×50um, which is 5000 times the cross-sectional area (1um×0.1um) of the liquid resistance flow channel 204 described with reference to Figures 1-2. Under this design, if the length of the common low resistance flow channel 214 is 10 times that of the liquid resistance flow channel 204, then the resistance of the common low resistance flow channel 214 is 1 / 500 of that of the liquid resistance flow channel 204. At the same time, since the common substrate perforation does not need to be close to a single detection unit, its size can be designed to be larger. For example, the cross-sectional area of ​​the common substrate perforation can be designed to be 50um×50um, and if the substrate thickness is 10 times the length of the liquid resistance flow channel 204, then the resistance of the common substrate perforation is 1 / 2500 of the resistance of the liquid resistance flow channel 204.

[0142] Furthermore, the width of the common low-resistance flow channel required in this embodiment can be smaller than the diameter of the substrate through-holes in other embodiments, thereby increasing the array density. For example, the cross-sectional area of ​​the substrate through-hole 205 described with reference to Figures 1-2 can be 10 μm × 10 μm. If the substrate through-hole 205 is circular, its diameter is approximately 11.3 μm. That is, if one detection unit corresponds to one substrate through-hole, the distance between two adjacent rows of detection units must be greater than 11.3 μm. In contrast, in this embodiment, by locating the first substrate through-hole 215 and the second substrate through-hole 215' at both ends of the common low-resistance flow channel 214, the substrate through-hole is not located between two adjacent rows of detection units. Therefore, the distance between two adjacent rows of detection units is determined solely by the dimensions of the common low-resistance flow channel 214. The cross-sectional area of ​​the common low-resistance flow channel 214 can be designed to be 10 μm × 50 μm. In this case, the horizontal dimension of the common low-resistance flow channel 214 in Figure 18 can be set to 10 μm and the vertical dimension to 50 μm. Therefore, the distance between two adjacent rows of detection units only needs to be greater than 10 μm. Therefore, by eliminating substrate through-holes between two adjacent rows of detection units, the distance between the two adjacent rows of detection units can be shortened, thereby further increasing the array density.

[0143] Due to the high resistance characteristics of the liquid resistance flow channel itself, the total resistance value of the common low resistance flow channel should be small. Therefore, the cross-sectional area of ​​the common low resistance flow channel 214 is 10um×50um, the cross-sectional area of ​​the first substrate through-hole 215 is 50um×50um, and the cross-sectional area of ​​the second substrate through-hole 215' is 50um×50um.

[0144] Example 6, sequencing chip:

[0145] The sequencing chip provided in this embodiment differs from that in Example 5 in that, as shown in Figures 19 and 20, multiple common low-resistance flow channels 214 converge at both ends, and the first substrate perforation and the second substrate perforation are set at the convergence of the two ends of the common low-resistance flow channel, and the first substrate perforation and the second substrate perforation can also be located in the area of ​​the buffer inlet or the buffer outlet. The size of the substrate perforation in this embodiment does not need to consider the size relationship with the common low-resistance flow channel, and can be set to a larger value at the convergence of the two ends of the common low-resistance flow channel, which is convenient for processing. Moreover, compared with the substrate perforation shared by two rows of sequencing units in Example 5, the substrate perforation in this embodiment can be shared by all sequencing units in the entire detection unit array, that is, the entire detection unit array shares a very small number of common substrate perforations (only two substrate perforations in this embodiment), which reduces the number of substrate perforations that need to be manufactured, thereby further reducing the manufacturing difficulty and manufacturing cost.

[0146] Example 7. Sequencing chip preparation method:

[0147] The method for preparing a sequencing chip provided in this embodiment is used to prepare the above-mentioned sequencing unit and sequencing chip according to Embodiments 1 to 4, and specifically includes:

[0148] S1, preparing a substrate 101 and a third structural layer 104, and forming an electrode 105 on the substrate 101;

[0149] As shown in Figure 21, a substrate 101 and a third structural layer 104 are first prepared. The substrate 101 and the third structural layer 104 can be integral, such as a silicon oxide wafer, or can be made of different compositions, such as an SOI wafer. Alternatively, the third structural layer 104 can be a layer of material fabricated in some manner on the lower surface of the substrate 101. The chip substrate is a base layer containing the circuit structure required for the device, manufactured using semiconductor technology.

[0150] S2, forming a sacrificial structure 106 of a liquid resistance flow channel on the substrate 101;

[0151] As shown in FIG22 , the sacrificial structure 106 of the liquid resistance flow channel is realized by a certain pattern transfer method (such as electron beam exposure or laser direct writing) and a material deposition process (physical vapor deposition or chemical vapor deposition). The sacrificial structure can be amorphous silicon or other materials.

[0152] S3, forming a first structural layer 102 covering the sacrificial structure 106 of the liquid resistance flow channel on the substrate 101, and forming a single-hole liquid storage cavity 203 in the first structural layer 102;

[0153] As shown in FIG23 , a first structural layer 102 covering a sacrificial structure is fabricated on the substrate 101 by a certain material deposition process, and a single-hole liquid storage cavity 203 is realized by a certain pattern transfer method (such as photolithography) and / or etching process (such as reactive ion etching).

[0154] S4, forming a second structural layer 103 above the first structural layer 102, and forming a sample flow channel 201 in the second structural layer 103;

[0155] As shown in FIG24 , a second structural layer 103 is fabricated above the first structural layer 102 by a deposition process, and a sample flow channel 201 is realized in the second structural layer by a certain pattern transfer method (eg, photolithography) and / or etching process (eg, reactive ion etching).

[0156] S5, forming a buffer flow channel 202 in the third structural layer 104;

[0157] As shown in FIG. 25 , the buffer flow channel 202 is realized in the third structural layer 104 by a certain pattern transfer method (eg, photolithography) and / or etching process (eg, reactive ion etching).

[0158] S6, forming a substrate through-hole 205 on the substrate 101 that communicates with the buffer flow channel 202 until a portion of the sacrificial structure of the liquid resistance flow channel is exposed;

[0159] As shown in FIG26 , a through-substrate hole 205 is formed on substrate 101 by a pattern transfer method (e.g., photolithography) and / or an etching process (e.g., reactive ion etching) until a portion of the sacrificial structure of liquid resistance flow channel 204 is exposed. Since the primary function of through-substrate hole 205 is to connect the microfluidic system, there is no particular requirement for its cross-sectional area.

[0160] S7, removing the sacrificial structure 106 of the liquid resistance flow channel to achieve communication between the single-hole liquid storage cavity 203 and the buffer flow channel 202;

[0161] As shown in FIG27 , the sacrificial structure 106 of the liquid resistive flow channel is removed by an etching method (e.g., xenon fluoride silicon etching), thereby completing the liquid resistive flow channel 204 connecting the two microfluidic channel systems. FIG28 is a top view of the completed sacrificial structure 106 of the liquid resistive flow channel, which is a simple linear structure.

[0162] In other embodiments, the processing of the liquid resistance flow channel can also be achieved through other forms, for example, step S2 can be replaced by: etching on the substrate to form the liquid resistance flow channel, and then bonding and assembling the first structural layer on the substrate with the liquid resistance flow channel.

[0163] Example 8. Sequencing chip preparation method:

[0164] The method for preparing a sequencing chip provided in this embodiment is used to prepare the sequencing chips provided in Examples 5 and 6, and specifically includes:

[0165] S1, preparing a substrate 101 and a third structural layer 104, and forming an electrode 105 on the substrate 101;

[0166] As shown in Figure 29, a substrate 101 and a third structural layer 104 are first prepared. The substrate 101 and the third structural layer 104 can be integral, such as a silicon oxide wafer, or they can be made of different materials, such as an SOI wafer. Alternatively, the third structural layer 104 can be a layer of material fabricated in some way on the lower surface of the substrate 101. The chip substrate is a base layer containing the circuit structure required for the device, manufactured using semiconductor technology.

[0167] S2, forming a sacrificial structure 106 of a liquid resistance flow channel on the substrate 101;

[0168] As shown in FIG30 , the sacrificial structure 106 of the liquid resistance flow channel is realized by a certain pattern transfer method (such as electron beam exposure or laser direct writing) and a material deposition process (physical vapor deposition or chemical vapor deposition). The sacrificial structure can be amorphous silicon or other materials.

[0169] S3, forming a first structural layer 102 covering the sacrificial structure 106 of the liquid resistance flow channel on the substrate 101, and forming a single-hole liquid storage cavity 203 and a common low-resistance flow channel 214 in the first structural layer 102;

[0170] As shown in FIG31 , a first structural layer 102 covering a sacrificial structure is produced above the substrate 101 by using a certain material deposition process, and a single-hole liquid storage cavity 203 and a common low-resistance flow channel 214 are realized by a certain graphic transfer method (e.g., photolithography) and / or corrosion process (e.g., reactive ion etching).

[0171] S4, forming a buffer flow channel 202 and a buffer inlet 212 in the third structural layer 104;

[0172] As shown in FIG. 32 , the buffer flow channel 202 and the buffer inlet 212 are realized in the third structural layer 104 by a certain pattern transfer method (eg, photolithography) and / or etching process (eg, reactive ion etching).

[0173] S5. Forming a first substrate through-hole 215 and a second substrate through-hole 215 ′ on the substrate 101 that are in communication with the buffer flow channel 202 , wherein the first substrate through-hole 215 and the second substrate through-hole 215 ′ are both in communication with the common low-resistance flow channel 214 ;

[0174] As shown in FIG. 33 , a first substrate through-hole 215 and a second substrate through-hole 215 ′ are formed on the substrate 101 by a certain pattern transfer method (eg, photolithography) and / or an etching process (eg, reactive ion etching).

[0175] S6, forming a second structural layer 103 on the temporary substrate 401 by a deposition process; as shown in FIG34,

[0176] S7, forming a sample flow channel 201 in the second structural layer 103;

[0177] As shown in FIG. 35 , the sample flow channel 201 and the sample inlet 211 are realized in the second structural layer 103 by a certain pattern transfer method (eg, photolithography) and / or etching process (eg, reactive ion etching).

[0178] S8. After flipping the second structural layer 103 with the temporary base 401, the second structural layer 103 and the first structural layer 102 are bonded by an alignment bonding method, and the second structural layer 103 covers the common low-resistance flow channel 214 in the first structural layer 102, as shown in FIG36.

[0179] S9. Remove the temporary substrate 401 by some method. For example, the method may be to dissolve the adhesive layer between the second structural layer 103 and the temporary substrate 401, so that the temporary substrate 401 is detached and removed, as shown in FIG37.

[0180] S10, removing the sacrificial structure 106 of the liquid resistance flow channel to achieve communication between the single-hole liquid storage cavity 203 and the common low-resistance flow channel 214;

[0181] As shown in FIG38 , the sacrificial structure 106 of the liquid resistance channel is removed by a certain etching method (such as xenon fluoride silicon etching, chromium etching solution or inorganic acid solution), thereby realizing a common low resistance channel 214 connecting the two sets of micro-channel systems.

[0182] The above specific embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the scope of the technical solutions of the present invention, and all of these should be included in the scope of the claims of the present invention.

Claims

1. A sequencing unit, comprising a substrate, a sample flow channel is arranged above the substrate, and a buffer flow channel is arranged below the substrate; characterized in that: A single-hole liquid storage cavity is arranged between the sample flow channel and the substrate; an electrode is arranged on the substrate, and one end of the electrode is connected to the single-hole liquid storage cavity; A substrate through-hole is also provided on the substrate, and the substrate through-hole is connected to the buffer flow channel; the substrate through-hole is connected to the single-hole liquid storage cavity through a liquid resistance flow channel.

2. The sequencing unit according to claim 1, characterized in that A first structural layer is arranged above the substrate, and the single-hole liquid storage cavity is arranged in the first structural layer.

3. The sequencing unit according to claim 2, characterized in that: A second structural layer is arranged above the first structural layer, the sample flow channel is arranged in the second structural layer, and the sample flow channel is communicated with the single-hole liquid storage cavity.

4. The sequencing unit according to any one of claims 1 to 3, characterized in that A third structural layer is arranged below the substrate, the buffer flow channel is arranged in the third structural layer, and the buffer flow channel is connected to the substrate through-hole.

5. The sequencing unit according to any one of claims 2 to 4, characterized in that: The liquid resistance flow channel is arranged on the lower surface of the first structural layer, and / or the liquid resistance flow channel is arranged on the upper surface of the substrate.

6. The sequencing unit according to any one of claims 1 to 5, characterized in that The liquid resistance flow channel is a straight extension structure, an arc structure or a folded line structure.

7. A sequencing chip, characterized in that: It comprises at least one row of sequencing units, and each row of sequencing units comprises the sequencing unit according to any one of claims 1 to 6.

8. The sequencing chip according to claim 7, characterized in that: Each row of sequencing units includes multiple sequencing units, and the sample flow channels of the multiple sequencing units are interconnected to form a common sample flow channel; the buffer flow channels of the multiple sequencing units are interconnected to form a common buffer flow channel.

9. The sequencing chip according to claim 8, characterized in that: One end of the common sample flow channels of different rows converges and is provided with a sample inlet, and the other end of the common sample flow channels of different rows converges and is provided with a sample outlet; One end of the common buffer flow channels of different rows converges and is provided with a buffer inlet, and the other end of the common buffer flow channels of different rows converges and is provided with a buffer outlet.

10. The sequencing chip according to claim 8 or 9, characterized in that: The common sample flow channels in different rows are isolated from each other or connected to form a whole flow channel; the common buffer flow channels in different rows are isolated from each other or connected to form a whole flow channel.

11. The sequencing chip according to any one of claims 8 to 10, characterized in that: The sequencing chip also includes an upper cover, which covers all common sample flow channels; a first interface is arranged in the upper cover, and the first interface is connected to the common sample flow channels.

12. The sequencing chip according to any one of claims 8 to 11, characterized in that: The sequencing chip further includes a lower cover, which covers all common buffer flow channels; a second interface is arranged in the lower cover, and the second interface is connected to the common buffer flow channels.

13. A sequencing chip, comprising a substrate, a sample flow channel is arranged above the substrate, and a buffer flow channel is arranged below the substrate, characterized in that: At least two rows of single-hole liquid storage cavities in communication with the sample flow channel are arranged between the sample flow channel and the substrate; an electrode is arranged on the substrate, and one end of the electrode is connected to the single-hole liquid storage cavity; At least one common low-resistance flow channel is also arranged above the substrate, and the common low-resistance flow channel is connected to the single hole The liquid storage chambers are connected through a liquid resistance flow channel; a first substrate through-hole connected to one end of the common low resistance flow channel is arranged on the substrate, and the first substrate through-hole is connected to the buffer flow channel.

14. The sequencing chip according to claim 13, characterized in that: A first structural layer is arranged above the substrate, and a single-hole liquid storage cavity and the common low-resistance flow channel are arranged in the first structural layer.

15. The sequencing chip according to claim 14, characterized in that: A second structural layer is arranged on the first structural layer, and at least one row of sample flow channels is arranged in the second structural layer. The row of sample flow channels corresponds to and is connected with at least one row of single-hole liquid storage cavities.

16. The sequencing chip according to any one of claims 13 to 15, characterized in that: A third structural layer is arranged below the substrate, and a buffer flow channel is arranged in the third structural layer.

17. The sequencing chip according to any one of claims 13 to 16, characterized in that: A membrane layer is arranged in the single-hole liquid storage cavity, and nanopores for molecules to pass through are arranged on the membrane layer.

18. The sequencing chip according to claim 17, characterized in that: The membrane layer is arranged at the interface between the sample flow channel and the single-hole liquid storage cavity.

19. The sequencing chip according to any one of claims 14 to 18, characterized in that: The liquid resistance flow channel is arranged on the lower surface of the first structural layer, and / or the liquid resistance flow channel is arranged on the upper surface of the substrate.

20. The sequencing chip according to any one of claims 13 to 19, characterized in that: The liquid resistance flow channel is a straight extension structure, an arc structure or a folded line structure.

21. The sequencing chip according to any one of claims 13 to 19, characterized in that: The substrate is also provided with a second substrate through-hole communicating with the other end of the common low-resistance flow channel, and the second substrate through-hole is communicated with the buffer flow channel.

22. The sequencing chip according to claim 21, characterized in that: A first substrate perforation is provided at one end of each common low-resistance flow channel, and a second substrate perforation is provided at the other end of each common low-resistance flow channel, and neither the first substrate perforation nor the second substrate perforation is located between two adjacent rows of single-hole liquid storage cavities.

23. The sequencing chip according to claim 22, characterized in that: The sample flow channels connected to a row of single-hole liquid storage chambers are connected to each other to form a common sample flow channel; one end of the common sample flow channels in different rows converges and a sample inlet is set, and the other end of the common sample flow channels in different rows converges and a sample outlet is set; a column of buffer flow channels located on one side of the first substrate perforation is a common buffer flow channel connected to multiple first substrate perforations, and a column of buffer flow channels located on one side of the second substrate perforation is a common buffer flow channel connected to multiple second substrate perforations.

24. The sequencing chip according to claim 23, characterized in that: The common sample flow channels in different rows are isolated from each other or connected to form a whole flow channel.

25. The sequencing chip according to claim 21, characterized in that: A plurality of common low-resistance flow channels converge at two ends, and a first substrate through-hole and a second substrate through-hole are arranged at the convergence of the two ends of the plurality of common low-resistance flow channels.

26. The sequencing chip according to claim 23, characterized in that: The sequencing chip also includes an upper cover, which covers all common sample flow channels; a first interface is arranged in the upper cover, and the first interface is connected to the common sample flow channels.

27. The sequencing chip according to claim 26, characterized in that: The sequencing chip further includes a lower cover, which covers all common buffer flow channels; a second interface is arranged in the lower cover, and the second interface is connected to the common buffer flow channels.

28. A method for preparing a sequencing chip, used for preparing the sequencing chip according to any one of claims 7 to 12, characterized in that: include: S1. preparing a substrate and a third structural layer, and forming an electrode on the substrate; S2, forming a sacrificial structure of a liquid resistance flow channel on the substrate; S3, forming a first structural layer covering the liquid resistance flow channel sacrificial structure on the substrate, and forming a single-hole liquid storage cavity in the first structural layer; S4, forming a second structural layer above the first structural layer, and forming a sample flow channel in the second structural layer; S5, forming a buffer flow channel in the third structural layer; S6, forming a substrate through-hole in communication with the buffer flow channel on the substrate until a portion of the sacrificial structure of the liquid resistance flow channel is exposed; S7, removing the sacrificial structure of the liquid resistance flow channel to achieve the connection between the single-hole liquid storage cavity and the buffer flow channel; S8. Construct a membrane layer in the single-hole liquid storage cavity.

29. A method for preparing a sequencing chip, used for preparing the sequencing chip according to any one of claims 13 to 27, characterized in that: include: S1. preparing a substrate and a third structural layer, and forming an electrode on the substrate; S2, forming a sacrificial structure of a liquid resistance flow channel on the substrate; S3, forming a first structural layer covering the liquid resistance flow channel sacrificial structure above the substrate, and forming a single-hole liquid storage cavity and a common low-resistance flow channel in the first structural layer; S4, forming a buffer flow channel on the third structural layer; S5, forming a first substrate through-hole and a second substrate through-hole communicating with the buffer flow channel on the substrate; S6, forming a second structural layer on the temporary substrate; S7, forming a sample flow channel on the second structural layer; S8, bonding the second structural layer with the temporary substrate to the first structural layer; S9, removing the temporary substrate; S10, removing the sacrificial structure of the liquid resistance flow channel.

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