A / d conversion device and battery monitoring integrated circuit device

Abstract

An A / D conversion device (101) comprises: an integrator (11) into which an input signal and the output of a DAC (13) are input; a quantizer (12) to which a reference potential is applied and into which the output of the integrator (11) is input; the DAC (13) for performing DA conversion of the output of the quantizer (12); a control circuit (10) for switching between two or more operating modes including a second-order ΔΣ mode and a cyclic mode; and a potential generating circuit (14) capable of switching the reference potential to be applied to the quantizer (12) in accordance with the operating mode.

Description

A / D conversion device and battery monitoring integrated circuit device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2023-137231, filed on August 25, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to an A / D conversion device and a battery monitoring integrated circuit device.

[0003] The applicant of the present application has proposed a technology for performing AD conversion processing using a hybrid mode that combines the ΔΣ method and the cyclic method, and has further proposed an A / D conversion device that operates in at least two modes: the ΔΣ mode of the ΔΣ method, the hybrid mode that combines the ΔΣ method and the cyclic method, and the cyclic mode of the cyclic method (see, for example, Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2021-044632

[0005] For example, in the case of a battery monitoring integrated circuit device that has a low-speed, high-precision battery status detection function and a high-speed, low-precision fault diagnosis function, implementing two A / D conversion devices to accommodate two different specifications would increase the circuit implementation area and power consumption.

[0006] Furthermore, if a single A / D converter is implemented so that it can switch between multiple operating modes, the reference potential will be fixed, causing the integrator operation in the A / D converter to become saturated and unstable, resulting in a deterioration in accuracy. Furthermore, providing a quantizer and reference voltage generation circuit for each operating mode will increase the power consumption of the entire quantizer and also increase the circuit implementation area.

[0007] The present disclosure has been made in consideration of the above circumstances, and its purpose is to provide an A / D conversion device and a battery monitoring integrated circuit device in which the reference potential to be applied to the quantizer can be set for each operating mode.

[0008] One aspect of the present disclosure comprises an integrator to which an input signal and the output of a DAC are input, a quantizer to which a reference potential is applied and to which the output of the integrator is input, the DAC that performs DA conversion of the output of the quantizer, a control circuit that switches between two or more operating modes including a second-order ΔΣ mode and a cyclic mode, and a potential generation circuit that can switch the reference potential applied to the quantizer depending on the operating mode.

[0009] According to one aspect of the present disclosure, the reference potential applied by the potential generating circuit to the quantizer can be switched depending on two or more operation modes, and the reference potential to be applied to the quantizer can be set for each operation mode.

[0010] The above and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which Fig. 1 is an electrical configuration block diagram of an A / D conversion device according to a first embodiment, Fig. 2 is an electrical configuration block diagram of a battery monitoring integrated circuit device according to the first embodiment, Fig. 3 is an electrical configuration block diagram of a specific example of an A / D conversion device according to the first embodiment, Fig. 4 is a detailed circuit configuration diagram of a specific example of an A / D conversion device according to the first embodiment (basic switch states in ΔΣ mode), Fig. 5 is a detailed circuit configuration diagram of a specific example of an A / D conversion device according to the first embodiment (basic switch states in cyclic mode and hybrid mode), Fig. 6 is a first electrical configuration diagram showing a part of a DAC according to the first embodiment, and Fig. 7 is a block diagram of a specific example of an A / D conversion device according to the first embodiment. FIG. 8 is a second electrical configuration diagram showing a part of the DAC in the first embodiment, FIG. 9 is a fourth electrical configuration diagram showing a part of the DAC in the first embodiment, FIG. 10 is a diagram explaining the signal transmission paths in the cyclic mode and the hybrid mode in the first embodiment, FIG. 11 is an electrical configuration diagram of a telescopic amplifier in the second embodiment, FIG. 12 is an electrical configuration diagram of a potential generating circuit in the third embodiment, FIG. 13 is an electrical configuration diagram of a potential generating circuit in the fourth embodiment, and FIG. 14 is an electrical configuration diagram of a switch in the fourth embodiment.

[0011] Several embodiments of the A / D conversion device will be described below. In each embodiment described below, components that perform the same or similar operations are denoted by the same or similar reference numerals, and descriptions thereof will be omitted as necessary.

[0012] First Embodiment To explain the technical essence, the configuration of an A / D conversion device 101 will be described with reference to Fig. 1. The A / D conversion device 101 shown in Fig. 1 performs AD conversion processing on an analog input signal Vin to obtain a high-resolution digital output, and is configured using a ΔΣ modulator equipped with an integrator 11, a DAC 13, a quantizer 12, a potential generation circuit 14, an adder / subtractor 15, and a control circuit 10. ΔΣ modulation is a type of pulse modulation method.

[0013] The integrator 11 receives the analog input signal Vin and the output of the DAC 13. Specifically, the integrator 11 receives and integrates the result obtained by adding the output of the DAC 13 to the analog input signal Vin or by subtracting the output of the DAC 13 from the analog input signal Vin using the adder-subtractor 15.

[0014] The quantizer 12 is composed of, for example, a comparator, to which a reference potential Vref is applied from the potential generating circuit 14 and to which the output of the integrator 11 is input, and which outputs the result of comparing the output of the integrator 11 with the reference potential Vref.

[0015] The quantizer 12 is configured as a continuous-time amplifier type or a dynamic type. The potential generating circuit 14 has a reference potential changeover switch 14a, and switches a reference potential Vref using the reference potential changeover switch 14a so that the output of the integrator 11 can be quantized by the quantizer 12, and outputs the reference potential Vref to the quantizer 12. The DAC 13 converts the output of the quantizer 12 and outputs it to the adder / subtractor 15. The output of the quantizer 12 is used as the output of the A / D conversion device 101.

[0016] The potential generating circuit 14 switches the reference potential Vref applied to the quantizer 12 depending on the operation mode. For example, if the quantization bits of the quantizer 12 are three levels, the reference potential Vref is switched between two levels, which is one level less than the three levels, for each operation mode and output to the quantizer 12. The quantizer 12 quantizes the input signal by comparing it with the two-level reference potential Vref.

[0017] The control circuit 10 switches between two or more operating modes including at least a second-order ΔΣ mode and a cyclic mode. The ΔΣ mode is a mode in which the analog input signal Vin is subjected to AD conversion processing using the ΔΣ method, and among these, the second-order ΔΣ mode is a mode in which processing is performed using the ΔΣ method using integrators 11 (a first-order integrator 11a and a second-order integrator 11b described below) connected in cascade in two stages.

[0018] The cyclic mode refers to a mode in which the analog input signal Vin is AD converted using a cyclic method. In addition, the operation modes that can be set by the control circuit 10 may include a hybrid mode in which the analog residue is AD converted using a cyclic method after AD conversion using a ΔΣ method, or may be configured to switch between three or more operation modes.

[0019] The hybrid mode is a mode in which the most significant bits of the analog input signal Vin are AD converted using a primary ΔΣ method, and then the analog residual is AD converted using a cyclic method. In the hybrid mode, a primary ΔΣ operation is performed at the start of AD conversion of the analog input signal Vin, a cyclic operation is performed by switching the on / off state of the switch during the AD conversion, and the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation are combined and output as the AD conversion result of the hybrid mode.

[0020] The first-order ΔΣ mode indicates a mode in which processing is performed by first-order ΔΣ operation using a single-stage integrator 11. The control circuit 10 switches between these operation modes and controls in accordance with the operation mode.

[0021] When the control circuit 10 operates the A / D conversion device 101 in the ΔΣ mode, it switches the switch SW to connect the digital filter 16 to the subsequent stage of the A / D conversion device 101, thereby using the output of the digital filter 16 as output data. When the control circuit 10 operates the A / D conversion device 101 in the cyclic mode or hybrid mode, it uses the output of the A / D conversion device 101 as output data as is.

[0022] In addition, in the hybrid mode, the A / D conversion device 101 uses a circuit in which a shift register and a digital accumulator circuit are cascade-connected (not shown) to combine and combine the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation. In the hybrid mode, the A / D conversion device 101 combines the AD conversion result of the primary ΔΣ operation as the most significant bits and the AD conversion result of the cyclic operation as the least significant bits.

[0023] <Method of Applying the A / D Conversion Device 101> Next, a method of applying the A / D conversion device 101 shown in Fig. 1 will be described. As shown in Fig. 2, the A / D conversion device 101 can be incorporated into a battery monitoring integrated circuit device 1. The battery monitoring integrated circuit device 1 monitors a battery 3, a battery pack 4, and the like mounted on a vehicle, and is configured as, for example, an ASIC. The battery 3 is a lead battery that serves as a battery auxiliary, and its positive terminal is connected to a vehicle load (not shown) via a transistor Q1, a shunt resistor Rs1, and a transistor Q2. The negative terminal of the battery 3 is connected to a ground line Lg. The ground line Lg is connected to the ground GND of the battery monitoring integrated circuit device 1.

[0024] The battery pack 4 is configured with multiple battery cells 4a, 4b...4c, which are secondary batteries such as lithium ion batteries, connected in series in multiple stages. A common mode voltage is superimposed on the multiple battery cells 4a, 4b...4c. This common mode voltage increases as the battery cells are connected to the upper stages of the battery pack 4, i.e., the higher the potential side. Note that Figure 1 and other figures illustrate two battery cells 4a-4b of the multiple battery cells 4a, 4b...4c and their corresponding configurations, as well as the bottom-most battery cell 4c.

[0025] The positive terminal of the battery cell 4a, which is located in the top row of the battery pack 4, i.e., on the highest potential side, is connected to the vehicle load via a transistor Q3, a shunt resistor Rs2, and a transistor Q4. The negative terminal of the battery cell 4c, which is located in the bottom row of the battery pack 4, i.e., on the lowest potential side, is connected to the ground line Lg.

[0026] The power supply path of the battery 3 to the vehicle load can be opened and closed by transistor Q1. In addition, the power supply path of the battery cell 4a to the vehicle load can be opened and closed by transistors Q3 and Q4. The battery monitoring integrated circuit device 1 has functions such as detecting the current flowing through the battery 3 by shunt resistor Rs1, detecting the current flowing through the battery pack 4, i.e., battery cells 4a to 4c, by shunt resistor Rs2, and detecting the voltages of the battery cells 4a and 4b.

[0027] The battery monitoring integrated circuit device 1 has terminals P1 and P2 corresponding to the respective terminals of the shunt resistor Rs1 and terminals P3 and P4 corresponding to the respective terminals of the shunt resistor Rs2. Each terminal of the shunt resistor Rs1 is connected to the terminals P1 and P2 via a filter 5 for removing noise. The filter 5 is an RC filter including a resistor R1 connected between the high-potential terminal of the shunt resistor Rs1 and the terminal P1, a resistor R2 connected between the low-potential terminal of the shunt resistor Rs1 and the terminal P2, and a capacitor C1 connected between the terminals P1 and P2.

[0028] Each terminal of the shunt resistor Rs2 is connected to terminals P3 and P4 via a filter 6. The filter 6 is an RC filter configured similarly to the filter 5, and includes resistors R3 and R4 and a capacitor C2. The battery monitoring integrated circuit device 1 includes terminals P5 and P6 corresponding to each terminal of the battery cell 4a, terminals P7 and P8 corresponding to each terminal of the battery cell 4b, and a terminal P9 for supplying ground potential (0 V).

[0029] Each terminal of the battery cell 4a is connected to terminals P5 and P6 via a filter 7. The filter 7 is an RC filter configured similarly to the filter 5 and includes resistors R5 and R6 and a capacitor C3. Each terminal of the battery cell 4b is connected to terminals P7 and P8 via a filter 8. The filter 8 is an RC filter configured similarly to the filter 5 and includes resistors R7 and R8 and a capacitor C4. The negative terminal of the battery cell 4c, i.e., the ground line Lg, is connected to terminal P9.

[0030] The battery monitoring integrated circuit device 1 includes a multiplexer 9 and an A / D converter 101. The multiplexer 9 includes switches S1 to S8, one terminal of which is connected to terminals P1 to P8, respectively. The other terminals of the switches S1, S3, S5, and S7 are commonly connected to a first output line Lo1. The other terminals of the switches S2, S4, S6, and S8 are commonly connected to a second output line Lo2. The control circuit 10 switches the switches S1 to S8 of the multiplexer 9, thereby enabling the A / D converter 101 to detect the voltages of the battery cells 4a, 4b, ..., 4c and further to detect the current flowing through the battery 3 or the battery pack 4.

[0031] Furthermore, a chop switch 17 is provided between the output of the multiplexer 9 and the input of the A / D conversion device 101. The chop switch 17 is configured by combining switches S11 to S14 as shown in the figure. The control circuit 10 turns on switches S11 and S13 and turns off switches S12 and S14, so that the voltage of the output line can be input directly to the A / D conversion device 101. The control circuit 10 turns off switches S11 and S13 and turns on switches S12 and S14, so that the voltage of the output line can be inverted and input to the A / D conversion device 101. This makes it possible to switch the polarity of the analog input signal Vin of the A / D conversion device 101.

[0032] <Specific Configuration Example of A / D Conversion Device 101> Specific configuration examples of the A / D conversion device 101 shown in Fig. 1 will be described below with reference to Fig. 3 to Fig. 10. As shown in Fig. 3, the integrator 11 includes a first-order integrator 11a, a second-order integrator 11b, and an integrator output selector switch 11c.

[0033] The first-order integrator 11a receives the analog input signal Vin and the output of the DAC 13 via an adder-subtractor 15a. The second-order integrator 11b receives the output of the first-order integrator 11a and the output of the DAC 13 via an adder-subtractor 15b. The integrator output selector switch 11c can switch between the output of the first-order integrator 11a and the output of the second-order integrator 11b as the input to the quantizer 12, and the control circuit 10 controls the switching of the integrator output selector switch 11c to switch between the output of the first-order integrator 11a and the output of the second-order integrator 11b as the input to the quantizer 12. This makes it possible to switch between the first-order ΔΣ mode of the first-order ΔΣ method and the second-order ΔΣ mode of the second-order ΔΣ method described above.

[0034] <Specific Configuration of Main Parts of A / D Conversion Device 101> Below, the specific configuration of main parts of the A / D conversion device 101 will be described with reference to Figures 4 and 5, and the operations in the second-order ΔΣ mode, cyclic mode, and hybrid mode will be described. Figure 4 shows the basic switch states in the second-order ΔΣ mode, and Figure 5 shows the basic switch states in the cyclic mode and hybrid mode.

[0035] 4 and 5 includes a primary integrator 11a, a secondary integrator 11b, an integrator output selector switch 11c, a quantizer 12, a DAC 13, and a potential generating circuit 14. An analog input signal Vin is input to an input terminal Tis of the primary integrator 11a.

[0036] The primary integrator 11a includes capacitor switching circuits 20p to 23p and 20m to 23m, and a fully differential operational amplifier 24. Capacitor switching circuits 20p to 22p and 20m to 22m are symmetrically connected to the differential input terminals of the fully differential operational amplifier 24. Furthermore, a capacitor switching circuit 23p is connected between the non-inverting input terminal and inverting output terminal of the fully differential operational amplifier 24, and a capacitor switching circuit 23m is connected between the inverting input terminal and non-inverting output terminal.

[0037] The differential input terminals of the operational amplifier 24 are connected to the common output nodes of the capacitor switching circuits 20p to 22p and 20m to 22m, respectively. The differential output of the operational amplifier 24 is input to the input node of the second-order integrator 11b. Note that in FIGS. 4 and 5, the reference numerals of the components on each side of the differential configuration are suffixed with "p" and "m," respectively. Because the configuration is symmetrical, in the following explanation, only the configuration on the side with the reference numeral suffixed with "p" will be explained, and the explanation of the configuration on the side with the reference numeral suffixed with "m" will be omitted.

[0038] The capacitor switching circuit 20p includes a capacitor Cs1p, switches SS11p to SS14p, SSD11p, and a D / A converter 25p shown in FIG. 6. The capacitor Cs1 is used as a sampling capacitance for sampling the analog input signal Vin input from the input terminal Tis. The capacitor Cs1p charges and discharges electrical charge in response to the control circuit 10 switching the switches SS11p to SS14p on or off. One terminal of the capacitor Cs1p is connected to the input terminal Tis via the switch SS11p and to a common potential Vcm via the switch SS14p. The other terminal of the capacitor Cs1p is connected to the input node of the operational amplifier 24 via the switch SS13p and to a common potential Vcm via the switch SS12p.

[0039] Fig. 6 shows a partial equivalent circuit of the capacitor switching circuit 20p shown in Fig. 4. As shown in Fig. 4 and Fig. 6, the D / A converter 25p includes a switch SDD1*p and a capacitor Csd1p. As shown in Fig. 6, the switch SDD1*p shown in Fig. 4 is composed of a plurality of switches SDD1Tp, SDD1Mp, and SDD1Bp.

[0040] The capacitor Csd1p is used as a DAC capacitance of the D / A converter 25p. As shown in FIG. 4, a switch SSD11p is connected between the input terminal Tis and the other terminal of the capacitor Csd1p. The switch SSD11p is a switch that is controlled when the capacitor Csd1p is used as a sampling capacitance, and is configured to be on / off controllable by the control circuit 10. The capacitor Csd1p may also function as a sampling capacitance for sampling the analog input signal Vin that is input from the input terminal Tis through the switch SSD11p.

[0041] The control circuit 10 selectively turns on the switches SDD1Tp, SDD1Mp, and SDD1Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, and Vrefm to the other terminal of the capacitor Csd1p. The D / A converter reference potentials Vrefp, Vcm, and Vrefm correspond to analog voltages obtained by D / A converting the quantized output of the quantizer 12, and have a relationship of, for example, Vrefp > Vcm > Vrefm, where Vcm is a common potential. Hereinafter, the D / A converter output selected from the D / A converter reference potentials Vrefp, Vcm, and Vrefm will be referred to as VR. The D / A converter reference potentials Vrefp, Vcm, and Vrefm are voltages that depend on the magnitude result of the quantizer 12 comparing the input signal with the reference potential Vref of the potential generation circuit 14.

[0042] The capacitor switching circuit 21p shown in FIG. 4 includes a capacitor Ccc1p, switches SC11p, SC14p, SCD11p to SCD13p, and a D / A converter 26p shown in FIG. 7. The capacitor Ccc1p is configured to charge and discharge in response to the control circuit 10 switching on and off the switches SC11p, SC14p, SCD12p, and SCD13p. One terminal of the capacitor Ccc1p is connected to the input node of the operational amplifier 24 via the switch SCD13p and to the node of the common potential Vcm via the switch SCD12p. The other terminal of the capacitor Ccc1p is connected to the output node of the primary integrator 11a via the switch SC11p and to the node of the common potential Vcm via the switch SC14p.

[0043] Fig. 7 shows a partial equivalent circuit of the capacitor switching circuit 21p shown in Fig. 4. As shown in Figs. 4 and 7, the D / A converter 26p includes a switch SCD1*p and a capacitor Ccd1p. The capacitor Ccd1p is used as a DAC capacitance of the D / A converter 26p. As shown in Fig. 7, the switch SCD1*p shown in Fig. 4 is composed of a plurality of switches SCD1Tp, SCD1Mp, and SCD1Bp.

[0044] The D / A converter 26p includes multiple switches SCD1Tp, SCD1Mp, and SCD1Bp and a capacitor Ccd1p. The control circuit 10 selectively turns on the switches SCD1Tp, SCD1Mp, and SCD1Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, and Vrefm to the other terminal of the capacitor Ccd1p as the D / A converter output VR. A switch SCD11p is connected between the output node of the primary integrator 11a and the other terminal of the capacitor Ccd1p. The switches SC11p and SC11p are used when sampling the voltage at the output node of the primary integrator 11a to the capacitors Ccc1p and Ccd1p in a cyclic manner, and are configured to be on / off controllable by the control circuit 10.

[0045] The capacitor switching circuit 22p shown in FIG. 4 includes a capacitor Ccc2p, switches SC21p, SC24p, SCD21p to SCD23p, and a D / A converter 27p shown in FIG. 8. The capacitor Ccc2p is configured to charge and discharge in response to the control circuit 10 switching on or off the switches SC21p, SC24p, SCD22p, and SCD23p. One terminal of the capacitor Ccc2p is connected to the input node of the operational amplifier 24 via the switch SCD23p and to the node of the common potential Vcm via the switch SCD22p. The other terminal of the capacitor Ccc2p is connected to the output node of the primary integrator 11a via the switch SC21p and to the node of the common potential Vcm via the switch SC24p.

[0046] Fig. 8 shows a partial equivalent circuit of the capacitor switching circuit 21p shown in Fig. 4. As shown in Figs. 4 and 8, the D / A converter 27p includes a switch SCD2*p and a capacitor Ccd2p. The capacitor Ccd2p is used as a DAC capacitance of the D / A converter 27p. As shown in Fig. 8, the switch SCD2*p shown in Fig. 4 is composed of a plurality of switches SCD2Tp, SCD2Mp, and SCD2Bp.

[0047] The D / A converter 27p includes multiple switches SCD2Tp, SCD2Mp, and SCD2Bp and a capacitor Ccd2p. The control circuit 10 selectively turns on the switches SCD2Tp, SCD2Mp, and SCD2Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, and Vrefm to the other terminal of the capacitor Ccd2p as the D / A converter output VR. A switch SCD21p is connected between the output node of the primary integrator 11a and the other terminal of the capacitor Ccd2p. The switches SC21p and SCD21p are used when sampling the voltage at the output node of the primary integrator 11a to the capacitors Ccc2p and Ccd2p in a cyclic manner, and are configured to be on / off controllable by the control circuit 10.

[0048] The capacitor switching circuit 23p shown in FIG. 4 includes switches SF11p, SF14p, SA12p, and a capacitor Cf11. The capacitor Cf11 is configured as a feedback capacitor between the input node of the operational amplifier 24 and the output node of the primary integrator 11a. One terminal of the capacitor Cf11 is connected to the input node of the operational amplifier 24 and to the node of common potential Vcm via the switch SA12p. The other terminal of the capacitor Cf11p is connected to the output node of the primary integrator 11a via the switch SF11p and to the node of common potential Vcm via the switch SF14. As mentioned above, the description of the wiring on the side marked with the subscript m will be omitted.

[0049] The switches in the capacitor switching circuits 20p to 23p and 20m to 23m are listed below: the primary integrator 11a includes switches SS11p to SS14p, SS11m to SS14m, SC11p, SC14p, SC11m, SC14m, SCD11p to SCD13p, SCD11m to SCD13m, SC21p, SC24p, SCD21p to SCD23p, SCD21m to SCD23m, SDD1*p, SCD1*p, SCD2*p, SF11p, SA12p, SF14p, SF11m, SA12m, and SF14m.

[0050] The input capacitors Cs1p, Csd1p, Cs1m, and Csd1m, and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, and Ccd2m of the D / A converters 25p to 27p and 25m to 27m that make up the DAC 12, are configured to have the same capacitance value.

[0051] The control circuit 10 turns on and off the switches SS11p to SS14p, SS11m to SS14m, SC11p, SC14p, SC11m, SC14m, SCD11p to SCD13p, SCD11m to SCD13m, SC21p, SC24p, SCD21p to SCD23p, SCD21m to SCD23m, SDD1*p, SCD1*p, SCD2*p, SF11p, SA12p, SF14p, SF11m, SA12m, and SF14m, thereby controlling the switches SS11p to SS14p, SS11m to SS14m, SC11p, SC14p, SC The gain of a switched capacitor amplifier that combines SF11m, SC14m, SCD11p to SCD13p, SCD11m to SCD13m, SC21p, SC24p, SCD21p to SCD23p, SCD21m to SCD23m, SDD1*p, SCD1*p, SCD2*p, SF11p, SA12p, SF14p, SF11m, SA12m, SF14m and capacitors Cs1p, Csd1p, Cs1m, Csd1m, Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, Ccd2m, Cf11p, and Cf11m can be switched.

[0052] It is preferable that the capacitors Cs1p, Csd1p, Cs1m, Csd1m and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, Ccd2m are configured by combining unit capacitors with the same unit capacitance and having the same area in an array. This minimizes mismatches in the capacitance values ​​of these capacitors. Furthermore, it is possible to reduce the gain error of the switched capacitor amplifier, achieve high linearity in the input / output characteristics of the A / D conversion device 101, and realize low gain error. Furthermore, it is possible to eliminate the need for extra capacitors and achieve a smaller device. While the capacitors Cs1p, Csd1p, Cs1m, Csd1m and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, Ccd2m that constitute the primary integrator 11a have been described here, the capacitors that constitute the secondary integrator 11b (see below) may also be configured to have the same capacitance value. Conversely, the capacitors may be configured to have different capacitance values.

[0053] A second-order integrator 11b is cascade-connected to the rear of the first-order integrator 11a. The second-order integrator 11b includes capacitor switching circuits 20bp, 20bm, 23bp, and 23bm, and a fully differential operational amplifier 24b. The capacitor switching circuits 20bp and 20bm are symmetrically connected to the differential input terminals of the fully differential operational amplifier 24b.

[0054] Furthermore, a capacitor switching circuit 23bp is connected between the non-inverting input terminal and inverting output terminal of the fully differential operational amplifier 24, and a capacitor switching circuit 23bm is connected between the inverting input terminal and non-inverting output terminal. In the following explanation, as in the above, only the configuration on the side with the subscript p will be explained, and the explanation of the configuration on the side with the subscript m will be omitted.

[0055] The capacitor switching circuit 20bp includes a capacitor Cs2p, switches SS21p to SS24p, and a D / A converter 25bp shown in FIG. 8. The capacitor Cs2p is used as a sampling capacitance for sampling the output voltage input from the output node of the primary integrator 11a through the switch SS21p. The capacitor Cs2p charges and discharges electric charge in response to the control circuit 10 switching the switches SS21p to SS24p on or off. The differential input terminals of the operational amplifier 24 are connected to the output nodes of the capacitor switching circuits 20bp and 20bm.

[0056] One terminal of the capacitor Cs2p is connected to the output node of the primary integrator 11a via a switch SS21p and to the node of the common potential Vcm via a switch SS24p, and the other terminal of the capacitor Cs2p is connected to the input node of the operational amplifier 24b via a switch SS23p and to the node of the common potential Vcm via a switch SS22p.

[0057] Fig. 9 shows a partial equivalent circuit of the capacitor switching circuit 20bp shown in Fig. 4. As shown in Fig. 4 and Fig. 9, the D / A converter 25bp includes a switch SSD2*p and a capacitor Csd2p. As shown in Fig. 9, the switch SSD2*p shown in Fig. 4 is composed of multiple switches SCD2Tp, SCD2Mp, and SCD2Bp.

[0058] The D / A converter 25bp includes a plurality of switches SDD2Tp, SDD2Mp, SDD2Bp and a capacitor Csd2. The control circuit 10 selectively turns on the switches SDD2Tp, SDD2Mp, SDD2Bp to apply one of the D / A converter reference potentials Vrefp, Vcm, and Vrefm to the other terminal of the capacitor Csd2 as the D / A converter output VR.

[0059] The capacitor switching circuit 23bp includes switches SF21p, SF24p, and SA21p, and a capacitor Cf21p. The capacitor Cf21p is configured as a feedback capacitor between the input node and output node of the operational amplifier 24b. One terminal of the capacitor Cf21p is connected to the output node of the operational amplifier 24b and to the node of common potential Vcm via a switch SA22p. The other terminal of the capacitor Cf21p is connected to the output node of the second-order integrator 11b via a switch SF21p and to the node of common potential Vcm via a switch SF24p. As mentioned above, the configuration of the side with the subscript m will not be described.

[0060] <Regarding the Integrator Output Changeover Switch 11c and the Reference Potential Changeover Switch 14a> The integrator output changeover switch 11c shown in Fig. 3 includes switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m shown in Fig. 4. As shown in Fig. 4, the switches SCMP1p and SCMP1m are connected between the output node of the primary integrator 11a and the input node of the quantizer 12. In addition, the switches SCMP2p and SCMP2m are connected between the output node of the secondary integrator 11b and the input node of the quantizer 12.

[0061] The control circuit 10 can selectively input the output of the primary integrator 11a or the output of the secondary integrator 11b to the quantizer 12 by switching between turning on the switches SCMP1p and SCMP1m and turning off the switches SCMP2p and SCMP2m, or turning off the switches SCMP1p and SCMP1m and turning on the switches SCMP2p and SCMP2m.

[0062] 3 generates the reference potentials VREF1P, VREF2P, VREF1M, and VREF2M shown in FIG. 4 or 5, and outputs them to the quantizer 12 as the reference potential Vref by selectively switching them using the reference potential changeover switch 14a.

[0063] The reference potential changeover switch 14a of the potential generating circuit 14 is composed of switches SCP1p, SCP2p, SCP1m, and SCP2m, and outputs a plurality of reference potentials Vref to the quantizer 12. Specific configuration examples of the potential generating circuit 14 will be described later in the third and fourth embodiments.

[0064] The control circuit 10 can input a reference potential Vref appropriate for the operating mode to the quantizer 12 by switching between turning on the switches SCP1p and SCP1m and turning off the switches SCP2p and SCP2m, or turning off the switches SCP1p and SCP1m and turning on the switches SCP2p and SCP2m.

[0065] 4 shows the basic states of the integrator output selector switch 11c and the reference potential selector switch 14a in the second-order ΔΣ mode. In the second-order ΔΣ mode, the control circuit 10 turns off the switches SCMP1p and SCMP1m and turns on the switches SCMP2p and SCMP2m to selectively input the output of the second-order integrator 11b to the quantizer 12. The control circuit 10 also turns on the switches SCP1p and SCP1m and turns off the switches SCP2p and SCP2m to selectively input the reference potential Vref suitable for the second-order ΔΣ mode to the quantizer 12.

[0066] 5 shows the basic states of the integrator output selector switch 11c and the reference potential selector switch 14a in the cyclic mode and the hybrid mode. In the cyclic mode and the hybrid mode, the control circuit 10 turns on the switches SCMP1p and SCMP1m and turns off the switches SCMP2p and SCMP2m to selectively input the output of the second-order integrator 11b to the quantizer 12. The control circuit 10 turns off the switches SCP1p and SCP1m and turns on the switches SCP2p and SCP2m to selectively input the reference potential Vref suitable for the cyclic mode or the hybrid mode to the quantizer 12.

[0067] In this way, it is desirable that the control circuit 10 switches the integrator output selector switch 11c and the reference potential selector switch 14a in synchronization with switching of the AD conversion operation mode, i.e., switching between the quadratic ΔΣ mode, the cyclic mode, and the hybrid mode, thereby providing the quantizer 12 with a reference potential Vref appropriate for each operation mode.

[0068] The quantizer 12 compares the integrator output with a reference potential Vref, generates a three-level (1.5-bit) quantized output, and feeds it back to the DAC 13. Which of the aforementioned D / A converter reference potentials Vrefp, Vcm, and Vrefm is output as the D / A converter output VR depends on the magnitude relationship between the input signal and the reference potential Vref of the potential generating circuit 14, as determined by the quantizer 12. Therefore, even if the stable operating range and saturation level of the integrator output differ for each operating mode, the potential generating circuit 14 can select an appropriate reference from the D / A converter reference potentials Vrefp, Vcm, and Vrefm and output it as the D / A converter output VR by switching the reference potential Vref. This allows the integrator output to be controlled within the stable operating range, enabling highly accurate A / D conversion.

[0069] <Explanation of Operation in Each Operation Mode> The following provides a brief explanation of the operation of the primary integrator 11a and the secondary integrator 11b in each operation mode: the secondary ΔΣ mode, the cyclic mode, and the hybrid mode. In the following explanation of operation, the switches that the control circuit 10 controls to be on in each operation mode will be explained, and the switches that it controls to be off will not be explained. Furthermore, since the configuration is differential and symmetrical as described above, the following explanation will be given without adding the subscripts "p, m" to the components that are symmetrical to the subscripts "p, m."

[0070] (1) Second-Order ΔΣ Mode In the second-order ΔΣ mode, the A / D conversion device 101 performs so-called oversampling type AD conversion processing. At this time, the potential generating circuit 14 generates a reference potential Vref suited to the second-order ΔΣ mode under the control of the control circuit 10 and outputs it to the quantizer 12, thereby adjusting the output of the quantizer 12. The reference potential Vref output by the potential generating circuit 14 to the quantizer 12 in the second-order ΔΣ mode is set to be smaller than the reference potential Vref output in the cyclic mode and hybrid mode, which will be described later. In the second-order ΔΣ mode, the first-order integrator 11a and the second-order integrator 11b are used for operation, but the operational stability of the integrator 11 can be ensured, allowing the quantizer 12 to perform appropriate quantization.

[0071] Both the primary integrator 11a and the secondary integrator 11b simultaneously perform a reset operation, a ΔΣ sample operation, and a ΔΣ hold operation, and then repeatedly perform the ΔΣ sample operation and the ΔΣ hold operation. At this time, the A / D conversion device 101 performs AD conversion processing by oversampling these operations a predetermined number of times, while the quantizer 12 continues to quantize and output, and the output of the quantizer 12 is low-pass filtered by the digital filter 16 to generate output data.

[0072] <Reset Operation> First, the control circuit 10 turns on switches SS14, SS12, SDD1M, SC14, SCD12, SCD1M, SC24, SCD22, SCD2M, SA12, and SF14 to discharge the accumulated charges in capacitors Cs1, Csd1, Ccc1, Ccd1, Ccc2, Ccd2, and Cf11 to a node at common potential Vcm, thereby resetting the primary integrator 11a. The control circuit 10 turns on switches SS22, SS24, SDD2M, SA22, and SF24 to discharge the accumulated charges in capacitors Cs2, Csd2, and Cf21 to a node at common potential Vcm, thereby resetting the secondary integrator 11b. Note that the control circuit 10 resets the digital filter 16 before switching to the ΔΣ mode.

[0073] During the ΔΣ mode described below, the control circuit 10 keeps the switches SCD12, SCD1M, SC14, SCD22, SCD2M, and SC24 of the primary integrator 11a on, so that the voltages across the capacitors Ccc1, Ccd1, Ccc2, and Ccd2 are kept at zero.

[0074] <ΔΣ Sampling Operation in ΔΣ Mode> The control circuit 10 turns on the switches SSD11, SS12, SS14, SCD1M, SCD12, SC14, SCD2M, SCD22, SC24, and SF11 of the primary integrator 11a. At this time, the control circuit 10 turns on the switches SSD11, SS12, and SS14 of the primary integrator 11a, causing the capacitor Csd1 to sample the analog input signal Vin. In addition, the control circuit 10 turns on the switch SF11, connecting the capacitor Cf11 between the inverting input terminal and output terminal of the operational amplifier 24.

[0075] Furthermore, the control circuit 10 turns on the switches SS21, SS22, and SSD2M of the second-order integrator 11b, thereby inputting the output of the first-order integrator 11a to the other terminal of the capacitor Cs1. At this time, the capacitor Cs2 samples the output of the first-order integrator 11a.

[0076] At the same time, the control circuit 10 turns on the switch SF21, connecting the capacitor Cf21 between the input node and the output node of the operational amplifier 24b. This allows the second-order integrator 11b to output a voltage corresponding to the charge stored in the capacitor Cf21. As described above, the control circuit 10 turns on the switch SCMP2, connecting the output of the second-order integrator 11b to the quantizer 12. This causes the quantizer 12 to quantize the output of the second-order integrator 11b and output a quantizer output Qout (Quantizer out). Based on the quantizer output Qout, the control circuit 10 selects one of the D / A converter reference potentials Vrefp, Vcm, or Vrefm to be output for D / A conversion.

[0077] <ΔΣ Hold Operation in ΔΣ Mode> Next, the control circuit 10 controls the switches SS14, SS13, SCD1M, SCD12, SC14, SCD2M, SCD22, SC24, and SF11 of the primary integrator 11a to turn on. At this time, the control circuit 10 turns on the switch SS13, thereby connecting one end of the capacitors Cs1 and Csd1 to the input terminal of the operational amplifier 24. In addition, the control circuit 10 turns on the switch SF11, thereby connecting the capacitor Cf11 to the input / output terminal of the operational amplifier 24.

[0078] The control circuit 10 also outputs the D / A converter output VR by turning on a switch (here, SDD1T) that constitutes the D / A converter. During the aforementioned <ΔΣ sample operation>, charge is accumulated in capacitor Csd1, but during <ΔΣ hold operation>, a charge corresponding to the D / A converter output VR is subtracted from the accumulated charge in capacitor Csd1, and the residual charge that is fed back is transferred to capacitor Cf11. As a result, the residual charge is accumulated in capacitor Cf11, and primary integrator 11a outputs an integrated voltage corresponding to the accumulated charge in capacitor Cf11 from its output node.

[0079] On the other hand, the control circuit 10 outputs the D / A converter output VR by turning on switches SS23, SS24, and SF21 in the second-order integrator 11b and a switch (here, SDD2T) of the D / A converter 25b. During the aforementioned <ΔΣ sample operation>, charge is accumulated in capacitor Cs2, but during <ΔΣ hold operation>, a charge corresponding to the D / A converter output VR is subtracted from the accumulated charge in capacitor Cs2, and the residual charge fed back is transferred to capacitor Cf21. As a result, the residual charge is accumulated in capacitor Cf21, and operational amplifier 24b outputs to the output node an integrated voltage by second-order integrator 11b corresponding to the accumulated charge in capacitor Cf21.

[0080] The first-order integrator 11a and the second-order integrator 11b simultaneously and alternately execute the aforementioned ΔΣ sample operation and ΔΣ hold operation a predetermined number of times. In this ΔΣ mode, the first-order integrator 11a and the second-order integrator 11b are in the same operating state at the same timing. The control circuit 10 of the A / D conversion device 101 oversamples these operations while the quantizer 12 continues to output values, and the output value of the quantizer 12 is low-pass filtered by the digital filter 16 to produce output data.

[0081] In this way, in the ΔΣ mode, the operational amplifier 24 of the primary integrator 11a and the operational amplifier 24b of the secondary integrator 11b are used, and the output of the secondary integrator 11b is quantized by the quantizer 12 while undergoing AD conversion processing by the ΔΣ method. The ΔΣ mode has secondary modulation characteristics and a greater noise shaping effect, enabling highly accurate A / D conversion.

[0082] (2) Hybrid Mode In the hybrid mode, the A / D conversion device 101 performs AD conversion processing on the analog input signal Vin using the ΔΣ method by using the first-order integrator 11a without using the operational amplifier 24b of the second-order integrator 11b, and then performs AD conversion processing on the residual using the cyclic method. At this time, the potential generating circuit 14 generates a reference potential Vref suited to the hybrid mode based on the control of the control circuit 10 and outputs it to the quantizer 12, thereby adjusting the quantized output of the quantizer 12.

[0083] In the hybrid mode, the A / D conversion device 101 may perform amplification processing by connecting a capacitor and a switch (neither of which are shown) in parallel with the capacitor Cf11 after performing AD conversion processing using the ΔΣ method and before performing AD conversion processing using the cyclic method, as described in Patent Document 1. The following description will be given of a configuration in which amplification processing is not performed.

[0084] <Reset Operation in Hybrid Mode> First, the control circuit 10 simultaneously resets the primary integrator 11a and the secondary integrator 11b. The processing operation at this time is the same as the reset operation in the ΔΣ mode, so a description thereof will be omitted. After that, the A / D conversion device 101 performs oversampling processing by alternately repeating the ΔΣ sampling operation and the ΔΣ hold operation of the ΔΣ method a predetermined number of times (e.g., several tens of times) using only the primary integrator 11a.

[0085] <ΔΣ Sampling Operation in Hybrid Mode> The control circuit 10 turns on the switches SDD1M, SS11, and SS12 of the primary integrator 11a, causing the capacitor Cs1 to sample the analog input signal Vin. At the same time, the control circuit 10 turns on the switch SF11, connecting the capacitor Cf11 between the input terminal and output terminal of the operational amplifier 24.

[0086] Furthermore, the control circuit 10 turns on the switch SCMP1 to connect the output of the primary integrator 11a to the quantizer 12. As a result, the quantizer 12 quantizes the output of the primary integrator 11a and outputs the digital signal to the control circuit 10, and the control circuit 10 selects the D / A converter output VR to be used in the subsequent ΔΣ hold operation.

[0087] On the other hand, the control circuit 10 turns on the switches SS22, SS24, SDD2M, and SF21 of the second-order integrator 11b, thereby setting the potentials across the capacitors Cs2 and Csd2 to the common potential Vcm and putting the operational amplifier 24 into a feedback state, so that the second-order integrator 11b can be put into an inactive state, as shown by the bold line in Figure 10.

[0088] <ΔΣ Hold Operation in Hybrid Mode> The control circuit 10 outputs the D / A converter output VR by turning on the switches SS14 and SS13 of the primary integrator 11a and the switch (here, SDD1T) of the D / A converter 25, and connects one end of the capacitors Cs1 and Csd1 to the inverting input terminal of the operational amplifier 24. During the aforementioned ΔΣ sample operation, charge is accumulated in the capacitor Cs1, but during the ΔΣ hold operation, a charge corresponding to the D / A converter output VR is subtracted from the accumulated charge in the capacitor Cs1, and the residual charge fed back is transferred to the capacitor Cf11. As a result, the residual charge is accumulated in the capacitor Cf11, and the operational amplifier 24 outputs from the output node an integrated voltage by the primary integrator 11a corresponding to the accumulated charge in the capacitor Cf11.

[0089] In this way, the A / D conversion device 101 performs AD conversion processing using the ΔΣ method by repeatedly executing the <ΔΣ sample operation in hybrid mode> and the <ΔΣ hold operation in hybrid mode> a predetermined number of times.

[0090] <Hybrid Mode Cyclic Operation Part 1> Thereafter, the A / D conversion device 101 performs cyclic AD conversion processing. The control circuit 10 turns on switches SC24, SCD22, and SCD2M to charge and discharge the accumulated charges in capacitors Ccc2 and Ccd2 to the common potential Vcm and reset them. The control circuit 10 also turns on switch SF11 to connect capacitor Cf11 between the input and output terminals of the operational amplifier 24.

[0091] Furthermore, the control circuit 10 turns on the switches SC11, SCD11, and SCD12 to connect the output node of the primary integrator 11a to one end of the capacitors Ccc1 and Ccd1, and samples the output voltage of the primary integrator 11a onto the capacitors Ccc1 and Ccd1.

[0092] <Hybrid Mode Cyclic Operation Part 2> Next, the control circuit 10 turns on switches SC14, SCD13, and a switch (here, SCD1T) of the D / A converter 26 to output the D / A converter output VR and connect one end of capacitors Ccc1 and Ccd1 to the input node of the operational amplifier 24. In the above-mentioned cyclic operation part 1, the output of the primary integrator 11a is sampled by capacitors Ccc1 and Ccd1, but in cyclic operation part 2, a charge corresponding to the D / A converter output VR is subtracted from the accumulated charge of capacitors Ccc1 and Ccd1, and the feedback residual charge is moved to capacitor Cf11. As a result, the residual charge is accumulated in capacitor Cf11.

[0093] At the same time, the control circuit 10 turns on the switches SC21, SCD21, and SCD22 to connect the output node of the primary integrator 11a to one end of the capacitors Ccc2 and Ccd2, and samples the output of the primary integrator 11a onto the capacitors Ccc2 and Ccd2. This allows the primary integrator 11a to perform a cyclic hold operation using the capacitor switching circuit 21 while also performing a cyclic sample operation using the capacitor switching circuit 22, allowing the cyclic sample operation and cyclic hold operation to be performed simultaneously.

[0094] <Hybrid Mode Cyclic Operation Part 3> Next, the control circuit 10 outputs the D / A converter output VR by turning on switches SC24, SCD23, and a switch (here, SCD2T) of the D / A converter 27, and connects one end of capacitors Ccc2 and Ccd2 to the inverting input terminal of the operational amplifier 24. In the above-mentioned cyclic operation part 2, the output voltage of the primary integrator 11a is sampled by capacitors Ccc2 and Ccd2, but in cyclic operation part 3, a charge corresponding to the D / A converter output VR is subtracted from the accumulated charge of capacitors Ccc2 and Ccd2, and the feedback residual charge is moved to capacitor Cf11. As a result, the residual charge is accumulated in capacitor Cf11.

[0095] At the same time, the control circuit 10 turns on the switches SC11, SCD11, and SCD12 to connect the output node of the primary integrator 11a to one end of the capacitors Ccc1 and Ccd1, and samples the output of the primary integrator 11a onto the capacitors Ccc1 and Ccd1. This allows the primary integrator 11a to perform a cyclic sample operation using the capacitor switching circuit 21 while performing a cyclic hold operation using the capacitor switching circuit 22, allowing the cyclic sample operation and cyclic hold operation to be performed simultaneously.

[0096] Thereafter, the primary integrator 11a repeats these cyclic operations 2 and 3. Therefore, the control circuit 10 adds the quantized value obtained by the cyclic AD conversion process to the value of the most significant bits generated by the ΔΣ method as the least significant bits while shifting the digits using a shift register or a data accumulation circuit, and outputs the result of this addition as output data. In this way, the final A / D conversion result is obtained.

[0097] (3) Cyclic Mode In cyclic mode, the A / D conversion device 101 performs cyclic AD conversion of the analog input signal Vin using the configuration of the first-order integrator 11a without using the second-order integrator 11b. To reduce power consumption, the operating current of the unused second-order integrator 11b is cut in this cyclic mode. The control circuit 10 may cut the operating current of the second-order integrator 11b by cutting off the power supply voltage VDD of the operational amplifier 24b that constitutes the second-order integrator 11b. This reduces current consumption. Furthermore, the potential generating circuit 14 generates a reference potential Vref suited to the cyclic mode under the control of the control circuit 10 and outputs it to the quantizer 12, thereby adjusting the output of the quantizer 12.

[0098] <Reset Operation in Cyclic Mode> First, the control circuit 10 simultaneously resets the first-order integrator 11a and the second-order integrator 11b. The processing operation at this time is the same as the reset operation in the ΔΣ mode, so a description thereof will be omitted. After that, the A / D conversion device 101 alternately repeats the cyclic sampling operation and the cyclic hold operation in the cyclic mode a predetermined number of times (for example, a dozen or so times) using only the first-order integrator 11a.

[0099] <Cyclic Sampling Operation in Cyclic Mode> The control circuit 10 turns on the switches SDD1M, SS11, and SS12 of the primary integrator 11a, causing the capacitor Cs1 to sample the analog input signal Vin. At the same time, the control circuit 10 turns on the switch SF11, connecting the capacitor Cf11 between the input and output terminals of the operational amplifier 24. The control circuit 10 also turns on the switch SCMP1, causing the output of the primary integrator 11a to be input to the quantizer 12.

[0100] Next, the control circuit 10 turns on switches SS13 and SS14 to transfer the charge accumulated in capacitor Cs1 to capacitor Cf11. At the same time, the control circuit 10 turns on switches SC11, SCD11, and SCD12 to connect the output node of the primary integrator 11a to one end of capacitors Ccc1 and Ccd1, and samples the output of the primary integrator 11a onto capacitors Ccc1 and Ccd1. This allows the primary integrator 11a to perform cyclic sampling using the capacitor switching circuit 21.

[0101] Thereafter, the primary integrator 11a repeats the same operations as <Cyclic Operation in Hybrid Mode Part 2> and <Cyclic Operation in Hybrid Mode Part 3>. This is the same as described above, so a detailed explanation will be omitted. As a result, AD conversion processing can be performed in a cyclic manner using the primary integrator 11a without using the secondary integrator 11b.

[0102] Summary of this embodiment According to this embodiment, the A / D conversion device 101 can be configured to share the quantizer 12 and the potential generating circuit 14 in the second-order ΔΣ mode, cyclic mode, and hybrid mode. This allows for miniaturization. When implemented in the same configuration area as before, the power used for other circuits can be increased and the configuration area can be increased, resulting in higher speed and higher accuracy. Furthermore, by using the integrator 11 described above, it is possible to configure the device by switching between the second-order ΔΣ mode and other operation modes.

[0103] The A / D conversion device 101 performs AD conversion processing using the first-order integrator 11a and the second-order integrator 11b in the second-order ΔΣ mode, and performs AD conversion processing using only the first-order integrator 11a in the hybrid mode and cyclic mode. As a result, the A / D conversion device 101 does not need to operate the second-order integrator 11b in modes other than the second-order ΔΣ mode, i.e., in the hybrid mode and cyclic mode.

[0104] The A / D conversion device 101 can reduce the power consumption of the second-order integrator 11b in the cyclic mode and the hybrid mode, thereby achieving low power consumption. Since the second-order integrator 11b is not used in the hybrid mode and the cyclic mode, an operational amplifier 24b of the second-order integrator 11b can be an operational amplifier with a lower gain error than the operational amplifier 24 of the first-order integrator 11a.

[0105] In this embodiment, the A / D conversion device 101 uses capacitor Csd1 as a sampling capacitance in ΔΣ mode, and capacitor Cs1 as a sampling capacitance in hybrid mode and cyclic mode. For example, if the capacitance values ​​of capacitors Cs1 and Csd1 are set to the same capacitance value, the gain of the input sampling capacitance value can be made the same between ΔΣ mode and other modes. Conversely, if the capacitance values ​​of capacitors Cs1 and Csd1 are set to different capacitance values, the gain of the input sampling capacitance value can be switched between ΔΣ mode and other modes.

[0106] Generally, when the ΔΣ mode is used, the A / D conversion accuracy is higher than that of the cyclic mode due to the effect of oversampling. However, when the ΔΣ mode is used, the A / D conversion accuracy can be maintained even if the capacitance value of the sampling capacitance by capacitor Csd1 is reduced. In this case, the configuration area of ​​the sampling capacitance by capacitor Csd1 can be minimized. Conversely, by setting the capacitance value of the sampling capacitance by capacitor Csd1 to a large value, the A / D conversion accuracy in the ΔΣ mode can be further improved.

[0107] Furthermore, the integrator output selector switch 11c can select whether the input to the quantizer 12 is the output of the primary integrator 11a or the output of the secondary integrator 11b. Therefore, in terms of the layout of the battery monitoring integrated circuit device 1, for example, when the primary integrator 11a and the secondary integrator 11b are arranged side by side in a predetermined direction (e.g., horizontally) along the surface of the semiconductor substrate, the quantizer 12 can be positioned in a direction intersecting the direction (above or below the direction). This configuration shortens the wiring connecting the primary integrator 11a, shown by the bold line in FIG. 10, to the quantizer 12 via the integrator output selector switch 11c. As a result, interference between circuits can be reduced, and circuit operation can be accelerated.

[0108] The reference potential Vref that the potential generating circuit 14 outputs to the quantizer 12 in the second-order ΔΣ mode is set to be smaller than the reference potential Vref that it outputs in the cyclic mode and the hybrid mode. Therefore, in the second-order ΔΣ mode, the operational stability of the integrator 11 can be ensured, and the quantizer 12 can perform appropriate quantization.

[0109] The capacitors Cs1p, Csd1p, Cs1m, and Csd1m, and the capacitors Csd1p, Ccd1p, Ccd2p, Csd1m, Ccd1m, and Ccd2m, may be configured by combining unit capacitors with the same area and unit capacitance in an array. This makes it easier to achieve matching and reduces mismatching. As a result, the gain error of the switched capacitor amplifier that constitutes the primary integrator 11a can be reduced, achieving high linearity and low gain error.

[0110] The control circuit 10 switches the operation mode by switching the integrator output selector switch 11c, eliminating the need for an extra capacitor. This allows the A / D conversion device 101 that realizes multiple operation modes to be configured as compact as possible.

[0111] According to this embodiment, the low-speed, high-accuracy second-order ΔΣ mode, the high-speed, low-accuracy cyclic mode, and the medium-speed, medium-accuracy hybrid mode can be realized using the same hardware. This can be configured at a lower cost than if these operating modes were implemented separately. Because the hybrid mode is a combination of the first-order ΔΣ mode and the cyclic mode, there is no need to prepare hardware for each operating mode, and it can be realized at a low cost.

[0112] Furthermore, when a high voltage of about 100 V is input as the analog input signal Vin, as in the battery monitoring integrated circuit device 1 described in this embodiment, capacitors Cs1p, Cs1m, Csd1p, and Csd1m, which serve as sampling capacitances, must have high withstand voltage capacitance. In this case, by configuring the A / D conversion device 101 of this embodiment, it is possible to achieve a configuration that can withstand high withstand voltage input, and it is also possible to switch the accuracy and speed by switching the operation mode, so it is possible to realize an A / D conversion device 101 that meets requirements.

[0113] For example, if the required accuracy and speed differ significantly between monitoring multiple battery cells 4a, 4b...4c and detecting the cell voltage of each battery cell 4a, 4b...4c with high accuracy and quickly scanning and diagnosing all of the multiple battery cells 4a...4c, a single A / D conversion device 101 can meet these requirements by switching operating modes.

[0114] Second Embodiment A second embodiment will be described with reference to Fig. 11. It is desirable to use a telescopic amplifier 224 with a gain boost amplifier as shown in Fig. 11 for the operational amplifiers 24, 24b that constitute the switched capacitor amplifier.

[0115] The telescopic amplifier 224 is configured by combining an input MOS transistor pair M1p-M1m that receives a differential input signal AINP-AINM, MOS transistor pairs M2p-M2m, M3p-M3m, and M4p-M4m that are telescopically cascode-connected to the input MOS transistor pair M1p-M1m, fully differential operational amplifiers A1 and A2, and a MOS transistor Mb that serves as a current source. Although not shown in FIG. 11, the MOS transistor Mb forms a current mirror circuit and is configured to pass a constant current Iss.

[0116] The MOS transistor pairs M1p-M1m and M2p-M2m are each composed of an n-channel MOSFET, and the MOS transistor pairs M3p-M3m and M4p-M4m are each composed of a p-channel MOSFET.

[0117] The fully differential operational amplifier A1 is provided for gain boost, and its differential input terminals are connected to a common connection point between the drains of MOS transistors M1p and M2p and between the sources of MOS transistors M1m and M2m, and its differential output terminals are connected to the gates of MOS transistors M2p and M2m.

[0118] The fully differential operational amplifier A2 is provided for gain boost, and its differential input terminals are connected to the common connection point of the drains of MOS transistors M4p and M3p and the common connection point of the drains of MOS transistors M4m and M3m. The differential output terminals of the fully differential operational amplifier A2 are connected to the gates of MOS transistors M3p and M3m. The MOS transistors M2p and M3p, and M2m and M3m are connected in common, and serve as output terminals that output differential output signals AOUTM-AOUTP.

[0119] The A / D conversion device 101 uses the operational amplifiers 24, 24b for switched capacitor amplifiers. A switched capacitor amplifier is configured by combining switches and capacitors (symbols omitted), and therefore has no current load. Therefore, by configuring the operational amplifiers 24, 24b using the telescopic amplifier 224 with a gain boost amplifier shown in FIG. 11, the switched capacitor amplifier can be configured with low power consumption and high accuracy.

[0120] However, if a single-stage amplifier is used, the current load will make it more likely to generate nonlinear errors. If a two-stage amplifier is used to increase the gain, the current consumption will increase. However, by adding fully differential operational amplifiers A1 and A2 for gain boost to a single-stage amplifier like the telescopic amplifier 224, it is possible to configure it with low power consumption and high precision.

[0121] The telescopic amplifier 224 tends to have a narrow input / output common voltage range (common range). However, as described in the first embodiment, the potential generating circuit 14 applies a changed reference potential Vref, which is the quantization threshold, to the quantizer 12. Therefore, even if the input range of the quantizer 12 is limited, the reference potential Vref can be adjusted to match the input range. This improves the flexibility of the input / output voltage range of the operational amplifier 24b, and the quantizer 12 can accurately quantize to an appropriate level even when the telescopic amplifier 224 is used for the operational amplifier 24b.

[0122] Third Embodiment A third embodiment will be described with reference to Fig. 12. In the third embodiment, an example configuration of the potential generating circuit 14 described in the first embodiment will be described as a potential generating circuit 314. The potential generating circuit 314 shown in Fig. 12 includes switches SCP1p, SCP2p, SCP1m, and SCP2m as a reference potential changeover switch 314a, and generates a plurality of reference potentials Vref to be compared by the quantizer 12. In Fig. 12, the plurality of reference potentials Vref are shown divided into a reference potential REFINP of a relatively high potential and a reference potential REFINM of a relatively low potential.

[0123] As shown in FIG. 12, the potential generating circuit 314 is configured by combining a resistor ladder Rr1 and MOSFETs M5p, M6p, M5m, and M6m. The MOSFETs M5p, M6p, M5m, and M6m are all n-channel. The resistor ladder Rr1 is configured by connecting multiple voltage-dividing resistors between a node to which the highest reference potential VREFP is applied and a node to which the lowest reference potential VREFM is applied. The reference potentials VREF2P, VREF1P, VREF1M, and VREF2M are generated by dividing the voltages of the multiple voltage-dividing resistors. Note that the relationship is VREF2P > VREF1P > VREF1M > VREF2M.

[0124] The switch SCP2p is composed of a MOSFET_M6p. The divided voltage VREF2P of the resistor ladder Rr1 is input to one of the drain or source of the MOSFET_M6p, and the other of the drain or source is connected to the input terminal of the reference potential REFINP of the quantizer 12. The switch SCP1p is composed of a MOSFET_M5p. The divided voltage VREF1P of the resistor ladder Rr1 is input to one of the drain or source of the MOSFET_M5p, and the other of the drain or source is connected to the input terminal of the reference potential REFINP of the quantizer 12.

[0125] The control circuit 10 can input one of the reference potentials VREF2P and VREF1P to the quantizer 12 as the reference potential REFINP by turning on one of the MOSFETs M5p and M6p.

[0126] The switch SCP1m is composed of a MOSFET_M5m. The divided voltage VREF1M of the resistor ladder Rr1 is input to one of the drain or source of the MOSFET_M5m, and the other of the drain or source is connected to the input terminal of the reference potential REFINM of the quantizer 12. The switch SCP2m is composed of a MOSFET_M6m. The divided voltage VREF2M of the resistor ladder Rr1 is input to one of the drain or source of the MOSFET_M6m, and the other of the drain or source is connected to the input terminal of the reference potential REFINM of the quantizer 12.

[0127] The control circuit 10 turns on one of the MOSFETs M5m and M6m, thereby inputting one of the reference potentials VREF1M and VREF2M as the reference potential REFINM to the quantizer 12. This allows the potential generating circuit 14 to input the reference potential Vref that satisfies the relationship REFINP>REFINM to the quantizer 12.

[0128] According to this embodiment, multiple reference potentials Vref (REFINP, REPINM) can be configured with low power consumption and in a small size by simply configuring a single resistor ladder Rr1. The larger the area of ​​the resistor ladder Rr1, the smaller the mismatch between each voltage-dividing resistor can be. Therefore, by adopting the resistor ladder Rr1 and increasing the mounting area of ​​each resistor in the resistor ladder Rr1, the effect of mismatch can be reduced.

[0129] When the control circuit 10 switches the output of the voltage dividing resistors by switching the MOS transistors M5p, M6p, M5m, and M6m on and off, the reference potential Vref fluctuates during the switching. For this reason, it is desirable to temporarily halt the AD conversion process when switching the operating mode of the A / D conversion device 101 and switch the reference potential Vref during this halt. Switching the reference potential Vref while the AD conversion process is temporarily halted prevents adverse effects on the AD conversion accuracy.

[0130] 13 and 14, a fourth embodiment will be described. In the fourth embodiment, a configuration example of the potential generating circuit 14 in the first embodiment will be described as a potential generating circuit 414, but the same components as in the third embodiment will be assigned the same reference numerals and will not be described again. In addition, in this embodiment, a configuration example of the integrator output selector switch 11c will be described as an integrator output selector switch 411c.

[0131] The potential generating circuit 414 includes a resistor ladder Rr2 in addition to the resistor ladder Rr1, and also includes switches SCP1p, SCP2p, SCP1m, and SCP2m as a reference potential changeover switch 414a, and generates a plurality of reference potentials Vref to be compared by the quantizer 12. In Fig. 13, the plurality of reference potentials Vref are shown divided into a reference potential REFINP of a relatively high potential and a reference potential REFINM of a relatively low potential.

[0132] The resistor ladder Rr2 is configured by connecting a plurality of voltage dividing resistors between the application node of the power supply voltage VDD and the application node of the lowest reference potential VREFM, and generates a common potential VCM0 by dividing the voltages of the plurality of voltage dividing resistors.

[0133] The switch SCP1p of the reference potential changeover switch 414a includes a MOSFET_M7p in addition to a MOSFET_M5p. The switch SCP1p is configured with two drains / sources of MOSFET_M5p and M7p connected in series. When the switch SCP1p is on, the control circuit 10 controls the MOSFET_M5p and M7p to be on and controls the MOSFET_M9p to be off. When the switch SCP1p is off, the control circuit 10 controls the MOSFET_M5p and M7p to be off and controls the MOSFET_M9p to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M9p.

[0134] The switch SCP2p of the reference potential changeover switch 414a includes a MOSFET_M8p in addition to a MOSFET_M6p. The switch SCP2p is configured with two drains / sources of MOSFET_M6p and M8p connected in series. When the control circuit 10 controls the switch SCP2p to be on, it controls the MOSFET_M6p and M8p to be on and controls the MOSFET_M10p to be off. When the control circuit 10 controls the switch SCP2p to be off, it controls the MOSFET_M6p and M8p to be off and controls the MOSFET_M10p to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M10p.

[0135] The switch SCP1m of the reference potential changeover switch 414a includes a MOSFET_M7m in addition to a MOSFET_M5m. The switch SCP1m is configured with two drain / source MOSFETs, M5m and M7m, connected in series. When the control circuit 10 controls the switch SCP1m to be on, it controls the MOSFETs M5m and M7m to be on and controls the MOSFET_M9m to be off. When the control circuit 10 controls the switch SCP1m to be off, it controls the MOSFETs M5m and M7m to be off and controls the MOSFET_M9m to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M9m.

[0136] The switch SCP2m of the reference potential changeover switch 414a includes a MOSFET_M8m in addition to a MOSFET_M6m. The switch SCP2m is configured with two drains / sources of MOSFET_M6m and M8m connected in series. When the control circuit 10 controls the switch SCP2m to be on, it controls the MOSFET_M6m and M8m to be on and controls the MOSFET_M10m to be off. When the control circuit 10 controls the switch SCP2m to be off, it controls the MOSFET_M6m and M8m to be off and controls the MOSFET_M10m to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET_M10m.

[0137] 14, the switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m of the integrator output changeover switch 411c may be configured by combining MOSFETs M11, M12, and M13, respectively. The switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m of the integrator output changeover switch 411c are configured by connecting the drain / source of two MOSFETs M11 and M12 in series.

[0138] When the control circuit 10 controls the switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m to be on, it controls the MOSFETs M11 and M12 to be on and controls the MOSFET M13 to be off. When the control circuit 10 controls the switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m to be off, it controls the MOSFETs M11 and M12 to be off and controls the MOSFET M13 to be on, thereby connecting the intermediate potential to the common potential VCM0 via the MOSFET M13.

[0139] When the reference potentials VREP1P, VREP2P, VREP1M, and VREP2M or the output of the operational amplifier 24b are close to the power supply potential VDD or the lowest reference potential VREFM (for example, ground potential), current may leak from the reference potential changeover switches SCP1p, SCP2p, SCP1m, and SCP2m and the integrator output changeover switches SCMP1p, SCMP2p, SCMP1m, and SCMP2m, resulting in large AD conversion errors.

[0140] As shown in FIG. 13, by configuring the potential generating circuit 414, an intermediate potential is set between each of the MOSFETs M5p-M7p, M5m-M7m, M6p-M8p, and M6m-M8m, and in particular, the gate-source voltage Vgs of the MOSFETs M5p or M6p, M5m or M6m can be made negative, and the substrate bias effect can be achieved, thereby reducing leakage and AD conversion errors, and improving accuracy.

[0141] As shown in FIG. 14, by configuring the integrator output changeover switch 411c, an intermediate potential is set between MOSFETs M11 and M12, and in particular, the gate-source voltage Vgs of MOSFET M11 can be made negative, thereby achieving a substrate bias effect, thereby reducing leakage, reducing AD conversion errors, and improving accuracy.

[0142] (Other Embodiments) The present disclosure is not limited to the above-described embodiments, and can be implemented in various modifications and variations without departing from the spirit of the present disclosure. For example, the following modifications or extensions are possible. Each component is conceptual and is not limited to the above-described embodiments.

[0143] The D / A converter output VR is not limited to three levels, and may be set appropriately according to the number of levels of the quantized value in the quantizer 12. The number of reference potentials Vref of the potential generating circuit 14 may also be set according to the number of levels of the quantized value in the quantizer 12. Furthermore, the number of levels of the D / A converter outputs VR of the DACs 25, 26, and 27 of the capacitor switching circuits 20, 21, and 22 may also be changed according to the number of levels of the quantized value.

[0144] The capacitance values ​​of capacitors Cs1p, Csd1p, Cs2p, Csd2p, Ccc1p, Ccc1p, Ccc2p, Ccd2p, Cf11p, Cf21p, Cs1m, Csd1m, Cs2m, Csd2m, Ccc1m, Ccc1m, Ccc2m, Ccd2m, Cf11m, and Cf21m may be scaled appropriately to correspond to the input / output range of each operational amplifier 24, 24b.

[0145] The present disclosure also includes the following aspects and modes in addition to the content described in the claims: [1] An A / D conversion device comprising: an integrator (11, 11a, 11b, 11c) to which an input signal and an output of a DAC are input, a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input, the DAC (13, 25p, 25m, 26p, 26m, 27p, 27m, 25bp, 25bm) that performs D / A conversion of the output of the quantizer, a control circuit (10) that switches between two or more operation modes including a second-order ΔΣ mode and a cyclic mode, and a potential generation circuit (14; 314; 414) that can switch the reference potential to be applied to the quantizer depending on the operation mode.

[0146] [2] The A / D conversion device of [1], wherein the integrator comprises: a first-order integrator (11a) that receives the input signal and the output of the DAC; a second-order integrator (11b) that receives the output of the first-order integrator and the output of the DAC; and an integrator output changeover switch (11c; 411c) that makes it possible to change over whether the input to the quantizer is the output of the first-order integrator or the output of the second-order integrator.

[0147] [3] The A / D conversion device according to [2], wherein in the cyclic mode, the first-order integrator is used for operation, and the operating current of the second-order integrator is cut.

[0148] [4] The A / D conversion device according to any one of [1] to [3], wherein the DAC comprises a DAC capacitance, the integrator comprises a switch and a switched capacitor amplifier configured by combining a sampling capacitance that inputs the input signal and a DAC capacitance of the DAC with the same capacitance value, and the gain of the switched capacitor amplifier is changed by switching the switch.

[0149] [5] The A / D conversion device according to any one of [1] to [4], wherein a telescopic amplifier (224) with a gain boost amplifier is used as the switched capacitor amplifier.

[0150] [6] An A / D conversion device according to any one of [1] to [4], wherein the control circuit switches between three or more modes, including a second-order ΔΣ mode that is switched by the integrator output changeover switch and uses the output of the second-order integrator, a cyclic mode that performs cyclic operation, and a hybrid mode that is switched by the integrator output changeover switch and switches between first-order ΔΣ operation that uses the output of the first-order integrator and the cyclic operation midway through conversion and performs AD conversion.

[0151] [7] An A / D conversion device according to any one of [1] to [6], wherein in the hybrid mode, the primary ΔΣ operation is performed at the start of the AD conversion, a cyclic operation is performed by switching the on / off state of a switch during the AD conversion, and the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation are combined and output as the AD conversion result in the hybrid mode.

[0152] [8] The A / D conversion device according to any one of [1] to [7], wherein the potential generating circuit is configured by combining a resistor ladder (Rr1) and a reference potential switching switch (SCP1p, SCP2p, SCP1m, SCP2m), and makes the reference potential changeable.

[0153] [9] The A / D conversion device according to any one of [1] to [8], wherein the control circuit switches the reference potential changeover switch in synchronization with switching of the operation mode of the AD conversion.

[0154]

[10] The A / D conversion device according to any one of [1] to [9], wherein the reference potential changeover switch is configured to have a first MOSFET and a second MOSFET connected in series, and when the reference potential changeover switch is turned off, the intermediate potential is connected to a common potential (VCM0) via a third MOSFET.

[0155]

[11] A battery monitoring integrated circuit device comprising: an A / D conversion device comprising: an integrator (11) to which an input signal and the output of a DAC are input; a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input; the DAC (13) having a DAC capacitance and performing D / A conversion of the output of the quantizer; a control circuit (20) that switches between two or more operation modes including a quadratic ΔΣ mode and a cyclic mode; and a potential generation circuit (14) that can switch the reference potential to be applied to the quantizer depending on the operation mode.

[0156] In the drawings, 1 indicates a battery monitoring integrated circuit device, 10 indicates a control circuit, 11 indicates an integrator, 12 indicates a quantizer, 13 indicates a DAC, 14, 314, and 414 indicate potential generating circuits, 25p, 25m, 26p, 26m, 27p, 27m, 25bp, and 25bm indicate D / A converters (DACs), and 101 indicates an A / D conversion device.

[0157] The techniques described in this disclosure may be implemented by a special purpose computer configured with a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the techniques described in this disclosure may be implemented by a special purpose computer configured with a processor comprising one or more dedicated hardware logic circuits. Alternatively, the techniques described in this disclosure may be implemented by one or more special purpose computers configured with a processor comprising one or more hardware logic circuits in combination with a processor and memory programmed to perform one or more functions. Furthermore, a computer program may be stored as instructions executed by a computer on a computer-readable non-transitory storage medium.

[0158] Although the present disclosure has been described based on the above-described embodiment, it is understood that the present disclosure is not limited to the embodiment or the structure described in the embodiment. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. An A / D conversion device comprising: an integrator (11, 11a, 11b, 11c) to which an input signal and a DAC output are input; a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input; the DAC (13, 25p, 25m, 26p, 26m, 27p, 27m, 25bp, 25bm) that performs D / A conversion of the output of the quantizer; a control circuit (10) that switches between two or more operating modes including a quadratic ΔΣ mode and a cyclic mode; and a potential generating circuit (14; 314; 414) that can switch the reference potential to be applied to the quantizer depending on the operating mode.

2. An A / D conversion device as described in claim 1, wherein the integrator comprises: a first-order integrator (11a) which inputs the input signal and the output of the DAC; a second-order integrator (11b) which inputs the output of the first-order integrator and the output of the DAC; and an integrator output changeover switch (11c; 411c) which makes it possible to change over whether the input to the quantizer is the output of the first-order integrator or the output of the second-order integrator.

3. The A / D conversion device according to claim 2, wherein in said cyclic mode, said first-order integrator is used for operation and an operating current of said second-order integrator is cut.

4. The A / D conversion device according to claim 3, wherein the DAC comprises a DAC capacitance, the integrator comprises a switch and a switched capacitor amplifier in which a sampling capacitance for inputting the input signal and a DAC capacitance of the DAC are combined to have the same capacitance value, and the gain of the switched capacitor amplifier is changed by switching the switch.

5. An A / D conversion device according to claim 4, wherein a telescopic amplifier (224) with a gain boost amplifier is used as the switched capacitor amplifier.

6. An A / D conversion device as described in claim 4 or 5, wherein the control circuit switches between three or more modes including a second-order ΔΣ mode that is switched by an output changeover switch and uses the output of the second-order integrator, a cyclic mode that performs cyclic operation, and a hybrid mode that is switched by the output changeover switch and switches between first-order ΔΣ operation that uses the output of the first-order integrator and cyclic operation midway through conversion to perform AD conversion.

7. An A / D conversion device as described in claim 6, wherein, in the hybrid mode, the primary ΔΣ operation is performed at the start of the AD conversion, a cyclic operation is performed by switching the on / off state of a switch during the AD conversion, and the AD conversion result of the primary ΔΣ operation and the AD conversion result of the cyclic operation are combined and output as the AD conversion result in the hybrid mode.

8. The A / D conversion device according to claim 4, wherein the potential generating circuit is configured by combining a resistor ladder (Rr1) and reference potential changeover switches (SCP1p, SCP2p, SCP1m, SCP2m), making the reference potential variable.

9. The A / D conversion device according to claim 8, wherein said control circuit switches said reference potential changeover switch in synchronization with the switching of said operation mode of the A / D conversion.

10. The A / D conversion device according to claim 9, wherein the reference potential changeover switch is configured to have a first MOSFET and a second MOSFET connected in series, and when the reference potential changeover switch is off, an intermediate potential between the first MOSFET and the second MOSFET is connected to a common potential (VCM0) via a third MOSFET.

11. An integrated circuit device for battery monitoring comprising an A / D conversion device comprising: an integrator (11) to which an input signal and the output of a DAC are input; a quantizer (12) to which a reference potential is applied and to which the output of the integrator is input; the DAC (13) having a DAC capacitance and performing D / A conversion of the output of the quantizer; a control circuit (20) for switching between two or more operating modes including a quadratic ΔΣ mode and a cyclic mode; and a potential generating circuit (14) capable of switching the reference potential to be applied to the quantizer depending on the operating mode.

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