Optical module

Abstract

An optical module (100). In the optical module (100), a bare die (4) is directly flip-mounted on a circuit board (3) of the optical module (100), such that high-speed signals on a host side and a line side can directly enter the interior of the bare die (4) through an electrical interface (3223) of the circuit board (3) into the circuit board (3). Therefore, the link of high-speed signals can be simplified, impedance abrupt change points are reduced, the transmission stability of the high-speed signals is improved, the integrity of the signals is improved, the transmission rate is improved, and the optical module (100) with a higher rate is implemented. Moreover, the thermal expansion coefficient of a first insulating dielectric layer (311) of a core layer structure (31) of the circuit board (3) matches the thermal expansion coefficient of the bare die (4), which can effectively improve the reliability of the bare die (4) flip-mounted on the circuit board (3).

Description

An optical module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 26, 2023, with application number 202322613213.9 and invention name “A Type of Optical Module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of optical communication technology, and in particular to an optical module. Background Art

[0003] With the rapid development of optical communications and the internet in recent years, user demand for networks has also surged, leading to a 50% to 80% annual increase in traffic on telecommunications backbone networks. To adapt to the rapidly developing network market, the transmission rate requirements for optical modules have also continued to increase, from 100G, 200G, and 400G to 800G and even 1.6T.

[0004] Current optical modules typically use semiconductor-packaged chips, such as digital signal processors (DSPs) and clock and data recovery (CDR) chips. These chips are typically packaged on a semiconductor package substrate, typically fabricated using a semi-additive process (SAP). Specifically, the bare chip is flip-chip mounted on the package substrate for packaging. The package substrate is then electrically connected to the printed circuit board (PCB) via a ball grid array (BGA). In this model, high-speed signals from the host enter the PCB via an electrical interface, then travel through striplines, microstrip lines, high-frequency coupling capacitors, PCB vias, and BGA balls to the package substrate. Finally, they pass through the striplines, microstrip lines, vias, and bumps on the package substrate before entering the bare chip. The same principle applies to high-speed signals on the line side.

[0005] The high-speed signal link in the above mode is complex and has many impedance mutation points, resulting in low transmission stability of high-speed signals. This cannot meet the requirements of high-speed optical modules, and the speed of optical modules is difficult to further increase. Utility Model Content

[0006] The purpose of the utility model is to provide an optical module that can solve the problems existing in the prior art, such as complex links and multiple impedance mutation points leading to low transmission stability of high-speed signals, inability to meet the requirements of high-speed optical modules, and difficulty in further improving the speed of optical modules.

[0007] In order to solve the above problems, the utility model provides an optical module, which includes: a shell and an optical component, a circuit board, a bare chip and a surface mount component arranged in the shell; wherein, the circuit board includes: a core layer structure, which includes a first insulating medium layer and a first conductive circuit layer arranged on both sides of the first insulating medium layer; and at least two layers of build-up layer structures, which are symmetrically arranged on both sides of the core layer structure; wherein, the surfaces of the two layers of the build-up layer structures farthest from the core layer structure on the side away from the core layer structure are provided with a surface circuit pattern, and the surface circuit pattern includes a fine flip-chip circuit, a surface mount circuit and an electrical interface; the bare chip is flip-chip on the fine flip-chip circuit, the surface mount component is mounted on the surface mount circuit, and the electrical interface is used for pluggable electrical connection with an external device.

[0008] Furthermore, the thermal expansion coefficient of the first insulating dielectric layer matches the thermal expansion coefficient of the bare chip; the thermal expansion coefficient of the first insulating dielectric layer is less than or equal to 13 ppm / °C.

[0009] Furthermore, the material of the first insulating dielectric layer is BT resin or BT-like resin.

[0010] Furthermore, the single-layer build-up structure includes a second insulating dielectric layer and a second conductive circuit layer arranged on the side of the second insulating dielectric layer away from the core layer structure; wherein, the second conductive circuit layers of the two layers of the build-up structure farthest from the core layer structure form the surface circuit pattern; wherein, the material of the second insulating dielectric layer is BT semi-cured sheet or BT-like semi-cured sheet.

[0011] Furthermore, the second conductive circuit layers of the two build-up structures farthest from the core layer structure both include a seed copper layer and a build-up copper layer stacked on the side of the seed copper layer away from the core layer structure; the seed copper layer is a thin copper layer with a thickness less than or equal to 5 microns.

[0012] Furthermore, the single-layer build-up structure includes adhesive-backed copper foil, which includes: copper foil and a resin coating without glass fiber, and the copper foil is located on a side of the resin coating away from the core layer structure.

[0013] Furthermore, the single-layer build-up structure also includes a copper-added layer arranged on the side of the adhesive-backed copper foil away from the core layer structure; the thickness of the copper foil is less than or equal to 5 microns; wherein, the two layers of copper foil of the build-up structure farthest from the core layer structure and the corresponding copper-added layers form the surface circuit pattern.

[0014] Furthermore, a multi-layer inner build-up layer structure is provided between the two build-up layer structures farthest from the core layer structure and the core layer structure; part of the inner build-up layer structure includes adhesive-backed copper foil, and is symmetrically arranged on both sides of the core layer structure; another part of the inner build-up layer structure includes a second insulating medium layer and a second conductive circuit layer arranged on the side of the second insulating medium layer away from the core layer structure, and is symmetrically arranged on both sides of the core layer structure.

[0015] Furthermore, the build-up structure comprises a high-speed circuit layer, and the high-speed circuit layer and the build-up structures on both sides adjacent thereto comprise adhesive-backed copper foil.

[0016] Furthermore, the bare chip includes one or more of a digital signal processing chip, a clock data recovery chip, a transimpedance amplifier chip, and a laser driver chip.

[0017] Furthermore, the electrical interface is a gold finger.

[0018] Furthermore, the optical module further includes a protective layer provided on the gold finger.

[0019] Furthermore, the protective layer is a nickel-palladium-gold plating layer.

[0020] Furthermore, the optical component includes a light emitting component and a light receiving component; the light emitting component and the light receiving component are electrically connected to the circuit board and electrically connected to the bare chip.

[0021] Furthermore, the optical component includes a photonic integrated chip; the photonic integrated chip is flip-chip mounted on the circuit board and electrically connected to the bare chip.

[0022] The advantages of this utility model are: the bare chip within the optical module is directly flip-mounted onto the module's circuit board, allowing high-speed signals from the host side to enter the circuit board through the circuit board's electrical interface and directly into the bare chip via strip lines, microstrip lines, high-frequency coupling capacitors, vias on the circuit board, and solder pads. The same applies to high-speed signals on the line side. This simplifies the high-speed signal link, reduces impedance discontinuities, improves high-speed signal transmission stability, and enhances signal integrity, further increasing the transmission rate of the optical module and enabling higher-speed optical modules. Furthermore, the thermal expansion coefficient of the first insulating dielectric layer of the circuit board's core structure matches that of the bare chip, effectively improving the reliability of flip-mounting the bare chip onto the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0024] FIG1 is an exploded schematic diagram of an optical module according to an embodiment of the present invention;

[0025] FIG2 is a schematic structural diagram of a circuit board assembly of an optical module according to an embodiment of the present invention;

[0026] FIG3 is a schematic structural diagram of a circuit board according to Example 1 of the present utility model;

[0027] FIG4 is a schematic structural diagram of a circuit board according to Example 2 of the present utility model;

[0028] FIG5 is a schematic structural diagram of a circuit board according to Example 3 of the present utility model;

[0029] FIG6 is a schematic structural diagram of a circuit board according to a fourth embodiment of the present invention.

[0030] Description of reference numerals:

[0031] 100. Optical module;

[0032] 1. Housing; 101. Upper housing; 102. Lower housing;

[0033] 2. Optical components;

[0034] 3. Circuit board; 4. Bare chip;

[0035] 5. Surface mount components; 6. Electrical connectors;

[0036] 7. Filling glue; 8. Protective layer;

[0037] 21. Light emitting component; 22. Light receiving component;

[0038] 23. Heat sink; 24. Optical interface;

[0039] 25. Optical processing assembly; 3001. Accommodation hole;

[0040] 301, first pad; 221, second pad;

[0041] 302, third pad; 211, fourth pad;

[0042] 31. Core layer structure; 32. Build-up layer structure;

[0043] 311. First insulating dielectric layer; 312. First conductive circuit layer;

[0044] 321, a second insulating dielectric layer; 322, a second conductive circuit layer;

[0045] 3221, fine flip-chip circuit; 3222, surface mount circuit;

[0046] 3223, electrical interface;

[0047] 341. Resin coating; 342. Copper foil. DETAILED DESCRIPTION

[0048] The following describes in detail the preferred embodiments of the present invention in conjunction with the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, to illustrate that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the scope of the present invention.

[0049] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this document are used to explain and illustrate the present invention, and are not used to limit the scope of protection of the present invention.

[0050] In the accompanying drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for the sake of ease of understanding and description, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

[0051] Example 1

[0052] As shown in Figures 1 and 2, the present invention provides an optical module 100. Optical module 100 includes a housing 1, an optical assembly 2, a circuit board 3, a bare chip 4, and surface mount components 5. The bare chip 4 and surface mount components 5 are mounted on the circuit board 3, forming a circuit board assembly.

[0053] The housing 1 includes an upper housing 101 and a lower housing 102 that are arranged opposite to each other.

[0054] In this embodiment, the optical component 2 includes a light emitting component 21 , a light receiving component 22 , a heat sink 23 , an optical interface 24 , and a light processing component 25 .

[0055] The light emitting assembly 21 and the light receiving assembly 22 are mounted on a heat sink 23, and are located on the heat sink 23 near one end of the circuit board 3, facilitating electrical connection to the circuit board 3. The light emitting assembly 21 includes a laser chip, which is electrically connected to the circuit board 3. The light receiving assembly 22 includes a photodetector chip and an amplifier chip, which are electrically connected to the amplifier chip, which is in turn electrically connected to the circuit board 3.

[0056] The heat sink 23 is disposed within the housing 1. In this embodiment, the heat sink 23 is made of a metal with good thermal conductivity, and is used to support the optical emitting assembly 21 and the optical receiving assembly 22. The heat sink 23 conducts the heat generated by the optical emitting assembly 21 and the optical receiving assembly 22 during operation to the housing 1, thereby quickly dissipating the heat through the housing 1.

[0057] The optical interface 24 is provided at the other end of the heat sink 23. The optical interface 24 can be a fiber optic socket or an MPO adapter, which is used to connect to an external fiber optic connector to transmit optical signals to an external fiber, or to transmit optical signals transmitted in an external fiber to the optical module 100.

[0058] The optical processing assembly 25 is disposed on the heat sink 23 and is located between the optical interface 24 and the optical transmitting assembly 21, and between the optical interface 24 and the optical receiving assembly 22. The optical processing assembly 25 typically includes a lens assembly, a wavelength division multiplexing / demultiplexing assembly, etc., and is used to couple, multiplex, or demultiplex the optical paths.

[0059] In other embodiments, the optical component 2 may also include a photonic integrated chip, which is flip-chip mounted on the circuit board 3 and electrically connected to the bare chip 4 .

[0060] As shown in Figure 1, the circuit board 3 is set in the housing 1, and the upper housing 101 and the lower housing 102 are covered to encapsulate the above-mentioned optical component 2 and the circuit board component (circuit board 3 and the bare chip 4 and surface mount components 5 thereon, etc.) in the housing 1.

[0061] The circuit board 3 has a receiving hole 3001 at one end near the heat sink 23. Receiving hole 3001 is used to accommodate the light receiving assembly 22. A first soldering pad 301 is provided on the circuit board 3 near the light receiving assembly 22. The light receiving assembly 22 has a second soldering pad 221. The first soldering pad 301 is electrically connected to the second soldering pad 221. The electrical connection between the circuit board 3 and the light receiving assembly 22 is achieved through the first soldering pad 301 and the second soldering pad 221.

[0062] The circuit board 3 has a third solder pad 302 adjacent to the optical emission assembly 21, and the optical emission assembly 21 has a fourth solder pad 211. The third solder pad 302 is electrically connected to the fourth solder pad 211. The electrical connection between the circuit board 3 and the optical emission assembly 21 is achieved through the third solder pad 302 and the fourth solder pad 211.

[0063] As shown in FIG. 3 , the circuit board 3 in this embodiment includes a core layer structure 31 and at least two build-up layer structures 32 .

[0064] As shown in FIG. 3 , the core layer structure 31 in this embodiment includes a first insulating dielectric layer 311 and first conductive circuit layers 312 disposed on both sides of the first insulating dielectric layer 311 .

[0065] The thermal expansion coefficient of the first insulating dielectric layer 311 matches that of the bare chip 4. Specifically, the thermal expansion coefficient of the first insulating dielectric layer 311 is less than or equal to 13 ppm / °C, which is close to the thermal expansion coefficient of the bare chip 4. This prevents deformation due to excessive thermal expansion coefficient from cracking the bare chip 4 or affecting the soldering reliability between the two. The thickness of the first insulating dielectric layer 311 ranges from 100 μm to 600 μm. In this embodiment, the thickness of the first insulating dielectric layer 311 is 160 μm. In other embodiments, the thickness of the first insulating dielectric layer 311 can also be 100 μm, 120 μm, 140 μm, 180 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, or 600 μm. This allows the bare chip 4 to be directly flip-chip mounted on the circuit board 3, while the surface mount components 5 and the electrical interface 3223 are also disposed on the circuit board 3.

[0066] The first insulating dielectric layer 311 is made of BT resin or BT-like resin to ensure the strength of the circuit board 3 and to match the thermal expansion coefficient of the bare chip 4 .

[0067] The build-up structures 32 are symmetrically arranged on both sides of the core structure 31. In this embodiment, the single-layer build-up structure 32 includes a second insulating dielectric layer 321 and a second conductive circuit layer 322 arranged on a side of the second insulating dielectric layer 321 away from the core structure 31.

[0068] The material of the second insulating dielectric layer 321 is BT prepreg or a BT-like prepreg. In this embodiment, the BT prepreg ensures the strength of the circuit board 3 while matching the thermal expansion coefficient of the bare chip 4. This supports the modified semi-additive process (mSAP), eliminating the need for expensive SAP processes and reducing the production cost of the optical module 100. Furthermore, compared to printed circuit board fabrication using etching, this method offers higher precision and can meet the design requirements of fine pitches.

[0069] The two build-up structures 32 furthest from the core structure 31 have a surface circuit pattern on their surfaces, which are located away from the core structure 31. This surface circuit pattern includes fine flip-chip circuits 3221, surface mount circuits 3222, and electrical interfaces 3223. Specifically, the second conductive circuit layers 322 of the two build-up structures 32 furthest from the core structure 31 form this surface circuit pattern.

[0070] Specifically, the second conductive circuit layers 322 of the two build-up structures 32 furthest from the core structure 31 each include a seed copper layer and a copper build-up layer stacked on the side of the seed copper layer away from the core structure 31. The seed copper layer is a thin copper layer with a thickness of less than or equal to 5 microns, enabling the use of an mSAP process to form the copper build-up layer and fine circuits on the thin copper layer. In this embodiment, the thickness of the seed copper layer is preferably 3 microns. This allows the use of a modified semi-additive process (mSAP) to form surface circuit patterns on the surfaces of the two build-up structures 32 furthest from the core structure 31, away from the core structure 31. This allows the production of fine surface circuits without the need for expensive SAP processes. Compared to printed circuit boards formed by etching, this process offers high precision and can meet fine-pitch design requirements. This allows the bare chip 4 to be flip-chip mounted directly on the circuit board 3, simplifying the wiring between the bare chip 4 and the circuit board 3 and thereby improving the high-frequency performance of the optical module 100.

[0071] The build-up layer structure disposed between the core layer structure 31 and the outermost build-up layer structure may be the same as the outermost build-up layer structure, or may be a build-up layer structure of a common circuit board.

[0072] The bare chip 4 is flip-chip mounted on the fine flip-chip circuit 3221. In this embodiment, the bare chip 4 includes one or more of a digital signal processing chip (DSP), a clock data recovery chip (CDR), a transimpedance amplifier chip, and a laser driver chip. The bare chip 4 is flip-chip mounted directly on the fine flip-chip circuit 3221 of the circuit board 3 and electrically connected to the circuit board 3 via electrical connectors 6. In this embodiment, the bare chip 4 has a relatively dense number of pins, and the electrical connector uses solder paste to connect the pins (bumps) of the bare chip 4 to the pads of the fine flip-chip circuit 3221 on the circuit board 3. In some embodiments, when the bare chip 4 has fewer pins, gold balls or ACF (anisotropic conductive paste) can also be used as the electrical connector.

[0073] The surface mount components 5 are mounted on the surface mount circuit 3222. The surface mount components 5 are mounted on the circuit board 3 using surface mount technology (SMT).

[0074] The electrical interface 3223 is used for pluggable electrical connection to the outside of the optical module 100. The electrical interface 3223 is provided at the end of the circuit board 3 away from the optical receiving assembly 22. In this embodiment, the electrical interface 3223 is a gold finger. Specifically, the electrical interface 3223 has a pattern and shape structure that conforms to the MSA definition for optical modules.

[0075] The optical module 100 further includes a filler 7 disposed between the bare chip 4 and the circuit board 3. The thermal expansion coefficient of the filler 7 matches the thermal expansion coefficient of the electrical connector 6, so that the filler 7 can better protect the electrical connector 6.

[0076] The bare chip 4 within the optical module 100 of the present invention is directly flip-mounted onto the circuit board 3. This allows high-speed signals from the host side to enter the circuit board 3 through the electrical interface 3223 of the circuit board 3 and then directly into the bare chip 4 via strip lines, microstrip lines, high-frequency coupling capacitors, vias, and pads on the circuit board 3. The same applies to high-speed signals from the line side. This simplifies the high-speed signal link, reduces impedance discontinuities, improves high-speed signal transmission stability, and enhances signal integrity, further increasing the transmission rate of the optical module 100 and enabling a higher-speed optical module 100. Furthermore, the thermal expansion coefficient of the first insulating dielectric layer 311 of the core structure 31 of the circuit board 3 matches that of the bare chip 4, effectively improving the reliability of the flip-mounting of the bare chip 4 onto the circuit board 3.

[0077] Example 2

[0078] As shown in Figure 4, this embodiment includes most of the technical features of Example 1. The difference between this embodiment and Example 1 is that in this embodiment, the single-layer build-up structure 32 includes a low-loss resin coated copper foil (RCC), and the resin coated copper foil includes: copper foil 342 and a resin coating 341 that does not contain glass fiber. The copper foil 342 is located on the side of the resin coating 341 away from the core layer structure 31.

[0079] The resin coating 341 is made of glass-free material, eliminating high-frequency glass fiber effects and improving CAF (Conductive Anodic Filament) resistance. The adhesive-backed copper foil provides a uniform film, making it more suitable for laser hole forming than traditional prepregs. Its stable expansion and contraction properties allow it to support via designs with a 50µm aperture and a 90µm pad. This allows for a minimum pitch of 115µm, making it easier to create fine circuits on the circuit board 3.

[0080] In this embodiment, the single-layer build-up structure 32 also includes a copper-added layer disposed on the side of the adhesive-backed copper foil away from the core structure 31. The thickness of this copper foil 342 is less than or equal to 5 microns, enabling the copper-added layer to be fabricated on the copper foil using the mSAP process and forming fine circuits. In this embodiment, the thickness of the copper foil 342 is preferably 3 microns. In this embodiment, the copper foils and corresponding copper-added layers of the two build-up structures 32 furthest from the core structure 31 form the surface circuit pattern. Specifically, a modified semi-additive process (mSAP) is used to form the surface circuit pattern on the side of the outermost build-up structure 32 away from the core structure 31. This eliminates the need for expensive SAP processes and allows for the production of fine surface circuits, thereby reducing the production cost of the optical module 100. Furthermore, compared to printed circuit boards formed using etching, this process offers higher precision and can meet fine-pitch design requirements. This allows the bare chip 4 to be flip-chip mounted directly on the circuit board 3, simplifying the wiring between the bare chip 4 and the circuit board 3 and improving the high-frequency performance of the optical module 100.

[0081] There are multiple inner build-up layer structures provided between the two build-up layer structures 32 farthest from the core layer structure 31 and the core layer structure 31 .

[0082] In some embodiments, the inner build-up layer structure between the core layer structure 31 and the outermost build-up layer structure 32 can adopt a build-up layer structure 32 including a second insulating dielectric layer 321 and a second conductive circuit layer 322 as in Example 1, or can adopt a back-adhesive copper foil structure as in Example 2, or a combination of the two.

[0083] When the inner layer build-up structure adopts a combination of Example 1 and Example 2, that is, part of the inner layer build-up structure includes adhesive-backed copper foil and is symmetrically arranged on both sides of the core layer structure 31; the other part of the inner layer build-up structure includes a second insulating dielectric layer 321 and a second conductive circuit layer 322 disposed on the side of the second insulating dielectric layer 321 away from the core layer structure 31, and is symmetrically arranged on both sides of the core layer structure 31. For example, the build-up structure 32 includes a high-speed circuit layer, and the build-up structures of the high-speed circuit layer and its upper and lower layers (and the layers adjacent to it) all use adhesive-backed copper foil as the build-up structure. The other inner layers can adopt the build-up structure of Example 1 or Example 2. This can eliminate the glass fiber effect during high-speed line transmission, thereby preventing the glass fiber effect of traditional prepregs from affecting high-frequency performance, thereby effectively improving the high-speed performance of the circuit board 3.

[0084] Example 3

[0085] As shown in Figure 5, this embodiment includes most of the technical features of Example 1. Since the surface circuit pattern is made using the mSAP process, it includes a gold finger located on the surface, and the wear resistance of the gold finger is relatively weak. The difference between this embodiment and Example 1 is that in this embodiment, in order to improve the plugging and unplugging wear resistance and the anti-oxidation and corrosion resistance of the gold finger, this embodiment provides a protective layer 8 on the gold finger. Specifically, the protective layer 8 can be a nickel-palladium-gold plating layer, that is, after the surface circuit pattern is made using the mSAP process, a nickel-palladium-gold plating layer is plated on the gold finger. As the protective layer 8 of the gold finger, the nickel-palladium-gold plating layer has excellent wear resistance and anti-oxidation and corrosion resistance.

[0086] Example 4

[0087] As shown in FIG6 , this embodiment includes most of the technical features of Example 2. The difference between this embodiment and Example 2 is that, in this embodiment, a protective layer 8 is provided on the gold finger to improve its insertion and removal wear resistance, as well as its oxidation and corrosion resistance. Specifically, protective layer 8 can be a nickel-palladium-gold plating layer, as described in Example 3.

[0088] Furthermore, the above provides a detailed introduction to an optical module provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application. At the same time, for those skilled in the art, based on the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An optical module, characterized in that: include: A housing and optical components, circuit boards, bare chips and surface mount components arranged in the housing; Wherein, the circuit board comprises: A core layer structure, comprising a first insulating medium layer and a first conductive circuit layer arranged on both sides of the first insulating medium layer; and At least two build-up structures are symmetrically arranged on both sides of the core structure; Wherein, the surfaces of the two layers of the build-up structure farthest from the core layer structure on the side away from the core layer structure are provided with surface circuit patterns, and the surface circuit patterns include fine flip-chip circuits, surface mount circuits and electrical interfaces; The bare chip is flipped on the fine flip-chip circuit, the surface mount component is mounted on the surface mount circuit, and the electrical interface is used for pluggable electrical connection with the outside.

2. The optical module according to claim 1, characterized in that: The thermal expansion coefficient of the first insulating dielectric layer matches the thermal expansion coefficient of the bare chip; the thermal expansion coefficient of the first insulating dielectric layer is less than or equal to 13 ppm / °C.

3. The optical module according to claim 1, characterized in that: The material of the first insulating dielectric layer is BT resin or BT-like resin.

4. The optical module according to claim 1, characterized in that: The single-layer build-up structure comprises a second insulating medium layer and a second conductive circuit layer arranged on a side of the second insulating medium layer away from the core layer structure; Wherein, the second conductive circuit layers of the two build-up structures farthest from the core layer structure form the surface layer circuit pattern; Wherein, the material of the second insulating dielectric layer is BT prepreg or BT-like prepreg.

5. The optical module according to claim 4, characterized in that: The second conductive circuit layers of the two build-up structures farthest from the core layer structure each include a seed copper layer and a build-up copper layer stacked on a side of the seed copper layer farthest from the core layer structure; The seed copper layer is a thin copper layer with a thickness less than or equal to 5 microns.

6. The optical module according to claim 1, characterized in that: The single-layer build-up structure includes adhesive-backed copper foil, which includes: copper foil and a resin coating without glass fiber, and the copper foil is located on a side of the resin coating away from the core layer structure.

7. The optical module according to claim 6, characterized in that: The single-layer build-up structure further includes a copper-building layer arranged on a side of the adhesive-backed copper foil away from the core layer structure; The thickness of the copper foil is less than or equal to 5 microns; The copper foils of the two build-up layers farthest from the core structure and the corresponding copper-added layers form the surface circuit pattern.

8. The optical module according to claim 4 or 7, characterized in that: A plurality of inner layer build-up layer structures are further arranged between the two build-up layer structures farthest from the core layer structure and the core layer structure; Part of the inner layer build-up structure includes adhesive-backed copper foil, and is symmetrically arranged on both sides of the core layer structure; Another part of the inner layer build-up structure includes a second insulating medium layer and a second conductive circuit layer arranged on a side of the second insulating medium layer away from the core layer structure, and is symmetrically arranged on both sides of the core layer structure.

9. The optical module according to claim 1, characterized in that: The build-up structure has a high-speed circuit layer, and the high-speed circuit layer and the build-up structures on both sides adjacent to the high-speed circuit layer include adhesive-backed copper foil.

10. The optical module according to claim 1, characterized in that: The bare chip includes one or more of a digital signal processing chip, a clock data recovery chip, a transimpedance amplifier chip and a laser driver chip.

11. The optical module according to claim 1, characterized in that: The electrical interface is a gold finger.

12. The optical module according to claim 11, characterized in that: It also includes a protective layer arranged on the gold finger.

13. The optical module according to claim 12, characterized in that: The protective layer is a nickel-palladium-gold plating layer.

14. The optical module according to claim 1, characterized in that: The optical assembly includes a light emitting assembly and a light receiving assembly; The optical transmitting component and the optical receiving component are electrically connected to the circuit board and electrically connected to the bare chip.

15. The optical module according to claim 1, characterized in that: The optical component includes a photonic integrated chip; The photon integrated chip is flipped onto the circuit board and electrically connected to the bare chip.

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