Layer transfer method

Abstract

The present disclosure relates to a method that comprises: forming a plurality of III-nitride layers over a substrate; forming a porous layer in the plurality of III-nitride layers; bonding the plurality of III-nitride layers to a handle wafer; and removing the handle wafer and at least one of the plurality of III-nitride layers from the substrate comprising cleaving the porous layer.

Description

[0001] LAYER TRANSFER METHOD

[0002] Technical field

[0003] The present application relates to a method of transferring a Ill-nitride semiconductor layer from a substrate.

[0004] Background

[0005] The ever-increasing demand for interconnected electronic devices has been enabled by modern day RF communications modules. Modules, such as an RF front end, are present in both consumer and commercial edge devices, as well as in the communications infrastructure networks which supports the edge devices. The ubiquitous nature of such RF communications modules places great demands on the performance of these modules, particularly from the perspective of smaller size, higher frequency performance, lower losses and higher power densities.

[0006] The fabrication techniques to produce such RF communications modules has been a key driver in enabling RF communication to meet modern day demands for wireless connectivity. In particular, the use of three-dimensional integrated circuit (3DIC) fabrication techniques has greatly reduced the footprint and power consumption for forming electronics modules, such as RF communication modules. 3DIC involves stacking a plurality of semiconductor devices, or chiplets in the vertical direction and forming interconnects between the devices or chiplets, such as through the use of vias and metallization, hybrid bonding and active or passive interposers.

[0007] 3DIC has become a well-established fabrication technique in the realm of Si, which is the material that has underpinned modern-day electronics for decades.

[0008] Summary

[0009] Increasingly, however, it is becoming desirable to form semiconductor devices, such as RF switches and high electron mobility transistors (HEMTs) for use in ICs, from Ill-nitride semiconductor materials, such as GaN. Ill-nitride semiconductor materials possess many attractive properties, which can lead to decreased semiconductor device size as well as reduced power consumption. The desirable properties of Ill-nitride semiconductor devices can be enhanced by using Ill-nitride semiconductor devices and chiplets in 3DIC fabrication techniques to form an IC. However, 3DIC fabrication techniques in Ill-nitride semiconductor material systems have not been widely explored and current proposed methods suffer from a number of drawbacks.

[0010] In particular, 3DIC techniques involve vertically stacking two or more semiconductor devices. The semiconductor devices are formed on substrates and the stacking may take place by bonding the semiconductor devices together. At least one of the substrates is then removed from the stacked semiconductor devices for the 3DIC fabrication process to be completed. However, techniques to remove the substrate from a Ill-nitride semiconductor device stack have a number of drawbacks.

[0011] One option is to grind the substrate away. Controlling the grind, such that, all of the substrate is removed, but not a portion of the lll-N device stack is challenging, as careful grinding control is involved in the process. Furthermore, in this method, the substrate is destroyed. Typical substrates used for forming lll-N device stacks include GaN, Sapphire and SiC. These substrates are not widely available and are thus expensive. Therefore, destroying the substrate increases waste and costs.

[0012] Another option is cleaving. This process involves implanting a high dose of gas ions (such as hydrogen) into a GaN substrate to be cleaved. The substrate is bonded to a handle wafer, and the bulk of the substrate is cleaved leaving a thin GaN layer bonded to the handle wafer. The gas ions thus act as a release layer in the cleaving process. The cleaving can be done by heating the substrate, which causes the volume of the gas atoms embedded in the substrate to increase, which releases the bulk substrate from the handle wafer leaving behind the thin GaN layer. The heating can be done with either an anneal process, localized heating with a laser, or other heating techniques. Another cleaving technique can involve a mechanical process.

[0013] The layer transfer process can involve transferring a single layer on to the handle wafer or a stack of layers on to the handle wafer. The substrate may thus comprise a GaN, silicon, or SiC substrate with one or more layers grown thereon comprising GaN or other semiconductor materials. The grown layers can thus be grown on the substrate using epitaxial growth techniques. The layer(s) transferred on to the handle wafer can subsequently be fabricated into semiconductor devices. The removed substrate can then be reused whereby ions are again implanted into the GaN bulk material for cleaving a thin layer of GaN. Optionally, a new set of layers can be grown on the surface of the cleaved substrate before or after the ion implantation.

[0014] The cleaving process presents a method where the substrate can be used a number of times. However, it also suffers from some drawbacks. For example, the thickness of the transferred layer(s) is limited, as the hydrogen ions cannot penetrate into the layer(s) beyond a critical thickness set by the implanted ion energy. The process of implanting the hydrogen ions is also expensive and is relatively energy intensive.

[0015] It is an object of the disclosure to obviate or eliminate at least some of the abovedescribed disadvantages associated with existing techniques.

[0016] According to a first aspect there is provided a method that comprises: forming a plurality of Ill-nitride layers over a substrate; forming a porous layer in the plurality of Ill-nitride layers; bonding the plurality of Ill-nitride layers to a handle wafer; and removing the handle wafer and at least one of the plurality of Ill-nitride layers from the substrate comprising cleaving the porous layer.

[0017] Brief description of the drawings

[0018] For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

[0019] Figures 1a-d are example steps in a layer transfer process;

[0020] Figures 2a-e are example steps in a layer transfer process;

[0021] Figures 3a-b are example steps in a layer transfer process;

[0022] Figures 4a-d are example steps in a layer transfer process;

[0023] Figures 5a-d are example steps in a layer transfer process.

[0024] Detailed Description Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metalorganic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase an then reacted at the surface to grow layers of desired composition.

[0025] Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer.

[0026] A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a lll-V material. The compounds have a 1 :1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Alo.25Gao.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As.

[0027] Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium nitride (GaN), silicon carbide (SiC), sapphire, indium phosphide (InP), and gallium antimonide (GaSb).

[0028] A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100> crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction.

[0029] Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type.

[0030] A pseudomorphic system is one in which a single-crystal thin layer overlies a singlecrystal substrate and where the layer and substrate have similar crystal structures and nearly identical lattice constants. In a pseudomorphic structure the in-plane lattice spacing of the thin layer adopts the in-plane lattice constant of the substrate and is therefore elastically strained, either compressively where the layer has a larger lattice spacing than the substrate or tensilely where the layer has a smaller lattice spacing than the substrate. A pseudomorphic structure is not constrained in the out-of-plane direction and so the lattice spacing of the thin layer in this direction may change to accommodate the strain generated by the mismatch between lattice spacing. The thin layer may alternatively be described as “coherent”, “commensurate”, “strained” or “unrelaxed”, which terms are often used interchangeably. In a pseudomorphic structure all the layers adopt the lattice spacing of the substrate in their respective in-plane lattice spacing.

[0031] A layer may be monolithic, that is comprising bulk material throughout.

[0032] A layer may be porous for some or all of its thickness. A porous layer includes gas or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayers. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively, the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and / or through the thickness of the layer (horizontally and / or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and / or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function.

[0033] A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided.

[0034] A fully depleted porous layer means a layer in which there are no charge carriers.

[0035] Examples according to the present disclosure provide a method for removing at least one of a plurality of lll-N semiconductor layers from a substrate. The method involves forming a porous layer in the plurality of lll-N semiconductor layers and removing the substrate by cleaving the porous layer.

[0036] It has been observed that some lll-N semiconductor materials, such as, GaN can be porosified by heavily doping the lll-N semiconductor material with an n-type dopant (n+) and subjecting the lll-N semiconductor material to an electrochemical etching process. Furthermore, the etchant is selective to the n+ doped lll-N semiconductor material, such that, material either side of the n+ doped lll-N semiconductor material is substantially unaffected by the electrochemical etch. Once the porous layer has been formed, the porous layer can be cleaved from the substrate in a further selective manner, whereby the porous layer may be effectively destroyed and the substrate and the semiconductor layers adjacent to the porous layer are left intact. The porous layer can thus effectively act as a release layer for a layer transfer process, where, as will be described in more detail below, at least one lll-N semiconductor layer can be bonded to an alternative substrate or handle wafer, and the substrate used for growth of the lll-N semiconductor layers can be removed.

[0037] Examples, according to the present disclosure thus present a method whereby a semiconductor substrate can be used to epitaxially grow a lll-N semiconductor layer stack and be subsequently removed from the lll-N semiconductor layer stack by the removal process involving the formation of the porous layer. As the etch and removal process is selective to the porous layer, the substrate is substantially unaffected and can thus be re-used many times for epitaxial growth. Substrates used for lll-N semiconductor epitaxial growth are not widely available and are expensive. Therefore, reuse of such substrates is advantageous to improve efficiency and decrease costs of fabrication processes involving 11 l-N semiconductor material. Furthermore, examples according to the present disclosure allow the use of substrates comprising larger diameters of 8 or 12 inches, such as Si substrates. Thus, the GaN layer grown and subsequently cleaved from the substrate also comprises the larger diameter and can be used for forming a larger number of semiconductor devices.

[0038] Examples according to the present disclosure further present a method whereby several 11 l-N semiconductor layers can be formed on the substrate prior to the substrate removal. Such a capability enables a complete epitaxial 11 l-N semiconductor device stack to be formed on the substrate before the substrate removal. The device stack may comprise all epitaxial device layers for forming a semiconductor device. Furthermore, examples according to the present disclosure allow a semiconductor device to be formed on the substrate including electrical contacts typically involved in front-end of line (FEOL) 3DIC fabrication techniques prior to the substrate removal. Examples according to the present disclosure, even further allow back end of line (BEOL) 3DIC fabrication techniques, such as the addition of dielectric material, vias and interconnects, as well as bonding the semiconductor wafer to another wafer including one or more semiconductor devices, prior to the substrate removal. As the removal is selective to the porous layer, the additional FEOL and BEOL fabrication layers, are also substantially unaffected by the porous etch and removal process. Such a technique is advantageous, as this allows greater design freedom throughout the fabrication process in relation when the substrate can be removed.

[0039] Figures 1a-d illustrate process steps 100a-d in a method for layer transfer.

[0040] Figure 1a is an example of first process step 100a in the method for layer transfer. Figure 1a illustrates a semiconductor wafer 100. Semiconductor wafer 100 comprises a substrate 110 and a plurality of lll-N semiconductor layers 120. The first process step illustrated in Figure 1a thus illustrates that the plurality of lll-N semiconductor layers 120 may be formed on the substrate 110. In some examples, the plurality of lll-N semiconductor layers 120 may be epitaxially grown on the substrate 110. The substrate 110 may thus comprise a material to permit the formation of epitaxial lll-N semiconductor layers. In some examples, the substrate may comprise Sapphire, Si, SiC or GaN. In some examples, the substrate may comprise a large diameter of 8 or 12 inches to allow the formation of epitaxial 11 l-N semiconductor layers with a large diameter corresponding to the substrate 110.

[0041] The semiconductor wafer 100 may comprise a buffer layer 121. Buffer layer 121 may comprise a material to assist in the crystallographic transition from the substrate 110 to the plurality of 11 l-N semiconductor layers 120. In some examples, the buffer layer may comprise AIN.

[0042] In other examples, the buffer layer 121 may comprise a material different to a lll-N semiconductor material and may be present between the plurality of lll-N semiconductor layers 120 and the substrate 110. For example, buffer layer 121 may comprise a rare earth oxide material, which can aid the crystallographic transition between the plurality of lll-N semiconductor layers 120 and some substrate materials such as Si.

[0043] In other examples, two or more buffer layers of differing compositions may be present between the substrate and the plurality of lll-N semiconductor layers 120.

[0044] The plurality of lll-N semiconductor layers 120 comprise a heavily doped n-type (n+) III- N semiconductor layer 122. In some examples, n+ lll-N semiconductor layer 122 may be doped n-type during the formation of the n+ lll-N semiconductor layer 122. However, in other examples, the plurality of semiconductor layers 120 may be grown on the substrate 110 and the lll-N semiconductor layer 122 may be doped n+ by implanting ions into the lll-N semiconductor layer 122. As will be described in more detail below, n+ III- N semiconductor layer 122 may be porosified, for example, by using an electrochemical etch process. In some examples, the n+ lll-N semiconductor layer 122 may comprise a doping concentration of at least 1 x 1018cm-3.

[0045] The plurality of lll-N semiconductor layers 120 further comprises a barrier layer 123, a channel layer 124 and an isolating buffer layer 125. As one skilled in the art will be familiar with, barrier layer 123, channel layer 124 and isolating buffer layer 125 may comprise semiconductor layers for forming a high electron mobility transistor (HEMT). In particular, GaN-based HEMTs are attractive for many electronic, power and RF communication applications. In one example, isolating buffer layer 125 and channel layer

[0046] 124 may comprise GaN and the barrier layer 123 may comprise AIGaN. In the illustrated example of Figure 1a, the barrier layer 123, channel layer 124 and isolating buffer layer

[0047] 125 are grown in the reverse order compared to the order in which they are commonly epitaxially grown to form a HEMT. However, as will be described in more detail below, isolating buffer layer 125 is bonded to a handle wafer, to flip the semiconductor layers such that electrical contacts can be formed on the barrier layer 123 and channel layer 124.

[0048] Examples according to the present disclosure will be described with reference to the formation of a lll-N based HEMT. However, it will be appreciated that the examples of the present disclosure may be implemented for the formation of any suitable lll-N semiconductor device.

[0049] Figure 1 b is an example of a second process step 100b in the method of layer transfer. Figure 1 b illustrates that a porous layer 122’ has been formed in the plurality of semiconductor layers 120. Porous layer 122’ may be formed by subjecting the semiconductor wafer 100 to an electrochemical etch process. The electrochemical etch process may involve submerging the semiconductor wafer 100 in an electrolyte solution along with an electrode. In some examples, the electrolyte solution may comprise hydrofluoric acid or sulfuric acid. The wafer 100 and the electrode are connected to an electrical source, such that the wafer acts as the anode and the electrode acts as the cathode. An electrical potential is applied to the wafer 100 and the electrode to form pores throughout the porous layer 122’.

[0050] The electrochemical reaction is selective to layers that are heavily doped n-type. Thus, during the electrochemical reaction, pores are formed throughout n+ lll-N semiconductor layer to form porous layer 122’. Furthermore, as no other layers within the wafer 100 are heavily doped n-type, the other layers are substantially unaffected by the etching process.

[0051] Figure 1c illustrates a third process step 100c in a method for layer transfer. Figure 1c illustrates that semiconductor wafer 100 is bonded to a handle wafer 130. Handle wafer 130 may comprise another substrate material which may be used as the substrate to support fabrication of a semiconductor device, such as a HEMT, from the plurality of semiconductor layers 120. In some examples, the handle wafer 130 may comprise glass, diamond, alumina, Si, high resistivity (HR) Si, trap rich (TR) Si or porous Si. In some examples, a dielectric layer may be present on the handle wafer 130. In other examples, the handle wafer may include active or passive devices, including, but not limited to, CMOS circuitry, passive devices such as resistors, capacitors, inductors, bipolar transistors, interconnects, or a combination thereof.

[0052] Figure 1d illustrates a fourth process step 100d in a method for layer transfer. Figure 1d illustrates removing the substrate 110 from the plurality of lll-N semiconductor layers 120. Figure 1d further illustrates that the buffer layer 121 is removed from the plurality of lll-N semiconductor layers 120.

[0053] The removal of the substrate 110 from the plurality of lll-N semiconductor layers 120 involves cleaving the porous layer 122’. The cleave may substantially remove the porous layer 122’ and leave the layers either side of porous layer 122’ substantially unaffected. In one example, the cleave may comprise a mechanical cleave where the substrate is removed from the plurality of lll-N semiconductor layers 120 by a mechanical process. For example, the mechanical cleave may comprise a razorblade cleave or waterjet cleave. In another example, the cleave may comprise a thermal cleave where heat is applied to the porous layer 122’. Thermal energy may be applied to the entire bonded wafer structure, such as by baking or annealing the structure, to remove the porous layer 122’. In another example, thermal energy may be locally applied to the porous layer 122’, for example, using a laser. In another example, a porous layer 122’ may be cleaved from the bonded semiconductor structure using a chemical cleave whereby the porous layer 122’ is chemically etched. For example, the porous layer 122’ may be chemically removed by submerging the semiconductor wafer in an acid solution. The acid may preferentially etch away the porous layer 122’ and leave the remaining layers of the semiconductor wafer substantially unaffected. In some examples, a combination of a mechanical, thermal and chemical cleave may be used to cleave the porous layer 122’ and remove the substrate 110 from the plurality of semiconductor layers 120.

[0054] Cleaving the porous layer 122’ may result in the substrate 110 being removed from the plurality of semiconductor layers 120 where the substrate 110 is substantially unaffected. Substrate 110 may thus be reused whereby a plurality of lll-N semiconductor layers can be grown on the substrate 110. In some examples, the surface of the substrate 100 for growth may be processed, for example, by polishing. In examples where buffer layer 121 is also removed on substrate 110, buffer layer 121 may be removed in the polishing process. As only a small fraction of the substrate 110 may be removed in the polishing process, the substrate 110 may be reused many times for the formation of lll-N semiconductor layers. In one example, the substrate 110 may be reused 100 times. Figure 1d further illustrates that the buffer layer 121 is removed from the plurality of 11 l-N semiconductor layers 120. In conventional examples, designing a buffer layer 121 , which can aid in the epitaxial deposition of the plurality of semiconductor layers 120 on substrate 110 and also does not detrimentally affect the performance of a semiconductor device fabricated from the plurality of semiconductor layers 120 can be challenging. Thus, in examples according to the present disclosure, the buffer layer 121 can be removed from the plurality of semiconductor layers 120, such that the buffer layer 121 does not form part of the resulting semiconductor device.

[0055] The plurality of 11 l-N semiconductor layers 120 bonded to handle wafer 130 may be further processed to form semiconductor devices, such as HEMTs, from the plurality of lll-N semiconductor layers 120. For example, electrical contacts for the source, drain and gate contacts may be fabricated on the lll-N semiconductor layers 120 using known FEOL fabrication techniques. However, in other examples, the electrical contacts and FEOL processing may be performed prior to the removal of substrate 110.

[0056] Figures 2a-e illustrate process steps in a method for layer transfer. Process steps 200a- e comprise corresponding elements to those present in process steps 100a-d. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality as described above.

[0057] Figure 2a is an example of first process step 200a in the method for layer transfer. Figure 2a illustrates a semiconductor wafer 200 comprising a substrate 110 and a plurality of lll-N semiconductor layers 120 on the substrate 110. Plurality of lll-N semiconductor layers 120 again comprises isolating buffer layer 125, channel layer 124 and barrier layer 123. However, in the example of Figure 2a, the plurality of lll-N semiconductor layers 120 are illustrated in reverse order compared to the examples of Figures 1a-d. Isolating buffer layer 125 is thus first epitaxially deposited on n+ semiconductor layer 122, channel layer 124 is epitaxially deposited on isolating buffer layer 125 and barrier layer 123 is epitaxially deposited on the channel layer 124.

[0058] Figure 2b is an example of a second process step 200b in a method of layer transfer. Figure 2b illustrates that porous layer 122’ has been formed in the plurality of lll-N semiconductor layers 120. Porous layer 122’ may be formed in a substantially corresponding way to that described above with respect to Figures 1a-d. Figure 2c is an example of a third process step 200c in a method of layer transfer. Figure 2b illustrates that semiconductor wafer 200 further comprises a first set of electrical contacts on the plurality of semiconductor layers 120. The electrical contacts comprise source contact 132, a gate contact 134 and a drain contact 136. In one example, the source contact 132, the gate contact 134 and the drain contact 136 may thus be formed on the plurality of 11 l-N semiconductor layers 120.

[0059] As illustrated in Figure 2c, source contact 132 and drain contact 136 are formed on channel layer 124. The formation of the source contact 132 and drain contact 136 on channel layer 124 may thus involve etching portions of the barrier layer 123.

[0060] Semiconductor wafer 200 further comprises a gate dielectric 138 on the barrier layer 123. Gate dielectric 138 may be deposited on the barrier layer 123 prior to the formation of the electrical contacts. In one example, a gate dielectric layer may be deposited on the barrier layer 123, which is etched to form the gate dielectric 138. Gate contact 134 may thus be formed on the gate dielectric 138.

[0061] Semiconductor wafer 200 further comprises a dielectric material 140 between the electrical contacts 132, 134, 136. In one example, dielectric material may be deposited on the electrical contacts 132, 134, 136 and the barrier layer 123, and subsequently polished to remove excess dielectric material.

[0062] Semiconductor wafer 200 may thus illustrate a semiconductor wafer that has undergone fabrication process typically associated with front end of line (FEOL) fabrication processes. The FEOL fabrication processes in lll-N material systems are typically used to form semiconductor devices from epitaxially grown lll-N material. In the illustrated example of Figure 2a, semiconductor wafer 200 has been fabricated to form a high electron mobility transistor (HEMT). However, in other examples, any suitable semiconductor device may be fabricated using FEOL processes.

[0063] Figure 2d is an example of a fourth process step 200d in the method for layer transfer. Figure 2d illustrates that a handle wafer 130 is bonded to semiconductor wafer 200d. Handle wafer 130 may be bonded to the semiconductor wafer 200d in a similar manner to that described above in relation to Figure 1c. Handle wafer 130 comprises a schematic illustration of a semiconductor device 131 formed on a substrate 210. Handle wafer 130 further comprises first handle wafer interconnect layer 280 and second handle wafer interconnect layer 290 formed on a substrate 210. Handle wafer 130 thus illustrates a wafer that has undergone fabrication processes to form semiconductor device 131 and interconnect layers 280, 290. Handle wafer 130 may thus illustrate a wafer that has undergone fabrication processes typically associated with back end of line (BEOL) fabrication processes.

[0064] First handle wafer interconnect layer 280 comprises a first handle wafer interconnect portion 282, a second handle wafer interconnect portion 284, a third handle wafer interconnect portion 286 and dielectric material 286 separating the first handle wafer interconnect portion 282, the second handle wafer interconnect portion 284 and the third handle wafer interconnect portion 286. Second handle wafer interconnect layer 290 comprises a fourth handle wafer interconnect portion 292 connected to the first handle wafer interconnect portion 282 and a fifth handle wafer interconnect portion 294 connected to the second handle wafer interconnect portion 284. Second handle wafer interconnect layer 290 further comprises dielectric material 296 separating the fourth handle wafer interconnect portion 292 and the fifth handle wafer interconnect portion 294.

[0065] The handle wafer interconnect portions 282-294 may thus be fabricated on the handle wafer 130 to provide interconnections to the semiconductor device 131. It will be appreciated that semiconductor device 131 may be one of a number of semiconductor devices that may be fabricated on the handle wafer 130. Thus, in some examples, handle wafer interconnect portions 282-294 may further provide connections to one or more semiconductor devices fabricated on handle wafer 130. It will further be appreciated that first handle wafer interconnect layer 280 and second handle interconnect layer 290 are two example interconnect layers fabricated on handle wafer 130. However, in other examples, more than two interconnect layers may be fabricated on the handle wafer 130 to form interconnections to multiple semiconductor devices.

[0066] The handle wafer 130 may thus be bonded to semiconductor wafer 200, such that the interface of the semiconductor wafer 200 comprising the electrical contacts 132, 134, 136 and dielectric material 140 are bonded to the handle wafer 130. Interconnects comprising the first handle wafer interconnect portion 282, the second handle wafer interconnect portion 284 and the third handle wafer interconnect portion 286 may thus be connected to the source contact 132, the gate contact 134 and the drain contact 136, respectively. In such examples, the HEMT formed on the semiconductor wafer 200 may be connected to the semiconductor device 131 on the handle wafer 130 via the handle wafer interconnect portions 282-294. The bonding step may thus form part of a 3DIC fabrication process.

[0067] Figure 2e is an example of a fifth process step 200e in the method for layer transfer. Figure 2e illustrates that substrate 110 is removed from the semiconductor wafer 200, which has been bonded to handle wafer 130. Substrate 110 may be removed from the semiconductor wafer 200 in a similar manner to that described above in relation to Figure 1d. Substrate 110 may thus be reused, for example, for the epitaxial growth of lll-N semiconductor layers in a similar manner to that described above.

[0068] Figures 2a-e illustrate process steps 200a-e in a method of layer transfer in a lll-N material system. Figures 2a-e further illustrate that fabrication techniques associated with FEOL fabrication processes may be carried out on a lll-N device stack to form a semiconductor device, such as a HEMT, prior to the removal of the substrate. In the examples of Figures 2a-e, the formation of the porous layer in the device stack is formed prior to the FEOL fabrication process. However, in other examples, the FEOL fabrication processes may be performed prior to the formation of the porous layer.

[0069] Figure 3a is an example of a process step 300a in the method for layer transfer. Figure 3a illustrates semiconductor wafer 300 comprising contacts 132, 134, 136 and dielectric material 138, 140, may be formed using FEOL fabrication processes in a similar manner to the that described above with respect to Figure 2c. Figure 3a illustrates that the FEOL fabrication processes are formed on a plurality of lll-N layers 120 comprising the non- porous n+ lll-N semiconductor layer 122. The FEOL fabrication process can thus take place prior to the electrochemical etch process to form the porous layer 122’ from the n+ lll-N semiconductor layer 122.

[0070] Referring briefly to Figure 1b, in the process step 100b, formation of porous layer 122’ in the semiconductor wafer 100 and the electrode may be orientated in the electrolyte solution such that the upper most surface of the semiconductor wafer 100, as illustrated in Figure 1b faces the electrode. The application of the current may thus form pores in the n+ lll-N semiconductor layer 122 as current passes from the top of the semiconductor wafer 100 towards the substrate 110. However, referring again to Figure 3a, if such an orientation were to be used for the semiconductor wafer 300b, the electrical contacts 132, 134, 136 and the dielectric material 140 may block the current from passing through the semiconductor wafer 300 from the top of the wafer 300 towards the substrate 110 and prevent porosifictaion of the n+ lll-N semiconductor layer 122.

[0071] Figure 3b thus illustrates an alternative process step 300b for the formation of the porous layer 122’. Figure 3b illustrates a process whereby a lateral electrochemical etch of the n+ lll-N semiconductor layer 122 may be performed to form the porous layer 122’.

[0072] Figures 3b illustrates that a mask 220 may be deposited on and around the electrical contacts 132, 134, 136, the dielectric material 140, the barrier layer 123, the channel layer 124 and the isolating buffer layer 125. In some examples, either side of the electrical contacts 132, 134, 136, the dielectric material 140, the barrier layer 123, the channel layer 124 and the drift layer 123 may be etched to form a mesa and allow the deposition of the mask 220 to the side surfaces of the barrier layer 123, the channel layer 124 and the isolating buffer layer 125. The semiconductor wafer 300 may be subsequently subjected to the electrochemical etch process. In such examples, the current may undercut the mask 220, such that pores are selectively formed in the n+ III- N semiconductor layer to form the porous layer 122’. In a similar manner to that described above, the electrochemical etch may leave the remaining layers of the semiconductor wafer 300 substantially unaffected.

[0073] Following the formation of the porous layer 122’, mask 220 may be removed from the semiconductor wafer 300. Semiconductor wafer 300 may be subsequently bonded to handle wafer 130 and the substrate 110 removed from the bonded wafer in a substantially corresponding may that described above with respect to Figures 2d and 2e.

[0074] Figures 2a-e and 3a-b thus illustrate process steps whereby FEOL fabrication processes may be performed on a semiconductor wafer to form one or more semiconductor devices, such as a HEMT. The semiconductor devices may subsequently be removed from a substrate and bonded to a handle wafer comprising interconnect layers using a layer transfer process where a porous layer can be conveniently used as a sacrificial layer in the layer transfer process. In other examples, BEOL fabrication processes may be performed on a substrate, prior to the substrate removal processes. Figures 4a-d illustrate process steps 400a-d in a method for layer transfer. Process steps 400a-d comprise corresponding elements to those present in process steps 100a- d, 200a-e and 300a-b. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality as described above.

[0075] Figure 4a illustrates an example of a first process step 400a in the method for layer transfer. Figure 4a illustrates a semiconductor wafer 400 that comprises a plurality of III- N semiconductor layers 120 and a porous layer 122’ formed in the plurality of lll-N semiconductor layers 120. In a similar manner to that described above, porous layer 122’ may be formed using an electrochemical etch process, which is selective to the n+ lll-N semiconductor layer 120.

[0076] Figure 4b is an example of a second process step 400b in the method for layer transfer. Figure 4b illustrates a semiconductor wafer 400 that comprises a plurality of lll-N semiconductor layers 120, a set of electrical contacts 132, 134, 136 and dielectric material 140, in a similar manner to that described above. FEOL fabrication techniques may thus be carried out on the semiconductor wafer 400 to form the set of electrical contacts 132, 134, 136 and dielectric material 140. Semiconductor wafer 400 further comprises a plurality of interconnect layers 150, 160, 170 over the set of electrical contacts 132, 134, 136 and dielectric material 140.

[0077] First interconnect layer 150 comprises a first interconnect portion 152 connected to the source terminal 132, second interconnect portion 154 connected to the gate terminal 134 and third interconnect portion 156 connected to the drain terminal 136. First interconnect layer 150 further comprises dielectric material 158 separating interconnect portions 154, 156, 158. In one example, dielectric material 158 may be deposited on the electrical contacts 132, 134, 136 and dielectric material 140 and vias may be formed in the dielectric material 158. Metal may subsequently be deposited into the vias to form the interconnect portions 152, 154, 156.

[0078] Second interconnect layer 160 comprises a fourth interconnect portion 162 connected to the first interconnect portion 152 and fifth interconnect portion 164 connected to the second interconnect portion 154. Second interconnect layer 160 further comprises dielectric material 166 separating the fourth interconnect portion 162 and the fifth interconnect portion 164. In a similar manner to that described above, dielectric material 166 may be deposited on the first interconnect layer 150 and vias may be formed in the dielectric material 166. Metal may subsequently be deposited into the vias to form the interconnect portions 162, 164.

[0079] Third interconnect layer 170 comprises a sixth interconnect portion 172 connected to the fourth interconnect portion 162 and a seventh interconnect portion 174 connected to the fifth interconnect portion 164. Third interconnect layer 170 further comprises dielectric material 176 separating the sixth interconnect portion 172 and the seventh interconnect portion 174. In one example, dielectric material 176 may be deposited on the second interconnect layer 160 and vias and patterns may be formed in the dielectric material 176. Metal may subsequently be deposited into the vias to form the interconnect portions 172, 174.

[0080] The interconnect portions illustrated in Figure 4b may thus be used to form interconnects to connect semiconductor devices to thereby form an IC. For example, semiconductor wafer 400 may illustrate a portion of a semiconductor wafer on which a plurality of semiconductor devices may be formed. As such, interconnects may be used to connect one semiconductor device to another. For example, second interconnect portion 154, fifth interconnect portion 164 and seventh interconnect portion 174 may form part of an interconnect to connect the gate terminal 134 to another semiconductor device located on the semiconductor wafer 400.

[0081] Figure 4b thus illustrates a semiconductor wafer 400 that has undergone fabrication processes, typically associated with BEOL fabrication processes, such as to form interconnects.

[0082] Figure 4c is an example of a third process step 400c in the method for layer transfer. Figure 4c illustrates that a handle wafer 130 is bonded to semiconductor wafer 400. Handle wafer 130 may be bonded to the semiconductor wafer 400 in a similar manner to that described above in relation to Figure 1c and Figure 2d.

[0083] Handle wafer 130 comprises a semiconductor device 131 , fourth interconnect layer 180 and fifth interconnect layer 190 formed on a substrate 210.

[0084] Fourth interconnect layer 180 comprises an eighth interconnect portion 182, a ninth interconnect portion 184 and dielectric material 186 separating the eighth interconnect portion 182 and the ninth interconnect portion 184. Fifth interconnect layer 190 comprises a tenth interconnect portion 192 connected to the eighth interconnect portion and an eleventh interconnect portion 194 connected to the ninth interconnect portion 184. Fifth interconnect layer 190 further comprises dielectric material 196 separating the tenth interconnect portion 192 and the eleventh interconnect portion 194.

[0085] Handle wafer 130 may thus be bonded to the semiconductor wafer 400 such that the eighth interconnect portion 182 contacts the sixth interconnect portion 172 and the ninth interconnect portion 184 contacts the seventh interconnect portion 174. First interconnect portion 152, fourth interconnect portion 162, sixth interconnect portion 172, eight interconnect portion 182 and tenth interconnect portion 192 may thus form part of an interconnect to connect source terminal 132 to semiconductor device 131 comprised on handle wafer 130. The interconnect portions illustrated in Figure 4c may thus form interconnects between two or more semiconductor devices comprised on semiconductor wafer 400 and on handle wafer 130. Handle wafer 130 thus comprises similar interconnect layers to that described above with respect to Figures 2d and 2e.

[0086] Thus, when handle wafer 130 is bonded to semiconductor wafer 400, second interconnect portion 154, fifth interconnect portion 164, seventh interconnect portion 174, ninth interconnect portion 184 and eleventh interconnect portion 194 may form part of an interconnect to connect the gate terminal 134 to a terminal of semiconductor device 131.

[0087] Handle wafer 130 may thus be bonded to the semiconductor wafer 400c as part of a 3DIC fabrication process.

[0088] Figure 4d is an example of a fourth process step 400c in the method for layer transfer. Figure 4d illustrates that substrate 110 is removed from the semiconductor wafer 400. Substrate 110 may be removed from the semiconductor wafer 400 in a similar manner to that described above in relation to Figure 1d and Figure 2d. Substrate 110 may thus be reused, for example, for the epitaxial growth of 11 l-N semiconductor layers in a similar manner to that described above.

[0089] The bonded semiconductor wafer structure comprising handle wafer 130 interconnect layers 150, 160, 170, 180, 190, electrical contacts 132, 134, 136 and 11 l-N semiconductor layers 120 may thus be subsequently used in further fabrication processes. Examples according to the present disclosure have thus illustrated that a plurality of III- N semiconductor layers may be transferred to a wafer and the substrate used to grow the plurality of lll-N semiconductor layers may be reused. Examples according to the present disclosure further illustrate that elements and layers associated with FEOL or BEOL fabrication processes may also be transferred to a handle wafer, along with the plurality of lll-N semiconductor layers. However, in some examples, a single lll-N layer may be transferred to a handle wafer.

[0090] Figures 5a-d illustrate process steps 500a-d in a method for layer transfer. Process steps 500a-d comprise corresponding elements to those present in process steps 100a- d, 200a-e, 300a-b and 400a-d. Said common elements are labelled with corresponding reference numerals and may comprise the same features and functionality as described above.

[0091] Figure 5a is an example of first process step 500a, which illustrates a semiconductor wafer 500 comprising a plurality of lll-N semiconductor layers formed on buffer layer 121 , on substrate 110. Plurality of lll-N semiconductor layers 120 comprises n+ lll-N semiconductor layer 122 and a first lll-N semiconductor layer 523. Buffer layer 121 and the plurality of lll-N semiconductor layers 120 may thus be epitaxially deposited on the substrate 110 in a similar manner to that described above.

[0092] Figure 5b illustrates a second process step 500b, which illustrates that a porous layer 122’ has been formed in the semiconductor wafer 500. Porous layer 122’ may be formed using a selective electrochemical etch process in a similar manner to that described above. First lll-N semiconductor layer 523 may thus not be doped n+ such that first lll-N semiconductor layer is left substantially unaffected by the electrochemical etch process.

[0093] Figure 5c illustrates a third process step 500c, which illustrates that a handle wafer 130 is bonded to the semiconductor wafer 500. Handle wafer 130 is thus bonded to the first lll-N semiconductor layer 523. Handle wafer 130 may be bonded to the semiconductor wafer 500 in a substantially corresponding way to that described above.

[0094] Figure 5d illustrates a fourth process step 500d, which illustrates that the first lll-N semiconductor layer 523 and the handle wafer 130 are removed from the buffer layer 121 and the substrate 110. Figure 5d further illustrates that the porous layer 122’ has been removed using a cleaving process, in a similar manner to that described above. The cleave process removes the first 11 l-N semiconductor layer 523 and the handle wafer 130 from the buffer layer 121 and the substrate 110. Substrate 110 may subsequently be reused in a similar manner to that described above.

[0095] Handle wafer 130 comprising first II l-N semiconductor layer 523 thus presents a template on which a 11 l-N semiconductor device stack may be epitaxially formed. For example, a channel layer and barrier layer may be grown on the first II l-N semiconductor layer 523 for forming a HEMT. However, in other examples, any combination of lll-N semiconductor layers, semiconductor layers or metal layers, may be epitaxially formed on the first lll-N semiconductor layer 523 to form an electronic or photonic semiconductor device.

[0096] Examples according to the present disclosure have presented a method for layer transfer whereby the removed substrate can be used a number of times for growth of lll-N layer(s). In some examples, a template comprising one or more semiconductor layers on a substrate may be removed and be reused a number of times for growth of lll-N layer(s). In a similar manner to that described above, lll-N layer(s) may be grown on the template and the template can be cleaved from the lll-N layer(s) using the porous layer as a release layer. The surface of the template may be processed, for example, using polishing and cleaning steps, and subsequently used for lll-N epitaxial growth. In some examples, growing a lll-N epitaxial layer stack on a template may result in improved growth compared to growing the lll-N epitaxial layer stack directly on to the substrate forming part of the template. For example, growth of a lll-N epitaxial layer stack on a template comprising a Si substrate and one or more buffer layers thereon may be improved compared to growth of a lll-N epitaxial stack directly on to the Si substrate.

[0097] It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A method comprising: forming a plurality of Ill-nitride layers over a substrate; forming a porous layer in the plurality of Ill-nitride layers; bonding the plurality of Ill-nitride layers to a handle wafer; and removing the handle wafer and at least one of the plurality of Ill-nitride layers from the substrate comprising cleaving the porous layer.

2. The method according to claim 1 further comprising forming a first set of one or more electrical contacts on the plurality of Ill-nitride layers; and bonding the plurality of Ill-nitride layers to the handle wafer, following forming the one or more electrical contacts.

3. The method according to claim 1 or 2 wherein forming the plurality of Ill-nitride layers comprises forming a device stack.

4. The method according to any preceding claim further comprising forming one or more interconnect layers over the plurality of Ill-nitride layers; and bonding the plurality of Ill-nitride layers to the handle wafer, following forming the one or more interconnect layers.

5. The method according to claim 4 wherein the one or more interconnect layers comprise dielectric material and one or more interconnect portions.

6. The method according to claim 5 wherein forming the one or more interconnect layers comprises: forming a first dielectric layer over the plurality of lll-N semiconductor layers; forming one or more vias in the first dielectric layer; and forming the one or more interconnect portions in the one or more vias.

7. The method according to any preceding claim wherein forming the porous layer comprises etching pores into one of the plurality of Ill-nitride layers.

8. The method according to claim 7 wherein the one of the plurality of Ill-nitride layers comprises an n-type dopant.

9. The method according to claim 8 further comprising, following forming the plurality of Ill-nitride layers, implanting ions into the one of the plurality of Ill-nitride layers.

10. The method according to any preceding claim wherein cleaving the porous layer comprises a mechanical cleave.

11. The method according to any preceding claim wherein cleaving the porous layer comprises a thermal cleave.

12. The method according to claim 11 wherein the thermal cleave comprises a laser cleave.

13. The method according to any preceding claim wherein cleaving the porous layer comprises a chemical cleave.

14. The method according to any preceding claim wherein the substrate comprises a different semiconductor material to the plurality of Ill-nitride layers.

15. The method according to claim 14 wherein the substrate comprises one of: SiC, Si, and sapphire.

16. The method according to any of claims 1 to 13 wherein the substrate comprises a lll-N semiconductor material.

17. The method according to claim 16 wherein the substrate comprises GaN or AIN.

18. The method according to any preceding claim wherein the handle wafer comprises one or more semiconductor layers, a second set of one or more electrical contacts over the one of more semiconductor layers, and a second set of one or more interconnect layers over the second set of one or more electrical contacts.

19. The method according to any preceding claim further comprising, following removing the plurality of Ill-nitride layers from the substrate, forming a second plurality of Ill-nitride layers on the substrate.

20. The method according to any preceding claim further comprising: applying a mask to one or more of the plurality of Ill-nitride layers; andresponsive to applying the mask, forming the porous layer.

21. The method according to any preceding claim further comprising: forming a buffer layer over the substrate; and forming the plurality of Ill-nitride layers over the buffer layer.

22. The method according to claim 21 wherein removing the handle wafer and at least one of the plurality of Ill-nitride layers from the substrate further comprises removing the buffer layer from the substrate.

23. The method according to any preceding claim wherein following removing the handle wafer and at least one of the plurality of Ill-nitride layers from the substrate, the handle wafer comprises a single Ill-nitride layer.

24. The method according to any preceding claim wherein the handle wafer comprises one of: glass, diamond, alumina, Si, high resistivity Si, trap rich Si or porous Si.

25. The method according to any preceding claim wherein forming the plurality of Ill- nitride layers over a substrate comprises forming the plurality of Ill-nitride layers over a template comprising the substrate, wherein the template comprises one or buffer layers over the substrate; and wherein removing the handle wafer and at least one of the plurality of Ill- nitride layers from the substrate comprises removing the handle wafer and at least one of the plurality of Ill-nitride layers from the template.

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