Selective ETCH of stack below metal mask using oxygen and fluorine

Abstract

A method of etching recessed features in a silicon containing stack below a metal containing mask is provided. An etch gas comprising oxygen and fluorine is provided. The etch gas is transformed into a plasma. The stack is exposed to the plasma for selectively etching the recessed features in the stack with respect to the metal containing mask.

Description

SELECTIVE ETCH OF STACK BELOW METAL MASK USING OXYGEN AND FLUORINECROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 588,089, filed October 5, 2023, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a carbon containing mask. The stack may be altemating / repeating layers into which the recessed feature is formed, or a thick film of a single layer of material. One example context where such a process may occur is memory applications such as dynamic random access memory (DRAM) and “not and” devices (NAND). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a carbon containing mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner, especially for high aspect ratio features having narrow widths and / or deep depths.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of etching recessed features in a silicon containing stack below a metal containing mask is provided. An etch gas comprising oxygen and fluorine is provided. The etch gas is transformed into a plasma. The stack is exposed to the plasma for selectively etching the recessed features in the stack with respect to the metal containing mask.

[0005] In another manifestation, a method of etching recessed features in a silicon containing stack below a metal containing mask is provided. An etch gas is provided comprising oxygen and fluorine. The etch gas is transformed into a plasma by providing a multistate pulsed RF power with two or three states. The stack is exposed to the plasma for etching the recessed features.

[0006] In another manifestation, an apparatus for etching recessed features in a silicon containing stack below a metal containing mask is provided. A substrate support supports a substrate inside a processing chamber. An RF power source provides RF power in the processing chamber. A gas source comprises an oxygen and fluorine source. A controller is controllably connected to the RF power source and the gas source and is configured to provide an etch gas comprising oxygen and fluorine, transform the etch gas into a plasma, and expose the stack to the plasma for selectively etching the recessed features in the stack with respect to the metal containing mask.

[0007] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0009] FIG. 1 depicts a flow chart describing a method of etching recessed features into a stack below a carbon containing mask according to various embodiments.

[0010] FIGS. 2A-2B illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.

[0011] FIG. 3 shows a semiconductor processing system that may be used in some embodiments.

[0012] FIG. 4 illustrates a computer system for implementing a controller used in some embodiments.

[0013] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION

[0014] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and / or structures have not been described in detail in order to notunnecessarily obscure the present disclosure.

[0015] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In various embodiments herein, the stack of materials includes one or more layers of one or more materials below a carbon containing mask. In some embodiments, at least one layer of the stack contains at least one of silicon, germanium, and metal. Silicon containing layers may contain silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, silicon oxycarbide, polysilicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and poly silicon. In some embodiments, the stack comprises an alternating silicon oxide film with silicon nitride films, or single silicon oxide layer, or single silicon layer. In some embodiments, the stack may be a conductive or dielectric layer that may be a metal or silicon containing layer.

[0016] The features etched into a stack may be cylinders, trenches, or other recessed features. The aspect ratio of such a feature is defined as the lateral critical dimension divided by the depth. As the aspect ratio of such features continues to increase, several issues arise including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) noncircularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, and (7) low etch rate.

[0017] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and an overall higher aspect ratio, which causes more issues during the etching of both mask and underlayer materials.

[0018] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of a feature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array. When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted.

[0019] Non-circularity of the features refers to deviations of the bottom hole shape away froma circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable.

[0020] Aspect-ratio dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.

[0021] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features. In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.

[0022] Low etch rate refers to an etch rate that is slower than desired for a particular application. Low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.

[0023] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.

[0024] Prior art NAND ONON (silicon oxide silicon nitride stacks) etching utilizes fluorine, hydrogen, and / or carbon containing plasmas to etch, generating silicon hexafluoride (SiF4), ammonia (NH3), water / hydroxide (H2O / OH), or carbon monoxide / carbon dioxide (CO / CO2) byproducts. Under cryogenic temperature, when the etch rate is high and there is a high density of etch byproducts accumulated at the etch front. NH3 can react with SiF4 in the presence of hydrogen and fluorine to form ammonium salt (NH4)2SiF6 (AFS). The AFS salt formation causes many different issues such as a pointy etch front, profile twisting, non-circularity, etc. Current NAND integration uses carbon containing masks to pattern ONON stacks. Due to a low selectivity of less than 1 to 10, the carbon mask has to be deposited quite thick to be able to transfer patterns successfully. A thick mask layer adds to the aspect ratio of both mask etch and ONON stack etch, which causes more high aspect ratio related issues such as aspect ratiodependent etching, etch stop, tapering, bowing, twisting, etc.

[0025] The techniques described herein may be used to etch recessed features into a stack below a mask without some or all of the issues identified above. In other words, the disclosed techniques may be used to etch recessed features into a stack below a mask with a high stack to mask selectivity and with reduced mask twisting, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, and sufficient etch rate.

[0026] To facilitate understanding, FIG. 1 is a high level flow chart of a method that may be used in some embodiments. A silicon containing stack with a metal containing mask is provided (step 104). FIG. 2A is a schematic cross-sectional view of a stack 204 that may be processed according to some embodiments, where the stack is under a metal containing mask 212, such as titanium nitride (TiN) mask. In some embodiments, the stack 204 may be formed over a substrate 208. In some embodiments, the stack 204 may comprise a silicon containing layer, such as silicon oxide, silicon nitride, or silicon. In some embodiments, the stack 204 may be a metal containing layer such as a pure or alloy conductive metal layer or a metal nitride or metal oxide. In some embodiments, the stack 204 may comprise a germanium containing layer. In some embodiments, the stack is a single bulk layer. In some embodiments, the stack is a plurality of layers. In some embodiments, the stack is a plurality of bilayers, trilayers, or more multiple layers.

[0027] An etch process is provided for etching the stack 204. A substrate support that supports the stack is cooled to a cryogenic temperature (step 108). In some embodiments, the substrate support is cooled to a cryogenic temperature below 0° C. In some embodiments, the substrate support is cooled to a temperature below -20° C. In some embodiments, the substrate support is cooled to a temperature below -40° C. In some embodiments, the substrate support is cooled to a temperature below -60° C.

[0028] An etch gas comprising oxygen and fluorine is provided (step 112). In some embodiments, the etch gas comprises at least one of oxygen difluoride (OF2) and a mixture of oxygen gas (O2) and fluorine gas (F2). In some embodiments, the etch gas comprises OF2 and a phosphorous containing component. In some embodiments, the phosphorous containing component comprises at least one of phosphorous trifluoride (PF3) and phosphorous pentafluoride (PF5). In some embodiments, the etch gas may further comprise a carrier gas such as argon (Ar), xenon (Xe), helium (He), and nitrogen gas (N2). In some embodiments, the etch gas may comprise additional fluorocarbon gases.

[0029] The etch gas is transformed into a plasma (step 116). In some embodiments, radio frequency (RF) power is used to transform the etch gas into a plasma. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then provided into the process chamber.

[0030] The plasma in various embodiments may be generated at a radio frequency (RF) power between about 5-200 kilowatts (kW), for example between about 10-100 kW, or between about 10-65 kW in some embodiments. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 10-65 kW, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 0.5-8 kW. In some embodiments, the first frequency component (e.g., about 400 kHz) may be provided at a power higher than 65 kW. These power levels assume that the RF power is delivered to a single 300 millimeter (mm) wafer. The power levels can be scaled linearly based on substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three-frequency RF power may be used to generate the plasma.

[0031] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power may be pulsed. In some embodiments, the pulsed RF may have two or three states, providing multistate pulsed RF power. A three state pulsing pulses between three different (high, medium, low) power levels. In some embodiments, the high power level has a 1% to 20% duty cycle, the medium power level has a 10% to 90% duty cycle, and the low power level has a 20% to 90% duty cycle. In some embodiments, one of the three power levels is 0 Watts. In some embodiments, the high power level is 2 to 20 times the low power levels and the medium power level is between the high power level and the low power level. In some embodiments, the RF power is pulsed at repetition rates of 1-50,000 Hz. The RF power may be pulsed between two non- zero values (e.g., between higher power and lower power states) or between zero and a non-zero value (e.g., between off and on states). Where the RF power is pulsed between two non-zero values, the powers may be a higher power state and a lower power state. The lower power state may correspond to an RF power of about 4 kW orlower. A pulsing duty cycle may be in the range of 1-50%. The pulsing may be at a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy at the substrate may be relatively high, for example between about 1-30 kilo electron volts (keV). The maximum ion energy is determined by the applied RF power in combination with the details of RF excitation frequencies, electrode sizes, electrode placement, chamber geometry, and plasma interactions.

[0032] In some embodiments, a bias in the range of 0 Watts (W) to 100 kilowatts (kW) is provided to accelerate ions toward the top surfaces of the stack 204. In some embodiments, a bias in the range of 100 W to 100 kW is provided.

[0033] The stack 204 is exposed to the plasma (step 120) causing recessed features to be selectively etched into the stack 204 with respect to the metal containing mask 212. FIG. 2B is a schematic cross-sectional view of a stack 204 after the recessed features 220 have been etched.

[0034] The use of a stack with a metal containing mask provides a higher selectivity and therefore a thinner mask. With a thinner mask, etch resolution is increased and the mask does not contribute as much to the aspect ratio. Providing an etch at cryogenic temperatures increases the adsorption of the etchants. Providing an etch gas comprising oxygen and fluorine provides a higher etch rate. Using such an etch gas to etch SiN or SiO forms byproducts of one or more of nitric oxide (NO), CO, SiF4, O2, nitrogen dioxide (NO2), carbonyl fluoride (COF2), and CO2 that are volatile at some cryogenic temperatures. Such an etch gas does not form byproducts of ammonia (NH3) salts that are not volatile at cryogenic temperatures. The addition of a phosphorous containing component causes the formation of POFX, such as phosphoryl fluoride (POF3), that is volatile at cryogenic temperatures.

[0035] Compared to using hydrogen fluoride (HF), OF2 has twice as many fluorine atoms per molecule than HF, allowing for faster etching. The faster etch rate of the stack allows for less etching of the mask. In addition, the oxygen from OF2 forms a volatile molecule with nitrogen facilitating the etching is silicon nitride (SiN). Although NH3 may be volatile at cryogenic temperatures, some NH3 salts, such as ammonium fluorosilicate (AFS) salt, ammonium fluoride (AF) salt, ammonium chloride salt, and ammonium bromide salt, are not volatile at cryogenic temperatures. The removal of nitrogen reduces or eliminates the formation of NH3 salts that are not volatile at cryogenic temperatures. It has been found that using OF2 allows for a faster etch of silicon oxide and silicon nitride with reduced bowing. In some embodiments, the etch gas is hydrogen free and NH3 free. In some embodiments, the etch gas may comprise small amounts of hydrogen.

[0036] One application for the disclosed methods is in the context of forming a vertical NAND device. In this case, the material into which the feature is etched may be a repeating layered structure. For instance, the material may include alternating layers of silicon oxide and silicon nitride. In other embodiments, the stack may comprise alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10-500 (e.g., between about 20-1000 individual layers). The features etched into the stack of layers may have a depth between about 2-15 pm, for example between about 5-9 pm. The features may have a width between about 40-450 nm, for example between about 50-100 nm or between about 40-85 nm. In some embodiments, the features have a width of less than 100 nm. In some embodiments, the features have a width of less than 85 nm.

[0037] As used herein, “high aspect ratio” as applied to features in a substrate refers to aspect ratios on the order of approximately 60: 1 or higher. More preferably, this range may include ratios greater than 100: 1, 120:1, 140:1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30:1, or 10:1.

[0038] The dimensional / parametric details provided herein, such as high aspect ratio, thickness, width, depth, etc., are for example and illustration only. Based on the disclosure described herein, it should be understood that varying dimensions / parameters may also be applicable or used.APPARATUS

[0039] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools / processes will be used or conducted together in a common fabrication facility.

[0040] Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby pattern it using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into anunderlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.

[0041] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0042] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value.

[0043] FIG. 3 is a schematic view of a plasma processing chamber 300 for plasma processing substrates, in an embodiment. In one or more embodiments, the plasma processing chamber 300 comprises a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 316, within a plasma processing chamber 304, enclosed by a chamber wall 350. Within the plasma processing chamber 304, the substrate 208 is positioned on top of the ESC 316 so that the ESC 316 is also a substrate support. The ESC 316 may provide a bias from an ESC power source 348. A gas source 310 is connected to the plasma processing chamber 304 through the gas distribution plate 306. In some embodiments, the gas source comprises an oxygen and fluorine source 312, such as an OF2 gas source, a phosphorous containing components source, such as a PF3 or PF5 gas source, and a source for other gases. An ESC temperature controller 351 is connected to the ESC 316 and provides temperature control of the ESC 316, allowing for the ESC 316 to be cooled to cryogenic temperatures. A radio frequency (RF) power source 330 provides RF power to the ESC 316 and an upper electrode. The RF power may be provided in a sinusoidal waveform or in other tailored waveforms. In this embodiment, the upper electrode is the gas distribution plate 306. In a preferred embodiment, 400 kilohertz (kHz), 13.56 megahertz(MHz), 1 MHz, 2 MHz, 60 MHz, and / or optionally, 27 MHz power sources make up the RF power source 330 and the ESC power source 348 to provide RF power at RF frequencies. A controller 335 is controllably connected to the RF power source 330, the ESC power source 348, an exhaust pump 320, and the gas source 310. A high flow liner 360 is a liner within the plasma processing chamber 304, which confines gas from the gas source and has slots 362. The slots 362 maintain a controlled flow of gas to pass from the gas source 310 to the exhaust pump 320. An example of such a plasma processing chamber is the Flex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0044] FIG. 4 is a high level block diagram illustrating a computer system 400 for implementing the controller 335 used in embodiments of the present inventions. The computer system may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 400 may include one or more processors 402 and further can include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), storage device 408 (e.g., hard disk drive), removable storage device 410 (e.g., optical disk drive), user interface devices 412 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and / or a communication interface 414 (e.g., wireless network interface). The communication interface 414 may allow software and / or data to be transferred between the computer system 400 and external devices via a link. The system may also include a communications infrastructure 416 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules may be connected.

[0045] Information transferred via communications interface 414 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 414, via a communication link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communication channels. With such a communications interface, it is contemplated that the one or more processors 402 might receive information from a network or might output information to the network in the course of performing the above-described method steps. Furthermore, method embodiments may execute solely upon the processors or may execute over a network such as the Internet in conjunction with remote processors that share a portion of the processing.

[0046] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0047] It is to be understood that the configurations and / or approaches described herein are exemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such references may be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.CONCLUSION

[0048] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intended that the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional stepand is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method of etching recessed features in a silicon containing stack below a metal containing mask, comprising: a. providing an etch gas comprising oxygen and fluorine; b. transforming the etch gas into a plasma; and c. exposing the stack to the plasma for selectively etching the recessed features in the stack with respect to the metal containing mask.

2. The method of claim 1, wherein the etch gas comprises at least one of oxygen difluoride and a mixture of oxygen gas and fluorine gas.

3. The method of claim 1, further comprising: placing the stack over a substrate support; and cooling the substrate support to a temperature below 0° C.

4. The method of claim 1, wherein the etch gas is hydrogen free.

5. The method of claim 1, wherein the stack comprises at least one of SiN, SiO, and SiON.

6. The method of claim 1, wherein the transforming the etch gas comprises providing an RF power, wherein the providing the RF power comprises providing at least one of providing continuous RF power and providing multistate pulsed RF power.

7. The method of claim 1, wherein the transforming the etch gas comprises providing a multistate pulsed RF power with two or three states.

8. The method of claim 1, wherein the etch gas further comprises at least one of phosphorous trifluoride and phosphorous pentafluoride.

9. The method of claim 1, wherein the etch gas is hydrogen fluoride (HF) free and ammonia free (NH3) free.

10. The method, as recited in claim 1, wherein the transforming the etch gas comprises providing a pulsed RF power with a duty cycle in a range of 1% to 50%.

11. A method of etching recessed features in a silicon containing stack below a metal containing mask, comprising: a. providing an etch gas comprising oxygen and fluorine; and b. transforming the etch gas into a plasma, comprising providing a multistate pulsed RF power with two or three states; and c. exposing the stack to the plasma for etching the recessed features.

12. The method of claim 11, wherein the etch gas comprises at least one of oxygen difluoride and a mixture of oxygen gas and fluorine gas.

13. The method of claim 11, further comprising: placing the stack over a substrate support; and cooling the substrate support to a temperature below 0° C.

14. The method of claim 11, wherein the etch gas is hydrogen free.

15. The method of claim 11, wherein the stack comprises at least one of SiN, SiO, and SiON.

16. The method of claim 11, wherein the etch gas further comprises at least one of phosphorous trifluoride and phosphorous pentafluoride.

17. An apparatus for etching recessed features in a silicon containing stack below a metal containing mask, comprising: a process chamber; a substrate support for supporting a substrate inside the processing chamber; an RF power source for providing RF power in the processing chamber; a gas source comprising an oxygen and fluorine source; and a controller, controllably connected to the RF power source and the gas source, configured to: a. provide an etch gas comprising oxygen and fluorine; b. transform the etch gas into a plasma; and c. expose the stack to the plasma for selectively etching the recessed features in the stack with respect to the metal containing mask.

18. The apparatus of claim 17, wherein the oxygen and fluorine source is a source of at least one of oxygen difluoride and a mixture of oxygen gas and fluorine gas.

19. The apparatus of claim 17, further comprising a temperature controller for controlling a temperature of the substrate support wherein the controller is further configured to cool the substrate support to a temperature below 0° C.

Images