High-voltage to low-voltage circuit, BMS circuit and microprocessor chip

Abstract

The present application provides a high-voltage to low-voltage circuit, a BMS circuit and a microprocessor chip. The high-voltage to low-voltage circuit comprises: a current mirror unit, comprising a first transistor and a second transistor, wherein a source electrode of the first transistor and a source electrode of the second transistor are respectively connected to a first power supply end, and a gate electrode of the first transistor is electrically connected to a gate electrode of the second transistor; a third transistor, wherein a drain electrode of the third transistor is electrically connected to a drain electrode of the first transistor, a gate electrode of the third transistor is grounded, and a source electrode of the third transistor is grounded by means of a first resistor; a voltage-regulator tube, wherein a negative electrode of the voltage-regulator tube is electrically connected to a drain electrode of the second transistor by means of a second resistor; and a diode, wherein a positive electrode of the diode is electrically connected to a positive electrode of the voltage-regulator tube, and a negative electrode of the diode is grounded. By using the third transistor to obtain relatively stable current, and compensating the current by the diode to obtain relatively stable voltage, a low-power-consumption and high-reliability conversion from high voltage to low voltage can be implemented for use by the chip.

Description

A high-voltage to low-voltage circuit, BMS circuit and microprocessor chip

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 16, 2023, with application number 202311338568.X and application name “A high-voltage to low-voltage circuit, BMS circuit and microprocessor chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a high-voltage to low-voltage circuit, a BMS circuit, and a microprocessor chip. Background Art

[0003] Integrated circuits for high-voltage power applications typically convert the high voltage power supply to low voltage for signal processing, and then convert it back to high voltage output after processing. This is because low-voltage chips are much smaller than high-voltage chips, and converting to low voltage can save chip costs. However, existing high-voltage to low-voltage circuits suffer from poor stability, which hinders their use in chips.

[0004] Summary of the Invention

[0005] The present application provides a high-voltage to low-voltage circuit, a BMS circuit and a microprocessor chip, so as to solve the problem that the high-voltage to low-voltage circuit in the prior art has poor stability, which in turn affects its use in chips.

[0006] In a first aspect, an embodiment of the present application provides a high-voltage to low-voltage conversion circuit, comprising:

[0007] a current mirror unit, comprising a first transistor and a second transistor, wherein a source of the first transistor and a source of the second transistor are respectively connected to a first power supply terminal, and a gate of the first transistor and a gate of the second transistor are electrically connected;

[0008] a third transistor, wherein a drain of the third transistor is electrically connected to the drain of the first transistor, a gate of the third transistor is grounded, and a source of the third transistor is grounded via a first resistor;

[0009] a voltage regulator tube, wherein a cathode of the voltage regulator tube is electrically connected to a drain of the second transistor via a second resistor;

[0010] A diode, wherein the anode of the diode is electrically connected to the anode of the voltage regulator tube, and the cathode of the diode is grounded.

[0011] In a possible implementation, the method further includes:

[0012] a fourth transistor, wherein a drain of the fourth transistor is connected to the first power supply terminal, a gate of the fourth transistor is connected to a node between the second resistor and the voltage regulator tube, and a source of the fourth transistor is grounded via a third resistor;

[0013] a first capacitor, the first capacitor being connected in parallel with the third resistor;

[0014] A voltage output terminal is connected to a node between the fourth transistor and the third resistor.

[0015] In a possible implementation, the method further includes:

[0016] a fifth transistor, wherein a source of the fifth transistor is connected to the first power supply terminal, and a drain of the fifth transistor is connected to a node between the second resistor and the voltage regulator tube;

[0017] a sixth transistor, wherein a source of the sixth transistor is connected to the first power supply terminal, and a gate of the fifth transistor is electrically connected to the gate of the sixth transistor;

[0018] a seventh transistor, wherein the drain of the seventh transistor is electrically connected to the drain of the sixth transistor, the source of the seventh transistor is connected to the second power supply terminal, and the gate of the seventh transistor is electrically connected to the voltage output terminal via a second capacitor.

[0019] In a possible implementation, the method further includes:

[0020] an eighth transistor, wherein a drain of the eighth transistor is connected to a node between the second resistor and the voltage regulator tube, and a source of the eighth transistor is grounded;

[0021] a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the gate of the eighth transistor, and a source of the ninth transistor is connected to the second power supply terminal;

[0022] a tenth transistor, wherein the drain of the tenth transistor is electrically connected to the drain of the ninth transistor, the gate of the tenth transistor is electrically connected to the voltage output terminal via a third capacitor, and the source of the tenth transistor is connected to the first power supply terminal.

[0023] In one possible implementation, the first transistor is an NMOS transistor, the second transistor is an NMOS transistor, the third transistor is a PMOS transistor, the fourth transistor is a PMOS transistor, the fifth transistor is a PMOS transistor, the sixth transistor is a PMOS transistor, and the seventh transistor is an NMOS transistor.

[0024] In one possible implementation, the first transistor is an NMOS transistor, the second transistor is an NMOS transistor, the third transistor is a PMOS transistor, the fourth transistor is a PMOS transistor, the eighth transistor is an NMOS transistor, the ninth transistor is an NMOS transistor, and the tenth transistor is a PMOS transistor.

[0025] In one possible implementation, the third transistor is a high-voltage depletion-type PMOS transistor, and the negative threshold voltage of the high-voltage depletion-type PMOS transistor is used to generate current in the first resistor. The beneficial effect of this design is that a relatively stable current is obtained by utilizing the negative threshold characteristics of the depletion-type PMOS, and a relatively stable voltage can be obtained by utilizing this micro-current through diode compensation and power tube output, which can achieve low-power consumption, high-reliability high-voltage conversion to low voltage for use by internal chips.

[0026] In a possible implementation, the output voltage of the voltage regulator has a positive temperature characteristic, the forward conduction voltage of the diode has a negative temperature characteristic, and the threshold turn-on voltage of the fourth transistor has a negative temperature characteristic.

[0027] Because the Zener diode's output voltage has a positive temperature characteristic, while the fourth transistor's threshold voltage has a negative temperature characteristic, without compensation, Vout will increase with temperature, resulting in poor temperature characteristics. Diode D1 is a forward-conducting diode in the process, and utilizing the negative temperature characteristic of its forward voltage to compensate significantly improves the output.

[0028] In a second aspect, an embodiment of the present application provides a BMS circuit, including:

[0029] An LDO, the LDO comprising the high-voltage to low-voltage conversion circuit according to any one of the first aspects, wherein an input end of the LDO is electrically connected to a battery pack;

[0030] A control module, wherein a first input end of the control module is electrically connected to an output end of the LDO, and the LDO is used to supply power to the control module.

[0031] In a possible implementation, the method further includes:

[0032] a voltage acquisition module, wherein the input end of the voltage acquisition module is electrically connected to the battery pack, the output end of the voltage acquisition module is electrically connected to the second input end of the control module, and the voltage acquisition module is used to collect voltage information of each battery cell in the battery pack and send the voltage information of each battery cell to the control module;

[0033] a DC / DC isolated step-down power supply module, wherein the first input terminal of the DC / DC isolated step-down power supply module is used to be electrically connected to the positive electrode of the battery pack, the second input terminal of the DC / DC isolated step-down power supply module is used to be electrically connected to the negative electrode of the battery pack, and the third input terminal of the DC / DC isolated step-down power supply module is electrically connected to the first output terminal of the control module, and the control module is used to control the voltage and current of the DC / DC isolated step-down power supply module;

[0034] A cell switching module, wherein the first input end of the cell switching module is electrically connected to the second output end of the control module, the second input end of the cell switching module is electrically connected to the output end of the DC / DC isolated step-down power supply module, the output end of the cell switching module is used to be electrically connected to the battery pack, and the cell switching module is used to receive the cell switching control instruction output by the control module, and switch the target cell to the connection path of the DC / DC isolated step-down power supply module according to the cell switching control instruction, so that the DC / DC isolated step-down power supply module charges the target cell.

[0035] In a possible implementation, the method further includes:

[0036] a current detection module, the current detection module being connected in series between the battery pack and the negative electrode of the battery pack, the output end of the current detection module being electrically connected to the input end of the control module, and the control module being configured to receive current detection information output by the current detection module;

[0037] an overcharge / over-discharge protection module, the overcharge / over-discharge protection module being connected in series between the battery pack and the negative electrode of the battery pack, the input end of the overcharge / over-discharge protection module being electrically connected to the third output end of the control module, the overcharge / over-discharge protection module being configured to receive a protection control signal output by the control module and to cut off or open a path between the battery pack and the negative electrode of the battery pack according to the protection control signal.

[0038] In a third aspect, an embodiment of the present application provides a microprocessor chip, comprising:

[0039] The high-voltage to low-voltage circuit according to any one of the first aspects.

[0040] The embodiment of the present application utilizes a third transistor to obtain a relatively stable current, and utilizes the current to obtain a relatively stable voltage through diode compensation, which can realize low power consumption, high reliability and high voltage conversion to low voltage for chip use. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] FIG1 is a circuit diagram of a high-voltage to low-voltage circuit in the related art;

[0043] FIG2 is a circuit diagram of another high-voltage to low-voltage circuit in the related art;

[0044] FIG3 is a circuit diagram of a high-voltage to low-voltage circuit provided in an embodiment of the present application;

[0045] FIG4 is a circuit diagram of another high-voltage to low-voltage conversion circuit provided in an embodiment of the present application;

[0046] FIG5 is a circuit diagram of another high-voltage to low-voltage conversion circuit provided in an embodiment of the present application;

[0047] FIG6 is a circuit diagram of a BMS circuit provided in an embodiment of the present application;

[0048] FIG7 is a circuit diagram of another BMS circuit provided in an embodiment of the present application;

[0049] FIG8 is a circuit diagram of another BMS circuit provided in an embodiment of the present application;

[0050] FIG9 is a schematic diagram of the structure of a microprocessor chip provided in an embodiment of the present application;

[0051] FIG10 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0053] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0054] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0055] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0056] Referring to Figure 1, a circuit diagram of a high-voltage to low-voltage circuit in the related art is shown. As shown in Figure 1, the high-voltage to low-voltage circuit includes transistors M101 and M102, resistors R101 and R102, a voltage regulator diode Z101, and a capacitor C101. Among them, the drain of transistor M101 is connected to the power supply Vdd, and the gate of transistor M101 is connected to the ground Gnd; one end of resistor R101 is electrically connected to the source of transistor M101; the cathode of Zener diode Z101 is electrically connected to the other end of resistor R101, and the positive electrode of Zener diode Z101 is connected to the ground Gnd; the drain of transistor M102 is connected to the power supply Vdd, and the gate of transistor M102 is connected to the node between resistor R101 and Zener diode Z101; one end of resistor R102 is electrically connected to the source of transistor M102, and the other end of resistor R102 is connected to the ground Gnd; one end of capacitor C101 is connected to the node between transistor M102 and resistor R102, and the other end of capacitor C101 is connected to the ground Gnd; the source of transistor M102 is connected to the voltage output terminal Vout. Among them, transistor M101 is a junction field-effect transistor (JFET) with a high-voltage negative threshold voltage. The voltage at one end of resistor R101 close to transistor M101 is approximately the absolute value of the threshold voltage of transistor M101. After current limiting by resistor R101, a relatively stable voltage is obtained at the negative terminal of Zener diode Z101. This voltage is used as the gate drive voltage of transistor M102, and the output voltage is obtained at the voltage output terminal Vout.

[0057] However, while the output voltage of Zener diode Z101 exhibits a positive temperature coefficient (i.e., the voltage increases with increasing temperature under the same conditions), the turn-on threshold voltage of transistor M102 typically exhibits a negative temperature coefficient (i.e., its threshold voltage decreases with increasing temperature). This results in a large temperature coefficient at the output voltage Vout. Furthermore, JFET devices are not available in some integrated circuit manufacturing processes, rendering this circuit architecture unusable.

[0058] Refer to Figure 2, which is a circuit diagram of another high-voltage to low-voltage circuit in the related art. As shown in Figure 2, the high-voltage to low-voltage circuit includes transistors M201, M202, M203, M204, M205, M206, M207, M208, M209, M210, M211, M212, and M213, resistors R201, R202, R203, and R204, and a capacitor C201. Among them, the source of transistor M201 is connected to the power supply Vdd; the source of transistor M202 is connected to the power supply Vdd, the gate of transistor M202 is electrically connected to the gate of transistor M201, and the drain of transistor M202 is connected to the ground Gnd through resistor R202; the source of transistor M203 is connected to the power supply Vdd, the gate of transistor M203 is connected to the node between transistor M202 and resistor R202, and the drain of transistor M203 is connected to ground through resistors R203 and R204 in sequence. The drain of transistor M204 is electrically connected to the drain of transistor M201, the source of transistor M204 is grounded to Gnd, and the gate of transistor M204 is connected to the node between resistor R203 and resistor R204; the source of transistor M205 is connected to the power supply Vdd; the source of transistor M206 is electrically connected to the gate and drain of transistor M205 respectively; the source of transistor M207 is electrically connected to the gate and drain of transistor M206 respectively; the source of transistor M208 is electrically connected to The gate and drain of transistor M207 are electrically connected, and the gate and drain of transistor M208 are electrically connected to the gate of transistor M203 respectively; one end of resistor R201 is connected to the node between transistor M202 and resistor R202, and the other end is connected to the node between transistor M203 and resistor R203 through capacitor C201; the gate and drain of transistor M209 are electrically connected to the drain of transistor M203 respectively; the gate and drain of transistor M210 are electrically connected to the source of transistor M209 respectively. The gate and drain of the transistor M211 are electrically connected to the source of the transistor M210 respectively; the gate and drain of the transistor M212 are electrically connected to the source of the transistor M211 respectively, and the source of the transistor M212 is grounded Gnd; the drain of the transistor M213 is electrically connected to the drain of the transistor 203, the gate of the transistor M213 is electrically connected to the gate of the transistor M212, and the source of the transistor M213 is grounded Gnd; the drain of the transistor M203 is connected to the voltage output terminal Vout.

[0059] In the high-voltage to low-voltage converter shown in FIG2 , the gate voltage of the transistor M204 is adjusted by the voltage divider formed by the resistors R203 and R204. The current on the resistor R202 is adjusted by the current mirror formed by the transistors M201 and M202, thereby adjusting the gate voltage of the transistor M203 to obtain the output voltage Vout.

[0060] However, as the voltage of power supply Vdd increases, the voltage across resistor R202 inevitably rises. When power supply Vdd reaches 80V or even higher, to maintain a stable output voltage, the voltage across resistor R202 remains around 78V. If the current distributed by this branch is 500nA, R2 will be greater than 156MΩ, which will occupy a large chip area. As the voltage rises further, the resistance of R202 will increase further. Even with a large resistor, the current in this branch will be very low when the voltage decreases, and the driving capability will be very weak, making this circuit unsuitable for high-voltage, low-power applications. Furthermore, the output of this circuit is heavily dependent on the threshold voltage Vth of transistor M204. ΔVth varies significantly with temperature and process corners, causing the output voltage Vout to vary by (R203+R204) / R204*ΔVth, resulting in poor circuit stability.

[0061] Referring to Figure 3, which is a circuit diagram of a high-voltage to low-voltage circuit provided in an embodiment of the present application, the high-voltage to low-voltage circuit includes a high-voltage to low-voltage module and a low-voltage output module.

[0062] Specifically, the high-voltage to low-voltage module includes a first transistor M1, a second transistor M2, a third transistor M3, a first resistor R1, a second resistor R2, a voltage regulator Z1, and a diode D1. Among them, the source of the first transistor M1 and the source of the second transistor M2 are respectively connected to the first power supply terminal Vdd, and the gate of the first transistor M1 is electrically connected to the gate of the second transistor M2; the drain of the third transistor M3 is electrically connected to the drain of the first transistor M1, the gate of the third transistor M3 is grounded, and the source of the third transistor M3 is grounded through the first resistor R1; the negative electrode of the voltage regulator Z1 is electrically connected to the drain of the second transistor M2 through the second resistor R2; the positive electrode of the diode D1 is electrically connected to the positive electrode of the voltage regulator Z1, and the negative electrode of the diode D1 is grounded. It should be noted that in the embodiment of the present application, the first transistor M1 and the second transistor M2 form a current mirror unit. In addition, the low-voltage output module includes a fourth transistor M4, a third resistor R3, and a first capacitor C1. Among them, the drain of the fourth transistor M4 is connected to the first power supply terminal Vdd, the gate of the fourth transistor M4 is connected to the node between the second resistor R2 and the voltage regulator Z1, and the source of the fourth transistor M4 is grounded through the third resistor R3; the first capacitor C1 and the third resistor R3 are connected in parallel; and the voltage output end is connected to the node between the fourth transistor M4 and the third resistor R3.

[0063] The operating principle of the high-voltage-to-low-voltage circuit provided in the embodiments of the present application is as follows: when VEN (VEN is the gate voltage of the third transistor M3) is greater than the threshold voltage Vth(M1) of the first transistor M1, a current IM flows through the first transistor M1; and under the current mirroring effect of the current mirror unit, the second transistor M2 outputs the same current IM (the current mirror unit can also be designed so that the currents flowing through the first and second transistors are proportional, that is, IM1 = αIM2). At this time, the gate voltage of the fourth transistor M4 is Vg(M4) = IM*R2, and the bias voltage of the fourth transistor M4 is Vbis(M4) = Vg(M4) - Vth(M4), where Vth(M4) is the threshold voltage of the fourth transistor M4. Therefore, as VEN gradually increases, Vbis(M4) also gradually increases, thereby activating the subsequent low-voltage current generator.

[0064] In addition, when VEN=0, the first resistor R1 can pull VEN down to Gnd, the second resistor R2 can pull up the gate voltage of the fourth transistor M4 to Vdd, and the third resistor R3 can pull down the bias voltage of the fourth transistor M4 to Gnd.

[0065] In an embodiment of the present application, a relatively stable current can be obtained in the first resistor R1 branch by using the third transistor M3, which can then provide a relatively stable current to the voltage regulator Z1 branch through the current mirror unit, thereby obtaining a gate drive voltage for the fourth transistor M4 at the upper end of the voltage regulator Z1. Since the output voltage of the voltage regulator Z1 has a positive temperature characteristic, the threshold turn-on voltage of the fourth transistor M4 has a negative temperature characteristic. In the absence of compensation, the output voltage Vout will increase with increasing temperature, resulting in poor temperature characteristics of the circuit. However, since the forward conduction voltage of the diode D1 has a negative temperature characteristic, compensating for the negative temperature characteristic of its forward conduction voltage can greatly improve the output.

[0066] In addition, in the embodiment of the present application, since there is no JFET device, the circuit architecture can still be used normally in certain integrated circuit manufacturing processes that do not have JFET devices.

[0067] In one possible implementation, the voltage regulator Z1 is a Zener diode D1 with a breakdown voltage of 5V. This means that the maximum gate voltage Vg(M4) of the fourth transistor M4 is 5V. Consequently, the maximum bias voltage Vbis(M4) of the fourth transistor M4 does not exceed 5V-Vth(M4), thereby enabling use by the subsequent low-voltage chip of the low-voltage current generator. Of course, those skilled in the art may set the breakdown voltage of the voltage regulator Z1 to other voltage values, such as 4V, 6V, or 8V, as needed, and this embodiment of the present application does not impose any specific limitations thereon.

[0068] In one possible implementation, the third transistor M3 is a high-voltage depletion-mode PMOS transistor, which uses its negative threshold voltage to generate a current in the first resistor R1 branch. The current is approximately |Vth(M3)| / R1, where Vth(M3) is the threshold voltage of the third transistor M3, and the absolute value of the threshold voltage is usually around 1V.

[0069] 3 , in the embodiment of the present application, the first transistor M1 is an NMOS transistor, the second transistor M2 is an NMOS transistor, the third transistor M3 is a PMOS transistor, and the fourth transistor M4 is a PMOS transistor. Those skilled in the art should understand that there are many types of transistors, and those skilled in the art can replace the first transistor M1, the second transistor M2, the third transistor M3, and / or the fourth transistor M4 with other types of transistors according to actual needs to achieve the same or similar functions as the high-voltage to low-voltage conversion circuit shown in FIG3 , and all of these should fall within the scope of protection of the present application.

[0070] Refer to Figure 4, which is a circuit diagram of another high-voltage to low-voltage circuit provided in an embodiment of the present application. As shown in Figure 4, the embodiment of the present application further includes an overshoot suppression circuit on the basis of the high-voltage to low-voltage circuit shown in Figure 3. Specifically, the overshoot suppression circuit includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a second capacitor C2. Among them, the source of the fifth transistor M5 is connected to the first power supply terminal Vdd, and the drain of the fifth transistor M5 is connected to the node between the second resistor R2 and the voltage regulator Z1; the source of the sixth transistor M6 is connected to the first power supply terminal Vdd, and the gate of the fifth transistor M5 is electrically connected to the gate of the sixth transistor M6; the drain of the seventh transistor M7 is electrically connected to the drain of the sixth transistor M6, the source of the seventh transistor M7 is connected to the second power supply terminal EP1, and the gate of the seventh transistor M7 is electrically connected to the voltage output terminal through the second capacitor C2.

[0071] The working principle of the overshoot suppression circuit provided in the embodiment of the present application is as follows: when there is no load current, the high-voltage to low-voltage conversion circuit operates in a stable no-load state; when the load switches from a heavy load to a light load, the output voltage Vout generates an overshoot, and the second capacitor C2 couples the overshoot voltage to the gate of the seventh transistor M7, thereby increasing the gate-source voltage of the seventh transistor M7, and increasing the drain-source current of the seventh transistor M7 and the sixth transistor M6, thereby increasing the current of the fifth transistor M5, increasing the charging speed of the parasitic capacitance of the gate of the fourth transistor M4, increasing the gate voltage of the fourth transistor M4, reducing the current provided to the load, and causing the output voltage Vout to quickly return to a stable voltage value.

[0072] In one possible implementation, the fifth transistor M5 is a PMOS transistor, the sixth transistor M6 is a PMOS transistor, and the seventh transistor M7 is an NMOS transistor. Those skilled in the art should understand that there are many types of transistors, and those skilled in the art can replace the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 with transistors of other types as needed to achieve the same or similar functions as the overshoot suppression circuit shown in FIG4 , and all of these should fall within the scope of protection of this application.

[0073] Refer to Figure 5, which is a circuit diagram of another high-voltage to low-voltage circuit provided in an embodiment of the present application. As shown in Figure 5, the embodiment of the present application further includes an undershoot suppression circuit on the basis of the high-voltage to low-voltage circuit shown in Figure 3. Specifically, the undershoot suppression circuit includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a third capacitor C3. Among them, the drain of the eighth transistor M8 is connected to the node between the second resistor R2 and the voltage regulator Z1, and the source of the eighth transistor M8 is grounded; the gate of the ninth transistor M9 is electrically connected to the gate of the eighth transistor M8, and the source of the ninth transistor M9 is connected to the second power supply terminal EP1; the drain of the tenth transistor M10 is electrically connected to the drain of the ninth transistor M9, the gate of the tenth transistor M10 is electrically connected to the voltage output terminal through the third capacitor C3, and the source of the tenth transistor M10 is connected to the first power supply terminal Vdd.

[0074] The working principle of the undershoot suppression circuit provided in the embodiment of the present application is as follows: when there is no load current, the circuit operates in a stable no-load state. When the load switches from a light load to a heavy load, the output voltage Vout generates an undershoot, and the third capacitor C3 couples the undershoot voltage to the gate of the tenth transistor M10. The drain-source current of the tenth transistor M10 and the ninth transistor M9 increases, thereby increasing the drain-source current of the eighth transistor M8, increasing the discharge speed of the output node voltage Vout, and causing the output voltage Vout to quickly return to a stable voltage value.

[0075] In one possible implementation, the eighth transistor M8 is an NMOS transistor, the ninth transistor M9 is an NMOS transistor, and the tenth transistor M10 is a PMOS transistor. Those skilled in the art should understand that there are many types of transistors, and those skilled in the art can replace the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 with transistors of other types as needed to achieve the same or similar functions as the undershoot suppression circuit shown in FIG5 , and all of these should fall within the scope of protection of this application.

[0076] In one possible implementation, the high-voltage to low-voltage circuit may include both the overshoot suppression circuit shown in FIG4 and the undershoot suppression circuit shown in FIG5 to maintain the stability of the output voltage Vout. For the sake of brevity, they are not described here in detail.

[0077] Corresponding to the above embodiment, an embodiment of the present application further provides a battery management system (BMS) circuit.

[0078] See Figure 6, which is a circuit diagram of a BMS circuit provided in an embodiment of the present application. As shown in Figure 6, the BMS circuit includes a control module and a low dropout regulator (LDO). The LDO includes the high-voltage to low-voltage converter described in the above embodiment. The input terminal of the LDO is electrically connected to the battery pack; the first input terminal of the control module is electrically connected to the output terminal of the LDO, and the LDO is used to power the control module.

[0079] It should be pointed out that the specific content of the high-voltage to low-voltage circuit involved in the embodiment of the present application can be found in the description of the above embodiment. For the sake of brevity, it will not be repeated here.

[0080] See Figure 7, which is a circuit diagram of another BMS circuit provided in an embodiment of the present application. As shown in Figure 7, based on the BMS circuit shown in Figure 6, the embodiment of the present application further includes: a voltage acquisition module, a DC / DC isolated step-down power supply module, and a battery cell switching module. Among them, the input end of the voltage acquisition module is used to be electrically connected to the battery pack, the output end of the voltage acquisition module is electrically connected to the second input end of the control module, the voltage acquisition module is used to collect the voltage information of each battery cell in the battery pack, and send the voltage information of each battery cell to the control module; the first input end of the DC / DC isolated step-down power supply module is used to be electrically connected to the positive pole of the battery pack, the second input end of the DC / DC isolated step-down power supply module is used to be electrically connected to the negative pole of the battery pack, the third input end of the DC / DC isolated step-down power supply module is electrically connected to the first output end of the control module, and the control module is used to control the voltage and current of the DC / DC isolated step-down power supply module; the first input end of the battery cell switching module is electrically connected to the second output end of the control module, the second input end of the battery cell switching module is electrically connected to the output end of the DC / DC isolated step-down power supply module, the output end of the battery cell switching module is used to be electrically connected to the battery pack, the battery cell switching module is used to receive the battery cell switching control instruction output by the control module, and switch the target battery cell to the connection path of the DC / DC isolated step-down power supply module according to the battery cell switching control instruction, so that the DC / DC isolated step-down power supply module charges the target battery cell.

[0081] In one possible implementation, the target cell is the cell with the lowest voltage in the battery pack, so that the DC / DC isolated step-down power module can charge the cell with the lowest voltage, thereby achieving voltage balancing. Preferably, the target cell is the cell with the lowest voltage in the battery pack.

[0082] The working principle of the BMS circuit provided in the embodiment of the present application is: when in the discharge state, the control module collects the voltage information of each battery cell of the battery pack. When the maximum voltage difference between each battery cell is greater than the set value, the control module controls the battery cell switching module to switch the battery cell with the lowest voltage (target battery cell) to the DC / DC isolated step-down power supply module circuit. At the same time, the charging current is set to be less than or equal to the output current of the battery pack, which is equivalent to connecting a power supply of the same voltage in parallel to the target battery cell, so that the discharge speed of the target battery cell is much lower than that of other batteries, thereby achieving voltage balance. When the voltage of the target battery cell is the same as the battery cell with the highest voltage, stop charging the target battery cell. The control module repeats the above process, and when the voltage difference between any two batteries is less than the set value, turns off the DC / DC isolated step-down power supply module. When in the charging state, the control module collects voltage information from each cell in the battery pack. When the maximum voltage difference between the cells is greater than the set value, the control module switches the cell with the lowest voltage (the target cell) to the DC / DC isolated buck power supply module circuit and sets the charging current so that the total charging current of the target cell is less than the maximum allowable charging current. When the voltage of the target cell is the same as that of the cell with the highest voltage, charging of the target cell is stopped. The control module repeats the above process and turns off the DC / DC isolated buck power supply module when the voltage difference of all cells is less than the set value.

[0083] Refer to Figure 8, which is a circuit diagram of another BMS circuit provided in an embodiment of the present application. As shown in Figure 8, the embodiment of the present application, based on the BMS circuit shown in Figure 7, further includes: a current detection module and an overcharge / over-discharge protection module. Among them, the current detection module is used to be connected in series between the battery pack and the negative pole of the battery pack, the output end of the current detection module is electrically connected to the input end of the control module, and the control module is used to receive the current detection information output by the current detection module; the overcharge / over-discharge protection module is used to be connected in series between the battery pack and the negative pole of the battery pack, the input end of the overcharge / over-discharge protection module is electrically connected to the third output end of the control module, the overcharge / over-discharge protection module is used to receive the protection control signal output by the control module, and cut off or conduct the path between the battery pack and the negative pole of the battery pack according to the protection control signal.

[0084] The working principle of the BMS circuit provided in the embodiment of the present application is as follows: the charge / discharge status and current value of the battery pack are obtained through the current detection module; when the input / output current is too large or a battery cell is overcharged or over-discharged, the control module controls the overcharge and over-discharge protection module to operate and cut off the input / output of the battery pack. Only when the trigger condition is removed, the overcharge and over-discharge protection module is reset to ensure the safety of the battery pack.

[0085] The BMS circuit provided in the embodiment of the present application can meet the requirements of low power consumption and high reliability for high-voltage to low-voltage conversion when the power supply voltage varies greatly (such as the normal operating power supply voltage range of the chip is 8V-80V, the voltage is high and the variation range is large).

[0086] Corresponding to the above embodiment, the embodiment of the present application further provides a microprocessor chip.

[0087] See Figure 9, which is a schematic diagram of the structure of a microprocessor chip provided in an embodiment of the present application. As shown in Figure 9, the microprocessor chip includes the high-voltage to low-voltage circuit described in the above embodiment. The details of the high-voltage to low-voltage circuit can be found in the description of the above embodiment and will not be repeated here for the sake of brevity.

[0088] In addition, the embodiments of the present application do not limit the specific functions or types of the microprocessor chip. For example, the microprocessor chip can be a control module, DSP, MPU, micro CPU, etc., which can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions, or a micro central control chip, system-on-chip chip, etc.

[0089] Corresponding to the above embodiment, an embodiment of the present application further provides an electronic device.

[0090] FIG10 is a schematic diagram illustrating the structure of an electronic device according to an embodiment of the present application. As shown in FIG10 , the electronic device includes the microprocessor chip described in the above embodiment. For details about the microprocessor chip, please refer to the description of the above embodiment. For the sake of brevity, the details will not be repeated here.

[0091] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0092] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented using a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0093] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0094] In the several embodiments provided in this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of this application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0095] The above description is merely a specific embodiment of the present application. Any person skilled in the art may easily conceive of variations or substitutions within the technical scope disclosed in this application, and such variations or substitutions shall be within the scope of protection of this application. The scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A high voltage to low voltage circuit, characterized in that: include: A current mirror unit, comprising a first transistor and a second transistor, wherein a source of the first transistor and a source of the second transistor are respectively connected to a first power supply terminal, and a gate of the first transistor and a gate of the second transistor are electrically connected; a third transistor, wherein a drain of the third transistor is electrically connected to the drain of the first transistor, a gate of the third transistor is grounded, and a source of the third transistor is grounded via a first resistor; A voltage regulator tube, wherein a cathode of the voltage regulator tube is electrically connected to a drain of the second transistor via a second resistor; A diode, wherein the anode of the diode is electrically connected to the anode of the voltage regulator tube, and the cathode of the diode is grounded.

2. The high voltage to low voltage circuit according to claim 1, characterized in that: The third transistor is a high-voltage depletion-type PMOS transistor, and the negative threshold voltage of the high-voltage depletion-type PMOS transistor is used to generate current in the first resistor.

3. The high voltage to low voltage circuit according to claim 2, characterized in that: Also includes: a fourth transistor, wherein a drain of the fourth transistor is connected to the first power supply terminal, a gate of the fourth transistor is connected to a node between the second resistor and the voltage regulator tube, and a source of the fourth transistor is grounded through a third resistor; A first capacitor, wherein the first capacitor is connected in parallel with the third resistor; A voltage output terminal is connected to a node between the fourth transistor and the third resistor.

4. The high voltage to low voltage circuit according to claim 3, characterized in that: Also includes: a fifth transistor, wherein a source of the fifth transistor is connected to the first power supply terminal, and a drain of the fifth transistor is connected to a node between the second resistor and the voltage regulator tube; a sixth transistor, wherein a source of the sixth transistor is connected to the first power supply terminal, and a gate of the fifth transistor is electrically connected to the gate of the sixth transistor; A seventh transistor, wherein the drain of the seventh transistor is electrically connected to the drain of the sixth transistor, the source of the seventh transistor is connected to the second power supply terminal, and the gate of the seventh transistor is electrically connected to the voltage output terminal through a second capacitor.

5. The high voltage to low voltage circuit according to claim 4, characterized in that: The first transistor is an NMOS transistor, the second transistor is an NMOS transistor, the third transistor is a PMOS transistor, the fourth transistor is a PMOS transistor, the fifth transistor is a PMOS transistor, the sixth transistor is a PMOS transistor, and the seventh transistor is an NMOS transistor.

6. The high voltage to low voltage circuit according to claim 3, characterized in that: Also includes: an eighth transistor, wherein a drain of the eighth transistor is connected to a node between the second resistor and the voltage regulator tube, and a source of the eighth transistor is grounded; a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the gate of the eighth transistor, and a source of the ninth transistor is connected to a second power supply terminal; A tenth transistor, wherein the drain of the tenth transistor is electrically connected to the drain of the ninth transistor, the gate of the tenth transistor is electrically connected to the voltage output terminal via a third capacitor, and the source of the tenth transistor is connected to the first power supply terminal.

7. The high voltage to low voltage circuit according to claim 6, characterized in that: The first transistor is an NMOS transistor, the second transistor is an NMOS transistor, the third transistor is a PMOS transistor, the fourth transistor is a PMOS transistor, the eighth transistor is an NMOS transistor, the ninth transistor is an NMOS transistor, and the tenth transistor is a PMOS transistor.

8. The high voltage to low voltage circuit according to claim 3, characterized in that: The output voltage of the voltage regulator has a positive temperature characteristic, the forward conduction voltage of the diode has a negative temperature characteristic, and the threshold turn-on voltage of the fourth transistor has a negative temperature characteristic.

9. A BMS circuit, characterized in that: include: An LDO, wherein the LDO comprises the high-voltage to low-voltage conversion circuit according to any one of claims 1 to 8, and an input end of the LDO is used to be electrically connected to a battery pack; A control module, wherein a first input terminal of the control module is electrically connected to an output terminal of the LDO, and the LDO is used to supply power to the control module.

10. The BMS circuit according to claim 9, characterized in that: Also includes: A voltage acquisition module, wherein the input end of the voltage acquisition module is electrically connected to the battery pack, the output end of the voltage acquisition module is electrically connected to the second input end of the control module, and the voltage acquisition module is used to collect voltage information of each battery cell in the battery pack and send the voltage information of each battery cell to the control module; A DC / DC isolated step-down power supply module, wherein the first input end of the DC / DC isolated step-down power supply module is used to be electrically connected to the positive electrode of the battery pack, the second input end of the DC / DC isolated step-down power supply module is used to be electrically connected to the negative electrode of the battery pack, and the third input end of the DC / DC isolated step-down power supply module is electrically connected to the first output end of the control module, and the control module is used to control the voltage and current of the DC / DC isolated step-down power supply module; A cell switching module, wherein a first input end of the cell switching module is electrically connected to a second output end of the control module, a second input end of the cell switching module is electrically connected to an output end of the DC / DC isolated step-down power supply module, an output end of the cell switching module is used to be electrically connected to the battery pack, and the cell switching module is used to receive a cell switching control instruction output by the control module, and switch a target cell to a connection path of the DC / DC isolated step-down power supply module according to the cell switching control instruction, so that the DC / DC isolated step-down power supply module charges the target cell; A current detection module, the current detection module is used to be connected in series between the battery pack and the negative electrode of the battery pack, the output end of the current detection module is electrically connected to the input end of the control module, and the control module is used to receive the current detection information output by the current detection module; An overcharge / over-discharge protection module, the overcharge / over-discharge protection module is used to be connected in series between the battery pack and the negative electrode of the battery pack, the input end of the overcharge / over-discharge protection module is electrically connected to the third output end of the control module, the overcharge / over-discharge protection module is used to receive a protection control signal output by the control module, and cut off or conduct the path between the battery pack and the negative electrode of the battery pack according to the protection control signal.

11. A microprocessor chip, characterized in that: include: The high voltage to low voltage circuit according to any one of claims 1 to 8.

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