Carrier-selective contact layer, photovoltaic devices incorporating the layer, and manufacturing methods therefor

Abstract

The invention relates to a SiCx-based carrier-selective contact layer, which comprises at least one i-aSi layer and at least one conductive film layer stacked sequentially, with a front contact layer arranged between them. The front contact layer comprises at least one SiCx layer, which can be P-type, N-type, or intrinsic, with a total thickness of 2-80 nm. The invention also describes a method for manufacturing this contact layer using a PECVD method, with specific gas ratios for deposition. Additionally, the invention discloses a photovoltaic cell comprising a silicon wafer substrate with at least one SiCx- based carrier-selective contact layer on either the front or back side, or both.

Description

DESCRIPTIONTITLE OF INVENTION: [CARRIER-SELECTIVE CONTACT LAYER, PHOTOVOLTAIC DEVICES INCORPORATING THE LAYER, AND MANUFACTURING METHODS THEREFOR]REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority to Singapore patent application No. 10202303251 T, titled “Carrier Selective Contacts, Photovoltaic Devices Utilizing Them and Methods of Forming Thereof”, filed on 17 November 2024, the contents of which are incorporated herein by reference.TECHNICAL FIELD

[0002] The present disclosure relates generally to photovoltaic cell technology, specifically to structures of carrier-selective contact layers, photovoltaic cells incorporating these layers, and their manufacturing methods.BACKGROUND

[0003] The following discussion of the background to the invention is intended to facilitate an understanding of the present invention only. It should be appreciated that the discussion is not an acknowledgement or admission that any of the material referred to was published, known or part of the common general knowledge of the person skilled in the art in any jurisdiction as at the priority date of the invention.

[0004] Photovoltaic cells (also known as “solar cells”) are devices that efficiently absorb solar radiation and convert it into electrical energy through the photovoltaic effect. When sunlight strikes a semiconductor’s P-N junction, new electron-hole pairs are generated. Within the electric field of the P-N junction, holes migrate from the N- type region to the P-type region, while electrons move from the P-type region to the N- type region. Once the circuit is closed, an electric current flows. These photovoltaic cells form critical components of solar power generation systems. Notably, crystalline silicon heterojunction (SHJ) photovoltaic cells stand out as a promising next-generation photovoltaic technology, offering high energy conversion efficiency, a simple low- temperature manufacturing process, a low temperature coefficient, and dual-sidedpower generation capability. These advantages make them potential candidates for future advancements in solar energy technology.

[0005] Silicon carbide (SiC) is a material known for its wide bandgap of approximately 3.4 eV, which allows it to absorb only short-wavelength light below 400 nm, which is a range not typically utilized in conventional photovoltaic cells. Beyond its bandgap properties, SiC also exhibits high electrical conductivity, which enhances its resistance to potential-induced degradation (PID). This feature addresses the common challenge of balancing PID resistance with cell efficiency, among other benefits. Due to these attributes, SiC has become an important material in the design and enhancement of photovoltaic cells, contributing to more robust and efficient photovoltaic performance.

[0006] For example, U.S. Patent Application Publication No. US20160027951A1 , titled “Solar cell and method for manufacturing the same,” discloses a technique to reduce the resistivity of the solar cell by controlling the doping concentration ratio between the semiconductor substrate that forms the p-n junction and the emitter region located in the back surface field of the semiconductor substrate. Additionally, a tunneling layer (such as SiC or another dielectric material) is placed between the back surface field of the semiconductor substrate and the emitter region, to enable the electron-hole pairs generated by light incident on the semiconductor substrate to be separated by the p-n junction between the semiconductor substrate and the emitter region. U.S. Patent Application Publication No. US20200075789A1 , titled “Silicon heterojunction solar cells and methods of manufacture,” discloses a technique for improving heterojunction solar cells by introducing a passivated conductive stack that includes a thin wide-bandgap material layer as a passivation layer between the lightabsorbing silicon layer and the doped silicon base layer (preferably including silicon carbide, SiCx). This configuration provides a more uniform and temperature-stable passivated contact, enabling the heterojunction solar cell to withstand firing and / or thermal annealing. However, despite these advancements, these solar cells still encounter technical challenges in achieving optimal efficiency and performance.

[0007] Thus, there exists a need to develop improved photovoltaic cells and alleviate at least one of the aforementioned problems in the conventional arts.SUMMARY

[0008] Specifically, to address the above-mentioned technical problems, the present invention specifically uses the following technical solutions:

[0009] Accordingly, an aspect of the invention refers to a SiCx-based carrier-selective contact layer, comprising: at least one i-aSi layer and at least one conductive film layer stacked sequentially; and a front contact layer arranged between the at least one i-aSi layer and the at least one conductive film layer; wherein the front contact layer comprises at least one SiCx layer; wherein the at least one SiCx layer is configured to be a P-type doped SiCx layer, an N-type doped SiCx layer, or an intrinsic SiCx layer; wherein total thickness of the at least one SiCx layer is 2-80 nm.

[0010] In some embodiments, the SiCx-based carrier-selective contact layer further comprises: at least one doped aSi layer arranged between the at least one i-aSi layer and the front contact layer; wherein the at least one doped aSi layer is either N-type doped aSi layer or P-type doped aSi layer.

[0011] In some embodiments, the front contact layer comprises a single SiCx layer; and the single SiCx layer is configured to have a thickness of 1 .5 - 50 nm.

[0012] In some embodiments, the front contact layer comprises two SiCx layers: an inner layer closer to the at least one i-aSi layer, and an outer layer farther from the at least one i-aSi layer; wherein the inner layer is configured to have a thickness of 1 - 30 nm; and the outer layer is configured to have a thickness of 1-80 nm.

[0013] In some embodiments, the inner layer is configured to have a thickness of 2- 20 nm; and the outer layer is configured to have a thickness of 3-40 nm.

[0014] In some embodiments, the inner layer is configured to have a thickness of 5- 20 nm; and the outer layer is configured to have a thickness of 10-30 nm.

[0015] In some embodiments, the front contact layer comprises three or more SiCx layers: an inner layer closest to the at least one i-aSi layer, an outer layer farthest from the at least one i-aSi layer, and at least one intermediate layer arranged between the inner layer and the outer layer; wherein the inner layer is configured to have a thicknessof 0.5-30 nm; the outer layer is configured to have a thickness of 0.5-75 nm; the at least one intermediate layer is configured to have a total thickness of 1-80 nm.

[0016] In some embodiments, the inner layer is configured to have a thickness of 1- 20 nm; the outer layer is configured to have a thickness of 1 -40 nm; the at least one intermediate layer is configured to have a total thickness of 3-60 nm.

[0017] In some embodiments, the inner layer is configured to have a thickness of 5- 20 nm; the outer layer is configured to have a thickness of 5-40 nm; the at least one intermediate layer is configured to have a total thickness of 5-40 nm.

[0018] In some embodiments, the at least one doped aSi layer is configured to have a total thickness of 1-15 nm.

[0019] In some embodiments, the at least one doped aSi layer is configured to be as a single layer, having a thickness of 1-12nm.

[0020] In some embodiments, the at least one doped aSi layer is configured to have a thickness of 2-7nm.

[0021] In some embodiments, the at least one doped aSi layer is configured to be as a double layer, comprising an inner layer farther from the front contact layer and an outer layer closer to the front contact layer; wherein, the inner layer is configured to have a thickness of 1-5nm; and the outer layer is configured to have a thickness of 1- 14nm.

[0022] In some embodiments, the inner layer is configured to have a thickness of 2- 5nm; and the outer layer is configured to have a thickness of 2-1 Onm.

[0023] In some embodiments, the at least one doped aSi layer is configured as a multi-layer, comprising an inner layer farther from the front contact layer, an outer layer closer to the front contact layer, and at least one intermediate layer arranged between the inner layer and the outer layer; wherein the inner layer is configured to have a thickness of 1-5nm; the outer layer is configured to have a thickness of 1-1 Onm; and the at least one intermediate layer is configured to have a total thickness of 1 -1 Onm.

[0024] In some embodiments, the inner layer is configured to have a thickness of 2- 5nm; the outer layer is configured to have a thickness of 2-7nm; and the at least one intermediate layer is configured to have a total thickness of 2-7nm.

[0025] Another aspect of the invention refers to a method for manufacturing SiCx- based carrier-selective contact layer, comprising the steps of: S101 depositing at least one i-aSi layer on a substrate; S103 based on preset deposition parameters, depositing at least one SiCx layer with a total thickness of 2-80 nm on the at least one i-aSi layer using a PECVD method; the SiCx layer is an N-type doped SiCx layer, a P-type doped SiCx layer, or an intrinsic SiCx layer; S105 depositing at least one conductive film layer on the at least one SiCx layer; wherein the preset deposition parameters comprises: a gas ratio of CH4to SiH4is 0.05-10; and a gas ratio of PH3to SiH4is 0.5-10.

[0026] In some embodiments, the at least one SiCx layer is configured to have a total thickness of 2-50nm.

[0027] In some embodiments, the at least one SiCx layer is configured to have a total thickness of 2-20nm.

[0028] In some embodiments, the at least one SiCx layer is deposited on an upper surface of the at least one i-aSi layer, partially or entirely covering the upper surface of the at least one i-aSi layer.

[0029] In some embodiments, prior to the step S103, the method further comprises the step of depositing at least one doped aSi layer on the at least one i-aSi layer; wherein the at least one doped aSi layer is either N-type doped aSi layer or P-type doped aSi layer; and the at least one doped aSi layer is configured to have a total thickness of 1-15 nm.

[0030] In some embodiments, the at least one SiCx layer is deposited on an upper surface of the at least one doped aSi layer, partially or entirely covering the upper surface of the at least one doped aSi layer.

[0031] In some embodiments, the at least one doped aSi layer is configured as a single layer, having a thickness of 1-12 nm.

[0032] In some embodiments, if two N-type doped aSi layers are deposited, a first N- type doped aSi layer with a thickness of 1-14 nm and a second N-type doped aSi layer with a thickness of 1-14 nm are sequentially deposited on the at least one i-aSi layer; or, if two P-type doped aSi layers are deposited, a first P-type doped aSi layer with a thickness of 1-14 nm and a second P-type doped aSi layer with a thickness of 1 -14 nm are sequentially deposited on the at least one i-aSi layer.

[0033] In some embodiments, the first N-type doped aSi layer with a thickness of 1 -5 nm and the second N-type doped aSi layer with a thickness of 1 -14 nm are sequentially deposited on the at least one i-aSi layer; or, the first P-type doped aSi layer with a thickness of 1-5 nm and the second P-type doped aSi layer with a thickness of 1 -14 nm are sequentially deposited on the at least one i-aSi layer.

[0034] In some embodiments, the first N-type doped aSi layer with a thickness of 2-5 nm and the second N-type doped aSi layer with a thickness of 2-10 nm are sequentially deposited on the at least one i-aSi layer; or, the first P-type doped aSi layer with a thickness of 2-5 nm and the second P-type doped aSi layer with a thickness of 2-10 nm are sequentially deposited on the at least one i-aSi layer.

[0035] In some embodiments, if at least three N-type doped aSi layers are deposited, a first N-type doped aSi layer with a thickness of 0.5-14 nm, at least one third N-type doped aSi layer with a total thickness of 1-14 nm, and a second N-type doped aSi layer with a thickness of 0.5-14 nm are sequentially deposited on the at least one i-aSi layer; or, if at least three P-type doped aSi layers are deposited, a first P-type doped aSi layer with a thickness of 0.5-14 nm, at least one third P-type doped aSi layer with a total thickness of 1-14 nm, and a second P-type doped aSi layer with a thickness of 0.5-14 nm are sequentially deposited on the at least one i-aSi layer.

[0036] In some embodiments, the first N-type doped aSi layer with a thickness of 1 -5 nm, the at least one third N-type doped aSi layer with a total thickness of 1-10 nm, and the second N-type doped aSi layer with a thickness of 1 -10 nm are sequentially deposited on the at least one i-aSi layer; or, the first P-type doped aSi layer with a thickness of 1-5 nm, the at least one third P-type doped aSi layer with a total thickness of 1-10 nm, and the second P-type doped aSi layer with a thickness of 1 -10 nm are sequentially deposited on the at least one i-aSi layer.

[0037] In some embodiments, the first N-type doped aSi layer with a thickness of 2-5 nm, the at least one third N-type doped aSi layer with a total thickness of 2-7 nm, and the second N-type doped aSi layer with a thickness of 2-7 nm are sequentially deposited on the at least one i-aSi layer; or, the first P-type doped aSi layer with a thickness of 2-5 nm, the at least one third P-type doped aSi layer with a total thickness of 2-7 nm, and the second P-type doped aSi layer with a thickness of 2-7 nm are sequentially deposited on the at least one i-aSi layer.

[0038] Another aspect of the invention refers to a photovoltaic cell, comprising a silicon wafer substrate with a front side and a back side (also known as “rear side”); wherein at least one SiCx-based carrier-selective contact layer is placed on either the front side of the silicon wafer substrate, the back side of the silicon wafer substrate, or both.

[0039] In some embodiments, two SiCx-based carrier-selective contact layers are respectively placed on two spaced-apart local areas of the front side of the silicon wafer substrate, the back side of the silicon wafer substrate, or both.

[0040] In some embodiments, the SiCx-based carrier-selective contact layer placed on the front side of the silicon wafer substrate is configured to partially or entirely cover a first surface of the front side of the silicon wafer substrate; or, the SiCx-based carrier- selective contact layer placed on the back side of the silicon wafer substrate is configured to partially or entirely cover a second surface of the back side of the silicon wafer substrate.

[0041] In some embodiments, the photovoltaic cell is a tandem photovoltaic cell comprising a first photovoltaic cell unit and a second photovoltaic cell unit; and, wherein the first photovoltaic cell unit comprises a first SiCx-based carrier-selective contact layer placed on the front side of the first silicon wafer substrate; and the second photovoltaic cell unit comprises a second carrier-selective contact layer configured to be placed on the first SiCx-based carrier-selective contact layer.

[0042] In some embodiments, the second carrier-selective contact layer is the SiCx- based carrier-selective contact layer according to the various embodiments of the present invention.

[0043] In some embodiments, two SiCx-based carrier-selective contact layers placed on two spaced-apart local areas on either the front side of the silicon wafer substrate or the back side of the silicon wafer substrate; wherein the two SiCx-based carrier- selective contact layers comprise a P-type doped SiCx layer and a N-type doped SiCx layer.

[0044] In some embodiments, a P-type doped SiCx layer is placed on one side of the silicon wafer substrate; and, a N-type doped SiCx layer is placed on opposite side of the silicon wafer substrate.

[0045] Other aspects and features of the present invention will become apparent to those of ordinary skill in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

[0046] The present invention achieves various technical advantages over the conventional photovoltaic devices.

[0047] First, the contact properties of the SiCx layer are adjustable, enabling optimal integration with adjacent layers. This tunability improves the overall contact quality, thereby enhancing the efficiency of photovoltaic cells. Additionally, with its wide bandgap, the SiCx layer offers greater transparency to light, allowing more light to be absorbed by the photovoltaic cell. This feature increased light absorption leads to a higher short-circuit current (Jsc) and boosts overall device performance.

[0048] The SiCx layer also significantly minimizes charge carrier recombination losses at the front surface of the photovoltaic cell, which can result in a higher opencircuit voltage (Voc) for the photovoltaic cells. This reduction in recombination directly contributes to improved energy conversion efficiency.

[0049] Additionally, a notable feature of the SiCx layer is its adjustable bandgap, which reduces contact resistance and lowers the series resistance to current flow. This property facilitates smoother current flow across the layers, further enhancing device efficiency.

[0050] Furthermore, the SiCx layer exhibits higher conductivity compared to the traditional n-aSi layer, simplifying charge carrier collection and contributing to increased efficiency. Its versatility is another technical advantage: the SiCx layer can function aseither a p-type or n-type layer, depending on the doping used, offering a cost-effective solution for production processes.

[0051] Finally, the SiCx layer can be deposited through PECVD method, making it easily integrable into existing industrial production lines. This compatibility with standard production / manufacturing processes ensures that the novel SiCx layer can be widely adopted across the industry, making it a significant advancement in photovoltaic cell technology.BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In the figures, which illustrate, by way of non-limiting examples only, embodiments of the present invention:

[0053] [Fig. 1]: a schematic diagram of a carrier-selective contact layer (CSC) according to an embodiment of the present invention;

[0054] [Fig. 2]: a schematic diagram of a carrier-selective contact layer used as a electron-selective contact (ESC) according to an embodiment of the present invention;

[0055] [Fig. 3]: a schematic diagram of a carrier-selective contact layer used as an hole-selective contact (HSC) according to an embodiment of the present invention;

[0056] [Fig. 4]: a schematic diagram of a carrier-selective contact layer applied as an HSC in a photovoltaic cell according to an embodiment of the present invention;

[0057] [Fig. 5]: a schematic diagram of a carrier-selective contact layer applied as both an ESC and an HSC in a photovoltaic cell according to an embodiment of the present invention;

[0058] [Fig. 6]: a schematic diagram of a carrier-selective contact layer applied as an ESC in a photovoltaic cell according to an embodiment of the present invention;

[0059] [Fig. 7]: a schematic diagram of a carrier-selective contact layer placed on the back side of a silicon wafer substrate in a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0060] [Fig. 8]: a schematic diagram of a carrier-selective contact layer placed on the front side of a silicon wafer substrate in a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0061] [Fig. 9]: a schematic diagram of a carrier-selective contact layer placed on a designated local area of the front side of a silicon wafer substrate in a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0062] [Fig. 10]: a schematic diagram of carrier-selective contact layers placed on two designated areas of the back side of a silicon wafer substrate in a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0063] [Fig. 11]: a schematic diagram of a carrier-selective contact layer placed on the back side of the silicon wafer substrate of a first photovoltaic cell unit of a tandem photovoltaic cell according to an embodiment of the present invention;

[0064] [Fig. 12]: a schematic diagram of a carrier-selective contact layer placed between the front side of the silicon wafer substrate of a first photovoltaic cell unit and a carrier-selective contact layer of a second photovoltaic cell unit; wherein both the first and second photovoltaic cell units are from a tandem photovoltaic cell.

[0065] [Fig. 13]: a schematic diagram of carrier-selective contact layers functioning as an ESC on the back side and as an HSC on the front side of a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0066] [Fig. 14]: a schematic diagram of carrier-selective contact layers functioning as an ESC on the front side and as an HSC on the back side of a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0067] [Fig. 15]: a schematic diagram of carrier-selective contact layers functioning as both an ESC and an HSC on the front side of a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0068] [Fig. 16]: a schematic diagram of carrier-selective contact layers functioning as both an ESC and an HSC on the back side of a front and back contact photovoltaic cell according to an embodiment of the present invention;

[0069] [Fig. 17]: a schematic diagram of carrier-selective contact layers functioning as an ESC on the front side and as an HSC on the back side of a tandem photovoltaic cell according to an embodiment of the present invention;

[0070] [Fig. 18A]: a flowchart of a method for manufacturing the above carrier- selective contact layer according to a first embodiment of the present invention;

[0071] [Fig. 18B]: a flowchart of a method for manufacturing the above carrier- selective contact layer according to a second embodiment of the present invention;

[0072] [Fig. 18C]: a flowchart of a method for manufacturing the above carrier- selective contact layer according to a third embodiment of the present invention;

[0073] [Fig. 18D]: an illustrative diagram showing the method for forming SiCx CSC according to an embodiment of the present invention;

[0074] [Fig. 18E]: an illustrative diagram showing the method for fabricating the photovoltaic cells according to an embodiment of the present invention;

[0075] [Fig. 19]: a comparison of efficiencies between photovoltaic cells using (i) aSi ESC and (ii) SiCx ESC of the present invention;

[0076] [Fig. 20]: a comparison of pseudo fill factors between heterojunction (HJ) photovoltaic cells using (i) aSi ESC and (ii) SiCx ESC of the present invention;

[0077] [Fig. 21]: a comparison of fill factors between photovoltaic cells using (i) aSi ESC and (ii) SiCx ESC of the present invention;

[0078] [Fig. 22]: a comparison of resistance values between photovoltaic cells using (i) aSi ESC and (ii) SiCx ESC of the present invention;

[0079] [Fig. 23]: experimental results demonstrating the impact of total n-aSi thickness on the efficiency of photovoltaic cell;

[0080] [Fig. 24]: experimental results demonstrating the impact of thickness of innermost SiCx layer on the efficiency of photovoltaic cell ;

[0081] [Fig. 25]: experimental results demonstrating the Impact of thickness of outermost SiCx layer on the efficiency of photovoltaic cell;

[0082] [Fig. 26]: experimental results showing the effect of different N-type doping levels on bandgap Eg;

[0083] [Fig. 27]: experimental results showing the effect of varying C content on bandgap Eg;

[0084] [Fig. 28]: experimental results showing the effect of different N-type doping levels on extinction coefficient k.

[0085] [Fig. 29]: experimental results showing the effect of varying C content on extinction coefficient k.

[0086] [Fig. 30]: a schematic diagram of a CSC in Si HJ solar cells and a typical Si HJ solar cell according to the conventional arts.DETAILED DESCRIPTION

[0087] Throughout this document, unless otherwise indicated to the contrary, the terms “comprising”, “consisting of’, “having” and the like, are to be construed as non- exhaustive, or in other words, as meaning “including, but not limited to”.

[0088] Furthermore, throughout the document, unless the context requires otherwise, the word “include” or variations such as “includes" or “including” will be understood to imply the inclusion of a stated integer or group of integers but not the exclusion of any other integer or group of integers.

[0089] Throughout the description, some of the abbreviations used are listed in Table .1 below.

[0090] Table 1 :

[0091] Unless defined otherwise, all other technical and scientific terms used herein have the same meaning as is commonly understood by a skilled person to which the subject matter herein belongs.

[0092] According to various embodiments there is a novel carrier selective contact (CSC) structure that utilizes doped silicon carbide (SiCx) thin film layer(s).

[0093] Referring to Fig. 1 , the carrier-selective contact layer of the present invention comprises at least one intrinsic amorphous silicon layer (i-aSi layer) 121 , a conductive film layer (TCF) 500, and a front contact layer positioned between them. Specifically, the front contact layer comprises at least one SiCx layer with a total thickness of 2-80 nm.

[0094] In some embodiments, the SiCx layer may comprise: at least one doped SiCx layer 127 or at least one intrinsic SiCx layer. The doped SiCx layer 126 can be a N-typedoped SiCx layer (n-doped SiCx layer(s)) 126b, or a P-type doped SiCx layer (p-doped SiCx layer(s)) 126a. When the SiCx layer is intended to be used as the ESC of the solar cell, the SiCx layer is N-type doped SiCx layer; and when the SiCx layer is intended to be used as the HSC of the solar cell, the SiCx layer is P-type doped SiCx layer.

[0095] In some embodiments, the at least one i-aSi layer 121 is formed on a silicon wafer substrate 11 via the PECVD method. Specifically, the silicon wafer substrate 11 is selected based on several criteria: crystallinity, dopant type, thickness, surface morphology, and electrical resistivity.

[0096] The wafer may be mono- or multi-crystalline, with monocrystalline being preferred. The dopant type can be either p-type (e.g., boron (B) or gallium (Ga)) or n- type (e.g., phosphorus (P)), with a preference for n-type.

[0097] The wafer thickness typically ranges from 50 to 180 pm, with a preferred range of 80-160 pm.

[0098] Surface morphology may be either textured or planar. A random pyramidal texture with an average feature height of 0.5 to 3 pm (preferably 0.5 to 1.5 pm) can be adopted. Notably, this surface morphology applies to the side where the SiCx-based carrier-selective contact layer (CSC) will be applied, just prior to CSC deposition or placement. Lastly, the wafer’s resistivity is ideally between 0.1 and 100 Q-cm, with a preferred range of 0.5-10 Q-cm.

[0099] In various embodiments, the i-aSi layer(s) or stack may comprises one, two, three, four, or even more layers, with a preferred configuration of two or three layers in some particular embodiments. The material used can be intrinsic amorphous silicon (aSi). The total thickness (THK) of the i-aSi layers typically ranges from 1 to 15 nm. If there are 2 layers, the innermost layer (THKin) and the outermost layer (THKout) each can be configured to have a thickness of 1-14 nm. For stacks with three or more layers, the innermost layer (THKin) can be configured to have a thickness of 0.5-14 nm, the middle layer(s) (THKmid) (also known as “intermediate layer(s)’’) can be configured to have a thickness of 1-14 nm, and the outermost layer (THKout) can be configured to have a thickness of 0.5-14 nm. A possible set of configurations are summarized in Table 2 below.

[0100] Table 2:

[0101] In some embodiments, the SiCx layer(s) or stack may comprise one, two, three, or even more layers, with a preferred configuration of two or three layers in some particular embodiments. The layer material can be intrinsic SiCx or doped SiCx, with either n-type or p-type doping. The crystal grain size of the SiCx layers typically ranges from 2 nm to 300 pm.

[0102] The total thickness (THK) of the SiCx layer(s) is generally between 2 and 80 nm. For a stack of two layers, the innermost layer (THKin) can be configured to have a thickness of 1 to 30 nm, and the outermost layer (THKout) can be configured to have a thickness of 1 to 80 nm. For stacks of three or more layers, the innermost layer (THKin) can be configured to have a thickness of 0.5 to 30 nm, the middle layer(s) or intermediate layer(s) (THKmid) can be configured to have a thickness of 1 to 80 nm, and the outermost layer (THKout) can be configured to have a thickness of 0.5 to 75 nm. A possible set of configurations are provided in the Table 3 below.

[0103] Table 3:

[0104] Properties of the SiCx Layers / Stack: pc,TCF / sicx^ 0.1 Q-cm2and pc,sicx / asi^ 0.1Q-cm2

[0105] In some embodiments, if the SiCx layer is constructed as a single layer, comprising only one N-type doped SiCx layer, one P-type doped SiCx layer, or one intrinsic SiCx layer. The thickness of the SiCx layer ranges from 1 .5 to 50 nm.

[0106] In some embodiments, if the SiCx layer comprises two layers (i.e., constructed as a double layer), the layer closest to at least one i-aSi layer (i.e., also nearest to the silicon wafer substrate 11 ) is designated as the inner layer and has a thickness of 1-30 nm. The layer farthest from the i-aSi layer (i.e., also farthest from the silicon wafer substrate 11) is designated as the outer layer, with a thickness of 1-80 nm. In some embodiments, the inner layer is configured to have a thickness of 2-20 nm, and the outer layer is configured to have a thickness of 3-40 nm. In some embodiments, the inner layer’s thickness is 5-20 nm, and the outer layer’s thickness is 10-30 nm.

[0107] In some embodiments, if the SiCx layer is configured to comprise three or more layers, the layer closest to the i-aSi layer (i.e., also nearest to the silicon wafer substrate 11 ) serves as the inner layer and has a thickness of 0.5-30 nm. The layer farthest from the i-aSi layer (i.e., also farthest from the silicon wafer substrate 11) serves as the outer layer with a thickness of 0.5-75 nm. At least one intermediate layer positioned between the inner and outer layers is configured to have a combined thickness of 1-80 nm (i.e., total thickness). In some embodiments, the inner layer is configured to have a thickness of 1-20 nm, the outer layer is configured to have a thickness of 1-40 nm, and the total thickness of the intermediate layer(s) is 3-60 nm. In some embodiments, the inner layer is configured to have a thickness of 5-20 nm, the outer layer is configured to have a thickness of 5-40 nm, and the intermediate layer(s) is configured to have a total thickness of 5-40 nm.

[0108] In some embodiments, the TCF (transparent conductive film) layer(s) or stack may comprise one, two, or three layers, with two layers being adopted in some embodiments. The materials for the TCF layers may include one or more transparent conductive oxides (TCOs), which may be either intrinsic or doped, including InOx, ZnOx, TiOx, WOx, or NiOx. The dopants may be selected from Sn, Zn, W, Ti, Ce, Nb, H, Al, B, P, F, among others, with doping fractions ranging from 0.5% to 15% or more. Organic materials such as graphene, carbon nanotubes, or PEDOT (Poly(3,4-ethylenedioxythiophene)) may also be used. In some embodiments, the TCF compositions comprise 1-10% Sn-doped InOx, 10% Zn-doped InOx, W-doped InOx, or Ce-doped InOx. The total thickness of the TCF layer(s) is generally between 50 and 200 nm. For configurations with two layers, the inner layer can be configured to have a thickness of 5-30 nm, and the outer layer can be configured to have a thickness of 5- 190 nm. For configurations with three layers, the innermost layer can be configured to have a thickness of 5-30 nm, the intermediate layer can be configured to have a thickness of 5-80 nm, and the outermost layer can be configured to have a thickness of 5-185 nm. A possible set of configurations are provided in the Table 4 below.

[0109] Table 4:

[0110] Properties of TCF Layers / Stack: pc.TCF / siCx^ 0.1 fl-cm2and pc,siCx / asiS 0.1 flan2.

[0111] Referring to Fig. 1 , the present invention also provides an alternative carrier- selective contact layer. This alternative carrier-selective contact layer comprises the layers described above; however, in some embodiments, the carrier-selective contact layer further comprises at least one doped aSi layer positioned between the at least one i-aSi layer and the front contact layer. Specifically, this doped aSi layer 125 may be an N-type doped aSi layer 125b or a P-type doped aSi layer 125a.

[0112] For example, at least one N-type doped aSi layer 125b may be positionedbetween the at least one i-aSi layer 121 and the at least one N-type doped SiCx layer 126b. Another example includes at least one P-type doped aSi layer 125a placed between the at least one i-aSi layer 121 and the at least one P-type doped SiCx layer 126a. When the SiCx layer is intended to be used as the ESC of the solar cell, the SiCx layer is N-type doped SiCx layer; and when the SiCx layer is intended to be used as the HSC of the solar cell, the SiCx layer is P-type doped SiCx layer.

[0113] Additionally, at least one P-type doped aSi layer or at least one N-type doped aSi layer may be positioned between the at least one i-aSi layer and the at least one intrinsic SiCx layer.

[0114] In some embodiments, the total thickness of the at least one doped aSi layer is between 1 and 15 nm.

[0115] In some embodiments, if the doped aSi layer comprises only one N-type or one P-type doped aSi layer, the thickness of this doped aSi layer is 1 -12 nm. In some embodiments, the thickness of this doped aSi layer is between 2 and 7 nm.

[0116] In some embodiments, if the doped aSi layer comprises two layers, the inner layer, which is closer to the silicon wafer substrate 1 1 (i.e., farther from the front contact layer), has a thickness of 1-5 nm, while the outer layer, positioned farther from the silicon wafer substrate 1 1 (i.e., closer to the front contact layer), has a thickness of 1 -14 nm. In some embodiments, the inner layer thickness is 2-5 nm, and the outer layer thickness is 2-10 nm.

[0117] In some embodiments, if the doped aSi layer comprises three or more layers, the inner layer closet to the silicon wafer substrate 1 1 (i.e., farther from the front contact layer) can be configured to have a thickness of 1 -5 nm, and the outer layer, positioned farthest from the substrate 1 1 (i.e., closer to the front contact layer), can be configured to have a thickness of 1 -10 nm. The total thickness of at least one intermediate layer positioned between the inner and outer layers is 1 -10 nm. In some embodiments, the inner layer thickness is 2-5 nm, the outer layer thickness is 2-7 nm, and the intermediate layer(s) collectively have a thickness of 2-7 nm.

[0118] In some embodiments, the doped aSi layer(s) 125 or stack may comprise zero, one, two, three, or more layers, with one or two layers being preferred in someparticular embodiments. The layer material is doped aSi, which may be either N-type or P-type doped. The total thickness of the doped aSi layer(s) 125 typically ranges from 1 to 15 nm in some embodiments. For configurations with two layers, the thickness of the innermost layer (THKin) is 1-14 nm, and the outermost layer (THKout) is also 1-14 nm. For stacks with three or more layers, the innermost layer (THKin) has a thickness of 0.5- 14 nm, the intermediate layer(s) (THKmid) have a thickness of 1 -14 nm, and the outermost layer (THKout) has a thickness of 0.5-14 nm. A possible set of configurations for these layers are provided in the Table.5 below.

[0119] Table 5:

[0120] Properties of the Doped aSi Layers / Stack: pc,asi / sicx 0.1 Q-cm2.

[0121] A photovoltaic cell may incorporate both a SiCx electron-selective contact (SiCx ESC) 12d and a SiCx hole-selective contact (SiCx HSC) 12b. Referring to Figures 7 and 8, the SiCx CSC 12 in the present invention can be applied to the front side of a solar cell as an ESC, while other layers are used on the back side. Alternatively, the SiCx CSC 12 can be positioned on the back side of the solar cell as an HSC, with other layers 700 on the front side. Additionally, as shown in Fig. 13 and 14, the SiCx CSC 12 can be applied to both the front and back sides of the solar cell, serving as an ESC and HSC, respectively. This configuration is suitable for silicon heterojunction (HJ) solar cells, including both front-and-back contact and fully back-contact solar cells, as well as tandem solar cells.

[0122] Each CSC can be applied to either or both sides of the photovoltaic cell and may cover the entire surface or only a portion of one side. Referring to Fig. 9, the SiCx CSC 12 in the present invention may completely / entirely cover the upper surface of the silicon wafer substrate 11 on the front side of the solar cell, functioning as an ESC. Alternatively, the SiCx CSC 12 may cover only a specified local area of the front side. Similarly, the SiCx CSC 12 can fully cover the lower surface of the silicon wafer substrate 11 on the back side, acting as an HSC. As shown in Fig. 10, the SiCx CSC 12 may also cover only a designated local area of the back side (i.e., partially covering the back side of the solar cell), while an additional CSC 13 is arranged on the remaining lower surface on the back side, with another layer 700 positioned between them. Electrodes 600 are then applied on both the SiCx CSC 12 and the additional CSC 13.

[0123] As shown in Fig. 16, two SiCx CSC 12 layers respectively cover two local regions of the lower surface on the back side of the silicon wafer substrate, with another layer 700 (such as a recombination layer) arranged between them. Of course, as shown in Fig. 15, two SiCx CSC 12 layers may also be simultaneously placed on two local regions of the lower surface on the front side of the silicon wafer substrate.

[0124] Referring to Figuresl 1 , 12 and 17, in other embodiments, the SiCx CSC 12 in this invention can be applied in tandem photovoltaic cells. Specifically, the SiCx CSC 12 can be positioned on the back side of the silicon wafer substrate 11 in one solar cell unit within the tandem structure (covering either the entire back side or a specific region) to act as an HSC. Additionally, the SiCx CSC 12 can be placed between the front side of this silicon wafer substrate 11 and other layers 700a of another solar cell unit in the tandem structure (covering either the full front side or a designated area) to serve as an ESC. These other layers 700a may include recombination layers or carrier-selective contact layers of the other solar cell unit in the tandem structure.

[0125] Embodiment 1 : SiCx HSC Based on the Present Invention

[0126] Referring to Fig. 3, the SiCx HSC in this embodiment includes at least one intrinsic amorphous silicon (i-aSi) layer 121 , at least one P-type doped amorphous silicon (aSi) layer 125a, at least one conductive film layer 500, and at least one P-type doped SiCx layer 126a positioned between the P-type doped aSi layer 125a and the conductive film layer 500. The total thickness of the P-type doped SiCx layer 126a is 2- 80 nm.

[0127] Referring to Figures 4 and 7, based on the above SiCx HSC 12b, the present invention also provides a photovoltaic cell that comprises a silicon wafer substrate 11 with a hole-selective contact layer positioned on the back side of the silicon wafer substrate 11. Specifically, the hole-selective contact layer uses the SiCx HSC 12b described above. An electron-selective contact layer is positioned on the front side of the silicon wafer substrate 11 and employs a different electron-selective contact layer, such as the N-type doped aSi ESC 12a.

[0128] Embodiment 2: SiCx ESC Based on the Present Invention

[0129] Referring to Fig. 2, the SiCx ESC 12d in this embodiment comprises at least one intrinsic amorphous silicon (i-aSi) layer 121 , at least one N-type doped amorphous silicon (aSi) layer 125b, at least one conductive film layer 500, and at least one N-type doped SiCx layer 126b positioned between the N-type doped aSi layer 125b and the conductive film layer 500. The total thickness of the N-type doped SiCx layer 126b is 2- 80 nm.

[0130] Referring to Figures 6 and 8, based on the above SiCx ESC 12d, the present invention also provides a solar cell that comprises a silicon wafer substrate 11 with an electron-selective contact layer positioned on the front side of the substrate 11. Specifically, the electron-selective contact layer uses the SiCx ESC 12d described above, while the hole-selective contact layer positioned on the back side of the silicon wafer substrate 11 employs a different hole-selective contact layer, such as the P-type doped aSi HSC 12c.

[0131] Referring to Fig. 5, based on the above SiCx HSC and SiCx ESC, the present invention also provides another solar cell configuration. This configuration comprises a silicon wafer substrate 11 with two carrier-selective contact layers positioned on the front and back sides. The front-side carrier-selective contact layer uses the SiCx ESC from Embodiment 2, while the rear-side carrier-selective contact layer uses the SiCx HSC from Embodiment 1 .

[0132] Embodiment s: Manufacturing Methods

[0133] Referring to Fig. 18A, the present invention also provides a method for manufacturing the above SiCx CSC. Specifically, this manufacturing method comprisesthe following steps:

[0134] S101 : Depositing at least one intrinsic amorphous silicon (i-aSi) layer 121 on a silicon wafer substrate.

[0135] Deposition method: PECVD with the processing parameters summarized in Table 6 below (these processing parameters are valid for various i-aSi layers).

[0136] Table. 6:

[0137] S103, Depositing at least one SiCx layer on the at least one i-aSi layer using a PECVD method.

[0138] Deposition method: PECVD with the processing parameters summarized in Table 7 below (these processing parameters are valid for various doped SiCx layers).

[0139] Table ?:

[0140] In some embodiments, the SiCx layer may be an N-type doped SiCx layer 126b, a P-type doped SiCx layer 126a, or an intrinsic SiCx layer.

[0141] In some embodiments, the total thickness of the deposited N-type doped SiCx layer 126b, P-type doped SiCx layer 126a, or intrinsic SiCx layer is between 2 and 80 nm. In some embodiments, the total thickness is between 2 and 50 nm, and preferably between 2 and 20 nm in some particular embodiments. Specifically, the thickness can be adjusted based on varying practical requirements.

[0142] S105, depositing at least one conductive film layer 500 on the at least oneSiCx layer using sputtering deposition method.

[0143] Deposition method for the formation of the TCF layer(s): sputtering deposition with the processing parameters summarized in Table 8 below (these processing parameters are valid for various TCF layers).

[0144] Table 8:

[0145] Referring to Fig. 18B, Fig. 18D and Fig. 18E, the present invention also provides another method for manufacturing a SiCx ESC. Specifically, this manufacturing method comprises the following steps:

[0146] S101 , Depositing at least one intrinsic amorphous silicon (i-aSi) layer 121 on a silicon wafer substrate.

[0147] S102a, Depositing at least one N-type doped amorphous silicon (aSi) layer125b on the at least one i-aSi layer 121 using the PECVD method.

[0148] Deposition method: PECVD method with the processing parameters summarized in Table 9 below (these processing parameters are valid for various doped aSi layers).

[0149] Table 9:

[0150] S103a: Depositing at least one N-type doped SiCx layer 126b on the at least one N-type doped aSi layer 125b using the PECVD method.

[0151] In some embodiments, the specific steps and parameters for depositing the N-type doped SiCx layer 126b in step S103a may refer to those described in step S103of the previous embodiments.

[0152] In some embodiments (see Fig. 18D and Fig. 18E), the at least one SiCx layer may be deposited on the entire upper surface of the at least one N-type doped aSi layer (i.e., fully covering this surface) or only on at least one designated local area of this upper surface (i.e., partially covering this surface).

[0153] S105: placing at least one TCF layer 500 on the at least one N-type dopedSiCx layer 126b using the sputtering method.

[0154] Referring to Fig. 18C, Fig. 18D and Fig. 18E, the present invention further provides a method for preparing a SiCx HSC. Specifically, this method comprises the following steps:

[0155] S101 , Depositing at least one intrinsic amorphous silicon (i-aSi) layer 121 on a silicon wafer substrate.

[0156] S102b, Depositing at least one P-type doped amorphous silicon (aSi) layer125a on the at least one i-aSi layer 121 using the PECVD method.

[0157] Deposition method: PECVD method with the processing parameters summarized in Table 10 below (these processing parameters are valid for various doped aSi layers).

[0158] Table 10:

[0159] S 103b, Depositing at least one P-type doped SiCx layer 126a on the at least one P-type doped aSi layer 125a using the PECVD method.

[0160] In some embodiments, the specific steps and parameters for depositing the P-type doped SiCx layer 126a in step S103b may refer to the detailed steps and parameters for step S103 in the previous embodiments.

[0161] In some embodiments, the at least one SiCx layer can be deposited to fully cover the upper surface of the at least one P-type doped aSi layer or, alternatively, to cover only a designated local area of this surface (i.e., partially covering this surface).

[0162] S105, placing at least one TCF layer 500 on the at least one P-type dopedSiCx layer 126a using the sputtering method.

[0163] As previously discussed, the SiCx layer has a higher bandgap compared to amorphous silicon (aSi). When applied directly to a solar cell structure in a traditional manner, this higher bandgap can increase the series resistance within the photovoltaic cell, thereby reducing solar cell performance. In the present invention, by adjusting features, properties, thicknesses, and process parameters for the doped SiCx layer, doped and intrinsic aSi layers, and the transparent conductive film (TCF) layer, the photovoltaic cell achieves a low series resistance. This configuration also supports a high pseudo-fill factor and potential improvements in short-circuit current density (Jsc), addressing the limitations of SiCx-based carrier-selective contacts (CSCs) and resulting in a high-performance SiCx CSC.

[0164] More specifically, in conventional heterojunction photovoltaic cells, the n-aSi layer is commonly used as the front contact layer. However, due to its lower bandgap, the n-aSi layer exhibits higher parasitic light absorption, which reduces the short-circuit current and thus impacts device efficiency. This additional optical loss in n-aSi-based CSCs limits the overall performance of current photovoltaic devices.

[0165] The present invention introduces the SiCx layer as the front window layer in place of the traditional n-aSi layer. With a higher bandgap than n-aSi, the SiCx layer reduces absorption losses, allowing the device to generate more current. As a result, device efficiency is enhanced, which can lower the cost per watt.

[0166] However, due to the SiCx layer’s higher bandgap relative to aSi, a work-function mismatch can occur between the SiCx layer and the adjacent layers, such as the TCF above and the intrinsic or doped aSi layer below in the photovoltaic cell structure. This work-function mismatch in conventional SiCx layers leads to increased series resistance in the photovoltaic cell, reducing the overall performance of solar cells.

[0167] Thus, in the present invention, adjusted features, properties, thicknesses, and process parameters for the doped SiCx, doped and intrinsic aSi layers, and the TCF layer mitigate this series resistance while achieving a high pseudo-fill factor and enhanced Jsc. Consequently, this invention overcomes previous challenges associated with SiCx-based CSCs and provides a high-performance SiCx CSC.

[0168] Referring to Fig. 19, the efficiency of the solar cell using the SiCx ESC 12d in this invention is comparable to the efficiency of a solar cell using the aSi ESC 12a.

[0169] Referring to Fig. 20, compared to conventional heterojunction (HJ) solar cells (see Fig. 30), the HJ cells using the SiCx ESC 12d as the electron-selective contact layer show a 1 .7% increase in pseudo-fill factor (PFF).

[0170] Referring to Fig. 21 , the fill factor (FF) of the solar cell based on the SiCx ESC 12d in this invention is similar to that of the solar cell based on the aSi ESC 12a.

[0171] Referring to Fig. 22, the series resistance (Rseries) of the solar cell using the SiCx ESC 12d in this invention is similar to that of the solar cell using the aSi ESC 12a.

[0172] Referring to Fig. 23, as the thickness of the SiCx layer or the underlying n-aSi layer increases, the solar cell efficiency (i.e., Efficiency Loss / Gain) gradually improves. Specifically, this is reflected in the following: with an increase in the thickness of the n- aSi layer, the short-circuit current (Jsc) shows little change, while the fill factor (FF) gradually increases, and the open-circuit voltage (Voc) also gradually increases.

[0173] Referring to Fig. 24, the thickness of the N-type doped SiCx layer (or P-type doped SiCx layer, or intrinsic SiCx layer) closest to the silicon wafer substrate (i.e., SiCx L1 Thk) affects the solar cell efficiency. Specifically, when the thickness of the SiCx layer L1 is 10 nm, there is a comparatively lower efficiency loss (i.e., efficiency loss / gain). In contrast, when the thickness is 13 nm or 6 nm, the efficiency loss becomes more pronounced.

[0174] Referring to Fig. 25, the thickness of the N-type doped SiCx layer (or P-type doped SiCx layer, or intrinsic SiCx layer) farthest from the silicon wafer substrate (i.e., SiCx L2 Thk) also affects the solar cell efficiency. Specifically, when the thickness of the SiCx layer L2 is 20 nm (based on testing of two batches with similar results), the efficiency loss is relatively lower compared to other thicknesses, such as 13 nm and 26 nm.

[0175] Referring to Fig. 26 and Fig. 27, using the formation of an N-type doped SiCx layer as an example, when the gas ratio of PH3to SiH4remains constant, an increase in carbon content (i.e., the gas ratio of CH4to SiH4) results in a gradual increase in the bandgap Eg . Conversely, when the carbon content (i.e., the gas ratio of CH4to SiH4) remains constant, an increase in the gas ratio of PH3to Si H4causes the bandgap Eg to trend downward.

[0176] Referring to Fig. 28 and Fig. 29, also using the formation of an N-type doped SiCx layer as an example, when the gas ratio of PH3to SiH4remains constant, an increase in carbon content (i.e., the gas ratio of CH4to SiH4) leads to a gradual increase in the extinction coefficient k. Conversely, when the carbon content (i.e., the gas ratio of CH4to SiH4) remains constant, an increase in the gas ratio of PH3to SiH4leads to a gradual decrease in the extinction coefficient k.

[0177] However, an increase in the bandgap Eg may result in higher series resistance Rseries in the photovoltaic cell, while an increase in the extinction coefficient k may lead to an increase in the short-circuit current Jsc of the photovoltaic cell. Therefore, in the present invention, to achieve photovoltaic cell efficiency, the gas ratios can be determined as follows: a gas ratio of PH3to SiH4between 0.5 and 10 (preferably 0.5 to 5 in some embodiments), and a gas ratio of CH4to SiH4between 0.05 and 10 (preferably 0.05 to 3 in some embodiments).

[0178] Other embodiments

[0179] According to various embodiments, the present invention discloses: (1 ) a novel carrier selective contact (CSC) structure that utilizes doped silicon carbide (SiCx) thin film layer(s) (Aspect #1); (2) a method to form a high performance SiCx-based CSC structure described in Aspect #1 (Aspect #2); (3) photovoltaic solar cells that comprise partially of the CSC structure described in Aspect #1 (Aspect #3); and (4) methods toform high performance photovoltaic solar cells utilizing in part the formation method for SiCx-based CSC structure of Aspect #2 (Aspect # 4).

[0180] According to the first Aspect (Aspect #1), the present invention discloses a SiCx-based CSC structure suitable for forming electron-selective (ESC) or hole- selective contacts (HSC) and comprises the following components: (a) one or more intrinsic amorphous silicon (i-aSi) layers, and (b) one or more (n- or p-) doped amorphous silicon layers (n-aSi or p-aSi) (optional), and (c) one or more (n- or p-) doped SiCx layers (n-SiCx or p-SiCx), and (d) one or more transparent conductive film (TCF) layers.

[0181] According to the second Aspect (Aspect #2), the present invention discloses a method of forming the CSC structure in Aspect #1 . The process sequence consists of deposition of one or more layers of i-aSi using plasma enhanced chemical vapour deposition (PECVD), followed by deposition of one or more layers of doped aSi using PECVD, followed by deposition of one or more layers of doped SiCx using PECVD, followed by deposition of one or more layers of TCF using magnetron sputtering.

[0182] According to the third Aspect (Aspect #3), the present invention discloses photovoltaic photovoltaic cells that utilize one or more of the SiCx-based CSCs (Aspect #1 ) are described. This invention is specifically for the use of CSCs for photovoltaic cells made using silicon wafer substrates and covers the use of only one or two SiCx CSCs in a photovoltaic cell. Where only one SiCx CSC is utilized, the CSC (Aspect #1) may be an SiCx ESC (n-SiCx based CSC) or SiCx HSC (p-SiCx based CSC). A photovoltaic cell may also contain both a SiCx ESC and a SiCx HSC CSC. Any CSC may be applied to either or both sides of the photovoltaic cell, may be applied to the entire surface of the one side or to some fraction thereof. A SiCx CSC may be in contact with electrodes or may contact other layers that comprise, for example, recombination layers or carrier selective layers of another photovoltaic cell placed above the silicon photovoltaic cell. Thus, the application of SiCx-based CSCs to a range of photovoltaic cell architectures is described including commercially relevant silicon heterojunction photovoltaic cells (both front-and-back contact photovoltaic cells and all-back contact photovoltaic cells) as well as tandem photovoltaic cells.

[0183] According to the fourth Aspect (Aspect #4), the present invention discloses a method of forming the photovoltaic cells described in Aspect #3 wherein the formationmethod of the SiCx CSC (Aspect #2) forms a part of the sequence of steps required to form the photovoltaic cell. The specific steps that may be applied before and after the formation of the CSC until the completion of the photovoltaic cell are described. An example process flow for making a front-and-back contact silicon heterojunction photovoltaic cell with a single SiCx CSC is shown as an example.

[0184] One embodiment of Aspect #1 (a SiCx ESC) formed using an embodiment of Aspect #2 and applied in an embodiment of Aspect #3 (a front-and-back contact silicon heterojunction photovoltaic cell with said SiCx ESC) that is fabricated via an embodiment of Aspect #4 is described. The photovoltaic cell so formed is shown to have high performance for important photovoltaic cell parameters.

[0185] In summary, the present invention introduces a novel approach that incorporates a silicon carbide (SiCx) layer in place of the conventional n-aSi layer. This SiCx layer provides several distinct technical advantages that enhance the efficiency and performance of photovoltaic cells.

[0186] Compared to aSi, SiCx has a higher bandgap width Eg (up to 3.4 eV), which means greater transparency. This increased transparency enables the solar cell to absorb more light, resulting in a higher short-circuit current Jsc and thus improved solar cell efficiency. However, the higher bandgap Eg of SiCx also implies lower conductivity, which can lead to higher series resistance Rseries in the solar cell (see Fig. 26). If conventional SiCx is applied directly to the solar cell structure in the conventional manner, a “work-function mismatch" may occur between the SiCx and the conductive film layer, as well as with the traditional intrinsic aSi layer (or doped aSi layer), thereby increasing the series resistance Rseries and ultimately reducing the overall performance of the solar cell based on the SiCx CSC. In other words, applying traditional SiCx directly to a solar cell, in the conventional way, may not necessarily improve the cell’s photoelectric conversion efficiency and might even reduce it. Therefore, it is crucial to find an effective way to leverage the high transparency of SiCx without negatively impacting the performance of the solar cell.

[0187] Doping can improve the conductivity of SiCx, thereby reducing the series resistance Rseries in the solar cell. However, doping also affects the bandgap width Eg and the extinction coefficient k of SiCx. A higher extinction coefficient k increases the short-circuit current Jsc of the solar cell. Therefore, balancing parameters such asRseries, bandgap width Eg , and extinction coefficient k (or short-circuit current Jsc, are required for achieving the effective application of SiCx in solar cells.

[0188] In the present invention, a front contact layer comprising at least one doped SiCx layer of specific thickness is used in contact with a conductive film layer (e.g., TCF layer). This SiCx layer operates synergistically with an intrinsic aSi layer (or a doped aSi layer of specific thickness) and the conductive film layer, resulting in a solar cell with low series resistance and high pseudo-fill factor (pFF) (see Fig. 20). Compared to conventional SiCx-based solar cells, the approach of the present invention the overall performance of solar cells and photovoltaic devices. Additionally, the solar cell in this invention has a greater potential for improving short-circuit current Jsc.

[0189] It should be further appreciated by the person skilled in the art that variations and combinations of features described above, not being alternatives or substitutes, may be combined to form yet further embodiments falling within the intended scope of the invention.

[0190] As would be understood by a person skilled in the art, each embodiment, may be used in combination with other embodiment or several embodiments.

[0191] Reference Numbers:11 : Silicon wafer substrate;12: SiCx-based CSC (SiCx CSC);12a: n-aSi ESC (aSi ESC);12b: p-SiCx-based HSC (SiCx HSC);12c: p-aSi HSC (aSi HSC);12d: n-SiCx-based ESC (SiCx ESC);121 : i-aSi layer(s);125: doped aSi layer(s);125a: p-doped aSi layer(s);125b: n-doped aSi layer(s);126: doped SiCx layer(s);126a: p-SiCx layer(s);126b: n-SiCx layer(s);13: additional CSC500: TCF layer(s);: Electrode; : other layer(s); a: Other layers for tandem photovoltaic cells.

Claims

Claims1. A SiCx-based carrier-selective contact layer, comprising: at least one i-aSi layer and at least one conductive film layer stacked sequentially; and a front contact layer arranged between the at least one i-aSi layer and the at least one conductive film layer; wherein the front contact layer comprises at least one SiCx layer; wherein the at least one SiCx layer is configured to be a P-type doped SiCx layer, an N-type doped SiCx layer, or an intrinsic SiCx layer; wherein total thickness of the at least one SiCx layer is 2-80 nm.

2. The SiCx-based carrier-selective contact layer according to claim 1 , further comprising: at least one doped aSi layer arranged between the at least one i-aSi layer and the front contact layer; wherein the at least one doped aSi layer is either N-type doped aSi layer or P- type doped aSi layer.

3. The SiCx-based carrier-selective contact layer according to claim 1 , wherein, the front contact layer comprises a single SiCx layer; and the single SiCx layer is configured to have a thickness of 1 .5 - 50 nm.

4. The SiCx-based carrier-selective contact layer according to claim 1 or 2, wherein, the front contact layer comprises two SiCx layers: an inner layer closer to the at least one i-aSi layer, and an outer layer farther from the at least one i-aSi layer; wherein the inner layer is configured to have a thickness of 1- 30 nm; and the outer layer is configured to have a thickness of 1-80 nm.

5. The SiCx-based carrier-selective contact layer according to claim 4, wherein, the inner layer is configured to have a thickness of 2-20 nm; and the outer layer is configured to have a thickness of 3-40 nm.

6. The SiCx-based carrier-selective contact layer according to claim 5, wherein, the inner layer is configured to have a thickness of 5-20 nm; and the outer layer is configured to have a thickness of 10-30 nm.

7. The SiCx-based carrier-selective contact layer according to claim 1 or 2, wherein, the front contact layer comprises three or more SiCx layers: an inner layer closest to the at least one i-aSi layer, an outer layer farthest from the at least one i-aSi layer, and at least one intermediate layer arranged between the inner layer and the outer layer; wherein the inner layer is configured to have a thickness of 0.5-30 nm; the outer layer is configured to have a thickness of 0.5-75 nm; the at least one intermediate layer is configured to have a total thickness of 1-80 nm.

8. The SiCx-based carrier-selective contact layer according to claim 7, wherein, the inner layer is configured to have a thickness of 1-20 nm; the outer layer is configured to have a thickness of 1 -40 nm; the at least one intermediate layer is configured to have a total thickness of 3-60 nm.

9. The SiCx-based carrier-selective contact layer according to claim 8, wherein, the inner layer is configured to have a thickness of 5-20 nm; the outer layer is configured to have a thickness of 5-40 nm; the at least one intermediate layer is configured to have a total thickness of 5-40 nm.

10. The SiCx-based carrier-selective contact layer according to claim 2, wherein the at least one doped aSi layer is configured to have a total thickness of 1-15 nm.11 . The SiCx-based carrier-selective contact layer according to claim 10, wherein, the at least one doped aSi layer is configured to be as a single layer, having a thickness of 1-12nm.

12. The SiCx-based carrier-selective contact layer according to claim 11 , wherein, the at least one doped aSi layer is configured to have a thickness of 2-7nm.

13. The SiCx-based carrier-selective contact layer according to claim 10, wherein, the at least one doped aSi layer is configured to be as a double layer, comprising an inner layer farther from the front contact layer and an outer layer closer to the front contact layer; wherein, the inner layer is configured to have a thickness of 1-5nm; and the outer layer is configured to have a thickness of 1-14nm.

14. The SiCx-based carrier-selective contact layer according to claim 13, wherein, the inner layer is configured to have a thickness of 2-5nm; and the outer layer is configured to have a thickness of 2-1 Onm.

15. The SiCx-based carrier-selective contact layer according to claim 10, wherein, the at least one doped aSi layer is configured as a multi-layer, comprising an inner layer farther from the front contact layer, an outer layer closer to the front contact layer, and at least one intermediate layer arranged between the inner layer and the outer layer; wherein the inner layer is configured to have a thickness of 1-5nm; the outer layer is configured to have a thickness of 1-1 Onm; and the at least one intermediate layer is configured to have a total thickness of 1-10nm.

16. The SiCx-based carrier-selective contact layer according to claim 15, wherein, the inner layer is configured to have a thickness of 2-5nm; the outer layer is configured to have a thickness of 2-7nm; and the at least one intermediate layer is configured to have a total thickness of 2-7nm.

17. A method for manufacturing SiCx-based carrier-selective contact layer, comprising the steps of:S101 depositing at least one i-aSi layer on a substrate;S103 based on preset deposition parameters, depositing at least one SiCx layer with a total thickness of 2-80 nm on the at least one i-aSi layer using a PECVD method; the SiCx layer is an N-type doped SiCx layer, a P-type doped SiCx layer, or an intrinsic SiCx layer;S105 depositing at least one conductive film layer on the at least one SiCx layer; wherein the preset deposition parameters comprises: a gas ratio of CH4to SiH4is 0.05-10; and a gas ratio of PH3to SiH4is 0.5-10.

18. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 17, wherein the at least one SiCx layer is configured to have a total thickness of 2-50 nm.

19. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 18, wherein the at least one SiCx layer is configured to have a total thickness of 2-20nm.

20. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 17, wherein the at least one SiCx layer is deposited on an upper surface of the at least one i-aSi layer, partially or entirely covering the upper surface of the at least one i-aSi layer.21 . The method for manufacturing SiCx-based carrier-selective contact layer according to any one of claims 17 to 20, wherein, prior to the step S103, the method further comprises the step of depositing at least one doped aSi layer on the at least one i-aSi layer; wherein the at least one doped aSi layer is either N-type doped aSi layer or P- type doped aSi layer; and the at least one doped aSi layer is configured to have a total thickness of 1-15 nm.

22. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 21 , wherein the at least one SiCx layer is deposited on an upper surface of the at least one doped aSi layer, partially or entirely covering the upper surface of the at least one doped aSi layer.

23. The method for manufacturing a SiCx-based carrier-selective contact layer according to claim 21 , wherein, the at least one doped aSi layer is configured as a single layer, having a thickness of 1-12 nm.

24. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 21 , wherein, if two N-type doped aSi layers are deposited, a first N-type doped aSi layer with a thickness of 1-14 nm and a second N-type doped aSi layer with a thickness of 1-14 nm are sequentially deposited on the at least one i-aSi layer; or, if two P-type doped aSi layers are deposited, a first P-type doped aSi layer with a thickness of 1-14 nm and a second P-type doped aSi layer with a thickness of 1-14 nm are sequentially deposited on the at least one i-aSi layer.

25. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 24, wherein, the first N-type doped aSi layer with a thickness of 1-5 nm and the second N-type doped aSi layer with a thickness of 1-14 nm are sequentially deposited on the at least one i-aSi layer; or,the first P-type doped aSi layer with a thickness of 1-5 nm and the second P-type doped aSi layer with a thickness of 1-14 nm are sequentially deposited on the at least one i-aSi layer.

26. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 25, wherein, the first N-type doped aSi layer with a thickness of 2-5 nm and the second N-type doped aSi layer with a thickness of 2-10 nm are sequentially deposited on the at least one i-aSi layer; or, the first P-type doped aSi layer with a thickness of 2-5 nm and the second P-type doped aSi layer with a thickness of 2-10 nm are sequentially deposited on the at least one i-aSi layer.

27. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 21 , wherein, if at least three N-type doped aSi layers are deposited, a first N-type doped aSi layerwith a thickness of 0.5-14 nm, at least one third N-type doped aSi layer with a total thickness of 1-14 nm, and a second N-type doped aSi layerwith a thickness of 0.5-14 nm are sequentially deposited on the at least one i-aSi layer; or, if at least three P-type doped aSi layers are deposited, a first P-type doped aSi layerwith a thickness of 0.5-14 nm, at least one third P-type doped aSi layerwith a total thickness of 1-14 nm, and a second P-type doped aSi layer with a thickness of 0.5-14 nm are sequentially deposited on the at least one i-aSi layer.

28. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 27, wherein, the first N-type doped aSi layer with a thickness of 1-5 nm, the at least one third N-type doped aSi layer with a total thickness of 1-10 nm, and the second N-type doped aSi layer with a thickness of 1-10 nm are sequentially deposited on the at least one i-aSi layer; or, the first P-type doped aSi layer with a thickness of 1-5 nm, the at least one third P-type doped aSi layer with a total thickness of 1-10 nm, and the second P-type doped aSi layer with a thickness of 1-10 nm are sequentially deposited on the at least one i-aSi layer.

29. The method for manufacturing SiCx-based carrier-selective contact layer according to claim 28, wherein, the first N-type doped aSi layer with a thickness of 2-5 nm, the at least one third N-type doped aSi layer with a total thickness of 2-7 nm, and the second N-type dopedaSi layer with a thickness of 2-7 nm are sequentially deposited on the at least one i-aSi layer; or, the first P-type doped aSi layer with a thickness of 2-5 nm, the at least one third P-type doped aSi layer with a total thickness of 2-7 nm, and the second P-type doped aSi layer with a thickness of 2-7 nm are sequentially deposited on the at least one i-aSi layer.

30. A photovoltaic cell, comprising a silicon wafer substrate with a front side and a back side; wherein at least one SiCx-based carrier-selective contact layer is placed on either the front side of the silicon wafer substrate, the back side of the silicon wafer substrate, or both; wherein the at least one SiCx-based carrier-selective contact layer is selected from any one of claims 1 - 16.31 . The photovoltaic cell according to claim 30, wherein, two SiCx-based carrier-selective contact layers are respectively placed on two spaced-apart local areas of the front side of the silicon wafer substrate, the back side of the silicon wafer substrate, or both.

32. The photovoltaic cell according to claim 30, wherein, the SiCx-based carrier-selective contact layer placed on the front side of the silicon wafer substrate is configured to partially or entirely cover a first surface of the front side of the silicon wafer substrate; or, the SiCx-based carrier-selective contact layer placed on the back side of the silicon wafer substrate is configured to partially or entirely cover a second surface of the back side of the silicon wafer substrate.

33. The photovoltaic cell according to claim 30, wherein, the photovoltaic cell is a tandem photovoltaic cell comprising a first photovoltaic cell unit and a second photovoltaic cell unit; and, wherein the first photovoltaic cell unit comprises a first SiCx-based carrier- selective contact layer placed on the front side of the first silicon wafer substrate; and the second photovoltaic cell unit comprises a second carrier-selective contact layer configured to be placed on the first SiCx-based carrier-selective contact layer.

34. The photovoltaic cell according to claim 33, wherein,the second carrier-selective contact layer is the SiCx-based carrier-selective contact layer according to any one of claims 1 - 16.

35. The photovoltaic cell according to claim 30, wherein, two SiCx-based carrier-selective contact layers placed on two spaced-apart local areas on either the front side of the silicon wafer substrate or the back side of the silicon wafer substrate; wherein the two SiCx-based carrier-selective contact layers comprise a P-type doped SiCx layer and a N-type doped SiCx layer.

36. The photovoltaic cell according to claim 30, wherein, a P-type doped SiCx layer is placed on one side of the silicon wafer substrate; and, a N-type doped SiCx layer is placed on opposite side of the silicon wafer substrate.

Images