Systems and methods of thin film thermoelectric device fabrication

Abstract

Disclosed herein are systems and methods for improving thin film thermoelectric fabrication and performance. A method for fabricating a thin film thermoelectric device includes coupling an n-type structure and a p-type structure to a first header. The method may also include positioning, by at least two force points, a first end and a second end of the n-type structure to the first header and positioning, by at least two force points, a first end and a second end of the p-type structure to the first header. The method may also include bonding the n-type structure and the p-type structure to the first header. The n-type or p-type structure contains epitaxially grown contact layers. For example, a p-type structure includes a p-type material sandwiched between two heavily doped p+ layers. Similarly, an n-type structure includes an n-type material sandwiched between two heavily doped n+ layers.

Description

SYSTEMS AND METHODS OF THIN FILM THERMOELECTRIC DEVICE FABRICATIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims benefit under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 63 / 599,441 filed on November 15, 2023 and U.S. Provisional Patent Application No. 63 / 599,436, filed on November 15, 2023, which are hereby incorporated by reference in their entireties.STATEMENT REGARDING FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT

[0002] This invention was made with Government support under Contract No. 21-C-0088 awarded by the National Reconnaissance Office. The Government has certain rights in the invention.FIELD

[0003] This disclosure relates generally to systems and methods of thin-film thermoelectric device fabrication.BACKGROUND

[0004] Thermoelectric devices utilize a thermoelectric effect to directly convert an electric power input into a temperature differential to generate a heating effect or cooling effect. This thermoelectric effect, referred to as the “Peltier effect,” is achieved by connecting together two different thermoelectric materials, one being a p-type material and the other being an n-type material, with a metal interconnect to form an electrical junction. Applying a voltage across the junction induces a current flow, thereby cooling at this junction (producing a cooling effect) while rejecting heat at the opposite end of the junction (producing a heating effect). The thermoelectric device could also turn a temperature differential into electric power, using the so-called Seebeck effect - this is complimentary to the Peltier effect - and the material properties and device requirementsare similar for both the cooling / heating with electrical power input and electrical power generation with an external heat-source generated temperature differential.SUMMARY

[0005] In some aspects, a method for fabricating a thin film thermoelectric device includes coupling an n-type structure and a p-type structure to a first header. The method may also include positioning, by at least two force points, a first end and a second end of the n-type structure to the first header and positioning, by at least two force points, a first end and a second end of the p-type structure to the first header. The method may also include bonding the n-type structure and the p-type structure to the first header.

[0006] In some aspects, a method for fabricating a thin film thermoelectric device includes forming a plurality of contact bumps on a header. The method may also include etching the plurality of contact bumps to remove an oxide layer and bonding one or more thermoelectric modules to the plurality of contact bumps.

[0007] In some aspects, a thermoelectric device comprises a header, an n-type material, and a p-type material. The n-type and p-type materials may be bonded to the header and have step heights that are less than 25 microns.BRIEF DESCRIPTION OF THE DRAWINGS / FIGURES

[0008] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the relevant art(s) to make and use aspects described herein.

[0009] FIG. 1 shows a thermoelectric device, according to some aspects.

[0010] FIG. 2 shows a method for fabrication, according to some aspects.

[0011] FIG. 3 shows a thermoelectric material, according to some aspects.

[0012] FIG. 4A and 4B show a schematic of thermoelectric element bonding, according to some aspects.

[0013] FIG. 5 shows a plot of device figure of merit versus etch time, according to some aspects.

[0014] FIG. 6A and 6B show a schematic of thermoelectric device positioning, according to some aspects.

[0015] FIG. 7 shows a method, according to some aspects.

[0016] FIGS. 8A, 8B, and 8C show exemplary test data of a 2 by 2 thermoelectric device, according to some aspects.

[0017] FIG. 9 shows a computer system, according to some aspects.

[0018] The features of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears. Unless otherwise indicated, the drawings provided throughout the disclosure should not be interpreted as to-scale drawings.DETAILED DESCRIPTION

[0019] The aspects described herein, and references in the specification to “one aspect,” “an aspect,” “an exemplary aspect,” “an example aspect,” etc., indicate that the aspects described can include a particular feature, structure, or characteristic, but every aspect may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same aspect. Further, when a particular feature, structure, or characteristic is described in connection with an aspect, it is understood that it is within the knowledge of those skilled in the art to effect such feature, structure, or characteristic in connection with other aspects whether or not explicitly described.

[0020] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “on,” “upper” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can likewise be interpreted accordingly.

[0021] The terms “about,” “approximately,” or the like can be used herein indicates the value of a given quantity that can vary based on a particular technology. Based on the particular technology, the terms “about,” “approximately,” or the like can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0022] Aspects of the present disclosure can be implemented in hardware, firmware, software, or any combination thereof. Aspects of the disclosure can also be implemented as instructions stored on a computer-readable medium, which can be read and executed by one or more processors. A machine-readable medium can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium can include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Furthermore, firmware, software, routines, and / or instructions can be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc. The term “machine-readable medium” can be interchangeable with similar terms, for example, “computer program product,” “computer-readable medium,” “non-transitory computer- readable medium,” or the like. The term “non-transitory” can be used herein to characterize one or more forms of computer readable media except for a transitory, propagating signal.Overview

[0023] Described herein are various embodiments of systems and methods for fabrication of thin film thermoelectric devices.

[0024] Thermoelectric devices may utilize a thermoelectric effect to directly convert an electric power input into a temperature differential to generate a heating effect or cooling effect. This thermoelectric effect, referred to as the “Peltier effect,” can be achieved by connecting together two different thermoelectric materials, one being a p-type material and the other being an n-type material, with a metal interconnect to form an electrical junction. Applying a voltage across the junction can induce a current flow, therebycooling at this junction (producing a cooling effect) while rejecting heat at the opposite end of the junction (producing a heating effect). The thermoelectric device may also turn a temperature differential into electric power, using the so-called Seebeck effect. This is complimentary to the Peltier effect - and the material properties and device requirements are similar for both the cooling / heating with electrical power input and electrical power generation with an external heat-source generated temperature differential.

[0025] In some aspects, thermoelectric devices may contain an array of p-n electrical junctions. These devices may be used for electronics cooling, air conditioning, refrigeration, thermal control, energy harvesting, or any combination thereof.

[0026] The performance of a thermoelectric device can be based on the energy conversion efficiency (for both heating and cooling) of the device’s thermoelectric material. This efficiency can be determined by the material’s “figure of merit” (ZT), a2T which can be defined by the following equation: ZT = — where a, T, p, and Kt are theSeebeck coefficient, absolute temperature, electrical resistivity, and total thermal conductivity, respectively.

[0027] In one embodiment, a method of improving ZT can include utilizing CHESS structures as the p-type and n-type materials. In some aspects, each of the thermoelectric structures can include a controlled hierarchical engineered superlattice structure (CHESS) structure or material. In some aspects, the thermoelectric structures can include p-type CHESS (P-CHESS) structures and n-type CHESS (N-CHESS) structures. In some aspects, the pair of thermoelectric structures can include one of the P-CHESS structures and one of the N-CHESS structures.

[0028] In some aspects, each of the P-CHESS structures can include a first CHESS material including first CHESS periods. In some aspects, each of the first CHESS periods may include a first p-type semiconductor material layer disposed adjacent to a second p- type semiconductor material layer. In some aspects, for each of the first CHESS periods, the first p-type semiconductor material layer can include p-type bismuth telluride (Bi2Tes), and the second p-type semiconductor material layer can include p-type antimony telluride (Sb2Te3) or a p-type bismuth antimonide alloy (BixSb2-x Tea). In some aspects, for each of the first CHESS periods, the first p-type semiconductor material layer can include a first periodic table Group V-VI, II- VI, or IV compound doped to form a second p-type semiconductor material, and the second p-type semiconductor materiallayer can include a second periodic table Group V-VI, II- VI, or IV compound doped to form a second p-type semiconductor material. As used herein, the term "semiconductor material" can include, but is not limited to, Bi2Te3, Sb2Te3, Sb2-xBixTe3, Bi, Sb, PbTe, PbSe, PbTei-xSex, PbS, PnSnTe, Si, Ge, SixGei-x, or any other suitable material or combination thereof.

[0029] In some aspects, each of the N-CHESS structures can include a second CHESS material including second CHESS periods. In some aspects, each of the second CHESS periods can include a first n-type semiconductor material layer disposed adjacent to a second n-type semiconductor material layer. In some aspects, for each of the second CHESS periods, the first n-type semiconductor material layer can include n-type Bi2Te3, and the second n-type semiconductor material layer can include n-type Bi2Se3 or n-type Bi2Te3-xSex. In some aspects, for each of the second CHESS periods, the first n-type semiconductor material layer can include a first periodic table Group V-VI, II- VI, or IV compound doped to form a first n-type semiconductor material, and the second n-type semiconductor material layer can include a second periodic table Group V-VI, II- VI, or IV compound doped to form a second n-type semiconductor material structure (CHESS) structure or material. As used herein, the term "semiconductor material" can include, but is not limited to, Bi2Te3, Bi2Se3,Bi2Te3-xSex, Bi, Sb, PbTe, PbSe, PbTei-xSex, PbS, PnSnTe, Si, Ge, SixGei-x, or any other suitable material or combination thereof. In some aspects, the thermoelectric structures can include p-type CHESS (P-CHESS) structures and n-type CHESS (N-CHESS) structures. In some aspects, the pair of thermoelectric structures can include one of the P-CHESS structures and one of the N-CHESS structures.

[0030] In some aspects, figure of merit (ZT) may also be improved though the implementation of novel thin-film thermoelectric device fabrication methods. In one example, doped contact layers may be epitaxially grown on either side of an n-type or p- type element. The doped contact layers may lower the contact resistivity between the n- type or p-type thermoelectric structure and metal contacts.

[0031] In another example, n-type or p-type elements are etched to remove defects that are formed between the original substrate on which an epitaxial film (e.g., n-type or p- type element) is grown and the epitaxial film. Etching times may be increased from about 60 seconds to about 120 seconds to better remove deep defects in an n-type thermoelectric structure.

[0032] In another example, force points can be used to hold n-type elements and p-type elements in place while the n- and p-type elements are bonded to a header. This may reduce bending and twisting of the n-type and p-type elements during bonding and lower step height to below about 25 microns.

[0033] In another example, a robotic system may automatically pick and place thermoelectric elements onto a header. This can improve speed and accuracy of thermoelectric device fabrication.

[0034] FIG. 1 shows a block diagram of an example thermoelectric device 100, according to some aspects. Thermoelectric device 100 may include a thermoelectric module 102 and a header 104, on which thermoelectric module 102 is disposed.

[0035] In some aspects, thermoelectric module 102 may include a p-type thermoelectric element 106, an n-type thermoelectric element 108, a metallization layer 110, and a header 112.

[0036] In some aspects, p-type thermoelectric element 106 may comprise a first surface that contains metallization layer 110. The first surface may be disposed on a bottom surface of header 112. P-type thermoelectric element 106 may also comprise an opposing second surface attached to a metal post 116. An ohmic contact may be established between metal post 116 and header 104 using, for example, an electrically conductive element 118 (e.g., a contact pad or solder bump). Electrically conductive element 118 may comprise a low-resistance ohmic material such as indium (In) or the like.

[0037] In one non-limiting aspect, p-type thermoelectric element 106 includes p-type Bi2Te / Sb2Te3 or Bi2Te3 / Sb2-xBixTe3 superlattice thermoelectric material, which facilitates improved carrier mobility.

[0038] In some aspects, n-type thermoelectric element 108 may similarly include a first surface containing metallization layer 110. The first surface may be disposed on a bottom surface of header 112. N-type thermoelectric element 108 may also include an opposing second surface comprising a metal post 117. An ohmic contact (e.g., another electrically conductive element 124) may be disposed between meatal post 117 and header 104.

[0039] In one non-limiting aspect, n-type thermoelectric element 108 may include n-type Bi2Te3 / Bi2Se3 or Bi2Te3 / Bi2SexTe3-x superlattice thermoelectric material, which facilitates improved carrier mobility.

[0040] In some aspects, p-type thermoelectric element 106 and n-type thermoelectric element 108 are each formed of a superlattice thermoelectric material, such as a CHESS structure. For example, p-type thermoelectric element 106 may include a p-type superlattice structure containing Bi2Te3 / Sb2Te3 and n-type thermoelectric element 108 may include an n-type superlattice structure including Bi2Te3 / Bi2Se3.

[0041] Although thermoelectric module 102 is depicted as having one p-type thermoelectric element 106 and one n-type thermoelectric element 108, it may be understood by a person of ordinary skill in the art that thermoelectric module 102 may contain two or more p-type thermoelectric elements 106 and two or more n-type thermoelectric elements 108 without departing from the scope of the aspects described herein.

[0042] In some aspects, header 104 may be formed from various thermally conductive materials, for example, aluminum nitride.

[0043] FIG. 2 shows a flowchart of a method 200, according to some aspects. Method 200 may describe steps for fabricating a thin-film thermoelectric device. It is to be appreciated that not all steps may be needed to perform the disclosure provided herein. Furthermore, some of the steps may be performed simultaneously or in a different order than the ones shown in FIG. 2, as will be understood by a person of ordinary skill in the art.

[0044] At 202, method 200 may include growing p-type and / or n-type thermoelectric materials on a parent substrate(s). The parent substrate may include a GaAs wafer, a Si wafer, a sapphire wafer, a germanium (Ge) wafer, or the like. Methods for growing the p- type and n-type thermoelectric materials may include metal-organic chemical vapor deposition and molecular beam epitaxy. In some aspects, the p-type and n-type thermoelectric materials may comprise epitaxially grown CHESS structures.

[0045] In one non-limiting example, heavily doped p-type or n-type contact layers are grown on the parent substrate(s) with the p-type or n-type thermoelectric material. This may improve electrical connections between the thermoelectric materials and metal layers, as described in FIG. 1. More details of growth of doped contact layers are described in reference to FIG. 3 below.

[0046] At 204, method 200 may include adding a metallization layer to the p-type and / or n-type materials. The metallization layer may provide an electrical contact between thethermoelectric materials and a first header. A material for the metallization layer may be chosen to achieve desired contact resistivities. For example, electroplated nickel (Ni) may provide favorable (low) contact resistivities for both P- and N- CHESS structures. The metallization layer may be added using lithography techniques.

[0047] At 206, method 200 may include cutting the n-type and p-type thermoelectric materials. The materials may be cut into individual n-type or p-type thermoelectric elements (e.g., 106 and 108 in FIG. 1).

[0048] In one non-limiting example, the n-type and p-type material may be cut into strips about 0.1-0.5 millimeters wide and about 1-2 inches long.

[0049] At 208, method 200 may include bonding at least one p-type thermoelectric element and at least one n-type thermoelectric element to a first header. The p-type and n- type thermoelectric elements may be bonded face down such that the metallization layer deposited at step 204 is in contact with the first header. Plated tin or tin preform material may be placed between the first header and the n-type and p-type elements to aid in the bonding.

[0050] In some aspects, a series of force points (e.g., pins) may hold the p-type and n- type elements in place. The positioning of the force points during bonding is described in detail in FIGS. 4 A and 4B.

[0051] At 210, method 200 may include removing the parent substrate (e.g., GaAs) from the p-type and n-type thermoelectric elements. Removing the parent substrate may leave a second side of the p-type and n-type elements exposed for further processing. In some aspects, the parent substrate is removed via etching, or the like.

[0052] At 212, method 200 may include etching the second side of the p-type and n-type thermoelectric elements. The second side of the p-type and n-type thermoelectric elements, which were previously attached to the parent substrate, may contain defects that negatively affect device performance (e.g., lower ZT). The etching may remove portions of the thermoelectric elements that contain these defects. In some aspects, the p-type and n-type thermoelectric elements may be etched for about 60-150 seconds.

[0053] At 214, method 200 may include adding metal contact posts to a second surface of the p-type and / or n-type materials. Metallization layers may be achieved through a patterned photoresist via lithography techniques. Metallizations can be achieved byelectroplating a contact like Ni / Cu / Au or through e-beam evaporation. The metal contact posts may connect to a second header.

[0054] At 216, method 200 may include etching contact bumps located on the second header. The contact bumps may comprise a metal, such as indium (In) or the like. Etching may remove an oxide layer along a top surface of the contact bump. This may improve bonding between the thermoelectric modules and the second header. In some aspects, the contact bumps are etched for about 5-10 seconds, for example in a mixture of 1 :5 or 1 : 10 = HC1:H2O. The contact bumps may be rinsed with deionized water after the etching.

[0055] At 218, method 200 may include bonding one or more thermoelectric modules to the second header. Each thermoelectric element in the one or more thermoelectric modules may be bonded to one or more of the contact bumps. For example, each of a p- type or n- type element in a thermoelectric module may be bonded to one, two, three, etc. contact bumps. A flux material, may be applied to the In contact bumps before bonding.

[0056] In some aspects, performance of thermoelectric devices may be enhanced by improving electrical contact between thermoelectric elements (i.e., p- and n-type materials) and metallic elements (e.g., contact pads, metallization layers, headers, etc.). In some aspects, electrical contacts may be improved by integrating contact layers during the growth of a thermoelectric element.

[0057] FIG. 3 shows a schematic of a thermoelectric element 300, according to some aspects. Thermoelectric element 300 may contain a thermoelectric material 302 (e.g., p- or n-type material) sandwiched between contact layers 304.

[0058] In some aspects, contact layers 304 may be configured to lower specific contact resistivities of thermoelectric element 300. For example, contact layers 304 may contain heavily doped p- or n-type materials (e.g., n-type Bi2Te3-xSexor p-type Sb2Te3).

[0059] In one non-limiting example, thermoelectric material 302 may comprise an N- CHESS or P-CHESS structure with an electron concentration around 1 X 1019to 3 X 1019cm3, and contact layers 304 may comprise an N+ doped material with an electron concentration around 6 X 1019to 1 X 102° cm3. This arrangement may yield a contact resistivity between about 2.5-7.5 x 10-7 Ohm / cm2.

[0060] Contact layers 304 may be epitaxially grown in sequence with thermoelectric material 302. For example, a contact layer 304 may be epitaxially grown on top of a buffer layer 306 disposed on a substrate 308. Then, thermoelectric material 302 may begrown on top of the contact layer. Then, a second contact layer is grown on top of thermoelectric material 302.

[0061] FIGS. 4A and 4B show schematics of thermoelectric module fabrication, according to some aspects. A thermoelectric module, as described in reference to FIG. 1, may comprise one or more p-type elements 402 and one or more n-type elements 404 coupled to a header 406. The p- and n-type elements may be bonded to header 406. When bonding, p-type elements 402 and n-type elements 404 can be held in place by force points (e.g., pins) 408. However, even with applied force, the p- and n- type elements may still swivel, rotate, and / or twist, which can increase a step height between the p- and n-type elements and the header. This may reduce accuracy in the final assembly of thermoelectric modules.

[0062] In some aspects, force points 408 may be positioned to reduce swiveling, rotating, and / or twisting during bonding. For example, in FIGS. 4A and 4B, two force points 408 are placed along the long axis of p-type element 402 and n-type element 404. The force points 408 are also staggered horizontally along a short axis of both the p- and n-type elements. This configuration may reduce step heights to less than about 25 microns, less than about 5 microns, or less than about 3 microns. The skewed pin arrangement described in FIGS. 4A and 4B may be scaled to an array of thermoelectric modules.

[0063] In some aspects, thermoelectric thin film device performance may also be improved by etching p-type and n-type thermoelectric elements after a parent substrate is removed, e.g., as described in step 212 of method 200. In some aspects, increased etching time is correlated with higher device ZT.

[0064] FIG. 5 shows a plot 500 of thermoelectric structure ZT versus buffer etch time, according to some aspects. Plot 500 may include an axis 502, which shows etch time in unit seconds, an axis 504, which shows average calculated ZT, and data 506, which plots average ZT as a function of time.

[0065] As shown in FIG. 5, longer etch times correlate to higher average ZT values and improved device performance. For example, an etch time of 90 seconds yields an average ZT of around 0.5, while an etch time of 110 seconds yields an average ZT of around 0.9. This may be due to an increased depth of defects and / or slow etch rate for n-type materials.

[0066] In some aspects, thermoelectric thin film device fabrication may also be improved through automatic alignment and placement of thermoelectric modules. This can speed up fabrication time and reduce human error.

[0067] FIG. 6A and 6B depict placement of a series of thermoelectric modules onto a common header according to some aspects.

[0068] FIG. 6A shows a schematic of a common header 600, according to some aspects. Header 600 may contain a plurality contact bumps 602. Contact bumps 602 may be comprised of a low resistance ohmic material, such as indium (In) or the like.

[0069] In some aspects, contact bumps 602 may be arranged in an array on the surface of header 600. For example, in FIG. 6A, contact bumps 602 are arranged in sub-arrays 604, each containing four contact bumps. The sub-arrays 604 are arranged in a larger 4 by 5 array. Other arrangements of contact bumps are possible, based on the knowledge of a person of ordinary skill in the art. In some aspects, the arrangement of contact bumps corresponds to the desired arrangement of thermoelectric modules.

[0070] FIG. 6B shows a schematic of thermoelectric module placement on a header, according to some aspects. In FIG. 6B, a series of thermoelectric modules 606 are positioned on header 600. Similar to thermoelectric modules 102 described in FIG. 1, thermoelectric modules 606 may each contain one or more p-type elements 605 and one or more n-type elements 607 bonded to a common header 608 (with a metallization layer in between). The second ends of each of the p-type and n-type elements may contain an ohmic metal post 609. In some aspects, the thermoelectric modules 606 are placed on header 600, such that the ohmic metal posts 609 are aligned and in contact with one or more contact bumps 602.

[0071] In some aspects, a robotic system 610 is configured to automatically position thermoelectric modules 606 on header 600. A processor in robotic system 610 may execute set of instructions. For example, the set of instructions may instruct the robotic arm to pick up a thermoelectric module 606 from a location and position it on a set of contact bumps 602. The robotic system may also include mechanisms designed to pick up thermoelectric modules 606, such as vacuum grippers, mechanical grippers, or the like.

[0072] In an alternative embodiment, p-type and n-type materials may be applied to header 600 before header 608 is added. Here, robotic system 610 may grab and positionone or more n-type elements / p-type elements 607 on header 600. Then header 608 is placed and bonded on top of the p-type and n-type elements.

[0073] FIG. 7 shows a flowchart of a method 700, according to some aspects. In some implementations, method 700 may be used for automatic assembly of thin film thermoelectric device arrays. It is to be appreciated that not all steps may be needed to perform the disclosure herein. Furthermore, some of the steps may be performed simultaneously or in a different order than the ones shown in FIG. 7, as will be understood by a person of ordinary skill in the art.

[0074] At 702, a robotic system may receive an image of a plurality of contact bumps positioned on a header, according to some aspects. A processor in the robotic system may analyze the image to determine heights and lateral positions of the contact pads.

[0075] At 704, the robotic system may receive a set of instructions, according to some aspects. The set of instructions may outline a series of steps for automatically picking and placing thermoelectric modules on a header. The heights and lateral positions of the contact bumps may be incorporated into the set of instructions.

[0076] At 706, the robotic system may apply flux to one or more contact pads, according to some aspects. During the applying, the robotic system may, in response to the received instructions, move the robotic arm towards the flux, pick up the flux, and position the flux on the one or more contact pads.

[0077] At 708, the robotic system may position a thermoelectric module on a header, according to some aspects. During the positioning, the robotic system may, in response to the received instructions, move the robotic arm towards the thermoelectric module, pick up the thermoelectric module, and position the thermoelectric module, such that each p- type element and each n-type element in the thermoelectric module is positioned on one or more contact bumps. To account for the thickness of the flux applied at 706, the target height coordinate of the thermoelectric material may be adjusted by about 30 microns. This may be accomplished by negative over travel of the robotic arm.

[0078] If additional thermoelectric modules need to be placed on the header, as outlined in the set of instructions, 706 and 708 may be repeated until all thermoelectric modules are placed on the header. Then, method 700 may end at 710.

[0079] Assembling thin film thermoelectric modules automatically using a robotic system may yield efficient and reliable devices. FIGS. 8 A, 8B, and 8C show exemplary test data of a 2 by 2 thermoelectric device, according to some aspects.

[0080] FIG. 8A shows device voltage output as a function of temperature difference across two sides of a thermoelectric device, according to some aspects. Axis 802 shows temperature difference in units Kelvin (K). Axis 804 shows open circuit thermoelectric voltage in unit volts (V). Data 806 shows results for a first test (circles), data 808 shows results for a second test (squares), data 810 shows results for a third test (diamonds), and data 812 shows results for a fourth test (triangles). The test data is consistent across the tests. As temperature difference increases, the output voltage increases.

[0081] FIG. 8B shows device power as a function of temperature difference across two sides of a device, according to some aspects. Axis 814 shows temperature difference in units Kelvin (K). Axis 816 shows power in unit milliwatts (mW). Data 818 shows results for a first test (circles), data 820 shows results for a second test (squares), data 822 shows results for a third test (diamonds), and data 824 shows results for a fourth test (triangles). As temperature difference increases, the output power increases. The test data is consistent across the four tests.

[0082] FIG. 8C shows estimated efficiency of a thermoelectric device as a function of temperature difference across two sides of a thermoelectric device, according to some aspects. Axis 826 shows temperature difference in units Kelvin (K). Axis 828 shows estimated efficiency as a percentage. Data 830 shows results for a first test (circles), data 832 shows results for a second test (squares), data 834 shows results for a third test (diamonds), and data 836 shows results for a fourth test (triangles). Here, measured efficiencies are consistent across the four tests. The estimated efficiencies of about 11% are higher than those obtainable in COTS bulk Bi2Te3 based modules (about 5%).

[0083] FIG. 9 illustrates an example computer system 900 useful for implementing various embodiments, such as those described in FIGS. 6B and 7.

[0084] Computer system 900 may include one or more processors (also called central processing units, or CPUs), such as a processor 904. Processor 904 may be connected to a communication infrastructure or bus 906.

[0085] Computer system 900 may also include user input / output device(s) 903, such as monitors, keyboards, pointing devices, etc., which may communicate with communication infrastructure 906 through user input / output interface(s) 902.

[0086] One or more of processors 904 may be a graphics processing unit (GPU). In an embodiment, a GPU may be a processor that is a specialized electronic circuit designed to process mathematically intensive applications. The GPU may have a parallel structure that is efficient for parallel processing of large blocks of data, such as mathematically intensive data common to computer graphics applications, images, videos, etc.

[0087] Computer system 900 may also include a main or primary memory 908, such as random access memory (RAM). Main memory 908 may include one or more levels of cache. Main memory 908 may have stored therein control logic (i.e., computer software) and / or data.

[0088] Computer system 900 may also include one or more secondary storage devices or memory 910. Secondary memory 910 may include, for example, a hard disk drive 912 and / or a removable storage device or drive 914. Removable storage drive 914 may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, tape backup device, and / or any other storage device / drive.

[0089] Removable storage drive 914 may interact with a removable storage unit 918. Removable storage unit 918 may include a computer usable or readable storage device having stored thereon computer software (control logic) and / or data. Removable storage unit 918 may be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, and / any other computer data storage device. Removable storage drive 914 may read from and / or write to removable storage unit 918.

[0090] Secondary memory 910 may include other means, devices, components, instrumentalities or other approaches for allowing computer programs and / or other instructions and / or data to be accessed by computer system 900. Such means, devices, components, instrumentalities or other approaches may include, for example, a removable storage unit 922 and an interface 920. Examples of the removable storage unit 922 and the interface 920 may include a program cartridge and cartridge interface (such as that found in video game devices), a removable memory chip (such as an EPROM or PROM) and associated socket, a memory stick and USB port, a memory card and associated memory card slot, and / or any other removable storage unit and associated interface.

[0091] Computer system 900 may further include a communication or network interface 924. Communication interface 924 may enable computer system 900 to communicate and interact with any combination of external devices, external networks, external entities, etc. (individually and collectively referenced by reference number 928). For example, communication interface 924 may allow computer system 900 to communicate with external or remote devices 928 over communications path 926, which may be wired and / or wireless (or a combination thereof), and which may include any combination of LANs, WANs, the Internet, etc. Control logic and / or data may be transmitted to and from computer system 900 via communication path 926.

[0092] Computer system 900 may also be any of a personal digital assistant (PDA), desktop workstation, laptop or notebook computer, netbook, tablet, smart phone, smart watch or other wearable, appliance, part of the Internet-of-Things, and / or embedded system, to name a few non-limiting examples, or any combination thereof.

[0093] Computer system 900 may be a client or server, accessing or hosting any applications and / or data through any delivery paradigm, including but not limited to remote or distributed cloud computing solutions; local or on-premises software (“onpremise” cloud-based solutions); “as a service” models (e.g., content as a service (CaaS), digital content as a service (DCaaS), software as a service (SaaS), managed software as a service (MSaaS), platform as a service (PaaS), desktop as a service (DaaS), framework as a service (FaaS), backend as a service (BaaS), mobile backend as a service (MBaaS), infrastructure as a service (laaS), etc.); and / or a hybrid model including any combination of the foregoing examples or other services or delivery paradigms.

[0094] Any applicable data structures, file formats, and schemas in computer system 900 may be derived from standards including but not limited to JavaScript Object Notation (JSON), Extensible Markup Language (XML), Yet Another Markup Language (YAML), Extensible Hypertext Markup Language (XHTML), Wireless Markup Language (WML), MessagePack, XML User Interface Language (XUL), or any other functionally similar representations alone or in combination. Alternatively, proprietary data structures, formats or schemas may be used, either exclusively or in combination with known or open standards.

[0095] In some embodiments, a tangible, non-transitory apparatus or article of manufacture comprising a tangible, non-transitory computer useable or readable mediumhaving control logic (software) stored thereon may also be referred to herein as a computer program product or program storage device. This includes, but is not limited to, computer system 900, main memory 908, secondary memory 910, and removable storage units 918 and 922, as well as tangible articles of manufacture embodying any combination of the foregoing. Such control logic, when executed by one or more data processing devices (such as computer system 900), may cause such data processing devices to operate as described herein.

[0096] The present invention has been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0097] The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and / or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0098] The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A method, comprising: coupling an n-type structure and a p-type structure to a first header; positioning, by at least two force points, a first end and a second end of the n-type structure to the first header, wherein a first force point of the at least two force points and a second force point of the at least two force points are staggered along a horizontal direction; positioning, by at least two force points, a first end and a second end of the p-type structure to the first header, wherein a first force point of the at least two force points and a second force point of the at least two force points are staggered along a horizontal direction; and bonding the n-type structure and the p-type structure to the first header.

2. The method of claim 1, wherein a step height of the n-type structure and a step height of the p-type structure are each less than about 25 microns.

3. The method of claim 1, further comprising: removing a parent substrate from a first surface of the p-type structure and a first surface of the n-type structure; and etching the first surface the p-type structure and the first surface of the n-type structure.

4. The method of claim 3, wherein the etching comprises: etching the first surface of the p-type structure for about 60 to 120 seconds to remove a defective layer due to epitaxial growth; and etching the first surface of the n-type structure for about 60 to 120 seconds to remove a defective layer due to epitaxial growth.

5. The method of claim 1, further comprising etching one or more contact bumps located on a second header.

6. The method of claim 1, further comprising: bonding a first surface of a portion of the p-type structure comprising Ohmic contact posts to a contact bump located on a second header, and bonding a first surface of a portion of the n-type structure comprising Ohmic contact posts to another contact bump located on the second header.

7. The method of claim 6, where the contact bump and the another contact bump comprise electroplated Indium with a thickness of about 5 to 40 microns.

8. The method of claim 1, wherein the n-type structure and the p-type structure are controlled hierarchically engineered superlattice structures (CHESS).

9. A method, comprising: forming a plurality of contact bumps on a header; etching the plurality of contact bumps to remove an oxide layer on the plurality of contact bumps; and bonding one or more thermoelectric modules to the plurality of contact bumps, the thermoelectric modules having p- and n- type areas bonded to two or more contact bumps in the plurality of contact bumps.

10. The method of claim 9, further comprising applying flux to the plurality of contact bumps.

11. The method of claim 9, further comprising positioning the one or more thermoelectric modules on the plurality of contact bumps using a robotic tool.

12. The method of claim 11, wherein the positioning comprises compensating for thickness variations of flux applied to the plurality of contact bumps through negative over-travel of the robotic tool.

13. The method of claim 9, further comprising imaging the plurality of contact bumps to determine position and height of the plurality of contact bumps on the header.

14. A device comprising: a header; a n-type material comprising a first surface that is bonded to the header; and a p-type material comprising a first surface that is bonded to the header, wherein the n-type material and the p-type material comprise step heights less than about 25 microns.

15. The device of claim 14, wherein a second surface of the n-type material and a second surface of the p-type material are each bonded to two or more contact bumps disposed on another header.

16. The device of claim 14, wherein the n-type material and the p-type material are controlled hierarchically engineered superlattice structures (CHESS).

17. The device of claim 14, further comprising: a first contact layer, disposed on the first surface of the n-type material; a second contact layer disposed on the second surface of the n-type material; a third contact layer, disposed on the first surface of the p-type material; and a fourth contact layer, disposed on the second surface of the p-type material, wherein the first and second contact layers are P+ materials, and wherein the third and fourth contact layers are N+ materials.

18. The device of claim 17 wherein the n-type material comprises doping in the range of 1 X 1019to 3 x 1019cm3and the third and fourth contact materials comprises doping between 6 x 1019to 1 x IO20cm3.

19. The device of claim 17, wherein the p-type material comprises doping in the range of 1 x 1019to 3 x 1019cm3and the first and second contact materials comprises doping between 6 x 1019to 1 x IO20cm3.

20. An array comprising at least two devices of claim 14.

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