Automatic recovery apparatus and method through undervoltage detection of physical layer device

Abstract

An automatic recovery method through undervoltage detection of a physical layer device according to an embodiment of the present invention comprises the steps of: updating the state of a link connected to a host device in at least one physical layer device connected to the host device; checking a link state register after updating the state of the link; determining whether the link state register has a valid value; determining whether the physical layer device has an undervoltage register if the state of the link is not a valid value; and initializing the physical layer device if the value of the undervoltage register is checked.

Description

Automatic recovery device and method through low voltage detection of physical layer device

[0001] The invention relates to an automatic recovery device and method through low voltage detection of a physical layer device.

[0002] Interconnects are widely used to facilitate communication between devices in a network. Generally speaking, electrical signals are transmitted by devices coupled to a physical medium (e.g., a bus, coaxial cable, or twisted pair or signal line).

[0003] According to the Open Systems Interconnection (OSI) model, Ethernet-based computer networking technologies use baseband transmission (i.e., electrical signals are discrete electrical pulses) to transmit data packets, and ultimately messages, between network devices. According to the OSI model, specialized circuitry called a physical layer (PHY) device or controller interfaces between the analog domain of the line and the digital domain of the data link layer, which operates on packet signaling. While the data link layer may include one or more sublayers, in Ethernet-based computer networking, the data link layer typically includes at least a media access control (MAC) layer, which provides a control abstraction of the physical layer. For example, when transmitting data to another device on the network, the MAC controller may prepare frames for the physical medium, add error correction elements, and implement collision avoidance. Furthermore, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare frames for higher layers.

[0004] There are various network topologies that implement physical and link layers (and, without limitation, can include other layers). The Peripheral Component Interconnect (PCI) standard and Parallel Advanced Technology Attachment (ATA) can implement multi-drop bus topologies. A trend since the early 2000s has been to use point-to-point bus topologies; for example, the PCI Express standard and the SATA (Serial ATA) standard implement point-to-point topologies.

[0005] A typical point-to-point bus topology may implement lines between each device (e.g., dedicated point-to-point) or may implement lines between devices and switches (e.g., without limitation, switched point-to-point). In a multi-drop topology, the physical medium is a shared bus, and each network device is coupled to the shared bus via circuitry selected based on the type of physical medium (e.g., without limitation, coaxial or twisted pair).

[0006] Point-to-point bus topologies, such as dedicated point-to-point or switched point-to-point topologies, require more wires and more expensive materials than multi-drop topologies, in part due to the greater number of links between devices. In certain applications, such as automotive, there may be physical constraints that make it difficult to directly connect devices, and topologies that do not require the same number or direct connections in the network or sub-network (e.g., without limitation, multi-drop topologies) may be less affected by such constraints.

[0007] Devices on a baseband network (e.g., an unrestricted, multi-drop network) share the same physical transmission medium and typically use the entire bandwidth of that medium for transmission (i.e., the digital signal used for baseband transmission occupies the entire bandwidth of the medium). Consequently, only one device on the baseband network can transmit at any given time. Therefore, medium access control methods are used to handle contention on the shared transmission medium.

[0008] When a host device and a physical layer device share a common power source within a computer system and the main voltage drops, the physical layer device becomes unable to recognize the host interface and the physical layer device becomes unable to operate. At this time, the host device is in a normal state, but the physical layer device becomes abnormal. In this case, the physical layer device becomes abnormal until the entire system is rebooted or reset. In addition, due to incorrect information transmitted by the physical layer device, the target device may recognize the connection as poor and recognize it as a link down problem.

[0009] Embodiments of the invention may provide an automatic recovery device and method when an abnormal voltage is detected in a physical layer device.

[0010] An embodiment of the invention can provide a device and method for recognizing when a physical layer device enters a failure and automatically restoring the physical layer device's function in the background.

[0011] A method for automatic recovery through low voltage detection of a physical layer device according to an embodiment of the invention may include, in at least one physical layer device connected to a host device, the steps of: updating a link status connected to the host device; checking a link status register after the link status update; determining whether the link status register has a valid value; if the link status is not a valid value, determining whether the physical layer device has a low voltage register; and if the value of the low voltage register is checked, initializing the physical layer device.

[0012] According to an embodiment of the invention, if the physical layer device does not have a low voltage register, a step of determining whether an initial data value is damaged may be included.

[0013] According to an embodiment of the invention, if the low voltage register value is not checked, the step of determining whether the initial data value is damaged and, if the initial data value is damaged, initializing the physical layer device may be included.

[0014] According to an embodiment of the invention, if the initial data value is in a normal state, a step of updating the link state can be performed.

[0015] According to an embodiment of the invention, if the link status register has a valid value, the step of linking up or linking down according to the valid value may be included.

[0016] An automatic recovery device through low voltage detection of a physical layer device according to an embodiment of the invention may include, in at least one physical layer device connected to a host device, a link status update unit for updating a link status connected to the host device; a link status detection unit for detecting a register of the updated link status; a link status recognition unit for recognizing a normal or abnormal link status by the link status register; a low voltage determination unit for checking an abnormal status in which the link status has a value of a low voltage register; and a failure recovery unit for initializing the physical layer device by the low voltage register value.

[0017] According to an embodiment of the invention, the fault recovery unit may include a fault recovery unit that initializes a physical layer device when an initial data value is damaged due to data loss.

[0018] According to an embodiment of the invention, the fault recovery unit can update the link status when there is no damage to the initial value in a state where the low voltage register is not registered or checked.

[0019] According to an embodiment of the invention, the physical layer device updates the link status in the background by the fault recovery unit, and the host device can recover itself in the background and synchronize with the physical layer device. The low voltage determination unit can confirm and provide an initial data value when the physical layer device does not have a low voltage register.

[0020] Embodiments of the invention enable a physical layer device to self-recover from an abnormal voltage drop, making it applicable to all systems having physical layer devices and enabling universal use. Furthermore, the self-recovery capability of the physical layer device allows it to be provided as an independent system.

[0021] According to an embodiment of the invention, when the entire system is reset, the user recognizes a failure and cannot use the product during the reboot period. However, when a failure occurs, the product can be used because the function can be automatically restored in the background within a short period of time. The invention can improve the reliability of mobile devices such as vehicles because the Ethernet interface chip (PHY Chip), i.e., the physical layer device, can self-recover from failures caused by abnormal voltage.

[0022] FIG. 1 is a block diagram showing an interface between a host device and a physical layer device according to an embodiment of the invention.

[0023] FIG. 2 is a flowchart illustrating an automatic recovery method through low voltage detection in the physical layer device of FIG. 1.

[0024] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which are shown by way of illustration specific exemplary embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized and structural, material, and process changes may be made without departing from the scope of the present disclosure.

[0025] The examples presented herein are not intended to be actual drawings of any particular method, system, device, or structure, but are merely idealized representations used to illustrate embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in various drawings may have the same or similar numbering for the convenience of the reader, but similarity in numbering does not necessarily imply that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0026] It will be readily appreciated that the components of the embodiments generally described herein and illustrated in the drawings may be arranged and designed in a wide variety of different configurations. Accordingly, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments.

[0027] The following description may include examples to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "exemplary," "by way of example," and "for example" means that the related description is illustrative, and although the scope of the present disclosure is intended to include examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0028] Accordingly, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure with unnecessary detail. Conversely, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Furthermore, the block definitions and the partitioning of logic between the various blocks are illustrative of specific implementations. It will be readily apparent to those skilled in the art that the present disclosure can be implemented with many other partitioning solutions. In most cases, details regarding timing considerations and the like have been omitted where such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the relevant art.

[0029] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referred to throughout this description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal for clarity of presentation and description. Those skilled in the art will appreciate that a signal may represent a bus of signals, where the bus may have various bit widths, and that the present disclosure may be implemented for any number of data signals, including a single data signal.

[0030] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. While a general-purpose computer that includes a processor is considered a special-purpose computer, a general-purpose computer is configured to execute computing instructions (e.g., software code) related to embodiments of the present disclosure.

[0031] It should also be noted that embodiments may be described in terms of processes depicted as flowcharts, flow diagrams, schematics, or block diagrams. While a flowchart may depict operational acts as a sequential process, many of these acts may be performed in other sequences, in parallel, or substantially simultaneously. Furthermore, the order of the acts may be rearranged. A process may correspond, without limitation, to a method, a thread, a function, a procedure, a subroutine, or a subprogram. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0032] In the disclosed embodiments, unless otherwise stated, a collision should be understood to refer to a logical collision (i.e., an actual collision is inferred / predicted, but signals from different nodes are not necessarily present on the shared transmission medium at the same time).

[0033] Protocols can be implemented at the physical layer for medium access tuning. For example, 10SPE (i.e., 10 Mbps Single Pair Ethernet) is a network technology specification currently under development by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE 802.3cg, and the 10SPE specification includes an optional PLCA arbitration sublayer that could theoretically be used to avoid collisions on a multi-drop bus. Other medium access tuning protocols, including time-aware protocols and traffic shaping protocols, can be implemented at the PHY. Generally speaking, one advantage of performing medium access tuning is that the MAC can still receive data after a collision is detected, since the received data that caused the collision should not be corrupted by the transmitted data. However, some legacy MACs assume that any collision is a real collision and are therefore configured to backoff and ignore any received data on the receive data line.

[0034]

[0035] FIG. 1 is a block diagram showing an interface between a host device and a physical layer device according to an embodiment of the invention, and FIG. 2 is a flowchart showing an automatic recovery method through low voltage detection in the physical layer device of FIG. 1.

[0036] Referring to FIGS. 1 and 2, the computer system includes a host device (15) and one or more physical (PHY) layer devices (20), and a power unit (30) supplies power required for each of the host device (10) and the physical layer devices (20). The host device (10) can receive and process requests from other computers or users, or be connected to a physical layer device (20) via a link and interface data to provide specific services, and functions as a network access device (NAD).

[0037] The above physical layer device (20) is a physical layer chip that communicates with the host device (10) and converts a digital network signal into an analog electrical signal within an Ethernet network system. The physical layer device (20) can function as a physical layer interface within another device. The network system may be, for example, a segment of a multi-drop network, a segment of a multi-drop sub-network, a multi-drop bus which is a segment of a mixed media network, or a combination or sub-combination thereof. As a non-limiting example, the network system can be, be a part of, or include one or more of a microcontroller-type embedded system, a user-type computer, a computer server, a laptop computer, a tablet, a handheld device, a mobile device, a wireless earbud or headphone device, a wired earbud or headphone device, an appliance sub-system, a lighting sub-system, a sound sub-system, a building control system, a home monitoring system (e.g., without limitation, for security or utility use), an elevator system or sub-system, a mass transit control system (e.g., without limitation, for aboveground trains, underground trains, trolleys, or buses), an automotive system or automotive sub-system, or an industrial control system.

[0038] The power supply unit (30) distributes and supplies the necessary power to the host device (10) and the physical layer device (20).

[0039]

[0040] When the physical layer device (20) communicates with the host device (10), if the main voltage of the link drops, the host device (10) may not be recognized and may enter an inoperable state. In this case, the entire system would have to be rebooted or reset, and during this time, the user would not be able to use the system properly. If the system cannot be used normally while driving a vehicle such as a mobile device, the accident rate may increase.

[0041] In an embodiment of the invention, even if the main voltage of the physical layer device (20) drops in the normal state of the host device (10), the physical layer device (20) can check for a low voltage state, and then recover itself in the background so that the host device (10) can recognize it and synchronize it. Specifically, the physical layer device (20) can include a link state update unit (21), a link state detection unit (22), a link state recognition unit (23), a low voltage (UV: Undervoltage) determination unit (24), and a fault recovery unit (25).

[0042] The above link status update unit (21) indicates changes in the physical connection status with the host device (10), i.e., updates the link status through an interface or link connected to the host device (10) (S21). The link status may be updated due to factors such as cable problems, hardware malfunctions, or network configuration changes, and such updates may be performed periodically, and the update cycle may be set according to a predetermined clock cycle.

[0043] The above link status detection unit (22) checks the status of the link detected by the link status detection unit (21) (S22), that is, determines it based on the value of the link status register (Reg: register). The link status register is one of the registers used in network equipment or chips, and is used to check and detect the status of the link, which is a physical connection of network equipment.

[0044] The above link status register indicates the up or down status of the link and determines the possibility of communication between the connected host device (10) and the physical layer device (20). This register can check whether the link is activated, whether the cable connection status is normal, and whether it is ready for data transmission, and is utilized as one of the tools for identifying and monitoring the link status in the operation and debugging of network devices.

[0045] The above link status register checks the link up or link down status due to the main voltage of the link connected to the host device (10) (S23). That is, the link status detection unit determines whether the link status is a valid value (0 or 1).

[0046]

[0047] The above link status recognition unit (23) recognizes the normal link up or down state (S24). At this time, if the link is in the up state (1: Link up), it is determined that data transmission is possible through the link, and if the link is in the down state (0: Link down), it is determined that data transmission is impossible through the link. When the link status recognition unit (23) is in the link up or down state, it recognizes that the link status is being read normally and that normal operation and communication between connected network devices are possible. Thereafter, the process proceeds to the step (S21) of updating the link status in the physical layer device (20) to determine the link status, and the above steps are repeated.

[0048]

[0049] If the link status recognition unit (23) recognizes that the link status is abnormal, a fault signal (Malfunction) is transmitted to the low voltage determination unit (24). Here, the control of the physical layer device (20) operates by transmitting commands from MDC (Management Data Clock) / MDIO (Management Data Input / Output). The MDC / MDIO is a serial bus for physical layer control and management in MAC, and can read and write the register of the physical layer device (20) and manipulate various functions of the physical layer device (20). When the MDIO value is read as 0xFFFF (value by the Pull Up circuit), it is recognized that the physical layer device (20) has entered a fault state. That is, 0xFFFF is a value in the pull-up circuit, all bits are set to 1, and this value represents a logical high voltage in the pull-up circuit. The pull-up circuit is a circuit that connects a signal line to a fixed voltage using an internal resistor.

[0050]

[0051] The above low voltage judgment unit (24) checks the low voltage register value (S26) when the physical layer device (20) has a low voltage register (UV Reg) (S25), and provides the initial data value (Init value check) when the physical layer device (20) does not have a low voltage register.

[0052] After determining whether the above low voltage register exists, the low voltage register value (UV resister value) is checked to review the status of the initial data value (S27). If the low voltage register value is checked, the physical layer device (20) is initialized (S28). If the low voltage register value is not checked, it is determined whether the initial data value is damaged (S27). That is, since there is a possibility of data loss, it is determined whether a low voltage has occurred based on a change in a specific initial value. If the initial data value is damaged, the physical layer device (20) is initialized (S28). If the initial data value is normal, it proceeds again to the link status update step (S21).

[0053] Here, among the physical layer devices (20), some devices may provide a low voltage (UV) entry point register or a similar register, which can be processed and used as data by the user. When determining whether the initial data value is damaged, if the physical layer device (20) does not provide a low voltage related register, it is determined whether a low voltage occurs due to damage to a specific value during initialization. In the case of the physical layer device (20), when power is re-applied, all existing register data values ​​are lost and initialized to the factory default values.

[0054] The above fault recovery unit (25) automatically recovers in the background when the physical layer device (20) is in an abnormal state such as low voltage, so that the user may not be aware of the system fault and there is no need for a waiting time due to rebooting.

[0055] In this way, when an abnormal voltage register is detected, the physical layer device (20) determines whether it is registered, and if a low voltage register is registered, it proceeds with normal initialization to recover. In addition, if the low voltage register is not registered and there is damage to the initial value, it proceeds with normal initialization to recover, and if the low voltage register is not registered and there is no damage to the initial data value, it proceeds to the link status update step in the background to perform automatic recovery. That is, the physical layer device (20) updates the abnormal link status in the background by the fault recovery unit (25). Therefore, when the host device (10) is in a normal state and the link is in an abnormal state such as a low voltage or a fault occurs, it automatically recovers its function in the background in a short time and synchronizes with the physical layer device (20). Accordingly, the problem that the user of the product cannot immediately recognize the fault status and cannot use the product during the reboot time can be solved.

Claims

1. For at least one physical layer device connected to the host device, A step of updating a link status connected to the above host device; After the above link status update, a step of checking the link status register; A step of determining whether the above link status register has a valid value; If the above link status is not a valid value, a step of determining whether the physical layer device has a low voltage register; and An automatic recovery method through low voltage detection of a physical layer device, comprising the step of initializing the physical layer device when the value of the above low voltage register is checked.

2. In paragraph 1, An automatic recovery method through low voltage detection of a physical layer device, comprising a step of determining whether an initial data value is damaged, when the physical layer device does not have a low voltage register.

3. In paragraph 2, A method for automatic recovery through low voltage detection of a physical layer device, comprising the steps of determining whether an initial data value is damaged if the above low voltage register value is not checked, and then initializing the physical layer device if the initial data value is damaged.

4. In paragraph 3, An automatic recovery method through low voltage detection of a physical layer device that performs a step of updating the link state when the above initial data value is normal.

5. In any one of paragraphs 1 to 4, An automatic recovery method through low voltage detection of a physical layer device, comprising the step of linking up or linking down depending on the valid value of the link status register if the above link status register has a valid value.

6. For at least one physical layer device connected to the host device, A link status update unit for updating a link status connected to the host device; A link status detection unit for detecting a register of the above updated link status; A link status recognition unit that recognizes the link status as normal or abnormal by the link status register; A low voltage judgment unit that checks for an abnormal state in which the above link status has a value of a low voltage register; and An automatic recovery device through low voltage detection of a physical layer device, including a fault recovery unit that initializes the physical layer device by the above low voltage register value.

7. In paragraph 6, The above fault recovery unit is an automatic recovery device through low voltage detection of a physical layer device including a fault recovery unit that initializes the physical layer device when the initial data value is damaged due to data loss.

8. In paragraph 7, The above fault recovery unit is an automatic recovery device through low voltage detection of a physical layer device that updates the link status when there is no damage to the initial value in a state where the above low voltage register is not registered or checked.

9. In paragraph 8, The above physical layer device updates the link status in the background by the above fault recovery unit, The above host device is an automatic recovery device through low voltage detection of the physical layer device that recovers itself in the background and synchronizes with the physical layer device.

10. In paragraph 9, The above low voltage judgment unit is an automatic recovery device through low voltage detection of a physical layer device that verifies and provides an initial data value when the physical layer device does not have a low voltage register.

Images