Array substrate, light-emitting substrate, backlight module, and display apparatus

Abstract

An array substrate. The array substrate comprises a substrate, a first conductive layer, at least one insulating layer, and a second conductive layer. The first conductive layer is arranged on one side of the substrate. The first conductive layer comprises a plurality of signal lines, and the plurality of signal lines comprise a plurality of device power lines. The at least one insulating layer is arranged on the side of the first conductive layer away from the substrate. The at least one insulating layer is provided with a first via penetrating through the at least one insulating layer. The second conductive layer is arranged on the side of the at least one insulating layer away from the substrate. The second conductive layer comprises a plurality of device conductive part groups and a plurality of chip conductive part groups. The device conductive part groups each comprise a plurality of first conductive parts arranged at intervals, and the device conductive part groups are configured to be connected to a light-emitting device. The chip conductive part groups each comprise a plurality of second conductive parts arranged at intervals, and the chip conductive part groups are configured to be connected to a microchip. The first conductive parts of the device conductive part groups are in electrical contact with the device power lines by means of the first via.

Description

Array substrate, light-emitting substrate, backlight module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a light-emitting substrate, a backlight module, and a display device. Background Art

[0002] With the development of light-emitting diode (LED) technology, backlight sources using submillimeter or even micron-scale light-emitting diodes (LEDs) have become widely used. This not only allows products using these backlights, such as liquid crystal displays (LCDs), to achieve contrast levels comparable to those of organic light-emitting diode (OLED) displays, but also allows these products to retain the technical advantages of LCDs, thereby improving display quality and providing users with a superior visual experience.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate includes a substrate, a first conductive layer, at least one insulating layer, and a second conductive layer. The first conductive layer is disposed on one side of the substrate. The first conductive layer includes multiple signal lines, including multiple device power lines. The at least one insulating layer is disposed on a side of the first conductive layer away from the substrate. The at least one insulating layer is provided with a first via extending through the at least one insulating layer. The second conductive layer is disposed on a side of the at least one insulating layer away from the substrate. The second conductive layer includes multiple device conductive portion groups and multiple chip conductive portion groups. The device conductive portion groups include multiple first conductive portions spaced apart and configured to connect to light-emitting devices. The chip conductive portion groups include multiple second conductive portions spaced apart and configured to connect to microchips. The first conductive portions of the device conductive portion groups are in electrical contact with the device power lines through the first vias.

[0005] In some embodiments, the array substrate includes multiple light-emitting units and multiple connecting lines, wherein the light-emitting units include multiple device conductive portion groups connected in series and / or in parallel, and the multiple device conductive portion groups in the same light-emitting unit are connected via the connecting lines. At least one of the connecting lines is located in the first conductive layer.

[0006] In some embodiments, the plurality of connecting lines include first-type connecting lines and second-type connecting lines, wherein the first-type connecting lines are staggered with orthographic projections of the plurality of signal lines on the substrate, and the second-type connecting lines at least partially overlap with orthographic projections of the plurality of signal lines on the substrate. All of the first-type connecting lines are located in the first conductive layer, and all of the second-type connecting lines are located in the second conductive layer.

[0007] In some embodiments, the plurality of signal lines further include a plurality of common voltage signal lines and a plurality of chip signal lines, the plurality of chip signal lines are divided into a plurality of chip signal line groups, and the plurality of chip signal lines in each chip signal line group are configured to connect to the same microchip.

[0008] The device power lines, the common voltage signal lines, and the chip signal lines all extend along a first direction. Along a second direction, each chip signal line group is located between two common voltage signal lines, and each common voltage signal line is located between the chip signal line group and the device power lines. The first direction intersects the second direction. The first-type connecting lines are located between adjacent device power lines and common voltage signal lines. And / or, the first-type connecting lines are located between adjacent common voltage signal lines and chip signal line groups.

[0009] In some embodiments, the light-emitting unit includes a first device conductive portion group, a second device conductive portion group, a third device conductive portion group, and a fourth device conductive portion group, the first device conductive portion group is connected to the device power line, and the fourth device conductive portion group is connected to the chip conductive portion group.

[0010] The plurality of connecting wires include a first connecting wire, a second connecting wire, and a third connecting wire. One end of the first connecting wire is connected to the first device conductive portion group, and the other end is connected to the second device conductive portion group. The first connecting wire is located in the first conductive layer. One end of the second connecting wire is connected to the second device conductive portion group, and the other end is connected to the third device conductive portion group. The second connecting wire is located in the second conductive layer. One end of the third connecting wire is connected to the third device conductive portion group, and the other end is connected to the fourth device conductive portion group. The third connecting wire is located in the first conductive layer.

[0011] In some embodiments, the device power line includes a main body, a first overlapping portion, and a second overlapping portion. The main body extends along a first direction. Along the second direction, at least one side of the main body is provided with a plurality of first openings and a plurality of second openings, and along the first direction, the plurality of first openings and the plurality of second openings are staggered one by one. The first direction intersects with the second direction. The first overlapping portion is connected to the main body and is located at the first opening. The second overlapping portion is connected to the main body and is located between adjacent first openings and second openings. The second overlapping portion includes a first sub-segment and a second sub-segment, the first sub-segment extends along the first direction, the second sub-segment extends along the second direction, and the first sub-segment is located on a side of the second sub-segment close to the adjacent first opening.

[0012] In some embodiments, the first sub-segment and the main body overlap at a boundary where they are close to each other. Alternatively, a gap exists between the first sub-segment and the main body, and the second overlapping portion further includes a third sub-segment, and the first sub-segment is connected to the main body via the third sub-segment.

[0013] In some embodiments, one end of the first sub-segment away from the second sub-segment is flush with a boundary of the first opening close to the second opening.

[0014] In some embodiments, the array substrate includes a plurality of light-emitting units arranged in an array along the first direction and the second direction. The light-emitting units include a plurality of device conductive portion groups connected in series and / or in parallel, the plurality of device conductive portion groups including a target device conductive portion group, the target device conductive portion group being a device conductive portion group among the plurality of device conductive portion groups that is in electrical contact with the device power line through the first via.

[0015] Along the first direction, of two adjacent light-emitting units, the first conductive portion of the target device conductive portion group of one light-emitting unit is electrically contacted with the first overlapping portion through the first via hole. The first conductive portion of the target device conductive portion group of the other light-emitting unit is electrically contacted with the second sub-segment through the first via hole.

[0016] In some embodiments, the plurality of signal lines further include a plurality of chip signal lines and a plurality of common voltage signal lines. The plurality of chip signal lines are divided into a plurality of chip signal line groups, and the plurality of chip signal lines in each chip signal line group are configured to connect to the same microchip. The device power line, the common voltage signal line, and the chip signal line all extend along a first direction. Along a second direction, each chip signal line group is located between two of the common voltage signal lines, and each common voltage signal line is located between the chip signal line group and the device power line. The first direction intersects the second direction.

[0017] The chip conductive portion group is located between two adjacent chip signal lines in the same chip signal line group. The at least one insulating layer is further provided with a second via and a third via that penetrate the at least one insulating layer. The array substrate further comprises a plurality of first adapter wires, the first adapter wires comprising a first routing segment and a second routing segment. The first routing segment is arranged in the first conductive layer and is located between the adjacent common voltage signal line and the chip signal line. The first conductive portion of the device conductive portion group is electrically contacted with the first routing segment through the second via. The second routing segment is arranged in the second conductive layer. One end of the second routing segment is electrically contacted with the first routing segment through the third via, and the other end crosses at least one chip signal line and is connected to the second conductive portion of the chip conductive portion group.

[0018] In some embodiments, the chip conductive portion group has a center line extending along the first direction, and a maximum distance between the third via and the center line is less than or equal to 2 mm.

[0019] In some embodiments, the at least one insulating layer is further provided with a fourth via and a fifth via that penetrate the at least one insulating layer. The array substrate further includes a plurality of second adapter wires and a plurality of third adapter wires. The plurality of second adapter wires are arranged on the second conductive layer. One end of the second adapter wire is connected to the chip signal line through the fourth via, and the other end is connected to the second conductive portion of the chip conductive portion group. The plurality of third adapter wires are arranged on the second conductive layer. One end of the third adapter wire is connected to the common voltage signal line through the fifth via, and the other end crosses at least one of the chip signal lines to connect to the second conductive portion of the chip conductive portion group.

[0020] In some embodiments, the second conductive layer further includes a third conductive portion, the array substrate further includes a first test line, the third conductive portion is connected to the signal line through the first test line, and at least one first test line is located in the first conductive layer.

[0021] In some embodiments, the array substrate includes multiple light-emitting units, multiple connecting lines, and multiple first adapter lines. The light-emitting units include multiple device conductive portion groups connected in series and / or in parallel. Multiple device conductive portion groups in the same light-emitting unit are connected via the connecting lines, and the light-emitting unit is connected to the chip conductive portion group via the first adapter line. The array substrate also includes a second test line, and the third conductive portion is connected to the connecting line or the first adapter line via the second test line. Furthermore, at least one second test line is located in the first conductive layer.

[0022] In some embodiments, the at least one insulating layer includes a first passivation layer, a first planarization layer, and a second passivation layer disposed in sequence, with the second passivation layer disposed on a side of the first planarization layer away from the first conductive layer. Furthermore, / or the array substrate further includes a third passivation layer disposed on a side of the second conductive layer away from the substrate.

[0023] In another aspect, a light-emitting substrate is provided. The light-emitting substrate includes an array substrate, a light-emitting device, and a microchip. The array substrate is any of the array substrates described in the above embodiments, the light-emitting device is connected to the device conductive portion group of the array substrate, and the microchip is connected to the chip conductive portion group of the array substrate.

[0024] In some embodiments, the light-emitting substrate further includes a first encapsulation portion, the first encapsulation portion covering the microchip. Furthermore, if the at least one insulating layer is provided with a third via hole and a fourth via hole penetrating the at least one insulating layer, the first encapsulation portion also covers the third via hole and the fourth via hole.

[0025] In another aspect, a backlight module is provided. The backlight module includes a light-emitting substrate as described in any of the above embodiments and a plurality of optical films. The light-emitting substrate has a light-emitting side and a non-light-emitting side opposite to each other, and the plurality of optical films are disposed on the light-emitting side of the light-emitting substrate.

[0026] In another aspect, a display device is provided, comprising the backlight module and a display panel as described in the above embodiment, wherein the display panel is disposed on a side of the plurality of optical films in the backlight module away from the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] FIG1 is a structural diagram of a display device according to some embodiments;

[0029] FIG2 is a structural diagram of another display device according to some embodiments;

[0030] FIG3 is a cross-sectional view of a display device according to some embodiments;

[0031] FIG4 is a top view of a light emitting substrate according to some embodiments;

[0032] FIG5 is a circuit diagram of a light emitting substrate according to some embodiments;

[0033] FIG6 is a wiring arrangement diagram of an array substrate according to some embodiments;

[0034] FIG7 is a cross-sectional view of an array substrate shown in FIG6 along section line AA;

[0035] 8, 9 and 10 are schematic diagrams showing different degrees of layering of connection traces in vias and device power lines in the related art;

[0036] FIG11 is a partial enlarged view of a portion C of an array substrate shown in FIG6 ;

[0037] FIG12 is a partial enlarged view of a portion D of an array substrate shown in FIG6 ;

[0038] FIG13 is a partial enlarged view of a portion D of another array substrate shown in FIG6 ;

[0039] FIG14 is a diagram showing the results of a reliability test of circuit traces located on the second conductive layer according to some embodiments;

[0040] FIG15 is a structural diagram of a device power line according to some embodiments;

[0041] FIG16 is a structural diagram of another device power supply line according to some embodiments;

[0042] FIG17 is a line graph showing the spacing between circuit traces in the first conductive layer of an array substrate and the thickness uniformity of the first conductive layer according to some embodiments;

[0043] FIG18 is a cross-sectional view of an array substrate shown in FIG6 along section line BB;

[0044] FIG19 is a wiring arrangement diagram of a light-emitting substrate according to some embodiments;

[0045] FIG20 is a partial enlarged view of a portion E of a light-emitting substrate shown in FIG19;

[0046] FIG21 is a partial enlarged view of a portion F of an array substrate shown in FIG6 ;

[0047] FIG22 is a partial enlarged view of a portion G of the array substrate shown in FIG6 . DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0049] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0050] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0051] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0052] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0055] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0058] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0059] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0060] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 1000 , which may be any device that displays an image, whether in motion (eg, video) or stationary (eg, still image), and whether textual or graphic.

[0062] For example, referring to FIG1 , the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, or the like.

[0063] For example, as shown in FIG1 , the display device 1000 may be a portable display product; for example, the display device 1000 may be the mobile phone shown in FIG1 . For another example, referring to FIG2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be the watch shown in FIG2 .

[0064] It should be noted that, depending on different application scenarios, the shape of the display surface of the display device 1000 is not unique. The shape of the display surface of the display device 1000 can be any one of circular, elliptical or polygonal, which is not specifically limited in the embodiments of the present disclosure.

[0065] In some embodiments, referring to FIG. 3 , the display device 1000 may be a liquid crystal display (LCD).

[0066] 3 , the display device 1000 includes a backlight module 100 , a display panel 200 and a cover plate 300 . The display panel 200 is disposed on a side of the backlight module 100 from which light is emitted, and the cover plate 300 is disposed on a side of the display panel 200 away from the backlight module 100 .

[0067] Referring to FIG3 , the backlight module 100 includes a light-emitting substrate 110 having a light-emitting side and a non-light-emitting side. The light-emitting side refers to the side of the light-emitting substrate 110 from which light is emitted (the upper side of the light-emitting substrate 110 in FIG3 ), i.e., the side from which light is emitted by the backlight module 100. The non-light-emitting side refers to the side opposite the light-emitting side (the lower side of the light-emitting substrate 110 in FIG3 ).

[0068] 3 , the backlight module 100 further includes a plurality of optical films 120 disposed on the light-emitting side of the light-emitting substrate 110 . The display panel 200 is disposed on a side of the optical films 120 away from the light-emitting substrate 110 .

[0069] The light emitted from the light-emitting substrate 110 passes through the optical film 120 and then is emitted toward the display panel 200. That is, the display panel 200 is disposed on the side of the optical film 120 that is away from the light-emitting substrate 110. It should be noted that the optical film 120 modulates the wavelength and / or propagation direction of the light emitted from the light-emitting substrate 110.

[0070] As shown in FIG3 , the light-emitting substrate 110 can directly emit white light, which is then modulated in its propagation direction after passing through the multiple optical films 120 and then emitted toward the display panel 200. Alternatively, the light-emitting substrate 110 can also emit light of other colors (e.g., blue light), which is then modulated in its wavelength and / or propagation direction after passing through the multiple optical films 120 and then emitted toward the display panel 200.

[0071] For example, referring to FIG3 , the plurality of optical films 120 include a scattering layer 121, a color conversion layer 122, a diffuser 123, and a composite film 124. The scattering layer 121, the color conversion layer 122, the diffuser 123, and the composite film 124 can be sequentially positioned away from the display panel 200. Specifically, the diffuser 123 can be positioned on the light-emitting side of the light-emitting substrate 110, the composite film 124 can be positioned on the side of the diffuser 123 away from the light-emitting substrate 110, the scattering layer 121 and the color conversion layer 122 can be positioned on the side of the diffuser 123 closer to the light-emitting substrate 110, and the display panel 200 can be positioned on the side of the composite film 124 away from the light-emitting substrate 110.

[0072] The scattering layer 121 blurs the light emitted by the light-emitting substrate 110 and provides support for the color conversion layer 122, the diffuser 123, and the composite film 124. The color conversion layer 122, when stimulated by light of a certain color emitted by the light-emitting substrate 110, converts that light into white light, thereby improving the utilization of the light energy of the light-emitting substrate 110. The diffuser 123 evens out the light passing through it. The composite film 124 improves the light extraction efficiency of the light-emitting substrate 110, thereby increasing the brightness of the display device 1000.

[0073] It should be noted that the composite film 124 may include a brightness enhancement film (BEF) and a dual brightness enhancement film (DBEF), which utilizes the principles of total reflection, refraction, and polarization to increase the light flux within a certain angle range to improve the brightness of the display device 1000.

[0074] For example, as shown in FIG3 , the light-emitting substrate 110 emits blue light. The color conversion layer 122 may include a red quantum dot material, a green quantum dot material, and a transparent material. When the blue light emitted by the light-emitting substrate 110 passes through the red quantum dot material, it is converted into red light; when the blue light passes through the green quantum dot material, it is converted into green light; the blue light can directly pass through the transparent material; then, the blue light, red light, and green light are mixed and superimposed in a certain proportion to present white light. Finally, the scattering layer 121 and the diffuser 123 can modulate the incident light of different propagation directions and emit it in a more uniform state, thereby improving the light shadow produced by the light-emitting substrate 110 and improving the display quality of the display device 1000.

[0075] In some embodiments, referring to FIG. 4 , the light-emitting substrate 110 has a light-emitting area A1 and a peripheral area A2 located on at least one side of the light-emitting area A1 .

[0076] The light emitting area A1 is configured to house electronic components 20, which may include, for example, light emitting devices 21 and / or microchips 22. The peripheral area A2 is configured to house a bonding circuit board, and may include, for example, a plurality of bonding pads P.

[0077] Exemplarily, referring to FIG. 3 and FIG. 4 , the light-emitting substrate 110 includes an array substrate 10 and an electronic component 20 . The electronic component 20 is disposed on the array substrate 10 and is located in the light-emitting area A1 .

[0078] 4 , the electronic component 20 may include a light emitting device 21 and / or a microchip 22 .

[0079] As shown in FIG4 , the light emitting device 21 may include a Micro LED and a Mini LED. The size (e.g., length) of the Micro LED is less than 50 μm, for example, 10 μm to 50 μm. The size (e.g., length) of the Mini LED is 50 μm to 150 μm, for example, 80 μm to 120 μm.

[0080] As shown in FIG4 , the microchip 22 may include a sensor chip and a driver chip. The sensor chip may be, for example, a photosensor chip or a thermal sensor chip, etc. The driver chip is used to provide a driving signal to the light emitting device 21 .

[0081] In some embodiments, as shown in FIG4 and FIG5 , the light-emitting substrate 110 includes a plurality of light-emitting units 210, and the plurality of light-emitting units 210 are arrayed in multiple rows and columns, each column includes a plurality of light-emitting units 210 arranged along a first direction X, and each row includes a plurality of light-emitting units 210 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0082] It should be noted that, herein, a plurality of light emitting units 210 arranged along the first direction X is referred to as a column of light emitting units 210 , and a plurality of light emitting units 210 arranged along the second direction Y is referred to as a row of light emitting units 210 .

[0083] Each light-emitting unit 210 includes multiple light-emitting devices 21 connected in series and / or in parallel. For example, as shown in FIG4 , each light-emitting unit 210 includes four light-emitting devices 21 connected in series. Of course, each light-emitting unit 210 may also include four, five, seven, or eight light-emitting devices 21, and the connection mode of the multiple light-emitting devices 21 in the light-emitting unit 210 is not limited to series connection; they may also be connected in parallel, but the embodiments of the present disclosure are not limited thereto.

[0084] The following takes an example in which a light-emitting unit 210 includes four light-emitting devices 21 connected in series to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

[0085] In addition, the microchip 22 can be a driver chip, for example, to drive the multiple light-emitting devices 21 to emit light. Here, one microchip 22 can only drive the multiple light-emitting devices 21 in one light-emitting unit 210 to emit light, or one microchip 22 can drive the multiple light-emitting devices 21 in multiple light-emitting units 210 to emit light.

[0086] For example, as shown in Figures 4 and 5, four light-emitting units 210 arranged adjacent to each other in two rows and two columns are electrically connected to the same microchip 22, and the microchip 22 is electrically connected to the four light-emitting units 210 respectively to drive multiple light-emitting devices 21 in the four light-emitting units 210 to emit light.

[0087] In some embodiments, as shown in FIG. 6 and FIG. 7 , the array substrate 10 includes a substrate 11 , a first conductive layer 30 , at least one insulating layer 40 , and a second conductive layer 50 .

[0088] As shown in FIG7 , substrate 11 may be a rigid substrate or a flexible substrate. The material of the rigid substrate includes at least one of glass, quartz, sapphire, ceramic, and polymethyl methacrylate (PMMA). The material of the flexible substrate includes at least one of epoxy resin, triazine, silicone resin, and polyimide.

[0089] As shown in FIG. 7 , the first conductive layer 30 is disposed on one side of the substrate 11 , the insulating layer 40 is disposed on the side of the first conductive layer 30 away from the substrate 11 , and the second conductive layer 50 is disposed on the side of the insulating layer 40 away from the substrate 11 .

[0090] It should be noted that the material of the first conductive layer 30 and the second conductive layer 50 includes at least one of copper, molybdenum-niobium alloy, nickel and indium tin oxide.

[0091] As shown in FIG7 , the at least one insulating layer 40 may include, for example, a first passivation layer 41, a first planar layer 42, and a second passivation layer 43 disposed in sequence, with the second passivation layer 43 disposed on a side of the first planar layer 42 away from the first conductive layer 30. That is, the first passivation layer 41 contacts the first conductive layer 30, and the second passivation layer 43 contacts the second conductive layer 50.

[0092] In addition, as shown in Figure 7, the array substrate 10 may also include a third passivation layer 44, a second flat layer 45 and a buffer layer 46, the third passivation layer 44 is arranged on the side of the second conductive layer 50 away from the substrate 11, the second flat layer 45 is arranged on the side of the third passivation layer 44 away from the substrate 11, and the buffer layer 46 is arranged between the substrate 11 and the first conductive layer 30.

[0093] It should be noted that the array substrate 10 may not include the second planar layer 45 and the buffer layer 46 , which is not specifically limited in the embodiment of the present disclosure.

[0094] The materials of the first passivation layer 41, the second passivation layer 43, the third passivation layer 44, and the buffer layer 46 may include at least one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, the materials of the first passivation layer 41, the second passivation layer 43, and the third passivation layer 44 all include silicon nitride.

[0095] The thickness of the first passivation layer 41, the second passivation layer 43 and the third passivation layer 44 is For example, the thickness of the first passivation layer 41 and the second passivation layer 43 is and The material of the first flat layer 42 includes resin. For example, the material of the first flat layer 42 includes epoxy resin.

[0096] The material of the first flat layer 42 and the second flat layer 45 includes a transparent resin. For example, the material of the first flat layer 42 and the second flat layer 45 includes epoxy resin.

[0097] The total thickness of the first and second planar layers 42, 45 is 4 μm to 10 μm. For example, the total thickness of the first and second planar layers 42, 45 is any one of 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm, 9.5 μm, and 10 μm. The thickness of the first and second planar layers 42, 45 can be designed based on actual conditions and is not specifically limited in the present disclosure.

[0098] In the related art, signal lines are arranged in the first conductive layer 30', and connection lines 51' are arranged in the second conductive layer 50'. The light-emitting devices and microchips are connected to the corresponding signal lines through the connection lines 51', and multiple light-emitting devices in the same light-emitting unit are connected through the connection lines 51'.

[0099] The signal line includes the device power line 31', and the light-emitting device is connected to the device power line 31' via a connecting trace 51'. The connecting trace 51' needs to pass through a via hole penetrating the insulating layer 40' to connect to the device power line 31'. However, delamination can easily occur between the connecting trace 51' and the device power line 31' within the via hole, as shown in Figures 8, 9, and 10. This results in poor overlap between the connecting trace 51' and the device power line 31', and low product yield.

[0100] Based on this, as shown in Figures 6 and 7, in the array substrate 10 provided in some embodiments of the present disclosure, the first conductive layer 30 includes multiple signal lines 310, and the second conductive layer 50 includes multiple device conductive part groups 510 and multiple chip conductive part groups 520.

[0101] As shown in FIG. 3 and FIG. 6 , the device conductive portion group 510 includes a plurality of first conductive portions 511 arranged at intervals, and the device conductive portion group 510 is configured to connect the light emitting device 21 .

[0102] For example, as shown in Figures 3 and 11, the device conductive portion group 510 includes two first conductive portions 511, which are respectively an anode conductive portion 512 and a cathode conductive portion 513. The two pins 12 of the light-emitting device 21 can be soldered to the two first conductive portions 511 of the device conductive portion group 510 to be fixed to the array substrate 10. Here, the solder can include tin, for example.

[0103] It should be noted that the number of the first conductive parts 511 of the device conductive part group 510 can be designed according to the number of pins of the light-emitting device 21. The number of the first conductive parts 511 of the device conductive part group 510 can also be 3, 4 or 6, etc., but the embodiments of the present disclosure are not limited to this.

[0104] As shown in FIG. 3 and FIG. 6 , the chip conductive portion group 520 includes a plurality of second conductive portions 521 arranged at intervals, and the chip conductive portion group 520 is configured to connect to the microchip 22 .

[0105] 3 , 12 , and 13 , the chip conductive portion group 520 may include 12 second conductive portions 521. The 12 pins 12 of the microchip 22 may be soldered to the 12 second conductive portions 521 of the chip conductive portion group 520 to be fixed to the array substrate 10. The solder may include tin, for example.

[0106] For example, referring to FIG5 , FIG12 and FIG13 , the chip conductive portion group 520 includes one clock conductive portion CLKP1 , one clock relay conductive portion CLKP2 , one address conductive portion Di_in, one address relay conductive portion Di_out, one chip power conductive portion VCCP, three ground conductive portions GNDP and four output conductive portions OutP.

[0107] It should be noted that the number of the second conductive parts 521 of the chip conductive part group 520 can be designed according to the number of pins of the microchip 22. The number of the second conductive parts 521 of the chip conductive part group 520 can also be 8, 10 or 14, etc., but the embodiments of the present disclosure are not limited thereto.

[0108] Some embodiments of the present disclosure are schematically described below by taking an example in which the device conductive portion group 510 includes two first conductive portions 511 and the chip conductive portion group 520 includes twelve second conductive portions 521 , but the embodiments of the present disclosure are not limited thereto.

[0109] As shown in FIG4 , a plurality of signal lines 310 are connected to a plurality of bonding pads P to receive at least one of lighting signals such as device power signals, chip power signals, address signals, clock signals, and common voltage signals from a circuit board.

[0110] For example, referring to Figures 5 and 6, the multiple signal lines 310 may include multiple device power lines 311, multiple common voltage signal lines 312 and multiple chip signal lines 313, and the multiple chip signal lines 313 are divided into multiple chip signal line groups 3130. The multiple chip signal lines 313 in each chip signal line group 3130 are configured to connect to the same microchip 22.

[0111] The multiple chip signal lines 313 of each chip signal line group 3130 may include a chip power signal 314, an address signal line 315, and a clock signal line 316. The common voltage signal line 312 is connected to the ground conductive portion GNDP of the chip conductive portion group 520 to provide a common voltage signal, such as a ground signal, to the microchip 22. The address signal line 315 is connected to the address conductive portion Di_in and the address relay conductive portion Di_out of the chip conductive portion group 520 to provide an address signal to the microchip 22. The clock signal line 316 is connected to the clock conductive portion CLKP1 and the clock relay conductive portion CLKP2 of the chip conductive portion group 520 to provide a clock signal to the microchip 22.

[0112] On this basis, as shown in Figures 5 and 6 , the multiple chip signal lines 313 of each chip signal line group 3130 may further include electromagnetic shielding signal lines 317. These electromagnetic shielding signal lines 317 are provided between the chip power signal line 314 and the address signal line 315, and between the address signal line 315 and the clock signal line 316, to provide electromagnetic shielding and improve the anti-interference capability of signal transmission. The electromagnetic shielding signal lines 317 may be connected to the common voltage signal line 312 to simplify the circuit structure.

[0113] In some embodiments, as shown in FIG5 and FIG6 , the device power lines 311 , the common voltage signal lines 312 , and the chip signal lines 313 all extend along a first direction X. Along a second direction Y, each chip signal line group 3130 is located between two common voltage signal lines 312 , and each common voltage signal line 312 is located between a chip signal line group 3130 and a device power line 311 .

[0114] A device power line 311 can be connected to the first conductive portion 511 (anode conductive portion 512) of the device conductive portion group 510 of a column of light-emitting units 210 to provide power signals to all light-emitting devices 21 in the light-emitting units 210. Furthermore, referring to FIG7 , the insulating layer 40 is provided with a first via H1 penetrating the insulating layer 40. The first conductive portion 511 (anode conductive portion 512) of the device conductive portion group 510 can be electrically contacted with the device power line 311 through the first via H1.

[0115] In this case, the first conductive portion 511 of the device conductive portion group 510 is in direct electrical contact with the device power line 311 through the first via H1, which is located below the first conductive portion 511. This improves the delamination between the first conductive portion 511 and the device power line 311 within the first via H1 due to the gravity of the light-emitting device 21 and the extrusion during the die-bonding process, reducing the risk of poor connection between the first conductive portion 511 and the device power line 311, and improving product yield.

[0116] FIG. 14 is a diagram showing the results of a reliability test of circuit traces located on the second conductive layer according to some embodiments.

[0117] As shown in FIG14 , when the thickness of the third passivation layer 44 is When the thickness of the second planar layer is 3 μm, the portion of the circuit trace located in the second conductive layer 50 located inside the via hole will corrode within 168 h, and the portion outside the via hole will corrode within 288 h.

[0118] As shown in FIG14 , when the thickness of the third passivation layer 44 is When the thickness of the second planar layer is 3 μm, the circuit traces in the second conductive layer 50 will be corroded at a portion located inside the via hole at 504 h, and at a portion located outside the via hole at 750 h.

[0119] As shown in FIG14 , when the thickness of the third passivation layer 44 is When the thickness of the second planar layer is 3 μm, the portion of the circuit trace located in the second conductive layer 50 located inside the via hole will corrode at 504 h, and the portion outside the via hole will corrode at 1000 h.

[0120] As shown in FIG14 , when the thickness of the third passivation layer 44 is When the thickness of the second planar layer is 4 μm, the portion of the circuit trace located in the second conductive layer 50 located inside the via hole will corrode within 750 h, and the portion outside the via hole will corrode within 1000 h.

[0121] Based on the above, it can be seen that the greater the thickness of the passivation layer and / or flat layer on the upper side of the circuit trace, the better the corrosion resistance of the circuit trace and the lower the risk of disconnection due to corrosion. Based on this, the connection between the device power line 311 and the first conductive part 511 of the device conductive part group 510 does not need to be arranged on the second conductive layer 50. This is equivalent to transferring the connection line connecting the light-emitting device 21 and the device power line 311 in the related art to the first conductive layer 30. In this way, the connection trace is also covered with an insulating layer 40. For example, the connection trace is also covered with a first passivation layer 41, a first flat layer 42 and a second passivation layer 43, that is, the thickness of the passivation layer and / or flat layer covering the connection trace is increased, thereby improving the corrosion resistance of the connection trace, reducing the risk of disconnection due to corrosion of the connection trace, and improving product yield.

[0122] Exemplarily, as shown in FIG. 15 and FIG. 16 , the device power line 311 includes a main body portion 3110 , a first overlapping portion 3111 and a second overlapping portion 3112 , and the first overlapping portion 3111 and the second overlapping portion 3112 are both connected to the main body portion 3110 .

[0123] As shown in Figures 15 and 16 , the main body 3110 extends along a first direction X and is connected to the bonding pad P. The main body 3110 may be, for example, in the shape of a straight bar. Along the second direction Y, at least one side of the main body 3110 is provided with a plurality of first openings 301 and a plurality of second openings 302 . The plurality of first openings 301 and the plurality of second openings 302 are arranged alternately along the first direction X.

[0124] 6 , 16 , and 17 , the first opening 301 and the second opening 302 can both be provided with corresponding light-emitting devices 21, that is, device conductive portion groups 510 can be provided. For example, the light-emitting unit 210 includes a first device conductive portion group 501, a second device conductive portion group 502, a third device conductive portion group 503, and a fourth device conductive portion group 504 connected in series, wherein the first device conductive portion group 501 is connected to the device power line 311, and the fourth device conductive portion group 504 is connected to the chip conductive portion group 520. In this case, along the first direction X, of two adjacent light-emitting units 210, the first device conductive portion group 501 of one light-emitting unit 210 can be provided at the first opening 301, and the second device conductive portion group 502 of the other light-emitting unit 210 can be provided at the second opening 302.

[0125] On this basis, the first overlapping portion 3111 may be a portion protruding from the first opening 301 of the main body 3110 , and the second overlapping portion 3112 may be a portion protruding from the outside of the straight bar-shaped main body 3110 .

[0126] As shown in Figures 6, 15, and 16, the first overlapping portion 3111 is provided in the first opening 301 and can be connected to one device conductive portion group 510. As shown in Figure 15, the first overlapping portion 3111 can be connected to a boundary of the first opening 301 away from the second overlapping portion 3112. As shown in Figure 16, the first overlapping portion 3111 can also be spaced a distance from a boundary of the first opening 301 away from the second overlapping portion 3112. This is not specifically limited in the present embodiment.

[0127] As shown in Figures 6, 15, and 16, the second overlapping portion 3112 is disposed between adjacent first openings 301 and second openings 302. The second overlapping portion 3112 includes a first subsegment 3113 and a second subsegment 3114. The first subsegment 3113 extends along a first direction X, and the second subsegment 3114 extends along a second direction Y. The first subsegment 3113 is located on a side of the second subsegment 3114 that is closer to the adjacent first opening 301. The second subsegment 3114 of the second overlapping portion 3112 can be connected to one device conductive portion group 510.

[0128] For example, referring to Figures 6, 11, and 16, along the first direction X, of two adjacent light-emitting units 210, the first conductive portion 511 of the target device conductive portion group M of one light-emitting unit 210 is electrically connected to the first overlapping portion 3111 through the first via H1. The first conductive portion 511 of the target device conductive portion group M of the other light-emitting unit 210 is electrically connected to the second sub-segment 3114 through the first via H1.

[0129] The target device conductive portion group M is the device conductive portion group 510 that is electrically connected to the device power line 311 through the first via H1 among the multiple device conductive portion groups 510. For example, the light-emitting unit 210 includes a first device conductive portion group 501, a second device conductive portion group 502, a third device conductive portion group 503, and a fourth device conductive portion group 504 that are sequentially connected in series, and the target device conductive portion group M is the first device conductive portion group 501.

[0130] Figure 17 is a line graph showing the spacing between circuit traces in the first conductive layer of an array substrate and the thickness uniformity of the first conductive layer according to some embodiments. As shown in Figure 17 , the smaller the spacing between circuit traces in the first conductive layer 30, the better the thickness uniformity of the first conductive layer 30.

[0131] Based on this, the first sub-segment 3113 is arranged between the device power line 311 and the common voltage signal line 312. In the process of preparing the first conductive layer 30 using an electroplating process, it is equivalent to dividing the larger etching gap between the device power line 311 and the common voltage signal line 312 into two smaller etching gaps. The two smaller etching gaps are the etching gap between the device power line 311 and the first sub-segment 3113, and the etching gap between the common voltage signal line 312 and the first sub-segment 3113, thereby shortening the spacing between adjacent circuit lines.

[0132] At this time, when using an electroplating process to form various traces located on the first conductive layer 30 with a relatively large thickness (for example, greater than or equal to 2 μm), the first sub-segment 3113 can serve as a companion plating process, thereby ensuring a high degree of thickness uniformity between the device power line 311 and the first sub-segment 3113, and also ensuring a high degree of thickness uniformity between the first sub-segment 3113 and the common voltage signal line 312, thereby compensating for the thickness difference between the device power line 311 and the first sub-segment 3113 and improving the thickness uniformity of the first conductive layer 30. Furthermore, providing the first sub-segment 3113 can also reduce the etching time required for patterning the first conductive layer 30, reduce the consumption of etching solution, and reduce costs.

[0133] 15 and 16 , the end of the first sub-segment 3113 away from the second sub-segment 3114 can be flush with the boundary of the first opening 301 near the second opening 302. In this way, the length of the first sub-segment 3113 in the first direction X can be set longer, which can provide better compensation and accompanying plating, further facilitating improved thickness uniformity of the first conductive layer 30, and further reducing the etching time required for patterning the first conductive layer 30, thereby reducing etching solution consumption and lowering costs.

[0134] In some embodiments, referring to FIG. 15 , the first subsegment 3113 can be directly connected to the main body 3110. For example, the first subsegment 3113 and the main body 3110 overlap at their respective adjacent boundaries. This eliminates any gap between the first subsegment 3113 and the main body 3110. This improves the thickness uniformity of the first conductive layer 30 when using an electroplating process to fabricate traces having a relatively large thickness (e.g., greater than or equal to 2 μm) on the first conductive layer 30. This also reduces the difficulty of patterning the first conductive layer 30 through etching, further reducing production costs.

[0135] In other embodiments, referring to FIG16 , a gap is defined between the first sub-segment 3113 and the main body 3110, and the second overlapping portion 3112 further includes a third sub-segment 3115, connecting the first sub-segment 3113 to the main body 3110 via the third sub-segment 3115. It should be noted that the dimension of the third sub-segment 3115 along the second direction Y is slightly greater than the dimension of the first sub-segment 3113 along the second direction Y. Thus, the difference in dimension between the third sub-segment 3115 and the first sub-segment 3113 along the second direction Y corresponds to the dimension of the gap between the first sub-segment 3113 and the main body 3110.

[0136] 6 and 7 , the array substrate 10 further includes a plurality of connection lines 60 , and the plurality of device conductive portion groups 510 in the same light emitting unit 210 are connected via the connection lines 60 . At least one connection line 60 is located in the first conductive layer 30 .

[0137] In this case, the connecting wires 60 between the multiple device conductive portion groups 510 are at least partially located in the first conductive layer 30, which is equivalent to transferring at least a portion of the connecting wires connecting the multiple device conductive portion groups 510 in the related art to the first conductive layer 30. In this way, the connecting wires (the connecting wires 60 located in the first conductive layer 30) are also covered with an insulating layer 40. For example, the connecting wires are also covered with a first passivation layer 41, a first flat layer 42, and a second passivation layer 43, thereby improving the corrosion resistance of the connecting wires (the connecting wires 60 located in the first conductive layer 30), reducing the risk of the connecting wires (the connecting wires 60 located in the first conductive layer 30) being disconnected due to corrosion, and improving product yield. At the same time, the increased wiring area of ​​the first conductive layer 30 is conducive to improving the thickness uniformity of the first conductive layer 30, reducing the etching time required for patterning the first conductive layer 30, reducing the consumption of etching solution, and reducing costs.

[0138] For example, as shown in Figures 6 and 7, the plurality of connecting lines 60 include first-type connecting lines 610 and second-type connecting lines 620. The first-type connecting lines 610 are staggered with the orthographic projections of the plurality of signal lines 310 on the substrate 11, and the second-type connecting lines 620 at least partially overlap with the orthographic projections of the plurality of signal lines 310 on the substrate 11. All of the first-type connecting lines 610 are located in the first conductive layer 30, and all of the second-type connecting lines 620 are located in the second conductive layer 50.

[0139] The first type connection line 610 may be located between adjacent device power lines 311 and common voltage signal lines 312 , and / or between adjacent common voltage signal lines 312 and chip signal line group 3130 .

[0140] For example, as shown in FIG6 , the light emitting unit 210 includes a first device conductive portion group 501 , a second device conductive portion group 502 , a third device conductive portion group 503 and a fourth device conductive portion group 504 connected in series.

[0141] On this basis, the plurality of connection lines 60 include a first connection line 61, a second connection line 62, and a third connection line 63. The first connection line 61 and the third connection line 63 are located in the first conductive layer 30, and the second connection line 62 is located in the second conductive layer 50. In this case, the first connection line 61 and the third connection line 63 are first-type connection lines 610, and the second connection line 62 is a second-type connection line 620.

[0142] One end of the first connecting wire 61 is connected to the first device conductive portion group 501, and the other end is connected to the second device conductive portion group 502. One end of the second connecting wire 62 is connected to the second device conductive portion group 502, and the other end is connected to the third device conductive portion group 503. One end of the third connecting wire 63 is connected to the third device conductive portion group 503, and the other end is connected to the fourth device conductive portion group 504.

[0143] From the above, it can be seen that in the array substrate 10 of the embodiment of the present disclosure, the connecting lines 60 (the first connecting line 61 and the third connecting line 63) that do not overlap with the signal line 310 are all arranged in the first conductive layer 30. This not only reduces the risk of corrosion and disconnection of the first connecting line 61 and the third connecting line 63, but also helps to improve the thickness uniformity of the first conductive layer 30 and reduce production costs.

[0144] In some embodiments, referring to FIG. 6 and FIG. 12 , the chip conductive portion group 520 is located between two adjacent chip signal lines 313 in the same chip signal line group 3130 , and the insulating layer 40 is further provided with a second via hole H2 and a third via hole H3 penetrating the insulating layer 40 .

[0145] On this basis, referring to FIG. 6 and FIG. 12 , the array substrate 10 further includes a plurality of first transfer lines 71 . The first transfer lines 71 include a first routing segment 711 and a second routing segment 712 .

[0146] As shown in FIG6 , FIG12 and FIG18 , the first routing segment 711 is located between the adjacent common voltage signal line 312 and chip signal line 313 , and the first conductive portion 511 of the device conductive portion group 510 is in electrical contact with the first routing segment 711 through the second via H2 .

[0147] As shown in Figures 6 and 12, one end of the second routing segment 712 is electrically connected to the first routing segment 711 through the third via H3, and the other end crosses over at least one chip signal line 313 to connect to the second conductive portion 521 of the chip conductive portion group 520. For example, the second routing segment 712 sequentially crosses over the chip power signal line 314, the electromagnetic shielding signal line 317, and the clock signal line 316 to connect to the second conductive portion 521 of the chip conductive portion group 520. Alternatively, the second routing segment 712 sequentially crosses over the address signal line 315, the electromagnetic shielding signal line 317, and the clock signal line 316 to connect to the second conductive portion 521 of the chip conductive portion group 520.

[0148] Based on the above, the first routing segment 711 does not overlap with the signal line 310 , and the second routing segment 712 overlaps with the chip signal line 313 . Therefore, the first routing segment 711 can be disposed in the first conductive layer 30 , and the second routing segment 712 can be disposed in the second conductive layer 50 .

[0149] In this case, in the array substrate 10 of the embodiment of the present disclosure, the portion of the first adapter line 71 that does not overlap with the signal line 310 (the first routing segment 711) is arranged in the first conductive layer 30. This not only reduces the risk of corrosion and disconnection of the first routing segment 711, but also helps to improve the thickness uniformity of the first conductive layer 30 and reduce production costs.

[0150] In some embodiments, as shown in Figures 6 and 12 , the chip conductive portion group 520 has a centerline L extending along the first direction X, and a maximum distance Dmax between the third via H3 and the centerline L is less than or equal to 2 mm. In this case, the third via H3 is relatively close to the chip conductive portion group 520 , making it easier for the third via H3 to be covered by the encapsulation portion 80 (see Figure 19 ) formed in a subsequent process, thereby improving waterproofness and corrosion resistance and reducing the risk of poor overlap between the second trace segment 712 and the first trace segment 711.

[0151] For example, referring to FIG19 , the light-emitting substrate 110 further includes a plurality of spaced-apart packaging portions 80 , each packaging portion 80 wrapping at least one electronic component 20 to protect the electronic component 20 , thereby improving the waterproofness, corrosion resistance and light extraction efficiency of the light-emitting substrate 110 .

[0152] The maximum length of the encapsulation portion 80 projected onto the substrate 11 in the first direction X and the second direction Y is 1 mm to 4 mm. For example, the maximum length of the encapsulation portion 80 projected onto the substrate 11 in the first direction X and the second direction Y is any one of 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, and 4 mm.

[0153] It should be noted that a highly thixotropic glue can be sprayed onto the electronic component 20 using a dispensing machine and then cured to form the encapsulation portion 80. Furthermore, the orthographic projection of the encapsulation portion 80 on the substrate 11 can be in the shape of a circle, an ellipse, a polygon, or an irregular shape combining straight lines and curves, which is not limited in the present embodiment.

[0154] It should be understood that the material of the encapsulation portion 80 should be adjusted accordingly for different types of electronic components 20. For example, if the electronic component 20 is an optical component, the encapsulation portion 80 may be made of a transparent material. If the electronic component 20 is a non-optical component, the material of the encapsulation portion 80 does not require light transmission and may be a transparent material, a reflective material, or a light-absorbing material.

[0155] It should be noted that the transparent material may include transparent silicone, the reflective material may include at least one of white ink, white resin and silicone white glue, and the light-absorbing material may include at least one of black ink, black resin and silicone black glue.

[0156] For example, referring to FIG. 19 , the encapsulation portion 80 includes a first encapsulation portion 81 and a second encapsulation portion 82 . The first encapsulation portion 81 covers the microchip 22, and the second encapsulation portion 82 covers the light-emitting device 21. Furthermore, the first encapsulation portion 81 can be made of a transparent material, while the second encapsulation portion 82 can be made of a reflective material to improve the light extraction efficiency of the light-emitting substrate 110.

[0157] It should be noted that the shapes of the orthographic projections of the second packaging portion 82 and the first packaging portion 81 on the substrate 11 may be the same or different, and the embodiment of the present disclosure does not limit this.

[0158] On this basis, as shown in Figures 12, 19 and 20, the first packaging part 81 also covers the third via H3. In this way, under the extrusion of the gravity of the first packaging part 81 itself and the expansion force generated by the curing process, the delamination phenomenon of the second routing segment 712 and the first routing segment 711 in the third via H3 can be improved, thereby reducing the risk of poor overlap between the second routing segment 712 and the first routing segment 711 and improving product yield.

[0159] In some embodiments, referring to FIG. 20 , the insulating layer 40 is further provided with a fourth via hole H4 and a fifth via hole H5 penetrating the insulating layer 40 .

[0160] On this basis, referring to FIG. 6 , FIG. 12 and FIG. 20 , the array substrate 10 further includes a plurality of second transfer lines 72 and a plurality of third transfer lines 73 , and the plurality of second transfer lines 72 and the plurality of third transfer lines 73 are disposed on the second conductive layer 50 .

[0161] The second adapter line 72 extends along the second direction Y, and one end of the second adapter line 72 is connected to the chip signal line 313 through the fourth via H4, and the other end is connected to the second conductive portion 521 of the chip conductive portion group 520. The third adapter line 73 extends along the second direction Y, and one end of the third adapter line 73 is connected to the common voltage signal line 312 through the fifth via H5, and the other end crosses at least one chip signal line 313 to connect to the second conductive portion 521 of the chip conductive portion group 520.

[0162] On this basis, the above-mentioned first packaging part 81 can also cover the fourth via H4. In this way, under the extrusion of the gravity of the first packaging part 81 itself and the expansion force generated by the curing process, the stratification phenomenon of the second adapter line 72 and the chip signal line 313 in the fourth via H4 can be improved, thereby reducing the risk of poor overlap between the second adapter line 72 and the chip signal line 313 and improving product yield.

[0163] 12 and 13 , in some embodiments, the array substrate 10 may further include a plurality of first pads 31 , and one chip conductive portion group 520 may correspond to one first pad 31 or to a plurality of first pads 31 . The first pad 31 is located in the first conductive layer 30 .

[0164] At this time, when using an electroplating process to form the various traces and first pads 31 located in the first conductive layer 30 with a relatively large thickness (for example, greater than or equal to 2 μm) , the first pads 31 can serve as a companion plating process. In this case, the spacing between the first pad 31 and the traces adjacent to it is smaller than the spacing between the traces adjacent to the first pad 31. This allows for a higher thickness uniformity between the first pad 31 and the traces adjacent to it, thereby compensating for the thickness differences between the traces adjacent to the first pad 31, improving the thickness uniformity of the traces adjacent to the first pad 31, and thus improving the thickness uniformity of the first conductive layer 30.

[0165] In some examples, as shown in FIG12 , the orthographic projection of a second conductive portion 521 of the chip conductive portion group 520 on the substrate 11 is within the orthographic projection of a first pad 31 on the substrate 11. Furthermore, the second conductive portion 521 can be electrically connected to or electrically insulated from the corresponding first pad 31. For example, the second conductive portion 521 can be electrically connected to the corresponding first pad 31. In this way, the first pad 31 can increase the conductive area, thereby reducing resistance and minimizing signal transmission loss.

[0166] In other examples, as shown in FIG13 , the orthographic projection of one chip conductive portion group 520 on the substrate 11 is within the range of the orthographic projection of one first pad 31 on the substrate 11. An insulating layer 40 is present between the chip conductive portion group 520 and the first pad 31. In this manner, one chip conductive portion group 520 corresponds to one first pad 31, simplifying the process and reducing manufacturing costs.

[0167] In some embodiments, referring to Figures 6, 21, and 22, the second conductive layer 50 further includes a third conductive portion 53, and the array substrate 10 further includes a test line 90. The third conductive portion 53 is connected to the signal line 310, the connecting line 60, or the first adapter line 71 via the test line 90. The third conductive portion 53 can provide a test point for lighting debugging, facilitating the inspection and debugging of each signal line 310, the connecting line 60, or the first adapter line 71, which is beneficial for the repair of the light-emitting substrate 110, thereby improving the maintainability of the light-emitting substrate 110 and improving the product yield.

[0168] 6 and 21 , the test lines 90 include first test lines 91, through which the third conductive portion 53 is connected to the signal line 310. Furthermore, at least one first test line 91 is located in the first conductive layer 30. For example, all first test lines 91 are located in the first conductive layer 30.

[0169] In this case, the first test line 91 is also covered with an insulating layer 40. For example, the first test line 91 is also covered with a first passivation layer 41, a first planarization layer 42, and a second passivation layer 43. This improves the corrosion resistance of the first test line 91, reduces the risk of the first test line 91 being disconnected due to corrosion, and improves product yield. At the same time, the routing area of ​​the first conductive layer 30 is increased, and the first test line 91 can also serve as a compensation and accompanying plating, which is beneficial for improving the thickness uniformity of the first conductive layer 30, reducing the etching time required for patterning the first conductive layer 30, reducing the consumption of etching solution, and reducing costs.

[0170] For example, referring to FIG6 and FIG22 , the test line 90 further includes a second test line 92, through which the third conductive portion 53 is connected to the connecting line 60 or the first adapter line 71. Furthermore, at least one second test line 92 is located in the first conductive layer 30. For example, all second test lines 92 are located in the first conductive layer 30.

[0171] In this case, the second test line 92 is also covered with an insulating layer 40. For example, the second test line 92 is also covered with a first passivation layer 41, a first planarization layer 42, and a second passivation layer 43. This improves the corrosion resistance of the second test line 92, reduces the risk of the second test line 92 being disconnected due to corrosion, and improves product yield. At the same time, the routing area of ​​the first conductive layer 30 is increased, and the second test line 92 can also serve as a compensation and accompanying plating, which is beneficial for improving the thickness uniformity of the first conductive layer 30, reducing the etching time required for patterning the first conductive layer 30, reducing the consumption of etching solution, and reducing costs.

[0172] 21 and 22 , in some embodiments, the array substrate 10 may further include a plurality of second pads 32, with one second pad 32 corresponding to one third conductive portion 53. The second pads 32 are located on the first conductive layer 30, so that the second pads 32 can also serve as compensation and accompanying plating, thereby improving the thickness uniformity of the first conductive layer 30.

[0173] For example, as shown in Figures 21 and 22 , the orthographic projection of a third conductive portion 53 on substrate 11 is within the orthographic projection of a second pad 32 on substrate 11. Furthermore, the third conductive portion 53 is electrically connected to the corresponding second pad 32. This increases the conductive area of ​​the second pad 32, thereby reducing resistance and minimizing signal transmission loss.

[0174] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate; A first conductive layer is provided on one side of the substrate; the first conductive layer includes a plurality of signal lines, and the plurality of signal lines include a plurality of device power lines; At least one insulating layer is provided on a side of the first conductive layer away from the substrate; the at least one insulating layer is provided with a first via hole penetrating the at least one insulating layer; A second conductive layer is arranged on a side of the at least one insulating layer away from the substrate; the second conductive layer includes a plurality of device conductive part groups and a plurality of chip conductive part groups, the device conductive part group includes a plurality of first conductive parts arranged at intervals, and the device conductive part group is configured to connect the light-emitting device; the chip conductive part group includes a plurality of second conductive parts arranged at intervals, and the chip conductive part group is configured to connect the microchip; the first conductive part of the device conductive part group is electrically contacted with the device power line through the first via.

2. The array substrate according to claim 1, comprising a plurality of light-emitting units and a plurality of connecting lines, wherein the light-emitting units include a plurality of device conductive portion groups connected in series and / or in parallel, and the plurality of device conductive portion groups in the same light-emitting unit are connected via the connecting lines; wherein: At least one connecting line is located in the first conductive layer.

3. The array substrate according to claim 2, wherein: The multiple connecting lines include a first type of connecting lines and a second type of connecting lines, the first type of connecting lines and the orthographic projections of the multiple signal lines on the substrate are staggered, and the second type of connecting lines and the orthographic projections of the multiple signal lines on the substrate at least partially overlap; all of the first type of connecting lines are located in the first conductive layer, and all of the second type of connecting lines are located in the second conductive layer.

4. The array substrate according to claim 2 or 3, wherein: The plurality of signal lines further include a plurality of common voltage signal lines and a plurality of chip signal lines, the plurality of chip signal lines are divided into a plurality of chip signal line groups, and the plurality of chip signal lines of each chip signal line group are configured to be connected to the same microchip; The device power line, the common voltage signal line and the chip signal line all extend along a first direction; Along the second direction, each chip signal line group is located between two common voltage signal lines, and each common voltage signal line is located between the chip signal line group and the device power line; the first direction intersects the second direction; The first type of connection line is located between adjacent device power lines and the common voltage signal lines; and / or the first type of connection line is located between adjacent common voltage signal lines and the chip signal line group.

5. The array substrate according to any one of claims 2 to 4, wherein: The light-emitting unit includes a first device conductive portion group, a second device conductive portion group, a third device conductive portion group and a fourth device conductive portion group, the first device conductive portion group is connected to the device power line, and the fourth device conductive portion group is connected to the chip conductive portion group; The plurality of connecting lines include: a first connecting line, one end of which is connected to the first device conductive portion group, and the other end of which is connected to the second device conductive portion group; the first connecting line is located in the first conductive layer; a second connecting line, one end of which is connected to the second device conductive portion group, and the other end of which is connected to the third device conductive portion group; the second connecting line is located in the second conductive layer; A third connecting line, one end of which is connected to the third device conductive portion group, and the other end of which is connected to the fourth device conductive portion group; the third connecting line is located in the first conductive layer.

6. The array substrate according to any one of claims 1 to 5, wherein: The device power line includes: The main body extends along a first direction; along a second direction, at least one side of the main body is provided with a plurality of first openings and a plurality of second openings, and along the first direction, the plurality of first openings and the plurality of second openings are staggered one by one; the first direction intersects the second direction; a first overlapping portion connected to the main body and located at the first opening; A second overlapping portion is connected to the main body and is located between the adjacent first opening and the second opening; the second overlapping portion includes a first sub-segment and a second sub-segment, the first sub-segment extends along the first direction, the second sub-segment extends along the second direction, and the first sub-segment is located on a side of the second sub-segment close to the adjacent first opening.

7. The array substrate according to claim 6, wherein: The first subsection and the main body portion are adjacent to each other at the same boundary; or, There is a gap between the first sub-segment and the main body, the second overlapping portion further includes a third sub-segment, and the first sub-segment is connected to the main body through the third sub-segment.

8. The array substrate according to claim 6 or 7, wherein: One end of the first sub-segment away from the second sub-segment is flush with a boundary of the first opening close to the second opening.

9. The array substrate according to any one of claims 6 to 8, comprising a plurality of light-emitting units, the plurality of light-emitting units being arranged in an array along the first direction and the second direction; the light-emitting units comprising a plurality of device conductive portion groups connected in series and / or in parallel, the plurality of device conductive portion groups comprising a target device conductive portion group, the target device conductive portion group being a device conductive portion group among the plurality of device conductive portion groups that is in electrical contact with the device power line through the first via; Along the first direction, among the two adjacent light-emitting units, the first conductive portion of the target device conductive portion group of one light-emitting unit is electrically contacted with the first overlapping portion through the first via hole; the first conductive portion of the target device conductive portion group of the other light-emitting unit is electrically contacted with the second sub-segment through the first via hole.

10. The array substrate according to any one of claims 1 to 9, wherein: The plurality of signal lines further include a plurality of chip signal lines and a plurality of common voltage signal lines, the plurality of chip signal lines are divided into a plurality of chip signal line groups, and the plurality of chip signal lines in each chip signal line group are configured to be connected to the same microchip; the device power line, the common voltage signal line, and the chip signal line all extend along a first direction; Along the second direction, each chip signal line group is located between two common voltage signal lines, and each common voltage signal line is located between the chip signal line group and the device power line; the first direction intersects the second direction; The chip conductive portion group is located between two adjacent chip signal lines in the same chip signal line group; The at least one insulating layer is further provided with a second via hole and a third via hole penetrating the at least one insulating layer; the array substrate further includes a plurality of first transfer lines, the first transfer lines including: a first routing segment provided in the first conductive layer and located between the adjacent common voltage signal line and the chip signal line; the first conductive portion of the device conductive portion group being in electrical contact with the first routing segment through the second via; The second routing segment is provided in the second conductive layer; one end of the second routing segment is electrically contacted with the first routing segment through the third via, and the other end thereof crosses at least one chip signal line and is connected to the second conductive portion of the chip conductive portion group.

11. The array substrate according to claim 10, wherein: The chip conductive portion group has a center line extending along the first direction; and a maximum distance between the third via and the center line is less than or equal to 2 mm.

12. The array substrate according to claim 10 or 11, wherein: The at least one insulating layer is further provided with a fourth via hole and a fifth via hole penetrating the at least one insulating layer; The array substrate further includes: A plurality of second transfer lines are provided on the second conductive layer; one end of the second transfer line is connected to the chip signal line through the fourth via hole, and the other end is connected to the second conductive portion of the chip conductive portion group; A plurality of third transfer lines are arranged in the second conductive layer; one end of the third transfer line is connected to the common voltage signal line through the fifth via hole, and the other end crosses at least one chip signal line and is connected to the second conductive part of the chip conductive part group.

13. The array substrate according to any one of claims 1 to 12, wherein: The second conductive layer further includes a third conductive portion, and the array substrate further includes: The third conductive portion is connected to the signal line through a first test line; and at least one first test line is located in the first conductive layer.

14. The array substrate according to claim 13, comprising a plurality of light-emitting units, a plurality of connecting wires, and a plurality of first adapter wires, wherein the light-emitting units include a plurality of device conductive portion groups connected in series and / or in parallel, the plurality of device conductive portion groups in the same light-emitting unit are connected via the connecting wires, and the light-emitting unit is connected to the chip conductive portion group via the first adapter wires; The array substrate further includes: a second test line, wherein the third conductive portion is connected to the connecting line or the first adapter line through the second test line; Furthermore, at least one second test line is located in the first conductive layer.

15. The array substrate according to any one of claims 1 to 14, wherein: The at least one insulating layer includes a first passivation layer, a first planar layer, and a second passivation layer arranged in sequence, and the second passivation layer is arranged on a side of the first planar layer away from the first conductive layer; and / or, The array substrate further includes a third passivation layer, the third passivation layer being arranged on the second conductive layer away from the one side of the substrate.

16. A light-emitting substrate, comprising: An array substrate, wherein the array substrate is the array substrate according to any one of claims 1 to 15; A light emitting device connected to the device conductive portion group of the array substrate; The microchip is connected to the chip conductive portion group of the array substrate.

17. The light-emitting substrate according to claim 16, further comprising: a first packaging portion covering the microchip; Furthermore, in a case where the at least one insulating layer is provided with a third via hole and a fourth via hole penetrating the at least one insulating layer, the first packaging portion further covers the third via hole and the fourth via hole.

18. A backlight module, comprising: The light-emitting substrate according to claim 16 or 17, wherein the light-emitting substrate has a light-emitting side and a non-light-emitting side opposite to each other; A plurality of optical films are arranged on the light-emitting side of the light-emitting substrate.

19. A display device comprising: The backlight module according to claim 18; The display panel is arranged on a side of the plurality of optical films in the backlight module away from the light-emitting substrate.

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