Planar device and switching function circuit

Abstract

A planar device and a switching function circuit, used for shielding the potential to which high-frequency jumping occurs on a chip in a planar device and reducing the electromagnetic interference caused by the potential to which high-frequency jumping occurs on the chip. The planar device comprises at least one chip and a substrate; the chip comprises a base; the base is arranged on the side of the chip close to the substrate, and the base is electrically connected to the substrate; at least one source and at least one gate are provided on the side of the chip away from the substrate; and the at least one source and the at least one gate are electrically connected to the chip, respectively; and the substrate is connected to a target potential point, and the target potential point is used for keeping the potential of the substrate in a low-frequency change state or a constant state.

Description

Planar devices and switching function circuits

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 4, 2023, with application number 202311686487.9 and invention name “Planar Device and Switching Function Circuit”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of power electronics technology, and in particular to a planar device and a switching function circuit. Background Art

[0003] Planar devices, especially those based on GaN, hold great promise for application in power electronics. However, the chip (either unidirectional or bidirectional) in conventional planar devices is attached to a heat sink via an insulating dielectric. This causes the chip's potential to fluctuate at high frequencies. This high-frequency fluctuation, caused by parasitic capacitance between the chip and the heat sink, generates a corresponding current that flows between the chip and the heat sink, leading to electromagnetic interference (EMI). Summary of the Invention

[0004] The present application provides a planar device and a switch function circuit for shielding the high-frequency jumping potential on the chip of the planar device and reducing the electromagnetic interference caused by the high-frequency jumping potential on the chip.

[0005] A first aspect of an embodiment of the present application provides a planar device, comprising: at least one chip and a substrate; the chip comprises a substrate; the substrate is arranged on a side of the chip close to the substrate, and the substrate is electrically connected to the substrate; at least one source and at least one gate are arranged on a side of the chip away from the substrate; the at least one source and the at least one gate are respectively electrically connected to the chip; the substrate is connected to a target potential point, and the target potential point is used to keep the potential of the substrate in a low-frequency changing state or a constant state.

[0006] Optionally, in a first embodiment of the first aspect, the planar device further includes at least one substrate electrode, and the potential of the substrate electrode is the same as that of the substrate.

[0007] Optionally, in a second embodiment of the first aspect, the substrate is a copper substrate or a ceramic substrate directly coated with copper on one side.

[0008] Optionally, in a third embodiment of the first aspect, the target potential point is a static potential point or a low-frequency potential point.

[0009] Optionally, in a fourth implementation of the first aspect, the target potential point is obtained by the AC phase / line voltage or the DC bus voltage through an impedance voltage divider circuit, and the impedance voltage divider circuit includes a capacitor and / or a resistor.

[0010] Optionally, in a fifth implementation of the first aspect, the target potential point is a designated potential point in the power module.

[0011] Optionally, in a sixth implementation of the first aspect, an average value of the voltage difference between the target potential point and each source in each chip is less than a preset value.

[0012] Optionally, in a seventh implementation of the first aspect, the at least one chip is a planar single-tube chip; a source, a gate, and a drain are provided on a side of the planar single-tube chip away from the substrate.

[0013] Optionally, in an eighth embodiment of the first aspect, the at least one chip is a half-bridge unidirectional chip, and the planar device further includes: a half-bridge midpoint; a first source, a first drain, a first gate, and a second gate are provided on the side of the half-bridge unidirectional chip away from the substrate; the first source, the first drain, the first gate, the second gate and the half-bridge midpoint are respectively connected to the half-bridge unidirectional chip.

[0014] Optionally, in a ninth embodiment of the first aspect, the at least one chip is a planar bidirectional chip; a first source, a second source, a first gate, and a second gate are provided on a side of the planar bidirectional chip away from the substrate; the first source, the second source, the first gate, and the second gate are respectively connected to the planar bidirectional chip.

[0015] Optionally, in a tenth embodiment of the first aspect, the at least one chip includes a first planar bidirectional chip and a second planar bidirectional chip, and the planar device further includes: a half-bridge midpoint; a first source, a first gate, and a second gate are provided on a side of the first planar bidirectional chip away from the substrate; a second source, a third gate, and a fourth gate are provided on a side of the second planar bidirectional chip away from the substrate; the first source, the first gate, and the second gate are respectively connected to the first side of the first planar bidirectional chip, the second source, the third gate, and the fourth gate are respectively connected to the first side of the second planar bidirectional chip, and the second side of the first planar bidirectional chip is connected to the second side of the second planar bidirectional chip and led to the half-bridge midpoint.

[0016] The second aspect of the embodiments of the present application provides a switching function circuit, comprising: at least two planar devices and a DC bus as described in the seventh embodiment of the first aspect; the at least two planar devices include a first planar device located on the upper tube of the first bridge arm and a second planar device located on the lower tube of the first bridge arm; the drain of the first planar device is connected to the positive pole of the DC bus; the source of the second planar device is connected to the negative pole of the DC bus; the source of the first planar device is connected to the drain of the second planar device.

[0017] Optionally, in the first embodiment of the second aspect, the at least two planar devices also include a third planar device located on the upper tube of the second bridge arm and a fourth planar device located on the lower tube of the second bridge arm; the drain of the third planar device is connected to the positive pole of the DC bus; the source of the fourth planar device is connected to the negative pole of the DC bus; and the source of the third planar device is connected to the drain of the fourth planar device.

[0018] The third aspect of the embodiments of the present application provides a switching function circuit, comprising: at least one planar device and a DC bus as described in the eighth implementation manner of the first aspect; the drain of each planar device is connected to the positive pole of the DC bus; and the source of each planar device is connected to the negative pole of the DC bus.

[0019] The fourth aspect of the embodiments of the present application provides a switching function circuit, comprising: at least two planar devices and filter capacitors described in the ninth embodiment of the first aspect, the filter unit comprising at least one capacitor; the at least two planar devices comprising a first planar device located on the upper tube of the first bridge arm and a second planar device located on the lower tube of the first bridge arm; the first source of the first planar device is connected to the first end of the filter unit and one end of the two single-phase alternating current lines; the first source of the second planar device is connected to the second end of the filter unit and the other end of the two single-phase alternating current lines; the second source of the first planar device is connected to the second source of the second planar device.

[0020] Optionally, in a first embodiment of the fourth aspect, the at least two planar devices further include a third planar device located on the upper tube of the second bridge arm and a fourth planar device located on the lower tube of the second bridge arm; the first source of the third planar device is connected to the first end of the filter unit and one end of the two single-phase AC lines; the first source of the fourth planar device is connected to the second end of the filter unit and the other end of the two single-phase AC lines; the second source of the third planar device is connected to the second source of the fourth planar device.

[0021] The fifth aspect of the embodiments of the present application provides a switching function circuit, including: three planar devices described in the ninth implementation manner of the first aspect, a first impedance, a second impedance, a third impedance, a first capacitor, a second capacitor and a third capacitor; the three planar devices include a first planar device located in the first bridge arm, a second planar device located in the second bridge arm and a third planar device located in the third bridge arm; the first AC phase line is connected to the second source of the first planar device and the first end of the first capacitor through the first impedance; the second AC phase line is connected to the second source of the second planar device and the first end of the second capacitor through the second impedance; the third AC phase line is connected to the second source of the third planar device and the first end of the third capacitor through the third impedance; the first source of the first planar device is connected to the first source of the second planar device and the first source of the third planar device; the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are connected.

[0022] A sixth aspect of the embodiments of the present application provides a switching function circuit, comprising: six planar devices described in the ninth implementation manner of the first aspect, a first impedance, a second impedance, a third impedance, a first capacitor, a second capacitor and a third capacitor; the six planar devices include a first planar device located on the upper tube of the first bridge arm, a second planar device located on the upper tube of the second bridge arm, a third planar device located on the upper tube of the third bridge arm, a fourth planar device located on the lower tube of the first bridge arm, a fifth planar device located on the lower tube of the second bridge arm and a sixth planar device located on the lower tube of the third bridge arm; a first AC phase line is connected to the second source of the fourth planar device and the second source of the first planar device through the first impedance; a second AC phase line is connected to the fifth planar device through the second impedance The second source of the planar device and the second source of the second planar device are connected; the third AC phase line is connected to the second source of the sixth planar device and the second source of the third planar device through the third impedance; the first source of the first planar device is connected to the first source of the second planar device and the first source of the third planar device; the first source of the fourth planar device is connected to the first source of the fifth planar device and the first source of the sixth planar device; the first end of the first capacitor is connected to the first AC phase line, the first end of the second capacitor is connected to the second AC phase line, the first end of the third capacitor is connected to the third AC phase line, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are connected.

[0023] The seventh aspect of the embodiments of the present application provides a switching function circuit, comprising: at least one planar device and a filter capacitor as described in the tenth embodiment of the first aspect, the filter capacitor comprising at least one capacitor; the first source of each planar device is connected to the first end of the filter unit and one end of the two-phase alternating current line; the second source of each planar device is connected to the second end of the filter unit and the other end of the two-phase alternating current line.

[0024] In the technical solution provided in the embodiments of the present application, a planar device includes at least one chip and a substrate; the chip includes a substrate; the substrate is disposed on the side of the chip close to the substrate and is electrically connected to the substrate; at least one source and at least one gate are disposed on the side of the chip away from the substrate; the at least one source and at least one gate are electrically connected to the chip; the substrate is connected to a target potential point, which is used to maintain the potential of the substrate in a low-frequency varying state or a constant state. In the embodiments of the present application, by connecting the substrate in the planar device to the target potential point, high-frequency potential variations on the chip in the planar device are shielded, thereby reducing electromagnetic interference between the chip and the heat sink. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram of parasitic capacitance in a planar device;

[0026] FIG2 is a schematic diagram of a planar device according to an embodiment of the present application;

[0027] FIG3 is another schematic diagram of a planar device according to an embodiment of the present application;

[0028] FIG4 is another schematic diagram of a planar device according to an embodiment of the present application;

[0029] FIG5 is a schematic diagram of the connection method of the target potential points in an embodiment of the present application;

[0030] FIG6 is another schematic diagram of a planar device according to an embodiment of the present application;

[0031] FIG7 is another schematic diagram of a planar device according to an embodiment of the present application;

[0032] FIG8 is an equivalent circuit symbol of a planar device including a planar single-transistor chip in an embodiment of the present application;

[0033] FIG9 is another schematic diagram of a planar device according to an embodiment of the present application;

[0034] FIG10 is another schematic diagram of a planar device according to an embodiment of the present application;

[0035] FIG11 is an equivalent circuit symbol of a planar device including a half-bridge unidirectional chip in an embodiment of the present application;

[0036] FIG12 is a schematic diagram of a unidirectional transistor combined into a bidirectional switch device;

[0037] FIG13 is another schematic diagram of a planar device according to an embodiment of the present application;

[0038] FIG14 is another schematic diagram of a planar device according to an embodiment of the present application;

[0039] FIG15 is an equivalent circuit symbol of a planar device including a planar bidirectional chip according to an embodiment of the present application;

[0040] FIG16 is another schematic diagram of a planar device according to an embodiment of the present application;

[0041] FIG17 is another schematic diagram of a planar device according to an embodiment of the present application;

[0042] FIG18 is an equivalent circuit symbol of a planar device including two planar bidirectional chips according to an embodiment of the present application;

[0043] FIG19 is a schematic diagram of laminating a planar device to a heat sink according to an embodiment of the present application;

[0044] FIG20 is another schematic diagram of the bonding of a planar device and a heat sink according to an embodiment of the present application;

[0045] FIG21 is a schematic diagram of a planar device including a planar single-transistor chip applied to a single-phase half-bridge circuit according to an embodiment of the present application;

[0046] FIG22 is a schematic diagram of a planar device including a half-bridge unidirectional chip applied in a single-phase half-bridge circuit according to an embodiment of the present application;

[0047] FIG23 is a schematic diagram of a planar device including a planar bidirectional chip applied to a single-phase half-bridge circuit according to an embodiment of the present application;

[0048] FIG24 is a schematic diagram of a planar device including a planar bidirectional chip applied to a single-phase full-bridge circuit according to an embodiment of the present application;

[0049] FIG25 is a schematic diagram of a planar device including a planar bidirectional chip applied to a three-phase half-controlled bridge circuit according to an embodiment of the present application;

[0050] FIG26 is a schematic diagram of a planar device including a planar bidirectional chip applied to a three-phase fully controlled bridge circuit according to an embodiment of the present application;

[0051] FIG27 is a schematic diagram of a planar device including two planar bidirectional chips used in a single-phase full-bridge circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The present application provides a planar device and a switch function circuit for shielding the high-frequency jumping potential on the chip of the planar device and reducing the electromagnetic interference caused by the high-frequency jumping potential on the chip.

[0053] The terms "first," "second," "third," "fourth," etc. (if any) in the specification and claims of the present application and in the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that the numbers used in this way are interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or apparatus.

[0054] When traditional planar switching devices are installed with an external heat sink and used in a circuit, the potential on the chip within the switching device experiences high-frequency fluctuations. As shown in Figure 1, there is parasitic capacitance C1 between the chip and the copper substrate (i.e., the base plate), and parasitic capacitance C2 between the copper substrate and the heat sink. When the chip switches at high frequencies in the circuit, this high-frequency fluctuation in potential is generated. This high-frequency fluctuation in potential generates a corresponding current flowing between the chip and the heat sink through the parasitic capacitance, resulting in high-frequency current fluctuations in the parasitic capacitance, which in turn causes electromagnetic interference problems.

[0055] In order to solve the electromagnetic interference problem, the present embodiment provides a planar device, as shown in FIG2 , which specifically includes:

[0056] at least one chip 110 and a substrate 120;

[0057] The chip 110 includes a substrate 111;

[0058] The substrate 111 is disposed on a side of the chip 110 close to the base plate 120 , and the substrate 111 is electrically connected to the base plate 120 ;

[0059] At least one source electrode 130 and at least one gate electrode 140 are provided on a side of the chip 110 away from the substrate 120 ;

[0060] The at least one source electrode 130 and the at least one gate electrode 140 are electrically connected to the chip 110 respectively;

[0061] The substrate 120 is connected to a target potential point, and the target potential point is used to keep the potential of the substrate 120 in a low-frequency changing state or a constant state.

[0062] Among them, the chip in the planar device can be a gallium nitride GaN chip, for example, a Cascade GaN chip or an enhanced GaN chip, which is not limited here.

[0063] The present application provides a planar device, which connects the substrate in the planar device to a target potential point with low-frequency potential changes or constant potential, limits the high-frequency current generated in the chip due to high-frequency potential changes to between the chip and the substrate, and eliminates the high-frequency voltage changes between the substrate and the external heat sink, thereby preventing high-frequency current changes from flowing between the chip and the external heat sink through parasitic capacitance, thereby reducing the impact of electromagnetic interference.

[0064] In a feasible implementation manner, as shown in FIG3 , the planar device further includes at least one substrate electrode 121 , and the potential of the substrate electrode 121 is the same as that of the substrate 120 .

[0065] Specifically, the substrate 120 is connected to the target potential point via a substrate electrode 121. The substrate electrode 121 is a separate pin.

[0066] As shown in FIG. 4 , the substrate 120 may be provided with two substrate electrodes 121 , which are respectively provided on two sides of the substrate 120 , that is, the pins of the two substrate electrodes 121 are provided on two sides of the planar device.

[0067] It is understandable that the substrate 120 may be provided with a substrate electrode 121 , which is provided on one side of the substrate 120 , that is, the pin of the substrate electrode 121 is provided on one side of the planar device.

[0068] In a feasible implementation manner, the substrate is a copper substrate or a ceramic substrate directly coated with copper on one side.

[0069] As shown in FIG3 or FIG4 , the substrate 120 is a copper substrate or a direct bond copper (DBC) ceramic substrate with copper on one side. The copper substrate is a copper frame and can be a single piece of metal copper.

[0070] It is understandable that other materials that meet the requirements may also be used as the substrate, and the specific details are not limited here.

[0071] In a feasible implementation manner, the target potential point is a static potential point or a low-frequency potential point.

[0072] The potential at the target potential point varies at a low frequency or remains constant relative to the potential in the radiator.

[0073] The target potential point is a static point or low-frequency varying potential point corresponding to the AC phase line, or a corresponding static point or low-frequency varying potential point in the circuit topology. It should be noted that in a circuit, the potentials of the target potential points connected to multiple planar devices can be equal or unequal.

[0074] It should be noted that there are two ways to connect the substrate electrode to the target potential point, which can be direct connection or indirect connection. For example, the substrate electrode can also be indirectly connected to the external specified potential through a high-frequency low-impedance device, such as a capacitor. As long as the shielding effect can be achieved, there is no specific limitation.

[0075] In a feasible implementation manner, the target potential point is obtained by an AC phase / line voltage or a DC bus voltage via an impedance voltage divider circuit, and the impedance voltage divider circuit includes a capacitor and / or a resistor.

[0076] When the impedance divider circuit includes capacitors, the target potential point can be the midpoint of the two capacitors, as shown in Figure 5(a); when the impedance divider circuit includes capacitors, the target potential point can be the connection point of multiple capacitors, as shown in Figure 5(b); when the impedance divider circuit includes resistors, the target potential point can be the connection point of two resistors, as shown in Figure 5(c). When the planar device is a planar single-transistor chip or a half-bridge unidirectional chip, the target potential point can be the midpoint of the two capacitors in the DC bus, as shown in Figure 5(d).

[0077] In a feasible implementation manner, the target potential point is a designated potential point in a power module.

[0078] For example, as shown in FIG5(e), the designated potential point in the power module is set as the target potential point.

[0079] In a feasible implementation manner, the average value of the voltage difference between the target potential point and each source in each chip is smaller than a preset value.

[0080] It can be understood that when the planar device includes a planar single-tube chip, the voltage difference between the target potential point and the source of the planar single-tube chip is less than the preset value; when the planar device includes a half-bridge unidirectional chip, the voltage difference between the target potential point and the source of the half-bridge unidirectional chip is less than the preset value; when the planar device includes at least one planar bidirectional chip, the average value of the voltage difference between the target potential point and each source of each planar bidirectional chip is less than the preset value.

[0081] In a feasible embodiment, as shown in FIG6 , the at least one chip 110 is a planar single-tube chip;

[0082] A source electrode 130 , a gate electrode 140 and a drain electrode 150 are provided on a side of the planar single-tube chip 110 away from the substrate 120 .

[0083] For example, as shown in FIG7 , a source electrode 130 , a gate electrode 140 and a drain electrode 150 are provided on a side of the planar single-tube chip 110 away from the substrate 120 .

[0084] The equivalent circuit symbol for a planar device equipped with a planar single-chip is shown in Figure 8, where G represents the gate, S represents the source, D represents the drain, and BS represents the substrate electrode. The substrate electrode 121 of the substrate 120 is suspended and connected to a target potential point. It should be noted that the substrate electrode BS can be electrically connected to the source or drain outside the planar device, thereby providing the target potential point via the phase / neutral line connected to the source or drain.

[0085] In a feasible embodiment, as shown in FIG9 , the at least one chip 110 is a half-bridge unidirectional chip, and the planar device further includes: a half-bridge midpoint 160 ;

[0086] As shown in FIG10 , the half-bridge unidirectional chip 110 is provided with a first source 130 ( S1 ), a first drain 150 ( D1 ), a first gate 140 ( G1 ) and a second gate 140 ( G2 ) on a side away from the substrate 120 ;

[0087] The first source 130 ( S1 ), the first drain 150 ( D1 ), the first gate 140 ( G1 ), the second gate 140 ( G2 ) and the half-bridge midpoint 160 ( HN ) are respectively connected to the half-bridge unidirectional chip.

[0088] The equivalent circuit symbol corresponding to the planar device equipped with a half-bridge unidirectional chip is shown in Figure 11, where G1 is the first gate, G2 is the second gate, S is the source, D is the drain, BS is the substrate electrode, and HN is the midpoint of the half bridge.

[0089] In an embodiment of the present application, two planar single-tube chips are grown on a substrate to form a half-bridge unidirectional chip, the two planar single-tube chips are electrically connected and the midpoint of the half-bridge is led out, and the substrate is connected to a low-frequency potential point or a static potential point, thereby shielding the high-frequency changes in the potential on the chip, reducing the electromagnetic interference between the chip and the heat sink, and thereby improving the integration of the application circuit.

[0090] It should be noted that the maximum performance of a bidirectional switch cannot be achieved by combining two unidirectional transistors. For example, as shown in FIG12(a), the maximum performance of a bidirectional switch cannot be achieved by combining two insulated gate bipolar transistors. Transistor (IGBT) realizes the bidirectional switching function. When the IGBT has an anti-parallel diode, it needs to be connected in series to realize the bidirectional switching function. The first IGBT has a gate G1, an emitter E1 and a collector C1, and the second IGBT has a gate G2, an emitter E2 and a collector C2. The emitter E2 of the second IGBT is connected to the collector C1 of the first IGBT to realize the bidirectional switching; or, as shown in Figure 12(b), the IGBT does not have an anti-parallel diode and needs to be connected in parallel to realize the bidirectional switching function. The first IGBT has a gate G1, an emitter E1 and a collector C1, and the second IGBT has a gate G2, an emitter E2 and a collector C2. The emitter E1 of the first IGBT is connected to the collector C2 of the second IGBT, and the emitter E2 of the second IGBT is connected to the collector C1 of the first IGBT to realize the bidirectional switching; or, the bidirectional switching function can also be realized by two enhancement mode metal oxide semiconductor field effect transistors (EMMTs). Transistor (MOSFET), referred to as MOS tube, as shown in Figure 12(c), uses two N-channel enhancement-mode MOS tubes to achieve a bidirectional switch function. The first N-channel enhancement-mode MOS tube has a gate G1, a source S1, and a drain D1, and the second N-channel enhancement-mode MOS tube has a gate G2, a source S2, and a drain D2. The source S1 of the first N-channel enhancement-mode MOS tube is connected to the source S2 of the second N-channel enhancement-mode MOS tube to achieve a bidirectional switch. Compared to the solution of using two unidirectional tubes to achieve a bidirectional switch, the embodiment of the present application provides a bidirectional chip, which integrates two planar single-tube chips on the same substrate to achieve bidirectional blocking and conducting functions. Compared to the combination of two planar devices (each planar device is provided with a planar single-tube chip, such as a GaN chip), the planar device with a bidirectional chip can effectively reduce size, cost, and parasitic parameters.

[0091] In a feasible embodiment, as shown in FIG13 , the at least one chip 110 is a planar bidirectional chip;

[0092] A first source 130 , a second source 130 , a first gate 140 , and a second gate 140 are provided on a side of the planar bidirectional chip away from the substrate 120 ;

[0093] The first source 130 ( S1 ), the second source 130 ( S2 ), the first gate 140 ( G1 ), and the second gate 140 ( G2 ) are respectively connected to the planar bidirectional chip.

[0094] As shown in FIG14 , a first source S1 , a second source S2 , a first gate G1 and a second gate G2 are provided on a side of the planar bidirectional chip away from the substrate 120 ;

[0095] The first source S1, the second source S2, the first gate G1, and the second gate G2 are respectively connected to the planar bidirectional chip. The equivalent circuit symbol corresponding to the planar device equipped with the planar bidirectional chip is shown in FIG15 , where G1 is the first gate, G2 is the second gate, S1 is the first source, S2 is the second source, and BS is the substrate electrode.

[0096] In a feasible embodiment, as shown in FIG16 , the at least one chip includes a first planar bidirectional chip and a second planar bidirectional chip, and the planar device further includes: a half-bridge midpoint 160 ;

[0097] A first source 130 ( S1 ), a first gate 140 ( G1 ) and a second gate 140 ( G2 ) are provided on a side of the first planar bidirectional chip away from the substrate 120 ;

[0098] A second source 130 ( S2 ), a third gate 140 ( G3 ) and a fourth gate 140 ( G4 ) are provided on a side of the second planar bidirectional chip away from the substrate 120 ;

[0099] The first source S1, the first gate G1 and the second gate G2 are respectively connected to the first side of the first planar bidirectional chip, the second source S2, the third gate G3 and the fourth gate G4 are respectively connected to the first side of the second planar bidirectional chip, and the second side of the first planar bidirectional chip is connected to the second side of the second planar bidirectional chip and led out to the half-bridge midpoint 160.

[0100] As shown in FIG17 , a first source S1 , a first gate G1 and a second gate G2 are provided on a side of the first planar bidirectional chip away from the substrate 120 ;

[0101] A second source S2, a third gate G3 and a fourth gate G4 are provided on a side of the second planar bidirectional chip away from the substrate 120;

[0102] The first source S1, the first gate G1 and the second gate G2 are respectively connected to the first side of the first planar bidirectional chip, the second source S2, the third gate G3 and the fourth gate G4 are respectively connected to the first side of the second planar bidirectional chip, and the second side of the first planar bidirectional chip is connected to the second side of the second planar bidirectional chip and led out to the half-bridge midpoint 160.

[0103] The equivalent circuit symbol corresponding to the planar device with two planar bidirectional chips is shown in Figure 18, where G1 is the first gate, G2 is the second gate, G3 is the third gate, G4 is the fourth gate, S1 is the first source, S2 is the second source, BS is the substrate electrode, and HN is the midpoint of the half bridge.

[0104] In an embodiment of the present application, two planar bidirectional chips are grown on two substrates, the two planar bidirectional chips are electrically connected and the midpoint pole of the half-bridge is brought out, and the substrate is connected to a low-frequency potential point or a static potential point, thereby shielding the high-frequency changes in potential on the chip, reducing the electromagnetic interference between the chip and the heat sink, and thereby improving the integration of the application circuit.

[0105] It should be noted that, in actual application, any of the above-mentioned planar devices also needs to dissipate heat through an insulating medium 170 and a heat sink 180. For example, as shown in FIG19 , the insulating medium 170 is arranged between the substrate 120 and the heat sink 180, that is, the insulating medium 170 is arranged below the substrate 120, and the heat sink 180 is arranged below the insulating medium 170.

[0106] In this embodiment, the substrate 120 is connected to a target potential point with low-frequency changes or no potential changes. The high-frequency current generated by the high-frequency changes in potential on the chip 110 is only between the chip and the substrate 120. There is no high-frequency changing voltage between the substrate 120 and the radiator 180. Therefore, the current without high-frequency changing flows between the substrate 120 and the radiator 180 through the parasitic capacitance, thereby eliminating or reducing the impact of electromagnetic interference.

[0107] It should be noted that when the substrate 120 uses copper 121 on one side of the DBC, the ceramic plate 122 in the DBC can play an insulating role, and the copper on the other side of the DBC can also play a heat dissipation role, forming a heat dissipation copper substrate 123, as shown in FIG20 ;

[0108] The ceramic plate 122 is positioned in the center of the DBC, and copper is placed on both sides of the DBC. Specifically, the DBC-side copper 121, ceramic plate 122, and heat-dissipating copper substrate 123 of the DBC substrate simultaneously provide insulation and heat dissipation. When a DBC substrate is used as substrate 120, the DBC substrate is bonded directly to the heat sink 180 without requiring the insulating medium 170 to pass through.

[0109] In the embodiment of the present application, by connecting the substrate in the planar device to the target potential point, high-frequency potential changes on the chip in the planar device are shielded, thereby reducing electromagnetic interference between the chip and the heat sink.

[0110] Please refer to Figures 21-27. Different planar devices are connected in different ways in the circuit. Different circuits have different wiring methods for bidirectional switches. For example, for single-phase half-bridge circuits, single-phase full-bridge circuits, and three-phase bridge circuits, the corresponding wiring methods are different when using the planar devices shown in Figures 8, 11, 15, or 18.

[0111] An embodiment of the present application provides a switching function circuit, in which a planar device adopts the planar single-tube chip shown in Figure 8, including at least two planar devices and a DC bus; the at least two planar devices include a first planar device located on the upper tube of the first bridge arm and a second planar device located on the lower tube of the first bridge arm; the drain of the first planar device is connected to the first end of the DC bus and the single-phase AC phase line; the source of the second planar device is connected to the second end of the DC bus and the neutral line; the source of the first planar device is connected to the drain of the second planar device.

[0112] For example, when the planar device shown in Figure 8 is used in a single-phase half-bridge circuit, the corresponding circuit is shown in Figure 21, where the sources or drains of the two planar devices that are not connected to the DC bus positive electrode BUS+ or the DC bus negative electrode BUS- are connected to each other, and the potential at point x is derived; the DC bus positive electrode BUS+ is connected to the drain D of the first planar device in the first bridge arm, and the DC bus negative electrode BUS- is connected to the source S of the second planar device in the first bridge arm; a bus unit consisting of a first capacitor C1 and a second capacitor C2 is located between the DC bus positive electrode BUS+ and the DC bus negative electrode BUS-; the substrate electrode BS of the first planar device is connected to the substrate electrode BS of the second planar device, and is derived to the midpoint o of the capacitor, where the potential at point x represents a high-frequency change in potential, and the potential at point o does not change.

[0113] Optionally, when the planar device shown in Figure 8 is used in a single-phase full-bridge circuit, the at least two planar devices also include a third planar device located on the upper tube of the second bridge arm and a fourth planar device located on the lower tube of the second bridge arm; the drain of the third planar device is connected to the positive pole of the DC bus; the source of the fourth planar device is connected to the negative pole of the DC bus; and the source of the third planar device is connected to the drain of the fourth planar device.

[0114] An embodiment of the present application provides a switching function circuit, wherein the planar device adopts the half-bridge unidirectional chip shown in Figure 11, including at least one planar device and a DC bus; the drain of each planar device is connected to the positive pole of the DC bus; the source of each planar device is connected to the negative pole of the DC bus.

[0115] For example, when the planar device shown in Figure 11 is used in a single-phase half-bridge circuit, the corresponding circuit is shown in Figure 22, where the midpoint of the half bridge of the planar device leads to the point x potential; the DC bus positive pole BUS+ is connected to the drain D of the planar device, and the DC bus negative pole BUS- is connected to the source S of the planar device; between the DC bus positive pole BUS+ and the DC bus negative pole BUS- is a bus unit composed of a first capacitor C1 and a second capacitor C2; the substrate electrode BS of the planar device is connected to the midpoint o of the capacitor, where the point x potential represents the high-frequency change of potential, and the point o potential does not change.

[0116] An embodiment of the present application provides a switching function circuit, wherein the planar device adopts the planar bidirectional chip shown in Figure 15, including at least two planar devices and a filtering unit, the filtering unit including at least one capacitor; the at least two planar devices include a first planar device located on the upper tube of the first bridge arm and a second planar device located on the lower tube of the first bridge arm; the first source of the first planar device is connected to the first end of the filtering unit and one end of the two single-phase alternating current lines; the first source of the second planar device is connected to the second end of the filtering unit and the other end of the two single-phase alternating current lines; the second source of the first planar device is connected to the second source of the second planar device.

[0117] For example, when the planar device shown in Figure 15 is used in a single-phase half-bridge circuit (that is, a planar bidirectional chip is provided in the planar device), the corresponding circuit is shown in Figure 23(a), where the substrate electrode BS of each planar device is connected and led to the potential point o; the first source S1 of the first planar device is connected to the first end of the filter unit and one end of the two single-phase AC lines; the first source S1 of the second planar device is connected to the second end of the filter unit and the other end of the two single-phase AC lines; the second source S2 of the first planar device is connected to the second source S2 of the second planar device, and the x-point potential is led out, and the filtering unit composed of the first capacitor C1 is between the two single-phase AC lines (phase line L and neutral line N); one end of the first capacitor C1 is determined as the potential point o, where the x-point potential represents the high-frequency change of the potential, and the o-point potential changes with the L / N AC low-frequency.

[0118] It can be understood that the filtering unit can also include two capacitors. For example, the filtering unit includes a first capacitor and a second capacitor; then the first end of the first capacitor is the first end of the filtering unit, the first end of the second capacitor is the second end of the filtering unit, and the second end of the first capacitor is connected to the second end of the second capacitor.

[0119] For example, when the planar device shown in Figure 15 is used in a single-phase half-bridge circuit (that is, a planar bidirectional chip is provided in the planar device), the corresponding circuit is shown in Figure 23(b), where the substrate electrode BS of each planar device is connected and led to the potential point o; the first source S1 of the first planar device is connected to the first end of the filter unit and one end of the two single-phase AC lines; the first source S1 of the second planar device is connected to the second end of the filter unit and the other end of the two single-phase AC lines; the second source S2 of the first planar device and the second source S2 of the second planar device are connected, and the x-point potential is led out, and the filtering unit composed of the first capacitor C1 and the second capacitor C2 is between the two single-phase AC lines (phase line L and neutral line N); the midpoint between the first capacitor C1 and the second capacitor C2 is determined as the potential point o, where the x-point potential represents the high-frequency change of the potential, and the o-point potential changes with the low frequency of the L / N AC or does not change.

[0120] It should be noted that the connection method with the target potential point can be direct connection, as shown in Figure 23(a) or 23(b), the substrate electrode BS is directly connected to the target potential point o; it can also be indirect connection, as shown in Figure 23(c). When indirectly connected, it is indirectly connected to the target potential point through a high-frequency low-impedance device (for example, capacitor C4). As long as the shielding effect can be achieved, there is no specific limitation.

[0121] It can be understood that in the above-mentioned single-phase half-bridge circuit using the planar device shown in FIG15, the substrate electrodes of the two planar devices are connected together and then led to the target potential point. In this embodiment, the substrate electrodes of the two planar devices can also be connected to different potential points respectively through a preset circuit structure. On the basis of the single-phase half-bridge circuit using the planar device shown in FIG15, the single-phase half-bridge circuit can also include 4 diodes. As shown in FIG23(d), the substrate electrode BS of the first planar device is connected to the cathode of the first diode D1 and the second diode D2; the substrate electrode BS of the second planar device is connected to the cathode of the third diode D3 and the fourth diode D4. The first source S1 of the first planar device is connected to the first end of the filtering unit, one end of the two single-phase AC power lines, the anode of the first diode D1, and the anode of the third diode D3; the first source S1 of the second planar device is connected to the second end of the filtering unit, the other end of the two single-phase AC power lines, the anode of the second diode D2, and the anode of the fourth diode D4; the second source S2 of the first planar device is connected to the second source S2 of the second planar device, and the x-point potential is derived. The filtering unit composed of the first capacitor C1 and the second capacitor C2 is between the two single-phase AC power lines (the phase line L and the neutral line N); wherein the x-point potential represents the high-frequency change of the potential.

[0122] When the voltage at one end of the single-phase AC power line is higher than the other end (the voltage of the phase line L is greater than the voltage of the neutral line N), the first diode D1 and the third diode D3 conduct, and the substrate electrode BS of the first planar device (the upper diode of the bridge arm) and the second planar device (the lower diode of the bridge arm) approach the potential point of the phase line L and vary with the low frequency of L. After the voltage is reversed (the voltage at one end of the single-phase AC power line is lower than the voltage at the other end of the single-phase AC power line, that is, the voltage of the phase line L is lower than the voltage of the neutral line N), the second diode D2 and the fourth diode D4 conduct, and the substrate electrode BS of the first planar device (the upper diode of the bridge arm) and the second planar device (the lower diode of the bridge arm) approach the potential point of the neutral line N and vary with the low frequency of N. This ensures that the substrate electrodes always approach the highest potential point when the AC power changes.

[0123] As shown in Figure 23(e), the substrate electrode BS of the first planar device is connected to the anode of the first diode D1 and the second diode D2; the substrate electrode BS of the second planar device is connected to the anode of the third diode D3 and the fourth diode D4; the first source S1 of the first planar device is connected to the first end of the filtering unit, one end of the two single-phase AC lines, the cathode of the first diode D1 and the cathode of the third diode D3; the first source S1 of the second planar device is connected to the second end of the filtering unit, the other end of the two single-phase AC lines, the cathode of the second diode D2 and the cathode of the fourth diode D4; the second source S2 of the first planar device is connected to the second source S2 of the second planar device, and the x-point potential is derived. Between the two single-phase AC lines (phase line L and neutral line N) is a filtering unit composed of a first capacitor C1 and a second capacitor C2; wherein the x-point potential represents the high-frequency change of potential.

[0124] When the voltage at one end of the single-phase AC power line is higher than the other end (the voltage of the phase line L is greater than the voltage of the neutral line N), the second diode D2 and the fourth diode D4 conduct, and the substrate electrode BS potential of the first planar device (the upper diode of the bridge arm) and the second planar device (the lower diode of the bridge arm) approaches the neutral line N potential point and varies with the low frequency of N. After the voltage is reversed (the voltage at one end of the single-phase AC power line is lower than the other end of the single-phase AC power line, that is, the voltage of the phase line L is lower than the voltage of the neutral line N), the first diode D1 and the third diode D3 conduct, and the substrate electrode BS potential of the first planar device (the upper diode of the bridge arm) and the second planar device (the lower diode of the bridge arm) approaches the phase line L potential point and varies with the low frequency of L. This ensures that the substrate electrodes always approach the lowest potential point when the AC power changes.

[0125] An embodiment of the present application provides a switching function circuit, in which the planar device adopts the planar bidirectional chip shown in Figure 15. Based on Figure 23(b), the at least two planar devices also include a third planar device located on the upper tube of the second bridge arm and a fourth planar device located on the lower tube of the second bridge arm; the first source of the third planar device is connected to the first end of the DC bus and the single-phase AC phase line; the first source of the fourth planar device is connected to the second end of the DC bus and the single-phase AC neutral line; the second source of the third planar device is connected to the second source of the fourth planar device.

[0126] For example, when the planar device shown in FIG15 is used in a single-phase full-bridge circuit, the corresponding circuit can also be shown in FIG24(a), including a first bridge arm and a second bridge arm, wherein the second sources S2 of the two planar devices (the first planar device and the third planar device) on the first bridge arm are connected to each other and lead to the x-point potential; the second sources S2 of the two planar devices (the second planar device and the fourth planar device) on the second bridge arm are connected to each other and lead to the y-point potential; one end of the two single-phase AC wires (phase line L) is connected to the first source S1 of the first planar device located on the first bridge arm and the third planar device located on the second bridge arm, and the other end of the two single-phase AC wires (neutral line L) is connected to the first source S1 of the first planar device located on the first bridge arm and the third planar device located on the second bridge arm. N) is connected to the first source S1 of the second planar device located at the bottom tube of the first bridge arm and the fourth planar device located at the bottom tube of the second bridge arm. A filtering unit consisting of a first capacitor C1 and a second capacitor C2 is located between the two lines of single-phase alternating current (phase line L and neutral line N). The midpoint between the first capacitor C1 and the second capacitor C2 is determined as the potential static point o. The substrate electrode BS of the first planar device is connected to the substrate electrode BS of the second planar device, the substrate electrode BS of the third planar device, and the substrate electrode BS of the fourth planar device, and is led to the midpoint o of the filtering unit. Among them, the potential at point x / y represents the high-frequency change of potential, and the potential at point o changes with the low frequency of the L / N alternating current or does not change.

[0127] It should be noted that the connection method with the target potential point can be direct connection, as shown in Figure 24(a), the substrate electrode BS is directly connected to the target potential point o; it can also be indirect connection, as shown in Figure 24(b). When indirectly connected, it is indirectly connected to the target potential point through a high-frequency low-impedance device (for example, capacitor C4). As long as the shielding effect can be achieved, there is no specific limitation.

[0128] An embodiment of the present application provides a switching function circuit, in which a planar device adopts the planar bidirectional chip shown in Figure 15, three planar devices, a first impedance, a second impedance, a third impedance, a first capacitor, a second capacitor and a third capacitor; the three planar devices include a first planar device located in the first bridge arm, a second planar device located in the second bridge arm and a third planar device located in the third bridge arm; the first AC phase line is connected to the second source of the first planar device and the first end of the first capacitor through the first impedance; the second AC phase line is connected to the second source of the second planar device and the first end of the second capacitor through the second impedance; the third AC phase line is connected to the second source of the third planar device and the first end of the third capacitor through the third impedance; the first source of the first planar device is connected to the first source of the second planar device and the first source of the third planar device; the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are connected.

[0129] For example, when the planar device shown in FIG15 is used in a three-phase half-controlled bridge circuit, the corresponding circuit is shown in FIG25(a), including a first bridge arm, a second bridge arm and a third bridge arm. The second source S2 in the first planar device on the first bridge arm is connected to the first end of the first capacitor C1, and is led from the connection point through the first impedance Z1 to the A-phase AC phase line (first AC phase line); the second source S2 in the second planar device on the second bridge arm is connected to the first end of the second capacitor C2, and is led from the connection point through the second impedance Z2 to the B-phase AC phase line (second AC phase line); the second source S2 in the third planar device on the third bridge arm is connected to the first end of the second capacitor C1, and is led from the connection point through the second impedance Z2 to the B-phase AC phase line (second AC phase line); The first ends of the three capacitors C3 are connected and led from the connection point to the C-phase AC phase line (third AC phase line) through the third impedance Z3; the first source electrodes S1 of the first planar device, the second planar device, and the third planar device are connected and lead to the x-point potential; the second ends of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are connected and lead to the o-point potential; the substrate electrode BS of the first planar device, the substrate electrode BS of the second planar device, and the substrate electrode BS of the third planar device are all connected to the o-point potential, where the x-point potential represents a high-frequency change in potential, and the o-point potential changes with the A / B / C alternating current at a low frequency or does not change.

[0130] It should be noted that the connection method with the target potential point can be direct connection or indirect connection, as shown in Figure 25(a), the substrate electrode is directly connected to the static potential point o, or it can be indirectly connected to the target potential point through a high-frequency low-impedance device (for example, a capacitor), or it can be a mixed connection, as shown in Figure 25(b), the substrate electrode of the first planar device is indirectly connected to point o through the first capacitor C1, the substrate electrode of the second planar device is indirectly connected to point o through the fourth capacitor C4, and the substrate electrode of the third planar device is directly connected to point o, that is, Figure 25(b) is a mixed connection (that is, it includes both direct connection and indirect connection). As long as the connection method adopted can achieve the shielding effect, it is not limited here.

[0131] The embodiment of the present application provides a switching function circuit, in which the planar device adopts the planar bidirectional chip shown in Figure 15, including six planar devices, a first impedance, a second impedance, a third impedance, a first capacitor, a second capacitor and a third capacitor; the six planar devices include a first planar device located on the upper tube of the first bridge arm, a second planar device located on the upper tube of the second bridge arm, a third planar device located on the upper tube of the third bridge arm, a fourth planar device located on the lower tube of the first bridge arm, a fifth planar device located on the lower tube of the second bridge arm and a sixth planar device located on the lower tube of the third bridge arm; the first AC phase line is connected to the second source of the fourth planar device and the second source of the first planar device through the first impedance; the second AC phase line is connected to the fifth planar device through the second impedance The second source of the planar device and the second source of the second planar device are connected; the third AC phase line is connected to the second source of the sixth planar device and the second source of the third planar device through the third impedance; the first source of the first planar device is connected to the first source of the second planar device and the first source of the third planar device; the first source of the fourth planar device is connected to the first source of the fifth planar device and the first source of the sixth planar device; the first end of the first capacitor is connected to the first AC phase line, the first end of the second capacitor is connected to the second AC phase line, the first end of the third capacitor is connected to the third AC phase line, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are connected.

[0132] For example, when the bidirectional switch shown in FIG15 is used in a three-phase fully controlled bridge circuit, the corresponding circuit is shown in FIG26(a), including a first bridge arm, a second bridge arm, and a third bridge arm. The second sources S2 of the two planar devices (the first planar device and the fourth planar device) on the first bridge arm are connected to each other and are led from the connection point through the first impedance Z1 to the A-phase AC line (the first-phase AC line); the second sources S2 of the two planar devices (the second planar device and the fifth planar device) on the second bridge arm are connected to each other and are led from the connection point through the second impedance Z2 to the B-phase AC line (the second AC line); the second sources S2 of the two planar devices (the third planar device and the sixth planar device) on the third bridge arm are connected to each other and are led from the connection point through the third impedance Z3 to the C-phase AC line (the third AC line). line); the first source electrodes S1 of the first planar device, the third planar device, and the fifth planar device are connected, and the x point potential is derived; the first source electrodes S1 of the second planar device, the fourth planar device, and the sixth planar device are connected, and the y point potential is derived; the first end of the first capacitor C1 is connected to the A phase AC line, the first end of the second capacitor C2 is connected to the B phase AC line, the first end of the third capacitor C3 is connected to the C phase AC line, the second end of the first capacitor C1, the second end of the second capacitor C2, and the second end of the third capacitor C3 are connected to obtain a common connection point o; the substrate electrodes BS of each planar device 30 are interconnected and derived to the common connection point o; wherein, on the planar device, the x / y point potential represents the high-frequency change of the potential, and the o point potential changes with the A / B / C alternating current at a low frequency or does not change.

[0133] It should be noted that the connection method with the target potential point can be direct connection, as shown in Figure 26(a), the substrate electrode BS is directly connected to the target potential point o; it can also be indirect connection, as shown in Figure 26(b). When indirectly connected, it is indirectly connected to the target potential point through a high-frequency low-impedance device (for example, capacitor C4). As long as the shielding effect can be achieved, there is no specific limitation.

[0134] An embodiment of the present application provides a switching function circuit, in which the planar device adopts the planar bidirectional chip shown in Figure 18, including at least one planar device and a filter capacitor, and the filter capacitor includes at least one capacitor; the first source of each planar device is connected to the first end of the filter unit and one end of the two single-phase alternating current lines; the second source of each planar device is connected to the second end of the filter unit and the other end of the two single-phase alternating current lines.

[0135] For example, when the planar device shown in Figure 18 is used in a single-phase full-bridge circuit, the corresponding circuit is shown in Figure 27(a), including a first planar device and a second planar device, the midpoint of the half bridge of the first planar device leads to the y-point potential; the midpoint of the half bridge of the second planar device leads to the x-point potential; the first source S1 of each planar device is connected to the first end of the filtering unit and one end of the two single-phase AC lines; the second source S2 of each planar device is connected to the second end of the filtering unit and the other end of the two single-phase AC lines; the filtering unit composed of the first capacitor C1 is between the two single-phase AC lines (phase line L and neutral line N); the substrate BS of each planar device is connected and led to the potential point o, where the x-point potential represents the high-frequency change of the potential, and the o-point potential changes with the low-frequency change of the L / N AC.

[0136] It can be understood that the filtering unit can also include two capacitors. For example, the filtering unit includes a first capacitor and a second capacitor; then the first end of the first capacitor is the first end of the filtering unit, the first end of the second capacitor is the second end of the filtering unit, and the second end of the first capacitor is connected to the second end of the second capacitor.

[0137] For example, when the planar device shown in Figure 18 is used in a single-phase full-bridge circuit, the corresponding circuit is shown in Figure 27(b), including a first planar device and a second planar device, the midpoint of the half bridge of the first planar device leads to the y-point potential; the midpoint of the half bridge of the second planar device leads to the x-point potential; the first source S1 of each planar device is connected to the first end of the filtering unit and one end of the two single-phase AC lines; the second source S2 of each planar device is connected to the second end of the filtering unit and the other end of the two single-phase AC lines; the filtering unit composed of the first capacitor C1 and the second capacitor C2 is between the two single-phase AC lines (phase line L and neutral line N); the substrate BS of each planar device is connected and led to the potential point o, where the x-point potential represents the high-frequency change of the potential, and the o-point potential changes with the low frequency of the L / N AC or does not change.

[0138] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0139] In addition, in the description of the embodiments of this application, unless otherwise specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0140] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0141] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0142] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art who is familiar with the technical field can still modify the technical solutions described in the above embodiments within the technical scope disclosed in the present application, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A planar device, characterized in that: include: at least one chip and a substrate; The chip includes a substrate; The substrate is arranged on a side of the chip close to the base plate, and the substrate is electrically connected to the base plate; At least one source and at least one gate are arranged on a side of the chip away from the substrate; The at least one source electrode and the at least one gate electrode are electrically connected to the chip respectively; The substrate is connected to a target potential point, and the target potential point is used to keep the potential of the substrate in a low-frequency changing state or a constant state.

2. The planar device according to claim 1, characterized in that The planar device further comprises at least one substrate electrode having the same potential as that of the substrate.

3. The planar device according to claim 1, characterized in that The substrate is a copper substrate or a ceramic substrate directly coated with copper on one side.

4. The planar device according to claim 1, characterized in that The target potential point is a static potential point or a low-frequency potential point.

5. The planar device according to claim 1, characterized in that The target potential point is obtained by an AC phase / line voltage or a DC bus voltage via an impedance voltage divider circuit, and the impedance voltage divider circuit includes a capacitor and / or a resistor.

6. The planar device according to claim 1, characterized in that The target potential point is a designated potential point in the power module.

7. The planar device according to claim 1, characterized in that The average value of the voltage difference between the target potential point and each source in each chip is less than a preset value.

8. The planar device according to any one of claims 1 to 7, characterized in that: The at least one chip is a planar single-tube chip; A source electrode, a gate electrode and a drain electrode are arranged on a side of the planar single-tube chip away from the substrate.

9. The planar device according to any one of claims 1 to 7, characterized in that: The at least one chip is a half-bridge type unidirectional chip, and the planar device further comprises: a half-bridge midpoint; A first source, a first drain, a first gate and a second gate are arranged on a side of the half-bridge unidirectional chip away from the substrate; The first source, the first drain, the first gate, the second gate and the midpoint of the half bridge are respectively connected to the half bridge type unidirectional chip.

10. The planar device according to any one of claims 1 to 7, characterized in that: The at least one chip is a planar bidirectional chip; A first source electrode, a second source electrode, a first gate electrode and a second gate electrode are arranged on a side of the planar bidirectional chip away from the substrate; The first source, the second source, the first gate and the second gate are respectively connected to the planar bidirectional chip.

11. The planar device according to any one of claims 1 to 7, characterized in that: The at least one chip includes a first planar bidirectional chip and a second planar bidirectional chip, and the planar device further includes: a half-bridge midpoint; A first source, a first gate and a second gate are disposed on a side of the first planar bidirectional chip away from the substrate; A second source, a third gate and a fourth gate are arranged on a side of the second planar bidirectional chip away from the substrate; The first source, the first gate and the second gate are respectively connected to the first side of the first planar bidirectional chip, the second source, the third gate and the fourth gate are respectively connected to the first side of the second planar bidirectional chip, and the second side of the first planar bidirectional chip is connected to the second side of the second planar bidirectional chip and led to the midpoint of the half bridge.

12. A switch function circuit, characterized in that: comprising at least two planar devices as claimed in claim 8 and a DC bus; The at least two planar devices include a first planar device located on an upper tube of the first bridge arm and a second planar device located on a lower tube of the first bridge arm; The drain of the first planar device is connected to the positive electrode of the DC bus; The source electrode of the second planar device is connected to the negative electrode of the DC bus; The source of the first planar device is connected to the drain of the second planar device.

13. The switch function circuit according to claim 12, characterized in that: The at least two planar devices further include a third planar device located on the upper tube of the second bridge arm and a fourth planar device located on the lower tube of the second bridge arm; The drain of the third planar device is connected to the positive electrode of the DC bus; The source electrode of the fourth planar device is connected to the negative electrode of the DC bus; The source of the third planar device is connected to the drain of the fourth planar device.

14. A switch function circuit, characterized in that: comprising at least one planar device as claimed in claim 9 and a DC bus; The drain of each planar device is connected to the positive electrode of the DC bus; The source of each planar device is connected to the negative electrode of the DC bus.

15. A switch function circuit, characterized in that: comprising at least two planar devices according to claim 10 and a filtering unit, wherein the filtering unit comprises at least one capacitor; The at least two planar devices include a first planar device located on an upper tube of the first bridge arm and a second planar device located on a lower tube of the first bridge arm; The first source electrode of the first planar device is connected to the first end of the filter unit and one end of the two single-phase alternating current lines; The first source electrode of the second planar device is connected to the second end of the filter unit and the other end of the two single-phase alternating current lines; The second source of the first planar device is connected to the second source of the second planar device.

16. The switch function circuit according to claim 15, characterized in that: The at least two planar devices further include a third planar device located on the upper tube of the second bridge arm and a fourth planar device located on the lower tube of the second bridge arm; The first source electrode of the third planar device is connected to the first end of the filter unit and one end of the two single-phase alternating current lines; The first source electrode of the fourth planar device is connected to the second end of the filter unit and the other end of the two single-phase alternating current lines; The second source of the third planar device is connected to the second source of the fourth planar device.

17. A switch function circuit, characterized in that: comprising three planar devices as claimed in claim 10, a first impedance, a second impedance, a third impedance, a first capacitor, a second capacitor and a third capacitor; The three planar devices include a first planar device located in the first bridge arm, a second planar device located in the second bridge arm, and a third planar device located in the third bridge arm; A first AC phase line is connected to the second source of the first planar device and the first end of the first capacitor through the first impedance; The second AC phase line is connected to the second source of the second planar device and the first end of the second capacitor through the second impedance; The third AC phase line is connected to the second source of the third planar device and the first end of the third capacitor through the third impedance; The first source of the first planar device is connected to the first source of the second planar device and the first source of the third planar device; The second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are connected.

18. A switch function circuit, characterized in that: comprising six planar devices as claimed in claim 10, a first impedance, a second impedance, a third impedance, a first capacitor, a second capacitor and a third capacitor; The six planar devices include a first planar device located on the upper tube of the first bridge arm, a second planar device located on the upper tube of the second bridge arm, a third planar device located on the upper tube of the third bridge arm, a fourth planar device located on the lower tube of the first bridge arm, a fifth planar device located on the lower tube of the second bridge arm, and a sixth planar device located on the lower tube of the third bridge arm; A first AC phase line is connected to the second source of the fourth planar device and the second source of the first planar device through the first impedance; The second AC phase line is connected to the second source of the fifth planar device and the second source of the second planar device through the second impedance; The third AC phase line is connected to the second source of the sixth planar device and the second source of the third planar device through the third impedance; The first source of the first planar device is connected to the first source of the second planar device and the first source of the third planar device; The first source of the fourth planar device is connected to the first source of the fifth planar device and the first source of the sixth planar device; The first end of the first capacitor is connected to the first AC phase line, the first end of the second capacitor is connected to the second AC phase line, the first end of the third capacitor is connected to the third AC phase line, and the second end of the first capacitor, the second end of the second capacitor and the second end of the third capacitor are connected.

19. A switch function circuit, characterized in that: comprising at least one planar device as claimed in claim 11 and a filter capacitor, wherein the filter capacitor comprises at least one capacitor; The first source electrode of each planar device is connected to the first end of the filter unit and one end of the two single-phase alternating current lines; The second source of each planar device is connected to the second end of the filter unit and the other end of the two single-phase alternating current lines.

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