Programmable slew rate control of cascode power devices

Abstract

A slew rate controller for cascode devices is disclosed, A slew rate controller in accordance with an aspect of the present disclosure may include a cascode device, which includes a first device and a second device coupled in cascode with the first device. A charge storage device, may be coupled between the first device and the second device. The charge storage device may control the slew rate of the cascode device.

Description

PROGRAMMABLE SLEW RATE CONTROL OF CASCODE POWER DEVICESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application Serial No. 63 / 608,010, filed on December 8, 2023, entitled “PROGRAMMABLE SLEW RATE CONTROL OF CASCODE POWER DEVICES,” and claims all the benefits derived from the priority filing date in all jurisdictions.FIELD OF DISCLOSURE

[0002] The present invention relates generally to slew rate control in power converters, and more specifically to programmable slew rate control of cascode power devices. BACKGROUND INFORMATION

[0003] Due to their high efficiency, small size, and low weight, switched mode power converters are often used in powering today's electronics from conventional wall sockets. According to switch-mode power-converter practice, high-voltage alternating-current (ac) input is converted into a well-regulated direct-current (de) output through an energy transfer element (e.g., a transformer). The switched mode power converter controller usually provides output regulation by sensing one or more inputs representative of one or more output quantities and controlling the output in a closed loop. In operation, a switch is utilized to provide the desired output by varying the duty cycle (typically the ratio of the on time of the switch to the total switching period), varying the switching frequency, or varying the number of pulses per unit time of the switch in a switched mode power converter.

[0004] One type of switch mode power converter is a resonant converter, which includes a resonant circuit (e.g., inductor(s) and capacitor(s)) as part of a power stage. A resonant circuitmay advantageously enhance power conversion efficiency by availing zero-current and / or zerovoltage switching.

[0005] A subset of resonant converters, the series inductor-inductor capacitor (LLC) converter, uses a resonant circuit with two inductors and one capacitor connected in series to form an LLC resonant circuit. Commonly, the power stage of an LLC converter is controlled so that power stage switches (e.g. , high-side and low-side devices) undergo zero-voltage switching (ZVS).

[0006] Other examples of converter topologies include a three-phase alternating current (AC) input active front end (AFE) topology and the bridgeless totem pole power factor correction (PFC) topology. Unlike resonant converter topologies, the three-phase ac input AFE topology and the bridgeless totem pole PFC topology undergo hard switching.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of slew rate control of cascode power devices are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] FIG. 1A illustrates a (half bridge LLC) power converter including variable gate driver circuits according to an embodiment.

[0009] FIG. IB illustrates a flyback power converter including a variable gate driver circuit according to another embodiment.

[0010] FIG. 1C illustrates a three-phase ac input active front end (AFE) including variable gate driver circuits according to another embodiment.

[0011] FIG. ID illustrates a bridgeless totem pole PFC input stage including variable gate driver circuits according to another embodiment.

[0012] FIG. 2 illustrates a cascode power device according to an embodiment.

[0013] FIG. 3 illustrates a cascode power device according to an embodiment.

[0014] FIG. 4A illustrates a cell device cross section of a depletion mode NFET according to an embodiment.

[0015] FIG. 4B illustrates a charge storage element corresponding to the embodiment of FIG. 4A.

[0016] FIG. 5 illustrates a partial metallization layout of a depletion mode NFET according to the embodiment of FIG. 4A-B.

[0017] FIG. 6 illustrates a top view metallization layout of a depletion mode NFET according to the embodiment of FIG. 5.

[0018] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of slew rate control of cascode power devices. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the teachings herein.DETAILED DESCRIPTION

[0019] In the following description, numerous specific details are set forth in order to provide a thorough understanding of slew rate control of cascode power devices. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the teachings herein. In other instances, well-known materials, components, and / or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0020] Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

[0021] In the context of the present application, when a transistor is in an “off-state” or “off’ the transistor blocks current and / or does not substantially conduct current. Conversely, when a transistor is in an “on-state” or “on” the transistor is able to substantially conduct current. By way of example, in one embodiment, a high-voltage transistor comprises an N-channel field-effect transistor (FET); the N-channel field-effect transistor (FET) may be a metal oxide semiconductor field effect transistor (MOSFET) with the high-voltage being supported between the first terminal, a drain, and the second terminal, a source. In another embodiment the fieldeffect transistor (FET) may be a junction field effect transistor (JFET), a depletion-mode device whereby transport is predominantly by majority carriers. Alternatively, and additionally, the FET may be a gallium nitride (GaN) FET and / or a GaN High Electron Mobility Transport (HEMT) FET device.

[0022] In some embodiments an integrated controller circuit may be used to drive a power switch when regulating energy provided to a load.

[0023] Also, for purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of an electronic circuit or Integrated circuit (IC) are defined or measured.

[0024] As described above one type of switched mode power converter is a resonant converter which uses a resonant circuit, also referred to as a resonant network or “tank” circuit, having inductance(s) and capacitance(s) as part of the power conversion process. Resonant converters may have some advantages compared to non-resonant switched mode power converters, such as soft switching (e.g., zero-voltage switching), generally higher efficiency, lower losses at higher frequency operation, and lower harmonic content in switching waveforms. These in turn can reduce packaging and component costs by allowing the use of smaller magnetic elements and smaller electromagnetic interference (EMI) filters.

[0025] Resonant converters often include a half-bridge circuit. The half-bridge circuit may include a low-side device (i.e., a low-side switch) and a high-side device (z.e., a high-side switch). During operation, the low-side device and high-side device may switch on and offaccording to a switching cycle. Additionally, as described herein, a switching cycle may include a deadtime whereby both the low-side device and high-side device remain off. For instance, there may be a break-before-make period (z.e., a deadtime) to mitigate shoot-through current.According to the teachings herein, during a break-before-make period (i.e., a deadtime) a switchnode voltage may decrease and / or increase (i.e., may “slew”).

[0026] Applications may include any converter topology such as an LLC converter which uses cascode power devices.

[0027] Modem power converters, including resonant converters, often use cascode power devices. A cascode power device may include an enhancement mode device (e.g., an enhancement mode n-channel field effect transistor) connected in cascode with a high-voltage depletion mode device (e.g., a high-voltage gallium nitride (GaN) and / or silicon carbide (SiC) field effect transistor). An enhancement mode device may often be referred to as a “normally off” device, and the depletion mode device may be referred to as a “normally on” device.

[0028] GaN devices may be used as fast switches, and can function at high frequencies. However, GaN devices often use negative voltages to turn off (i.e., stop carrying current). In integrated circuits (ICs), providing both positive and negative voltages is difficult on a single chip or die.

[0029] GaN transistors are often used in a cascode structure with a low voltage (LV) metal-oxide-semiconductor field effect transistor (MOSFET), where a switching signal or pulse is applied to the gate of the MOSFET. The Gate of the GaN device is connected to ground to allow the GaN device to always be on, which allows for the MOSFET to act as the controlling device to allow current to flow through the high power GaN device. The use of a cascode structure provides the advantage of unipolar voltage signals, e.g., always positive voltages, tocontrol the circuitry. However, this approach also has disadvantages, as the speed of turning the cascode circuit on and off, i.e., slew rate, is not as controllable, which could result in the breakdown of the rest of the circuit.

[0030] Additionally, as discussed above some converter topologies may rely on hard switching, a technique which, unlike ZVS, causes a switching device (e.g., high-side device and / or low-side device) to change state with nonzero voltage and current. Unfortunately, hard switching may give rise to higher levels of electromagnetic interference (EMI) and / or degrade converter efficiency. Thus, controlling slew rate in hard switching topologies, like the above mentioned active three phase AFE and the totem pole PFC topologies, may advantageously mitigate (reduce) EMI while improving converter efficiency.

[0031] Accordingly, there is a need for controlling slew rate in power converters using cascode power devices. Programmable slew rate control of cascode power devices is described herein.

[0032] FIG. 1A illustrates a (half bridge LLC) power converter 100 including variable gate driver circuits 143-144 according to an embodiment.

[0033] The power converter 100 may be configured as a half bridge LLC power converter 100; accordingly, it may also be referred to as a half bridge LLC power converter 100 without departing from the scope of the present disclosure.

[0034] As illustrated, power converter 100 includes a primary bridge circuit 103, a resonant transformer 107, a resonant capacitor CRES, rectifiers 71 and 72, an output capacitor Co, a feedback network 112, and a controller 114. The primary bridge circuit 103 includes a switch driver 102 and a half bridge 104. Additionally, the half bridge 104 includes a high-side (HS) cascode power device 126 and a low-side (LS) cascode power device 128. Also, the resonanttransformer 107 includes a transformer 106, a leakage inductor LLK, and a magnetizing inductorLM.

[0035] As illustrated, a direct current (de) input voltage VIN, referenced to ground GND, may be applied at a primary input (z.e., primary supply node NV) of power converter 100. Power converter 100 may convert input power from the primary input into de output power. The de output power may be delivered to the load 113 with a regulated output voltage Vo, referenced to a secondary ground RTN, and with output current Io.

[0036] The leakage inductor LLK, the magnetizing inductor LM, and the resonant capacitor CRES are connected in series between a switch node NSW and ground GND. The controller 114 may provide a drive signal CLKD to the switch driver 102, which in response, may provide a gate drive signal GH to the HS cascode power device 126 and a gate drive signal GL to the LS cascode power device 128.

[0037] Gate drive signals GH and GL may respectively drive the HS cascode power device 126 and LS cascode power device 128 to generate a switch node voltage Vx at switch node NSW. In turn, the switch node voltage Vx may drive the resonant transformer 107.

[0038] During operation, the transformer 106 may provide galvanic isolation between the primary side and the secondary side of power converter 100; in this way, signals on the primary side, referenced to ground GND, may be isolated from signals on the secondary side, referenced to a secondary ground RTN.

[0039] As illustrated, the primary winding 120 is electrically coupled in parallel with the magnetizing inductor LM SO that the in-phase winding terminal, as indicated by the dot (z.e., the dot terminal), connects to the leakage inductor LLK. The secondary winding 122 is electrically connected in series with the rectifier 72 between the secondary ground RTN and the secondaryoutput (z.e., secondary output node NVO) so that the in-phase winding terminal connects to the secondary output node NVO. The secondary winding 124 is electrically connected in series with the rectifier 71 between the secondary ground RTN and the secondary output node NVO so that the in-phase winding terminal connects to the cathode of rectifier 71.

[0040] Additionally, the anodes of rectifiers 71 and 72 both connect to the secondary ground RTN; and the output capacitor Co and the feedback network 112 are electrically coupled in parallel with the load 113 between the secondary output (z.e., secondary output node NVO) and secondary ground RTN. As illustrated, the controller 114 may provide drive signal CLKD based, at least in part, upon the feedback signal FB from the feedback network 112.

[0041] High side (HS) cascode power device 126 includes a first (lower) n-channel field effect transistor (NFET) 155 electrically coupled in cascode with a second (upper) NFET 156. Thus, the source of first (lower) NFET 155 may be electrically coupled to the switch node NSW. The drain of first (lower) NFET 155 may be electrically coupled to the source of second (upper) NFET 156; and the drain of second (upper) NFET 156 may be electrically coupled to primary supply node NV.

[0042] The first (lower) NFET 155 may be an enhancement mode NFET and the second (upper) NFET 156 may be a depletion mode NFET. For instance, the first (lower) NFET 155 may be a lateral and / or vertical enhancement mode NFET with a threshold voltage greater than zero; and the second (upper) NFET 156 may be a gallium nitride (GaN) depletion mode power device capable of sustaining a high drain-to-source voltage (e.g., one-thousand or greater volts). Accordingly, the gate of first (lower) NFET 155 may be electrically coupled to switch driver 102 to receive gate drive signal GH; and a gate of second (upper) NFET 156 may be electricallycoupled to the source of the first (lower) NFET 155. Also, as illustrated, the source of the second(upper) NFET 156 may be electrically coupled to the drain of the first (lower) NFET 155.

[0043] Low side (LS) cascode power device 128 includes a first (lower) n-channel field effect transistor (NFET) 165 electrically coupled in cascode with a second (upper) NFET 166. Thus, the source of first (lower) NFET 165 may be electrically coupled to ground GND. The drain of first (lower) NFET 165 may be electrically coupled to the source of second (upper) NFET 166; and the drain of second (upper) NFET 166 may be electrically coupled to the switch node NSW. Also, as illustrated, the gate of the second (upper) NFET 166 may be electrically coupled to the gate of first (lower) NFET 165 via the charge storage element CGDL.

[0044] The first (lower) NFET 165 may be an enhancement mode NFET and the second (upper) NFET 166 may be a depletion mode NFET. For instance, the first (lower) NFET 165 may be a lateral and / or vertical enhancement mode NFET with a threshold voltage greater than zero; and the second (upper) NFET 166 may be a gallium nitride (GaN) depletion mode power device capable of sustaining a high drain-to-source voltage (e.g., one-thousand or greater volts). Accordingly, the gate of first (lower) NFET 165 may be electrically coupled to switch driver 102 to receive gate drive signal GL; and a gate of second (upper) NFET 166 may be electrically coupled to the source of the first (lower) NFET 165.

[0045] During slew, the switch node voltage Vx may vary and give rise to displacement current (z.e., slew current). For instance, a slew condition at the switch node voltage Vx (z.e., slew) may give rise to a displacement current IXH (z'.e., a slew current IXH) in a charge storage element CGDH between primary supply node NV and the gate of NFET 155. Similarly, a slew condition at the switch node voltage Vx may also give rise to a displacement current IXL (z.e., a slew current IXL) in a charge storage element CGDL between the switch node NSW and the gate offirst (lower) NFET 165. The change in switch node voltage Vx with respect to time, i.e., the derivative of switch node voltage Vx with respect to time dVx / dt, may be referred to as the “slew rate” of the (LS) cascode power device 128 herein.

[0046] According to the teachings herein, the switch driver 102 may provide gate drive signals GH and GL to control slew rate. Controlling slew rate may advantageously protect the HS cascode power device 126 and the LS cascode power device 128; moreover, controlling slew rate may enhance device performance. For instance, controlling slew rate may enhance device performance by reducing supply node and / or ground node ringing.

[0047] The switch driver 102 may include one or more variable gate driver circuits 143, 144 and charge storage elements CGDH, CGDL.

[0048] The structure of FET devices creates natural capacitance for the first (lower) NFET 165 and the second (upper) NFET 166 as shown in FIG. IB. The capacitance of first (lower) NFET 165 and the capacitance of second (upper) NFET 166 may be Miller capacitances. There is no gain due to the cascode structure, and there is no Miller effect on first (lower) NFET 165. The gate of second (upper) NFET 166 is coupled to GND, so Cgan also does not see any switching effect during switching operations.

[0049] The change in current with respect to time (the derivative of current with respect to time) can be controlled by a control voltage, but this may not provide control on slew rate dVx / dt with control voltage. To reduce the slew, a resistor can be added to the gate of second (upper) NFET 166 to produce a time constant for slew rate dVx / dt; however, adding a resistor to the gate of second (upper) NFET 166 may have only a limited effect on slew rate dVx / dt.

[0050] Further, when a resistor is added to the gate of second (upper) NFET 166, noise and oscillation of the overall circuit may occur, and the gate voltage will increase during turnoffof second (upper) NFET 166. As such, the source voltage of second (upper) NFET 166 will increase, which adds to the breakdown of first (lower) NFET 165. The allowable resistance values for such a resistor are small, e.g., 3 Ohms, and the slew rate may be limited when the resistance is at such a maximum (3 Ohms). To make such a device programmable, large switches may be needed when the resistance of the device is smaller than the minimum resistor value, e.g., 0.5 Ohms. These switches may be large, and the cost and size of such switches may make such an approach cost prohibitive.

[0051] Also, according to the teachings herein, the slew rate of the HS cascode power device 126 and LS cascode power device 128 may be improved by increasing the capacitance of charge storage elements CGDH, CGDL.

[0052] According to the teachings herein, charge storage element CGDL may be realized, at least in part, from a field plate of the depletion mode NFET 166; and charge storage element CGDH may be realized, at least in part, from a field plate of the depletion mode NFET 156.

[0053] As illustrated, charge storage element CGDL may be electrically coupled between switch node NSW and the gate of first (lower) NFET 165; and charge storage element CGDH may be coupled between node NV and the gate of second (upper) NFET 166.

[0054] FIG. IB illustrates a power converter 100 including a variable gate driver circuit 143 according to another embodiment. The embodiment of FIG. IB is like that of FIG. 1A except it uses a flyback configuration, and therefore may operate as a flyback converter. Thus, power converter 100 of FIG. IB may also be referred to as a flyback power converter 100 without departing from the scope of the present disclosure. Accordingly, flyback power converter 100 may include an energy transfer element 176 and may exclude a HS cascode power device 126.

[0055] FIG. 1C illustrates a three-phase ac input active front end (AFE) 150 including variable gate driver circuits 143a-c, 144a-c according to another embodiment. The three-phase ac input AFE 150 includes half bridges 104a-c.

[0056] As discussed above, a three-phase ac input AFE 150 may be configured to undergo hard switching, and availing slew rate control may advantageously reduce EMI and enhance performance.

[0057] Half bridges 104a-c may be like half bridge 104 of FIG. 1A. For instance, half bridge 104a includes a HS cascode power device 126a and LS cascode power device 128a. Half bridge 104b includes a HS cascode power device 126b and a LS cascode power device 128b; and half bridge 104c includes a HS cascode power device 126c and a LS cascode power device 128c.

[0058] HS cascode power devices 126a-c may be like HS cascode power device 126 of FIG. 1 A. For instance, HS cascode power device 126a includes an upper NFET 156a, similar to upper NFET 156, and a lower NFET 155a, similar to lower NFET 155. HS cascode power device 126b includes an upper NFET 156b, similar to upper NFET 156, and a lower NFET 155b, similar to lower NFET 155; and HS cascode power device 126c includes an upper NFET 156c, similar to upper NFET 156, and a lower NFET 155c, similar to lower NFET 155.

[0059] Like charge storage element CGDH, charge storage elements CGDHI - CGDH3 are electrically coupled to improve slew rate control. Namely, charge storage element CGDHI is electrically coupled between a drain of upper NFET 156a and a gate of lower NFET 155a. Charge storage element CGDH2 is electrically coupled between a drain of upper NFET 156b and a gate of lower NFET 155b; and charge storage element CGDH3 is electrically coupled between a drain of upper NFET 156c and a gate of lower NFET 155c.

[0060] According to the teachings herein, charge storage elements CGDHI - CGDH3, like charge storage element CGDH, may be realized from a field plate (e.g., a gate field plate) of their respective upper NFETs 156a-c.

[0061] LS cascode power devices 128a-c may be like LS cascode power device 128 of FIG. 1 A. For instance, LS cascode power device 128a includes an upper NFET 166a, similar to upper NFET 166, and a lower NFET 165a, similar to lower NFET 165. LS cascode power device 128b includes an upper NFET 166b, similar to upper NFET 166, and a lower NFET 165b, similar to lower NFET 165; and LS cascode power device 128c includes an upper NFET 166c, similar to upper NFET 166, and a lower NFET 165c, similar to lower NFET 165.

[0062] Like charge storage element CGDL, charge storage elements CGDLI - CGDL3 are electrically coupled to improve slew rate control. Namely, charge storage element CGDLI is electrically coupled between a drain of upper NFET 166a and a gate of lower NFET 165 a. Charge storage element CGDL2 is electrically coupled between a drain of upper NFET 166b and a gate of lower NFET 165b; and charge storage element CGDLS is electrically coupled between a drain of upper NFET 166c and a gate of lower NFET 165c.

[0063] According to the teachings herein, charge storage elements CGDLI - CGDL3, like charge storage element CGDL, may be realized from a field plate (e.g., a gate field plate) of their respective upper NFETs 166a-c.

[0064] Variable gate driver circuits 144a-c are like variable gate driver circuit 144. For instance, variable gate driver circuit 144a provides gate drive signal GH1 to the HS cascode power device 126a (z.e., to the gate of lower NFET 155a). Variable gate driver circuit 144b provides gate drive signal GH2 to the HS cascode power device 126b (z'.e., to the gate of lowerNFET 155b); and variable gate driver circuit 144c provides gate drive signal GH3 to the HS cascode power device 126c (z.e., to the gate of lower NFET 155c).

[0065] According to the teachings herein, variable gate driver circuits 144a-c, like variable gate driver circuit 144, may provide and / or vary their respective gate drive signals (z.e., gate drive signals GH1-GH3) to control slew rate. For instance, a slew rate of switch node voltage Vxi at switch node NSW1 may be controlled by variable gate driver circuit 144a; and as described herein, by virtue of coupling charge storage element CGDHI at the gate of lower NFET 155a, slew rate may be advantageously enhanced. Similarly, slew rate of switch node voltage Vx2 at switch node NSW2 may be controlled by variable gate driver circuit 144b and enhanced by the coupling of charge storage element CGDHZ; and slew rate of switch node voltage Vx3 at switch node NSW3 may be controlled by variable gate driver circuit 144c and enhanced by the coupling of charge storage element CGDH3.

[0066] Variable gate driver circuits 143a-c are like variable gate driver circuit 143. For instance, variable gate driver circuit 143a provides gate drive signal GL1 to the LS cascode power device 128a (z.e., to the gate of lower NFET 165a). Variable gate driver circuit 143b provides gate drive signal GL2 to the LS cascode power device 128b (z.e., to the gate of lower NFET 165b); and variable gate driver circuit 143c provides gate drive signal GL3 to the LS cascode power device 128c (z.e., to the gate of lower NFET 165c).

[0067] Also, according to the teachings herein, variable gate driver circuits 143a-c, like variable gate driver circuit 143, may provide and / or vary their respective gate drive signals (z.e., gate drive signals GL1-GL3) to control slew rate. For instance, a slew rate of switch node voltage Vxi at switch node NSW1 may be controlled by variable gate driver circuit 143a; and as described herein, by virtue of coupling charge storage element CGDHLI at the gate of lower NFET165a, slew rate may be advantageously enhanced. Similarly, slew rate of switch node voltage Vx2 at switch node NSW2 may be controlled by variable gate driver circuit 143b and enhanced by the coupling of charge storage element CGDL2; and slew rate of switch node voltage Vx3 at switch node NSW3 may be controlled by variable gate driver circuit 143 c and enhanced by the coupling of charge storage element CGDL3.

[0068] FIG. ID illustrates a bridgeless totem pole PFC input stage 160 including variable gate driver circuits 143, 144 according to another embodiment.

[0069] As discussed above, a bridgeless totem pole PFC input stage 160 may also be configured to undergo hard switching, and availing slew rate control may advantageously reduce EMI and enhance performance.

[0070] Variable gate driver circuits 143, 144 and half bridge 104 may be like those of FIG. 1A; however, half bridge 104 operates as a high frequency leg in bridgeless totem pole PFC input stage 160.

[0071] The bridgeless totem pole PFC input stage 160 also includes a low frequency leg realized by half bridge 151. Half bridge 151 includes a high side (HS) NFET MN1 and a low side (LS) NFET MN2. High side NFET MN1 receives a gate signal GHX from a gate driver circuit 144x, and low side NFET MN2 receives a gate signal GLX from a gate driver circuit 143x. HS NFET MN1 is electrically coupled to LS NFET MN2 at node NSX; and half bridge 104 and half bridge 151 are coupled at node NVT.

[0072] In accordance with bridgeless totem pole configurations, an ac input 161 and inductor LI are electrically coupled between switch node NSW and node NX.

[0073] According to the teachings herein, the high frequency leg, realized by half bridge104, may be switched with enhanced slew rate control due, at least in part, to gate drive signalsGL GH and / or to charge storage elements CGDH and CGDL. As described herein, charge storage elements CGDH and CGDL may be realized from field plates (e.g., gate field plates) of their upper NFETs 156, 166, respectively.

[0074] FIG. 2 illustrates a cascode power device according to an embodiment.

[0075] As discussed herein, a cascode power device 128 includes a first (lower) n- channel field effect transistor (NFET) 165 electrically coupled in cascode with a second (upper) NFET 166. Second (upper) NFET 166 may be referred to as a depletion mode NFET 166 herein. The source of first (lower) NFET 165 may be electrically coupled to a potential V2, which may be a ground (GND) potential. Potential V2 is, in an aspect of the present disclosure, a lower voltage potential than potential VI, which is electrically coupled to the drain of second (upper) NFET 166. The drain of first (lower) NFET 165 may be electrically coupled to the source of second (upper) NFET 166; and the drain of second (upper) NFET 166 may be electrically coupled to a voltage potential at node V 1. The potential at node V 1 may be higher than the potential at the source of first (lower) NFET 165.

[0076] The first (lower) NFET 165 may be an enhancement mode NFET and the second (upper) NFET 166 may be a depletion mode NFET. For instance, the first (lower) NFET 165 may be a lateral and / or vertical enhancement mode NFET with a threshold voltage greater than zero; and the second (upper) NFET 166 may be a gallium nitride (GaN) depletion mode power device capable of sustaining a high drain-to-source voltage (e.g., a few hundred volts to one- thousand or greater volts). Accordingly, the gate of first (lower) NFET 165 may be electrically coupled to a driver or other circuitry to receive a gate drive signal GL; and a gate of second (upper) NFET 166 may be electrically coupled to the source of the first (lower) NFET 165. A capacitance between switch node NSW and the source of first (lower) NFET 165 is shown ascharge storage element CGD, and a charge storage element CFPD is shown between switch nodeNSW and the gate of first (lower) NFET 165.

[0077] During slew and / or other change in the voltage and / or current at the drain of depletion mode NFET 166, the node voltage VI may vary and give rise to displacement current (i.e., slew current) IDL, i.e., a change in current IDL. For instance, a slew condition may give rise to a displacement current IXL (i.e., a slew current IXL) in charge storage element CFPD between the switch node NSW and the gate of first (lower) NFET 165.

[0078] According to the teachings herein, charge storage element CFPD may be realized, at least in part, from a field plate of the depletion mode NFET 166; and charge storage element CGD may be the remaining, inherent charge storage element (e.g., capacitance) of the field plate device of the depletion mode NFET 166.

[0079] According to the teachings herein, gate drive signal GL selectively allows current to flow in first (lower) NFET 165, which effectively allows current flow through second (upper) NFET 166. By monitoring any change in current IDL (i.e., change in current IXL) via switch node NSW, a gate drive signal GL may be selectively switched on and off to provide switching of the current through cascode power device 128. Such switching may be determined to occur at any point during the change in voltage at node VI or at any value of change in current IDL. In some embodiments, cascode power device 128 may undergo zero voltage switching (ZVS). To effect ZVS, the gate drive signal GL may monitor the current and / or the voltage via charge storage element CGD or charge storage element CFPD.

[0080] In an aspect of the present invention, a device (i.e., depletion mode NFET 166) is provided that allows for the internal capacitance, i.e., the internal charge storage of depletion mode NFET 166, to be divided into at least two sections. One section is internally connected tothe gate of the depletion mode NFET 166 and another section is coupled to a node, called the field plate (FP) node. Other sections may be coupled to other locations or other circuit devices as desired. The ratio of the amount of capacitance devoted to the FP node and the remainder of the capacitance can be varied as desired without departing from the scope of the present disclosure.

[0081] In such a device, which may be used in a cascode structure, the FP node is connected to a control voltage (VCTRL). The control voltage controls the speed of the depletion mode NFET 166 turn on / off times together with first (lower) NFET 165 turn on / off.

[0082] The FP node is coupled to the gate of first (lower) NFET 165, which is driven by one or more gate drivers. To control the slew rate, some of the gate drivers may be placed in a tri-state so the input pulse width modulation (PWM) does not change the on / off state of the device.

[0083] In such an aspect of the present disclosure, the slew rate can be digitally controlled over a wide range. Further, the slew rate can be scaled by changing the capacitor ratio in the GaN instead of changing the gate driver.

[0084] FIG. 3 illustrates a cascode power device 128 according to an embodiment.

[0085] In an aspect of the present disclosure, a variable gate driver circuit 143 (also referred to as a variable gate driver herein) may be implemented as a series of parallel legs 302, 304, 306, and 308. Although four legs 302, 304, 306, 308 are shown, other configurations having a greater or fewer number of legs may be possible without departing from the scope of the present disclosure.

[0086] In an aspect of the present disclosure, one or more of the legs 302, 304, 306, 308 may be energized by the control block 310 and / or the control block 312 to control the voltage and / or current at node Ng. Since node Ng is coupled to an electrode of charge storage elementCFPD, variable gate driver circuit 143 may control the turn-on and turn-off of the cascode power device 314. Variable gate driver circuit 143 may be current dependent, i.e., the drive current to cascode power device 314 may be determined by fixed current sources, or voltage dependent, i.e., the drive current may be determined by gate-path resistance and voltage. Further, monitoring the node NSW and / or node Ng allows for a programmable variable gate driver circuit 143.

[0087] As such, a slew rate controller in accordance with an aspect of the present disclosure may include a cascode power device 314, which includes a low-voltage FET (LVFET) as a first device and a power device (power switch) as a second device coupled in cascode with the first device. As illustrated in FIG. 3, the first device is realized with NFET 165 and the second device is realized with NFET 166. A charge storage device CFPD may be coupled between the first device and the second device. The controller may also include variable gate driver circuit 143, which is coupled to the cascode power device 314. The charge storage device may shunt the gate of the first device to the drain of the second device.

[0088] The slew rate controller may be configured to provide a negative gain from the gate of the first device to the drain of the second device, and the charge storage device may be coupled between the gate of the first device and the drain of the second device as shown in FIG. 3.

[0089] The charge storage device may comprise an external capacitor, or may be an integral part of the second device, such as a field plate. The drain of the second device may be coupled to a switch node NSW as shown in FIG. 3. As described in FIG. 2, the first device may be an enhancement mode n-channel field effect transistor (NFET) and the second device may be a depletion mode NFET. Further, the depletion mode NFET is a depletion mode gallium nitride(GaN) NFET.

[0090] In an aspect of the present disclosure, the cascode power device 128 may be implemented in a power converter 100 as shown in FIGS. 1A and IB. A power converter in accordance with such an aspect may include a cascode power device 128 electrically coupled to an input of the power converter 100, a driver circuit 143 electrically coupled to a control connection of the cascode power device 128, wherein the driver circuit 143 is configured to selectively control the cascode power device 128 with a drive signal; and a charge storage device CGDL, electrically coupled to the control connection, wherein the charge storage device 128 shunts the control connection to a drain of the cascode power device 128 when the drive signal is provided.

[0091] Such a power converter may further optionally include a first transistor and a second transistor electrically connected in cascode. The control connection may be a first gate of the first transistor, and the drain may be a drain of the second transistor.

[0092] The power converter may include the first transistor being an enhancement mode n-channel field effect transistor (NFET) and the second transistor being a depletion mode NFET, and the power circuit may further comprise a third transistor and a fourth transistor electrically connected in cascode. The third transistor may be an enhancement mode n-channel field effect transistor (NFET) and the fourth transistor may be a depletion mode NFET.

[0093] As shown in FIGS. 1 A and IB, the power converter may have the power circuit electrically coupled to an energy transfer element of the power converter. The energy transfer element may be, for example, resonant transformer 107 or energy transfer element 176. The energy transfer element may be coupled to a load of the power converter, e.g., load 113, as shown in FIG. 1 A.

[0094] The driver circuit of such a power converter may selectively control the power circuit based at least in part on an oscillation on an input signal. The oscillation on the input signal, e.g., the oscillation on Vin (shown in FIG. 1A), may help control the driver circuit. This selective control of the power circuit may be at an interval determined at least in part by a frequency of the oscillation of the input signal.

[0095] Further, a driver circuit as shown in FIG. 3 may selectively controls the cascode circuit by selecting a number of legs of the driver circuit to select an amount of current to be supplied to the cascode circuit.

[0096] FIG. 4A illustrates a cell device cross section of a depletion mode NFET according to an embodiment.

[0097] A depletion mode NFET, e.g., depletion mode NFET 166, may be fabricated with a source metallization 402, a drain metallization 403, a gate field plate metallization 404, a gate metallization 405, insulation layers 410, 411, 412, 413, 415, 416, and an epitaxial (EPI) layer 417. Additional layers may also be incorporated without departing from the scope of the present disclosure.

[0098] Source metallization 402, drain metallization 403, gate field plate metallization 404, and gate metallization 405 may be coupled to various voltages to turn depletion mode NFET on and off, i.e., to selectively allow for current to flow or be blocked from flowing between source metallization 402 and drain metallization 403. Insulation layers 410, 412, 413, 415, and 416 isolate the metallized layers, i.e., source metallization 402, drain metallization 403, gate field plate metallization 404, and gate metallization 405, and the EPI layer 417, such that current flow through the depletion mode NFET is selectively controlled by the voltages present on the various metallized layers.

[0099] EPI layer 417 may comprise compound semiconductors and give rise to a two- dimensional electron gas (2DEG). For example, and not by way of limitation, EPI layer 417 may include aluminum gallium nitride (AlGaN) layers, GaN layers, SiC layers, or other semiconductor layers without departing from the scope of the present disclosure.

[0100] FIG. 4B illustrates a charge storage element 450 corresponding to the embodiment of FIG. 4A.

[0101] A charge storage element 450, e.g., a capacitor, may be formed between gate field plate metallization 404 and the drain metallization 403. Since capacitance is found by C = cA / d. where E is the absolute permittivity of the dielectric material, A is the area of the charge storing plates, and d is the distance between the areas where charge is stored, the voltages applied to gate field plate metallization 404 and the drain metallization 403 may store charges on those metallized volumes. Further, charge storage element 450 may be distributed, i.e., may be in multiple locations and / or be over various areas of the depletion mode NFET.

[0102] As shown in FIG. 4B, and as the above equation shows, the capacitance of charge storage element 450 may be determined, at least in part, by the thickness d of insulation layer 415. Further, the type of material used for insulation layer 415, e.g., SiN, SiC, A12O3, will also have an effect on the capacitance of charge storage element 450, as each material or materials used in insulation layer 415 may have a different permittivity. The thickness d of insulation layer 415 may be determined, at least in part, based on the proximity of the 2DEG with respect to the gate field plate metallization 404 and the drain metallization 403, as the 2DEG couples the drain metallization 402 underneath the gate field plate metallization 404.

[0103] The overall capacitance of charge storage element 450 may be in the range of IE- 16 Farads per micrometer to IE- 15 Farads per micrometer, but may be larger or smallerdepending on the geometry, size, and voltages applied to the depletion mode NFET. Further, the capacitance of charge storage element 450 may be non-linear. According to the teachings herein, the gate field plate metallization 404 may be routed to improve the slew of the depletion mode NFET, e.g., depletion mode NFET 156 and / or depletion mode NFET 166. Further, the gate field plate metallization 404 may be routed differently for depletion mode NFET 156 and depletion mode NFET 166 if desired.

[0104] For example, and not by way of limitation, as shown in FIG. 2, charge storage element 450 may be used to create and / or partially create charge storage element CFPD and / or charge storage element CGD. A combination of charge storage element 450 and an external charge storage element may be used to arrive at a desired capacitance of charge storage element CFPD and / or charge storage element CGD, charge storage element 450 may be used alone to arrive at a desired capacitance of charge storage element CFPD and / or charge storage element CGD, or an external charge storage element may be used alone to arrive at a desired capacitance of charge storage element CFPD and / or charge storage element CGD.

[0105] FIG. 5 illustrates a partial metallization layout of a depletion mode NFET according to an embodiment of FIG. 4A-B.

[0106] As discussed herein, a device in accordance with the present disclosure may include a plurality of cascode devices, e.g., HS cascode power device 126 and LS cascode power device 128 as shown in FIG. 1A, or a larger number of cascode connected devices. In such an aspect, a layout of such devices may comprise a plurality of cells, as shown in FIGS. 4A- 4B.

[0107] As seen from a top view, FIG. 5 shows one or more stripes 504a, one or more stripes 504b, and one or more stripes 505. Stripes 504a are electrically coupled to drainmetallization 403 of a depletion mode NFET, e.g., depletion mode NFET 166, stripes 504b are electrically coupled to a drain metallization 403 of the depletion mode NFET, and stripes 505 may be electrically coupled to a source metallization 402.

[0108] To the left of line 525, the interconnections for the depletion mode NFET may be patterned such that gate field plate metallization 404 is electrically coupled to gate metallization 405. In such an aspect of the present disclosure, this pattern of interconnections provides for charge storage element CGD as shown in FIG. 2.

[0109] To the right of line 526, the interconnections for the depletion mode NFET may be patterned so that the gate field plate metallization 404 is electrically coupled to a field plate (FP) (floating) node 515. The location of the bonding pad for FP node 515 is shown in FIG. 5. FP node 515 may be coupled to the gate of first (lower) NFET 165, which provides for charge storage element CPFD as shown in FIG. 2. By moving the location of lines 525 and 526, various amounts of capacitance can be added to or subtracted from charge storage element CGD and / or charge storage element CPFD, which allows for the slew of the overall device to be controlled in accordance with an aspect of the present disclosure.

[0110] FIG. 6 illustrates a top view metallization layout of a depletion mode NFET according to the embodiment of FIG. 5.

[0111] To electrically connect the depletion mode NFET, e.g., NFET 166, to other components in a circuit, external pads are often provided on a die or chip. In an embodiment, the source of a depletion mode NFET may be coupled to pad 602, the drain of a depletion mode NFET may be is coupled to pad 603, the gate of a depletion mode NFET may be coupled to pad 605, and the FP node 515, as discussed with respect to FIG. 5, may be coupled to pad 615. Within layout section 625, the gate field plate metallization 404 may be coupled to pad615, while outside layout section 625, the gate field plate metallization 404 is electrically coupled to gate metallization 405.

[0112] In such an aspect, a certain percentage, e.g., about three to seven percent, which may be five percent, or some other percentage of the total capacitance relating to charge storage element 450 may be used for charge storage element CFPD within layout section 625. With reference to FIG. 2, charge storage element CFPD may be realized by connecting FP node 515 via pad 615 to the gate of first (lower) NFET 165. Layout section 625 may be made larger or smaller to increase or decrease the percentage of total capacitance relating to charge storage element 450 that is used for charge storage element CFPD without departing from the scope of the present disclosure.

[0113] The amount of total capacitance relating to charge storage element 450 that can be used for charge storage element CGD corresponds with the interconnect portions outside layout section 625, where gate field plate metallization 404 is coupled to gate metallization 405.CONCLUSION

[0114] The above description of illustrated examples of the present disclosure, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms disclosed. For instance, other embodiments including motor driver topologies, having alternative switching configurations, may exist. While specific embodiments of, and examples for programmable slew rate in cascode power devices are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided forexplanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings herein.

[0115] The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

[0116] Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and / or states. Thus, such conditional language is not generally intended to imply that features, elements and / or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding whether these features, elements and / or states are included or are to be performed in any particular embodiment.

[0117] While certain embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the disclosure.Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form ofthe methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

[0118] Although the claims presented here are in single dependency format for filing at the USPTO, it is to be understood that any claim may depend on any preceding claim of the same type except when that is clearly not technically feasible.

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A slew rate controller, comprising: a first device; a second device coupled in cascode to the first device; a charge storage device coupled between the first device and the second device; and a driver configured to selectively provide a drive signal to a gate of the first device, wherein the charge storage device shunts the gate of the first device to a drain of the second device.

2. The slew rate controller of claim 1, wherein the first device and the second device are configured to provide a negative gain from the gate of the first device to the drain of the second device.

3. The slew rate controller of claim 1 , wherein the charge storage device is coupled between the gate of the first device and the drain of the second device.

4. The slew rate controller of claim 3, wherein the charge storage device comprises a capacitor.

5. The slew rate controller of claim 3, wherein the charge storage device is a field plate of the second device.

6. The slew rate controller of claim 1 , wherein a drain of the second device is electrically coupled to a switch node.

7. The slew rate controller of claim 1, wherein the first device is an enhancement mode n-channel field effect transistor (NFET) and the second device is a depletion mode NFET.

8. The slew rate controller of claim 7, wherein the depletion mode NFET is a depletion mode gallium nitride (GaN) NFET.

9. The slew rate controller of claim 1, wherein the charge storage device comprises an internal charge storage of the second device.

10. The slew rate controller of claim 9, wherein the internal charge storage of the second device is divided into a plurality of sections.

11. The slew rate controller of claim 10, wherein a first section of the plurality of sections is coupled between a drain of the second device and a source of the first device.

12. The slew rate controller of claim 1 1 , wherein a second section of the plurality of sections is coupled between a field plate of the second device and a gate of the first device.

13. The slew rate controller of claim 12, wherein a ratio between the first section of the plurality of sections and the second section of the plurality of sections is based at least in part on a slew rate of the slew rate controller.

14. A power converter, comprising: a cascode circuit electrically coupled to an input of the power converter; a driver circuit electrically coupled to a control connection of the cascode circuit, wherein the driver circuit is configured to selectively control the cascode circuit with a drive signal; and a charge storage device, electrically coupled to the control connection, wherein the charge storage device shunts the control connection to a drain of the cascode circuit when the drive signal is provided.

15. The power converter of claim 14, wherein the cascode circuit includes a first transistor and a second transistor electrically connected in cascode.

16. The power converter of claim 15, wherein the control connection is a first gate of the first transistor.

17. The power converter of claim 15, wherein the drain is a drain of the second transistor.

18. The power converter of claim 15, wherein the first transistor is an enhancement mode n-channel field effect transistor (NFET) and the second transistor is a depletion mode NFET.

19. The power converter of claim 15, wherein the cascode circuit further comprises a third transistor and a fourth transistor electrically connected in cascode.

20. The power converter of claim 19, wherein the third transistor is an enhancement mode n-channel field effect transistor (NFET) and the fourth transistor is a depletion mode NFET.

21. The power converter of claim 20, wherein the cascode circuit is electrically coupled to an energy transfer element of the power converter.

22. The power converter of claim 17, wherein an energy transfer element is coupled to a load of the power converter.

23. The power converter of claim 14, wherein the driver circuit selectively controls the cascode circuit based at least in part on an oscillation on an input signal.

24. The power converter of claim 23, wherein the driver circuit selectively controls the cascode circuit at an interval determined at least in part by a frequency of the oscillation.

25. The power converter of claim 14, wherein the driver circuit selectively controls the cascode circuit by selecting a number of legs of the driver circuit to select an amount of current to be supplied to the cascode circuit.

26. The power converter of claim 14, wherein the charge storage device comprises an internal charge storage of the cascode device.

27. The power converter of claim 26, wherein the internal charge storage of the cascode device is divided into a plurality of sections.

28. The power converter of claim 27, wherein a first section of the plurality of sections is coupled between a drain of a second device of the cascode device and a source of a first device of the cascode device.

29. The power converter of claim 28, wherein a second section of the plurality of sections is coupled between a field plate of the second device of the cascode device and a gate of the first device of the cascode device.

30. The power converter of claim 29, wherein a ratio between the first section of the plurality of sections and the second section of the plurality of sections is based at least in part on a slew rate of the power converter.

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