Ai training core based on dynamic programmable resistor array

Abstract

Described herein are circuits and systems for performing multiplication that are fast, reliable, and highly scalable. Some embodiments of the present disclosure provide an integrated circuit with a first circuit configured to multiply a first input by a first programmable scalar value using a first fixed impedance, a second circuit configured to multiply a second input by a second programmable scalar value using a second fixed impedance, and a third circuit configured to update the first programmable scalar value based on a signal propagated via the second circuit. Some embodiments of the present disclosure provide an integrated circuit with an array of multiplication circuits, each multiplication circuit having a selectable path with an impedance, and a state update circuit configured to control selection of the selectable path based on an output signal provided by a selectable path of another of the array of multiplication circuits.

Description

AI TRAINING CORE BASED ON DYNAMIC PROGRAMMABLE RESISTOR ARRAY RELATED APPLICATIONS

[0001] This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No.63 / 609,217, filed December 12, 2023, and entitled “AI Training Core Based on Dynamic Programmable Resistor Array,” which is incorporated herein by reference in its entirety for all purposes. TECHNICAL FIELD

[0002] Circuits and systems for multiplication, including integrated circuits configured to perform machine learning inference and / or training calculations, are generally described. BACKGROUND

[0003] Machine learning processing typically includes processing a multi-dimensional input vector through several computational layers, with each computational layer multiplying neuron values by respective connection weights. In a supervised learning algorithm, the connection weights are pre-programmed with values during training that appropriately transform training inputs into desired outputs. As a result, multiplication at each layer of a machine learning algorithm is designed to cumulatively reach a classification or regression result from the input that is consistent with the training the algorithm received.

[0004] Conventionally, machine learning processing is performed by general-purpose central processing units (CPUs). CPUs are designed to process information serially and are less efficient for highly-parallel computation, such as machine learning processing, which typically involves parallel processing of large, multi-dimensional inputs. Alternative solutions to general purpose CPUs are therefore desirable to improve speed, power efficiency, and associated costs of machine learning processing. SUMMARY OF THE DISCLOSURE

[0005] The present disclosure describes circuits and systems for performing multiplication that, in accordance with certain embodiments, are fast, reliable, and highly scalable. Some embodiments of the present disclosure provide an integrated circuit with a first circuit configuredto multiply a first input by a first programmable scalar value using a first fixed impedance, a second circuit configured to multiply a second input by a second programmable scalar value using a second fixed impedance, and a third circuit configured to update the first programmable scalar value based on a signal propagated via the second circuit. Some embodiments of the present disclosure provide an integrated circuit with an array of multiplication circuits, each multiplication circuit having a selectable path with an impedance, and a state update circuit configured to control selection of the selectable path based on an output signal provided by a selectable path of another of the array of multiplication circuits. Embodiments of the present disclosure may be produced at high scale both efficiently and reliably by leveraging existing integrated circuit and memory technologies.

[0006] Certain aspects relate to an integrated circuit. In some embodiments, the integrated circuit comprises a first circuit configured to multiply a first input by a first programmable scalar value using a first fixed impedance, a second circuit configured to multiply a second input by a second programmable scalar value using a second fixed impedance, and a third circuit configured to update the first programmable scalar value based on a signal propagated via the second circuit.

[0007] In some embodiments, the first circuit comprises a first plurality of impedance-switch pairs and the second circuit comprises a second plurality of impedance-switch pairs, each impedance-switch pair of the first plurality of impedance-switch pairs and the second plurality of impedance-switch pairs comprising a fixed impedance coupled in series with a switch, and the first plurality of impedance-switch pairs being coupled in parallel with one another and the second plurality of impedance-switch pairs being coupled in parallel with one another.

[0008] In some embodiments, the integrated circuit further comprises a fourth circuit configured to multiply a third input by a third programmable scalar value using a third fixed impedance, and the third circuit is configured to update the first programmable scalar value based on the signal propagated via the second circuit and a second signal propagated via the fourth circuit.

[0009] In some embodiments, the third circuit comprises an adder circuit and a state update circuit. In some embodiments, the first circuit and the second circuit are disposed in an array of unit cell circuits, unit cell circuits of the array arranged in subarrays, each subarray configured to multiply a respective input by a respective programmable scalar value using a respective fixed impedance, the first circuit comprising a first subarray of the subarrays and the second circuit comprising a second subarray of the subarrays, and the third circuit comprises, at least for eachsubarray, an adder circuit and a state update circuit configured to update the respective programmable scalar value based on a respective signal propagated via another subarray. In some embodiments, each unit cell circuit of the first circuit is co-located with the adder circuit and the state update circuit of the third circuit.

[0010] In some embodiments, the second circuit is configured to provide the signal to a counter circuit, and the third circuit is configured to obtain, from the counter circuit, a count value based on an output from the second circuit and update the first programmable scalar value based on the count value. In some embodiments, the integrated circuit further comprises the counter circuit. In some embodiments, the first circuit and the second circuit are disposed in an array of unit cell circuits, unit cell circuits of the array arranged in subarrays, each subarray configured to multiply a respective input by a respective programmable scalar value using a respective fixed impedance, the first circuit comprising a first subarray of the subarrays and the second circuit comprising a second subarray of the subarrays, the third circuit comprises, co-located with each subarray, an adder circuit and a state update circuit configured to update the respective programmable scalar value based on a respective signal propagated via another subarray, and a counter circuit is co- located with each subarray, the counter circuit of the subarray is configured to receive the respective signal, and the adder circuit and the state update circuit are configured to obtain a respective count value from the counter circuit.

[0011] In some embodiments, the first circuit is configured to receive a first value from a memory that sets the first programmable scalar value in the first circuit, and the third circuit is configured to store the first value in the memory used to set the first programmable scalar value in the first circuit. In some embodiments, the integrated circuit further comprises the memory configured to set the first programmable scalar value in the first circuit.

[0012] In some embodiments, a system comprises the integrated circuit and a processor configured to provide a labeled input-output pair to the integrated circuit, and the second circuit is configured to propagate the signal based on an input of the labeled input-output pair and / or based on an error with respect to an output of the labeled input-output pair.

[0013] Certain aspects relate to an integrated circuit. In some embodiments, the integrated circuit comprises an array of multiplication circuits, each multiplication circuit comprising a selectable path comprising an impedance and a state update circuit configured to control selection of theselectable path based on an output signal provided by a selectable path of another of the array of multiplication circuits.

[0014] In some embodiments, each multiplication circuit of the array of multiplication circuits is configured to receive the output signal as a first output signal from a first multiplication circuit of the array of multiplication circuits, receive a second output signal from a second multiplication circuit of the array of multiplication circuits, and generate a third output signal for the second multiplication circuit by propagating the first output signal via the selectable path, and the state update circuit is configured to control selection of the selectable path based on the first output signal and the second output signal.

[0015] In some embodiments, the selectable paths of at least a first subset of the array of multiplication circuits are configured to provide the output signals to respective counter circuits of at least a second subset of the array of multiplication circuits to control selection of the selectable paths of the second subset of the array of multiplication circuits, and the state update circuits of the second subset of the array of multiplication circuits are configured to control selection of the selectable paths of the second subset of the array of multiplication circuits based on a count value obtained from the respective counter circuits based on the output signals. In some embodiments, each multiplication circuit of the first subset and the second subset of the array of multiplication circuits comprises a first circuit terminal and a second circuit terminal, with the selectable path coupled between the first circuit terminal and the second circuit terminal, and the selectable path of each of the second subset of the array of multiplication circuits is coupled between the first circuit terminal of a first multiplication circuit of the first subset and the second circuit terminal of a second multiplication circuit of the first subset.

[0016] In some embodiments, each multiplication circuit of the second subset of the array of multiplication circuits further comprises an adder circuit coupled to an input of the state update circuit and configured to receive the count value from the counter circuit. In some embodiments, each multiplication circuit of the second subset of the array of multiplication circuits further comprises the counter circuit.

[0017] In some embodiments, the state update circuits of the second subset of the array of multiplication circuits are configured to control respective values stored in a memory, and the selectable paths of the second subset of the array of multiplication circuits are configured to be selected based on the respective values stored in the memory. In some embodiments, eachmultiplication circuit further comprises, for each selectable path of the multiplication circuit, a respective memory cell of the memory, the respective memory cell configured to store the respective value.

[0018] In some embodiments, the selectable path of each multiplication circuit further comprises a switch coupled in series with the impedance. In some embodiments, a subset of the array of multiplication circuits comprise a plurality of selectable paths coupled in parallel, each of the plurality of selectable paths comprising an impedance.

[0019] In some embodiments, a system comprises the integrated circuit and a processor configured to provide a labeled input and a labeled output to the integrated circuit, the selectable paths of the first subset of the array of multiplication circuits are configured to generate the output signal based on a propagation, through at least a portion of the array, of the labeled input and / or a propagation, through at least a portion of the array, of an error signal indicating a difference between an output of the array and the labeled output, and the state update circuits of the second subset of the array of multiplication circuits are configured to control selection of the selectable path based on a coincidence between the output signal and the error signal using the state update circuit.

[0020] Other advantages and novel features of the present disclosure will become apparent when considered in conjunction with the accompanying figures. In cases where the present specification and a document incorporated by reference include conflicting and / or inconsistent disclosure, the present specification shall control. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Non-limiting embodiments of the present disclosure will be described by way of example with reference to the accompanying figures, which are schematic and are not intended to be drawn to scale. In the figures, each identical or nearly identical component illustrated is typically represented by a single numeral. For purposes of clarity, not every component is labeled in every figure, nor is every component of each embodiment shown where illustration is not necessary to allow those of ordinary skill in the art to understand the disclosure. In the figures:

[0022] FIG.1A is a block diagram of an example system including an integrated circuit configured for multiplication, according to some embodiments;

[0023] FIG.1B is a block diagram of an alternative example system including an integrated circuit configured for multiplication that further includes a co-located memory, according to some embodiments;

[0024] FIG.1C is a block diagram of a further alternative example system including an integrated circuit configured for multiplication that further includes a co-located memory and a co-located coincidence tracker, according to some embodiments;

[0025] FIG.2A is a circuit diagram of an example multiplication circuit that may be included in the integrated circuit of any of FIGs.1A-1C, according to some embodiments;

[0026] FIG.2B is a circuit diagram of a programmable multiplier including the example multiplication circuit of FIG.2A along with a programming circuit, a memory cell, and a coincidence tracker, according to some embodiments;

[0027] FIG.3 is a circuit diagram of an example array of multiplication circuits that may be included in the integrated circuit of any of FIGs.1A-1C, according to some embodiments;

[0028] FIG.4A is a block diagram of an example neural network that may be implemented using programmable multipliers of FIG.3, according to some embodiments;

[0029] FIG.4B is a grid diagram of an example neural network layer, that may be implemented using programmable multipliers of FIG.3, performing a forward propagated multiplication, according to some embodiments;

[0030] FIG.4C is a grid diagram of the example neural network layer of FIG.4B performing a backpropagated multiplication, according to some embodiments;

[0031] FIG.4D is a block diagram of a synapse of the neural network of FIG.4A implemented using a multiplication circuit, according to some embodiments;

[0032] FIG.5A is a top view of a portion of an example integrated circuit including an array of resistor-based multiplication circuits that may be included in the system of FIG.1A, according to some embodiments;

[0033] FIG.5B is a top view of the portion of the example integrated circuit of FIG.5A with the first and second conductive portions hidden from view, according to some embodiments;

[0034] FIG.6A is a perspective view of a resistor that may be included in the resistor-based multiplication circuits of FIGs.5A and 5B, according to some embodiments;

[0035] FIG.6B is a top view of the conductive trace and electrodes of the resistor of FIG.6A, according to some embodiments;

[0036] FIG.7 is a top view of an alternative example of a unit cell circuit that may be included in the integrated circuit of FIGs.5A-5B, according to some embodiments;

[0037] FIG.8 is a block diagram of an example unit cell circuit with a multiplication path, an adder circuit, and a state update circuit, which may be included in the integrated circuit of FIGs. 5A-5B, according to some embodiments;

[0038] FIG.9 is a block diagram of an example unit cell circuit with a multiplication path, an adder circuit, a state update circuit, and a memory cell, which may be included in the integrated circuit of FIGs.5A-5B, according to some embodiments;

[0039] FIG.10 is a block diagram of an example unit cell circuit with a multiplication path, an adder circuit, a state update circuit, a memory cell, and a coincidence tracking circuit, which may be included in the integrated circuit of FIGs.5A-5B, according to some embodiments;

[0040] FIG.11 is a circuit diagram of an example adder circuit that may be included in the unit cell circuit of any of FIGs.8-10, according to some embodiments;

[0041] FIG.12 is a circuit diagram of an example counter circuit that may be included in the coincidence tracking circuit of FIG.10, according to some embodiments; and

[0042] FIG.13 is a table of counter values that may be obtained via the counter circuit of FIG. 12 corresponding to coincident events arising from probability-filtered signals input to the counter circuit, according to some embodiments. DETAILED DESCRIPTION

[0043] The present disclosure describes circuits and systems for performing multiplication that, in accordance with certain embodiments, are fast, reliable, and highly scalable. Some embodiments of the present disclosure provide an integrated circuit with a first circuit configured to multiply a first input by a first programmable scalar value using a first fixed impedance, a second circuit configured to multiply a second input by a second programmable scalar value using a second fixed impedance, and a third circuit configured to update the first programmable scalar value based on a signal propagated via the second circuit. Some embodiments of the present disclosure provide an integrated circuit with an array of multiplication circuits, each multiplication circuit having a selectable path with an impedance, and a state update circuit configured to control selection of the selectable path based on an output signal provided by a selectable path of another of the array of multiplication circuits. Embodiments of the presentdisclosure may be produced at high scale both efficiently and reliably by leveraging existing integrated circuit and memory technologies.

[0044] The inventors have recognized that memristive technologies could make machine learning computations and training faster and more efficient, but with drawbacks that make memristive technologies unsuitable for some applications. Memristors are circuit elements that may be programmed with a particular input-to-output transfer function, which may be used to perform a multiplication. On one hand, a large array of memristors may be programmed to apply respective scalar multiplication to a large number of input signals and thereby perform massively parallel multiplication at high speed. Memristors are particularly attractive for this purpose because they may be easily reprogrammed on-the-fly (e.g., without any changes to their fabricated structure) to obtain different transfer functions, permitting the array to be trained or retrained. For instance, changing the transfer functions of the memristors may update the connection weights used for memristive neuron multiplication. As a result, the same memristive structure could be reused repeatedly and retrained and / or adapted for completely different machine learning tasks.

[0045] On the other hand, however, the inventors recognized that memristive structures do not presently achieve reliable and accurate processing. For instance, while memristive structures may be advantageously reprogrammed with different transfer functions, memristive structures may not hold their programmed transfer functions with the degree of accuracy needed for consistent and low error computation. Thus, memristive technologies may require a tradeoff between performance over time and re-programmability.

[0046] Instead, the inventors recognized that, in accordance with some embodiments, circuitry for scalar multiplication using a fixed impedance and for updating the scalar values used for multiplication may achieve better performance than memristive structures with a similar programmability and re-programmability advantage. For example, multiplication by a programmable scalar value may use a fixed impedance coupled in series with a switch and the programmable scalar value may be updated (e.g., trained) by updating whether to turn the switch on or off. In some embodiments, circuitry with an array of selectable impedance paths and state update circuits configured to control selection of the selectable impedance paths may achieve better performance than memristive structures with a similar programmability advantage. For example, the selectable paths may be configured to perform a multiplication by a scalar valuebased on which subset(s) of the selectable paths are selected. Moreover, in some embodiments, multiplication structures may be implemented using existing integrated circuit technologies and reprogrammable scalar multiple configurations may be implemented using existing memory technologies, making the resulting circuits efficient and reliable to produce at scale. Such circuits may be especially useful, when configured as an array, for implementing a machine learning inference and / or training machine programmed (and reprogrammable) to perform multiplication on a large number of inputs.

[0047] FIG.1A is a block diagram of an example system 100a including an integrated circuit 102a configured for multiplication, according to some embodiments.

[0048] In some embodiments, system 100a may be configured for multiplication, such as may be used to perform a machine learning inference. For example, as shown in FIG.1A, system 100a includes a processor 110, an analog / digital (A / D) interface 130, an integrated circuit 102a having one or more programmable (Prog.) multiplication (Mult.) circuits 120, a memory 140, and a coincidence tracker 150. In an example of machine learning inference, processor 110 may be configured to provide an input signal to the multiplication circuit(s) 120 that is indicative of a neuron value N that is to be multiplied by a connection weight C to produce an output signal O indicative of the multiplication result N x C (e.g., either before or after the activation function is applied, depending on the embodiment). In this example of machine learning inference, the memory 140 may be programmed with the connection weight C so as generate path select signals that control the multiplication circuit(s) 120 to apply the connection weight C.

[0049] In some embodiments, system 100a may be configured for coincidence tracking, such as may be used to perform a machine learning inference (e.g., together with multiplication). In an example of machine learning training, the multiplication circuit(s) 120 may be configured to provide a signal Y and / or D to the coincidence tracker 150 to determine whether and / or to what extent to adjust the connection weight C, and the coincidence tracker 150 may provide an indication ∆ of whether and / or the extent to which the connection weight C should be updated. For instance, in a training operation that determines whether to adjust a connection weight C of a particular layer of a neural network, a signal from the multiplication circuit(s) 120 to the coincidence tracker 150 may be propagated based on an input to the neural network (e.g., forward propagated from a previous layer) and / or may be based on an error with respect to an output of the neural network (e.g., back-propagated from a next layer). In this example ofmachine learning training, the coincidence tracker 150 may be configured to, based on the signal(s) (e.g., forward and back-propagated signals), indicate to the system 100a (e.g., via the multiplication circuit(s) 120) that the connection weight C (e.g., of the particular layer) in the memory 140 should be updated. In some embodiments, such as shown in dashed line in FIG.1A, an input may be provided directly to the coincidence tracker 150 from the processor, such as at least one of Y and / or D, and / or a signal used for modulating Y and / or D as described further herein.

[0050] In some embodiments, the system 100a may be further configured to apply an activation (and / or deactivation function) to the multiplication result. Typical activation functions include ^ sigmoid ( ^^^^^), hyperbolic tangent (tanh (^)), rectified linear unit (ReLU) (max (0, ^)), LeakyReLU (max ^)), Maxout (max (^^ ^^^ + ^^, ^^^ + ^^)), and exponential linear unit (ELU)(^, ^ ≥ 0; ^(^^ − 1), ^ < 0). A deactivation function is typically the derivative of the activationfunction. In some embodiments, an activation and / or deactivation function may be applied by a component on the integrated circuit 102a, such as an activation and / or deactivation function circuit (e.g., analog circuitry providing and / or approximating the response of an activation and / or deactivation function). For instance, an analog activation and / or deactivation circuit may be included for each multiplication circuit, such as co-located with the multiplication circuit and / or elsewhere in the integrated circuit 102a. In some embodiments, an activation and / or deactivation function may be applied by a digital processing circuit, such as by digital processing components (e.g., logic gates of an FPGA and / or ASIC) within or separate from the integrated circuit 102a, and / or by the processor 110.

[0051] In some embodiments, a machine learning inference operation may include a multidimensional vector of neuron values N that are to be multiplied by a multidimensional vector of connection weights C (e.g., corresponding to respective synapses) programmed in the memory 140 to obtain a multidimensional vector output O when each vector component is processed by a respective multiplication circuit 120. For example, a multidimensional input vector may be provided to the integrated circuit 102a (e.g., from the processor 110), and the integrated circuit 102a may be configured to propagate the input vector via a plurality of multiplication circuits 120 (e.g., implementing neuron layers of a neural network) and return an output (e.g., to the processor 110). For instance, the integrated circuit 102a may be configured to apply activation functions in between implemented neural network layers. Alternatively oradditionally, the integrated circuit 102a may be configured to return an output (e.g., to the processor 110) between at least some multiplication circuits 120 (e.g., implementing a first neural network layer) and other multiplication circuits 120 (e.g., implementing a second neural network layer), such as for external activation of the output (e.g., by the processor 110).

[0052] In some embodiments, a machine learning training operation may include a multidimensional vector of forward-propagated signals Y (e.g., via a first neural network layer) and back-propagated signals D (e.g., via a second neural network layer) that are to be tracked for coincidence (e.g., using probability filtering) to determine whether to update a connection weight C (e.g., of a third neural network layer between the first and second layers). For example, forward-propagated signals Y may be obtained via a first neural network layer by multiplying input values to the first layer by a multidimensional vector of connection weights C of the first layer and applying an activation function to the multiplication results, and back-propagated signals D may be obtained via a second neural network layer by multiplying further back- propagated values (e.g., from a further next neural network layer) by a transpose of a multidimensional vector of connection weights C of the second layer (e.g., the same connection weights C used for multiplying neuron values N at the second layer) and applying a deactivation function to the multiplication results.

[0053] In some embodiments, system 100a may be formed using a number of integrated circuits on one or more circuit boards, such as a computer motherboard. In other embodiments, at least some components may be in communication with one another over a communication network, such as in a distributed cloud computing environment. As described herein, an integrated circuit may include one or more semiconductor dies having circuitry fabricated thereon and encapsulated in a package. Multiple dies within an integrated circuit package may be stacked and / or wire bonded together within the package.

[0054] In some embodiments, processor 110 may be a general-purpose central processing unit (CPU). For example, the processor 110 may be included within a general-purpose computer in which the integrated circuit 102a has been incorporated, such as by mounting into a slot on the motherboard in a modular configuration and / or through permanent affixation to the circuit board as part of its manufacturing. While a single processor 110 is shown in FIG.1A, it should be appreciated that multiple processors 110 may be used, whether in the same local computer system or in a distributed cloud computing environment. Further, while processor 110 is shownseparate from integrated circuit 102a in FIG.1A, it should be appreciated that a single integrated circuit (e.g., mixed analog / digital integrated circuit) may have both the processor 110 and multiplication circuit(s) 120 therein, such as on a single semiconductor die and / or on multiple dies stacked and / or wire bonded together within a single package. Further, while the processor 110 may be implemented as or including a CPU, in other embodiments the processor 110 may be implemented as or include a graphics processing unit (GPU), a field programmable gate array (FPGA), and / or an application-specific integrated circuit (ASIC), as embodiments described herein are not so limited.

[0055] In some embodiments, the A / D interface 130 may be configured to facilitate bi- directional communication between the processor 110 and analog circuitry (e.g., the multiplication circuit(s) 120) of the integrated circuit 102a. For example, as shown in FIG.1A, the A / D interface 130 includes a digital-to-analog converter (DAC) 132 and an analog-to-digital converter (ADC) 134 coupled between the processor 110 and the multiplication circuit(s) 120 of the integrated circuit 102a. In some embodiments, the input signal from the processor 110 may have a digital value representative of the neuron values N, which the A / D interface 130 may convert to an analog value (e.g., voltage and / or current amplitude) representative of the neuron values N. Likewise, the output signal O may have an analog value representative of the multiplication result, which the A / D interface may convert to a digital value representative of the multiplication result. It should be appreciated that some embodiments may omit one or each of DAC 132 and 134 and / or all of the A / D interface 130, such as where communication between the processor 110 and multiplication circuit(s) 120 is unidirectional, where the multiplication circuit(s) 120 are configured to process digital signals without an intervening DAC, where the multiplication circuit(s) 120 are configured to output digital signals without an intervening ADC, and / or where the processor 110 has at least some analog processing components for interfacing with the integrated circuit 102a.

[0056] In some embodiments, the multiplication circuit(s) 120 may be configured to multiply values represented in input signals received from processor 110 to provide output signals to processor 110 representing the result of the multiplication. For example, in some embodiments, the multiplication circuit(s) 120 may each include a plurality of selectable paths controllable to set the value by which the multiplication circuit(s) multiply values represented in input signals received from the processor 110. For instance, a subset of the paths may be selected using pathselect signals received by the memory 140. In some embodiments, the multiplication circuit(s) 120 may include parallel-coupled impedances having fixed impedance values and switches (e.g., transistors) coupled in series with respective impedances, such that states of the switches may be controlled to set the desired overall impedance of a multiplication circuit 120 to obtain a desired value by which to multiply a value represented in an input signal from the processor 110.

[0057] In some embodiments, the multiplication circuit(s) 120 may be further configured to receive labeled training data, such as a labeled input (e.g., at a first neural network layer) and a labeled output, which may be used for training (e.g., using a difference between the labeled output and an output of a last neural network layer). For example, a difference between the labeled output and an output of a multiplication circuit (e.g., implementing the last neural network layer) may indicate an amount of error in the output, which in turn may be back- propagated to intermediate multiplication circuits (e.g., implementing neural network layers between the first and last neural network layers) and used to determine whether and / or the extent to which to adjust connection weights C used at each multiplication circuit.

[0058] In some embodiments, the memory 140 may be configured to provide path select values to multiplication circuit(s) 120 for controlling multiplication of values represented in input signals from the processor 110. For example, the memory 140 may be configured to store at least one path select value for each multiplication circuit 120 of the integrated circuit 102a. For instance, each path select value may include a bit for each selectable path and / or switch of the respective multiplication circuit 120. In some embodiments, the memory 140 may include random access memory (RAM), such as static random-access memory (SRAM) and / or dynamic random access memory (DRAM), depending on the preferred and / or available memory for the application. Using RAM may be preferred for some applications to permit re-programming of path select values to change values by which the multiplication circuit(s) 120 are configured to multiply input values, which may be useful for training. However, permanent memory may be preferred for other applications, such as where at least some path select values and resulting multiplication are predetermined and not to be changed.

[0059] In some embodiments, the memory 140 may be at least a portion of a shared computer system memory where at least a portion is in communication with the integrated circuit 102a. In other embodiments, the memory 140 may be partially or entirely dedicated to storing configuration information for multiplication circuit 120. To set the path select values, in someembodiments, the memory 140 may be configured to receive the memory write and enable values from the processor 110 that control the path select values and / or individual bits within a path select value stored in the memory 140. In an example where the coincidence tracker 150 is communicatively coupled to the processor 110 via the multiplication circuit(s) 120, the processor 110 may be configured to update values in the memory 140 based on an indication conveyed from the tracker 150 via the multiplication circuit(s) 120, although in other examples the tracker 150 may be coupled directly to the processor 110 and / or to the memory 140.

[0060] In some embodiments, the integrated circuit 102a may be configured to perform activation between neural network layers implemented by multiplication circuits 120 of the integrated circuit 102a. For some applications, an analog input may be provided and an analog output obtained from the integrated circuit 102a, and / or a digital input may be provided and a digital output obtained from the integrated circuit 102a, facilitating omission of the A / D interface 130. For instance, outputs from one group (e.g., layer) of multiplication circuits 120 may be provided (e.g., after activation) as inputs to another group (e.g., layer) of multiplication circuits 120, such as may be used to implement some or all neural network processing within the integrated circuit 102a.

[0061] FIG.1B is a block diagram of an alternative example system 100b including an integrated circuit 102b configured for multiplication that further includes a co-located memory 140, according to some embodiments.

[0062] In some embodiments, the system 100b may be configured as described herein for the system 100a, such as including a processor 110, A / D interface 130, multiplication circuit(s) 120, and memory 140. In contrast to the embodiment of system 100a shown in FIG.1A, however, system 100b in FIG.1B is shown including multiplication circuit(s) 120 and memory 140 co- located in the integrated circuit 102b.

[0063] In some embodiments, memory cells of the memory 140 may be co-located with the multiplication circuit(s) 120. For example, each multiplication circuit 120 may have co-located therewith a memory cell of the memory 140 storing a path select value for controlling a respective path of the multiplication circuit 120. For example, the co-located memory cells may be bitcells (e.g., holding a single bit) and / or may be groups of bitcells (e.g., holding multiple bits). In this example, the memory 140 may be configured as described in connection with FIG. 1A, with path select values stored in the co-located bitcell(s) programmed by processor 110 andprovided to components of the multiplication circuit(s) 120. In some embodiments, circuits may be co-located in an integrated circuit by each circuit being disposed in the integrated circuit package. In some embodiments, circuits may be co-located with one another (e.g., within an integrated circuit package) by having the circuits disposed adjacent one another on a layer of the integrated circuit and / or stacked above or below one another (e.g., within a vertical unit cell that may be repeated substantially periodically in an array), proximate to one another with or without intervening layers therebetween.

[0064] In some embodiments, the multiplication circuit(s) 120 and memory 140 within the integrated circuit 102b may be formed on the same semiconductor die or on separate dies stacked and / or wire bonded and packaged together. The inventors have recognized that, regardless of whether memory cells of the memory 140 are co-located with respective ones of the multiplication circuit(s) 120, packaging the multiplication circuit(s) 120 and memory 140 may improve system efficiency in terms of device footprint and / or the number of interfaces through which the processor 110 is coupled. In some embodiments, a single bus may be used to communicate between the processor 110 and both the multiplication circuit(s) 120 and memory 140.

[0065] FIG.1C is a block diagram of a further alternative example system 100c including an integrated circuit 102c configured for multiplication that further includes a co-located memory 140 and a co-located coincidence tracker 150, according to some embodiments.

[0066] In some embodiments, the system 100c may be configured as described herein for the system 100b, such as including a processor 110, A / D interface 130, multiplication circuit(s) 120, and co-located memory 140. In contrast to the embodiments of systems 100a shown in FIG.1A in 100b shown in FIG.1B, however, system 100c in FIG.1C is shown including multiplication circuit(s) 120, memory 140, and coincidence tracker 150 co-located in the integrated circuit 102c.

[0067] In some embodiments, coincidence tracker 150 may include coincidence circuits co- located with ones of the multiplication circuit(s) 120 and / or memory cells of the memory 140, similar to those described for integrated circuit 102b. For example, each multiplication circuit 120 may have co-located therewith a memory cell of the memory 140 storing a path select value for controlling the multiplication circuit 120 and a coincidence tracking circuit of the coincidence tracker 150. For example, the coincidence tracking circuit of a first multiplicationcircuit may include a counter configured to receive a first signal via a second multiplication circuit (e.g., implementing a next neural network layer) and a second signal from a third multiplication circuit (e.g., implementing a previous neural network layer) to track coincidence between the first signal (e.g., using a stochastic pulse with a probability generated therefrom) and the second signal (e.g., using a stochastic pulse with a probability generated therefrom) for determining whether the value(s) in the memory 140 should be updated.

[0068] In some embodiments, the multiplication circuit(s) 120, memory 140, and coincidence tracker 150 within the integrated circuit 102c may be formed on the same semiconductor die or on separate dies stacked and / or wire bonded and packaged together. The inventors have recognized that, regardless of whether coincidence tracking circuits of the coincidence tracker 150 are co-located with respective ones of the multiplication circuit(s) 120 (and / or memory cells of the memory 140), packaging the multiplication circuit(s) 120, memory 140, and coincidence tracker 150 may improve system efficiency in terms of device footprint and / or the number of interfaces to and / or from the integrated circuit. It should be appreciated that, while not shown in FIG.1C, the coincidence tracker 150 may be co-located with the integrated circuit while the memory 140 is separate from the integrated circuit, such as where the memory 140 is a shared system memory (e.g., shared with the processor 110).

[0069] FIG.2A is a circuit diagram of an example multiplication circuit 212 that may be included in the system 100a, 100b, and / or 100c, according to some embodiments.

[0070] In some embodiments, the multiplication circuit 212 may be configured to receive an input signal 202 representing a first value and produce an output signal 204 representative of a second value that is a scalar multiplication of the first value. For example, one of the input signal 202 and the output signal 204 may be a voltage signal and the other of the input signal 202 and the output signal 204 may be a current signal. For instance, where the input signal 202 is a voltage signal (e.g., output by an ADC) and the output signal 204 is a current signal (e.g., output by applying the voltage signal to an impedance), the output signal 204 may have a current amplitude that represents an output value that is a scalar multiple of an input value represented in a voltage amplitude of the input signal 202.

[0071] In one illustrative example of representative value multiplication, an input signal 202 may be a voltage signal having a voltage of 1 Volt (V) and an output signal 204 may be a current signal having a current of 1 Milliampere (mA), For instance, the multiplication circuit 212 mayhave applied an impedance of 1 kilohm (kΩ) to the input signal 202 to produce the output signal 204. In this example, the range of input voltages of the input signal 202 may be from 1 V to 2 V, representing a range of neuron values from 1 to 2, and the range of output currents of the output signal 204 may be from 0.5 mA to 2 mA, representing a range of multiplication results from 1 to 4. Thus, the input signal 202 may represent a neuron value of 1 and the output signal 204 may represent a multiplication result of 2, indicating that the 1 kΩ impedance of the multiplication circuit 212 applied a connection weight multiplier of scalar value 2 to the input signal 202 to produce the output signal 204. While this example uses only nonzero voltages and currents as indicating values, other examples may use a zero voltage and / or zero current as indicating a value.

[0072] In some embodiments, the multiplication circuit 212 may be controllable to set an impedance between the input and the output of the circuit 212. For example, as shown in FIG. 2A, multiplication circuit 212 includes a plurality of selectable paths 206 coupled in parallel between the input and the output. In the illustrated example, each path 206 includes a switch 220. For instance, each switch 220 may be controllable to select its path 206 to be included in an overall parallel path from the input to the output of the circuit 212, with at least a portion of the input signal 202 propagating through each selected path 206 within the parallel path. As shown in the example of FIG.2A, each path 206 includes an impedance 210 coupled in series with the switch 220. Also shown in the example of FIG.2A, each path 206 includes an impedance-switch pair that includes an impedance 210 coupled in series with the switch 220. For example, by controlling the switch(es) 220 of one or more paths 206 to include the respective impedance(s) 210 in parallel between the input and the output, the overall impedance of the overall path from the input to the output may be controlled. Moreover, by using switches 220 to control selection of paths 206, impedances 210 with fixed impedance values may be used in the multiplication circuit 212 while achieving control over scalar multiplication to be obtained using the circuit.

[0073] Using the illustrative example above, the three paths 206 shown in FIG.2A may have impedances 210 of 1 kΩ, 2 kΩ, and 4 kΩ. To achieve the above-described multiplication of a neuron value of 1 represented in an input signal 202 having a voltage of 1 V by a scalar value connection weight of 2 to obtain a resulting output signal 204 representing a multiplication result having a current of 1 mA, only the path 206 including the impedance 210 of 1 kΩ may be selected by turning on the switch 220 connected in series with that impedance 210 to achieve thedesired output. While this example selects one path 206 to apply an impedance to an input to achieve a desired output, other examples may select multiple paths (e.g., with impedances 210 of 1 kΩ and 4 kΩ) to provide an overall (e.g., parallel) impedance (e.g., 800Ω, as this many provide more resolution (e.g., possible discrete impedance values) in setting the overall impedance.

[0074] In some embodiments, multiplication circuit 212 may be repeatedly programmable to select different subsets of paths 206 to obtain appropriate scalar multiple values (e.g., connection weights), as may be useful for machine learning training. For example, where fixed impedances 210 are used, scalar multiple values may be programmed (e.g., updated) in the circuit 212 by adjusting path select signals applied to the switches 220 to change which paths 206 are selected for inclusion in the overall path from the input to the output. It should be appreciated, however, that some applications may not take advantage of the re-programmable nature of such a circuit 212, such as by fixedly coupling at least some circuits 212 to read-only memory (ROM) that provides the path select signals.

[0075] In some embodiments, an impedance and switch may be in series when substantially all current flowing in one of the impedance and switch flows through the other of the impedance and switch (e.g., though some insignificant amount of current may flow elsewhere due to leakage). In some embodiments a plurality of paths (e.g., each including an impedance in series with a switch) may be coupled in parallel between an input and an output when each path necessarily has a same voltage across the path (e.g., the voltage difference between the input and output), and / or when substantially all current flowing from the input to the output is divided among the paths (e.g., though some significant amount of current may flow elsewhere due to leakage).

[0076] In some embodiments, a multiplication circuit 212 configured to perform scalar multiplication to produce an output signal as a multiplication of an input value may be used for either or each of a machine learning inference operation and a machine learning training operation. For example, as described further below, within a machine learning training operation, a first signal propagated via a first layer of a neural network and a second signal propagated via a second layer of the neural network may be used in combination (e.g., based on coincidence therebetween) to produce an indication of whether and / or the extent to which a connection weight in a third layer of the neural network (e.g., between the first and second layers) should be updated. In the illustrated embodiment, a first multiplication circuit 212 (e.g., in the first layer)may be configured to provide the first signal and a second multiplication circuit 212 (e.g., in the second layer) may be configured to provide the second signal. For instance, the first multiplication circuit (e.g., implementing a synapse in the first neuron layer) may be configured to output the first signal as a multiplication result (and / or an activated version of the multiplication result) and the second multiplication circuit (e.g., implementing a synapse in the second neuron layer) may be configured to output the second signal as a multiplication result (and / or a deactivated version of the multiplication result).

[0077] It should be appreciated that, while three paths 206 each including one switch 220 and one impedance 210 are shown in FIG.2A, any number of paths 206 may be included, and any number of switches 220 and / or impedances 210 may be included per path 206. Alternatively or additionally, a circuit 212 may be configured with sub-paths within some or all paths 206, each sub-path including a switch and an impedance. For instance, such a configuration may provide further ways of fine-tuning the desired overall impedance from the input to the output of the circuit 212.

[0078] FIG.2B is a circuit diagram of an example programmable multiplier 200 including the multiplication circuit 212 of FIG.2A coupled to a programming circuit 208, a memory cell 240, and a coincidence tracker 250, according to some embodiments.

[0079] In some embodiments, the programmable multiplier 200 may be configured to program a scalar value for multiplying the input signal 202 in the multiplication circuit 212 to obtain the output signal 204. For example, the illustrated multiplication circuit 212 may be a first circuit configured to perform a first scalar multiplication (e.g., implementing a synapse of a neural network layer), another multiplication circuit (not shown) may be a second circuit (e.g., implementing a synapse of a previous neuron layer or of a next neuron layer), and the programming circuit 208 may be a third circuit configured to update the scalar value used in the scalar multiplication. For instance, the update may be based on a first signal Y propagated (e.g., forward-propagated) via a multiplication circuit and a second signal D propagated (e.g., back- propagated) via another multiplication circuit (e.g., implementing previous and next layers of the neural network), respectively. In some embodiments, the update may be applied to a value stored in the memory cell 240 that sets the scalar value (e.g., by selecting a switch 220, whether individually or in combination with other stored values selecting other switches 220).

[0080] In some embodiments, the programmable multiplier 200 may be configured to control selection of a path 206, such as part of a machine learning training operation. For example, selection of a path 206 in the illustrated multiplication circuit 212 may be based on the first signal Y and the second signal D propagated via other the multiplication circuits (e.g., in response to the input signals 202 and current path select signals stored in the memory cells 240 for the respective multiplication circuits). For instance, during a machine learning training operation, the first signal Y may be derived from an input propagated through some or all multiplication circuits implementing earlier layers of the neural network and the second signal D may be derived from an output error back-propagated through some or all multiplication circuits implementing later layers of the neural network. In the illustrated example, the coincidence tracker 250 may be configured to output an indication of coincidence between the signals Y and D, which in turn may indicate whether and / or the extent to which the weight(s) may be updated by updating values stored in the memory cell(s) 240 using the programming circuit 208.

[0081] In some embodiments, the programming circuit 208 may be configured to receive an indication from the coincidence tracker 250, in turn based on the signals Y and D, that the path control value stored in the memory cell 240 for selecting the switch 220 should be updated. For example, as shown in FIG.2B, the adder circuit of the programming circuit 208 is shown coupled to the coincidence tracker 250 and the memory cell 240, and the state update circuit of the programming circuit is coupled between the adder circuit and the memory cell 240. For instance, the indication from the coincidence tracker 250 may be added, using the adder circuit, to a state maintained by the state update circuit (e.g., based on a value stored in the memory cell 240), which may be used to control to a path control value stored in the memory cell 240. In some embodiments, the programming circuit 208 may be co-located in the same integrated circuit as the multiplication circuit 212, whereas in other embodiments the programming circuit 208 may be separate, such as in its own integrated circuit and / or together with the memory cell 240.

[0082] While not shown in FIG.2B, it should be appreciated that an activation function may be applied to output signals and / or a deactivation function may be applied to back-propagated signals, such as by analog processing components of or coupled to the programmable multiplier 200 (e.g., within the same integrated circuit), and / or by digital processing components (e.g., processor 110) coupled to the programmable multiplier 200.

[0083] FIG.3 is a circuit diagram of an example array 300 of multiplication circuits that may be included in the system 100a, 100b, and / or 100c, according to some embodiments.

[0084] In some embodiments, each multiplication circuit 306a, 306b, 306c, and 306d may be configured in the manner described herein for the programmable multiplier 200. For example, in FIG.3, each multiplication circuit 306a, 306b, 306c, and 306d includes a plurality of paths, each path including a switch 320 and an impedance 310.

[0085] In some embodiments, multiplication circuits of the array 300 may be configured to perform multiply-accumulate (MAC) operations. For example, multiplication circuits of the array 300 may have inputs and / or outputs coupled together. In the example illustrated in FIG.3, the inputs of multiplication circuits 306a and 306b are coupled together to receive an input signal 302a and the inputs of multiplication circuits 306c and 306d are coupled together to receive an input signal 302b. Also shown in FIG.3, the outputs of multiplication circuits 306a and 306c are coupled together to produce an output signal 304a and the outputs of multiplication circuits 306b and 306d are coupled together to produce an output signal 304b. In the illustrated example, the output signal 304a may represent a sum of a first product obtained from the output of the multiplication circuit 306a together with a second product obtained from the output of the multiplication circuit 306c. For instance, where the multiplication circuits 306a and 306c output current signals, coupling the outputs of the circuits 306a and 306c may serve to combine the current signals, which may represent summing the values represented in the current signals. Moreover, in the illustrated example, each output signal 304a and 304b may represent a respective sum given by the following equation: (1) !",# = %",# ∗ '" + (),* ∗ '# ,in the input signal 302a, Ib is the neuron value represented in the input signal 302b, Xa,b is the scalar multiplier programmed into the respective multiplication circuit 306a or 306b, and Yc,dis the scalar multiplier programmed into the respective multiplication circuit 306c or 306d. It should be appreciated that the multiplication circuits 306a, 306b, 306c, and 306d could be configured to perform multiplication of signals received at the circuit terminals labeled as outputs in FIG.3 and to provide signals at the circuit terminals labeled as inputs in FIG.3, such as for a back-propagation multiplication.

[0086] In some embodiments, switches 320 of the multiplication circuits 306a, 306b, 306c, and 306d may be configured to receive path select signals that select a subset of one or more pathsthrough the circuit. For example, multiplication circuit 306a is shown configured to receive path select signals 1X, 1Y, and 1Z, multiplication circuit 306b is shown configured to receive path select signals 2X, 2Y, and 2Z, multiplication circuit 306c is shown configured to receive path select signals 3X, 3Y, and 3Z, and multiplication circuit 306d is shown configured to receive path select signals 4X, 4Y, and 4Z for controlling respective switches 320. In some embodiments, the path select signals may be provided by a memory, such as with each path select signal (e.g., 1X) being stored in a memory cell of the memory.

[0087] In some embodiments, impedances 310 within a multiplication circuit, such as circuit 306a, may be weighted with respect to one another. For example, FIG.3 shows a binary- weighted configuration in which the three impedances of the circuit 306a are doubled with respect to one another. For instance, a binary-weighted configuration of impedances of 1, kΩ, 2 kΩ, and 4 kΩ may be used to achieve the above-described multiplication by selecting the 1 kΩ path to obtain an overall impedance of 1 kΩ. Alternatively or additionally, multiple paths may be selected such that the overall impedance includes a parallel combination of the impedances (e.g., 800Ω parallel combination of 1 kΩ and 4 kΩ.

[0088] While four multiplication circuits 306a, 306b, 306c, and 306d are shown in the array 300 of FIG.3 by way of illustration, any number of multiplication circuits may be included in an array. Moreover, while all four multiplication circuits 306a, 306b, 306c, and 306d are shown in FIG.3 interconnected either at the input or output, it should be appreciated that in some implementations, multiplication circuits within an array may be interconnected to some other multiplication circuits in the array and separate from other multiplication circuits in the array. For example, in some embodiments, the four multiplication circuits shown in FIG.3 may comprise a subarray within a larger array where each subarray is programmed to perform a MAC operation. Further alternatively or additionally, operations other than MAC operations may be performed using multiplication circuits described herein, such as multiply-add (MAD) operations and / or solely multiplication operations.

[0089] FIG.4A is a block diagram of an example neural network 400 that may be implemented using a plurality of programmable multipliers 200, according to some embodiments.

[0090] In some embodiments, the illustrated neural network may be configured to process a plurality of inputs to obtain an output. For example, in FIG.4A, Input 1, Input 2, and Input 3 are provided to the network 400, and an Output 1, Output 2, and Output 3 are obtained from thenetwork 400. For instance, the inputs may be obtained from the processor 110 at an integrated circuit 102a, 102b, 102c that implements the network 400, and the output(s) may be provided to the processor 110, though in some cases, values may be obtained from and / or provided to the processor 110 between layers of the network 400.

[0091] In some embodiments, a neural network may include a plurality of layers. For example, as shown in FIG.4A, the illustrated neural network 400 has n layers. In the illustrated example, Layer 1 may be an input layer including 3 neurons. In some embodiments, each neuron may have synapses (e.g., implemented by respective multiplication circuits) that receive Input 1, Input 2, and Input 3, respectively. For instance, a multiplication circuit implementing a synapse may be configured to multiply an input by a connection weight to produce or at least contribute to an output of the neuron to which the synapse belongs. Also shown in FIG.4A, Layer n may be an output layer including 3 neurons having synapses (e.g., implemented by respective multiplication circuits) configured to produce the respective Output 1, Output 2, and Output 3.

[0092] In some embodiments, a neural network may be configured to propagate signals through the network from an input layer towards an output layer (e.g., forwardly), such as by having neurons of one layer provide outputs to synapses of neurons of the next layer. For example, as shown in FIG.4A, an intermediate layer k receives, at the ith synapses of the jth neuron (e.g., with synapses i implemented by multiplication circuits) the output values yik-1of the previous layer k-1 (not shown) and provides, at its neuron outputs, output values xjk, which may be activated to produce the output values yjkprovided to the jth synapse (e.g., implemented by a multiplication circuit) of each neuron i of the next layer k+1 (though it is appreciated here and further below that layer k+1 may have any number of neurons).

[0093] In some embodiments, a neural network may be configured to propagate signals through the network from an output layer towards an input layer (e.g., backwardly), such as by having synapses of one layer provide a derivation of an error signal to neurons of the preceding layer. For example, as shown in FIG.4A, a jth neuron (e.g., having synapses implemented by multiplication circuits) of the output Layer n receives an error signal +jn, which may be based on a difference between Output 3 and a labeled output used for a training operation, and provides a propagation of the error signal +jnas +in-1to each synapse (e.g., implemented by a multiplication circuit) of an ith neuron in the preceding Layer n-1. For instance, a multiplication circuit implementing an ith synapse of the jth neuron in Layer n that receives the error signal +jnmay beconfigured to generate and / or contribute to the propagated error signal +in-1by multiplying the received error signal +jnby the connection weight of the multiplication circuit (e.g., resulting in multiplication by a transpose of the connection weight matrix of the neuron). Similarly, at the intermediate layers shown in FIG.4A, multiplication circuits implementing synapses of neurons of the layer k+1 may receive back-propagated error signal +jk+1from the jth synapses of the next layer (not shown), synapses of the jth neuron of the layer k+1 may provide back-propagated error signal +ikto neurons of the layer k, the synapses of the ith neuron of the layer k may provide the back-propagated error signal +jk-1to neurons of the preceding layer (not shown), and the neurons of the input Layer 1 may receive the back-propagated error signal +j1from the jth synapses of the next layer (not shown).

[0094] While FIG.4A shows a neural network 400 in which each layer has 3 neurons, any number of neurons may be included in a layer, and layers may include different numbers of neurons, depending on the architecture implemented. For instance, while FIG.4A indicates that the illustrated layers have either i synapses and j neurons or vice versa, any number of synapses and / or neurons may be included in and / or interconnected for a particular depending on the architecture (e.g., fully connected, convolutional, recurrent, etc.). Moreover, while FIG.4A shows a neural network with three inputs and three outputs, any number of inputs and outputs may be used depending on the desired neural network architecture.

[0095] FIG.4B is a grid diagram of an example neural network layer 402 that may be implemented using programmable multipliers of FIG.3 performing a forward-propagated multiplication, according to some embodiments.

[0096] In some embodiments, the illustrated neural network layer 402 may be included in the neural network 400 of FIG.4A. For example, the illustrated neural network layer may be used as any or each neural network layer 402 in the network 400 shown in FIG.4A. As shown in FIG. 4B, the illustrated neural network layer 402 is the kth layer configured to receive input values . / 01^, which may correspond to activated output values from each neuron i of the preceding layer k-1 (not shown), and to provide output values ^20, which may correspond to sums, from each neuron j of the illustrated layer 402, of the input values . / 01^received at that neuron multiplied by respective connection weights 3 / 02 of the neuronIn the illustrated example, the neural network layer k has five neurons N1, N2, N3, N4, and N5, though any number of neurons may be included in a neural network layer.

[0097] In some embodiments, each neuron of a neural network layer may have synapses implemented by multiplication circuits. For example, in FIG.4B, the first neuron N1 has five multiplication circuits, each implementing an ith synapse of the neuron N1 (e.g., configured to receive an input value from a respective ith neuron of the preceding layer k-1). For instance, the multiplication circuit labeled in FIG.4B may implement a first synapse configured to receive an input value .^01^from the first neuron (e.g., i=1) of the preceding layer k-1 (not shown). In some embodiments, each multiplication circuit may be programmed with a connection weight by which to multiply a received input value. For example, the connection weight of the multiplication circuit labeled in FIG.4B may be 3^0^ , corresponding to the weight at the first synapse (e.g., i=1) of the first neuron N1 (e.g., of the layer k.

[0098] In some embodiments, each neuron of a layer may be configured to output a sum of connection-weighted input values. For example, the output values ^20shown output from the illustrated layer k in FIG.4B may be given by the following equation: (2) ^02 = ∑3 / 02. / 01^weight programmed into a multiplication circuit implementing the ithof the layer k (e.g., configured to receive an input value from the ith neuron of the previous layer k-1), and . / 01^is the input value (e.g., from the ith neuron of the previous layer k-1) to be multipliedmultiplication circuit implementing the ith synapse of the jth neuron. For instance, in FIG.4B, the first neuron N1 (e.g., j=1) is shown outputting a value ^^0, which may be given by the following equation: ^= ∑3 / 0^ . / 01^where 3 / 0^ is the connection weight applied by the multiplication circuit implementing the ith synapse of the first neuron N1 (e.g., j=1) and . / 01^is the input value (e.g., from the ith neuron of the previous layer k-1) to be multiplied by the multiplication circuit implementing the ith synapse of the first neuron N1.

[0099] In some embodiments, the sum ∑3 / 02. / 0may be a sum of outputs from multiplication circuits implementing the ith synapses of the jth neuron (e.g., j=1 for neuron N1), such as by coupling outputs of the multiplication circuits together as may combine current signals output from the multiplication circuits. It should be appreciated that other ways of additively couplingoutputs of multiplication circuits may be used, such as using a voltage summing circuit to sum voltage signals.

[0100] FIG.4C is a grid diagram of the example neural network layer 402 of FIG.4B performing a backpropagated multiplication, according to some embodiments.

[0101] In some embodiments, the illustrated neural network layer 402 may be configured to alternatively or additionally propagate error signals from a next layer to a preceding layer. For example, as shown in FIG.4C, the illustrated neural network layer is the kth layer configured to receive error values +20, which may respectively correspond to a deactivated value for the jth neuron of the layer k from the jth synapses of the next layer k+1 (not shown), and to provide error values 5 / 01^, which may correspond to sums, from the ith synapse of each neuron of the illustrated layer k, of the error values +20received at the respective jth neuron multiplied by the connection weight of that neuron at the ith synapse. In some embodiments, the synapses of the illustrated neurons may be implemented by multiplication circuits programmed with connection weights, as described herein in connection with FIG.4B.

[0102] In some embodiments, the output values 5 / 01^, shown in FIG.4C output from the illustrated layer k, may be given by the following equation: (4) 501^ / = ∑3 / 02 +20weight programmed into a multiplication circuit implementing the ith synapse of the jth neuron of the illustrated layer k (e.g., configured to provide an error value to the ith neuron of the previous layer k-1), and +20is the input value received at the jth neuron (e.g., from the next layer k+1) to be multiplied by the multiplication circuit implementing the ith synapse. For instance, in FIG.4C, the first synapses (e.g., i=1) of each neuron are shown outputting a value 5^01^, which may be given by the following equation: (5) 501^^ = ∑3^02 +20where 3^02 is the connection weight applied by the multiplication circuit implementing the first synapse (e.g., i=1) of the jth neuron (e.g., that received the respective input value +20from the next layer k+1), and +20is the input value received at the jth neuron from the next layer k+1 to be multiplied by the multiplication circuit.

[0103] In some embodiments, the sum ∑3^02 +20may be a sum of outputs from multiplication circuits implementing respective (e.g., i=1) of the jth neurons, such as by coupling outputs of the multiplicationas may combine current signals output from the multiplication circuits. It should be appreciated that other ways of additively coupling outputs of multiplication circuits may be used, such as using a voltage summing circuit to sum voltage signals.

[0104] FIG.4D is a block diagram of an example programmable multiplier implementing a synapse 404 of the neural network of FIG.4A, according to some embodiments.

[0105] In some embodiments, a synapse of a neuron of the neural network of FIG.4A may be configured as shown in FIG.4D, such as including a multiplication circuit 212 coupled to a coincidence tracker 250 and memory (not shown).

[0106] In some embodiments, the multiplication circuit 212 may be configured to multiply an input, from a multiplication circuit implementing a previous layer of the network, by a programmable scalar value to produce an output for another multiplication circuit implementing a next layer of the network. For example, in FIG.4D, the multiplication circuit 212 is shown configured to receive an input . / 01^. For instance, the illustrated multiplication circuit 212 may be configured to implement the ith synapse of a neuron in the layer k of the network of FIG.4A, with the input . / 01^propagated via a multiplication circuit (not shown) that implements a synapse of the ith neuron in the layer k-1. In some embodiments, the input . / 01^may be propagated via a plurality of multiplication circuits (not shown) that implement respective synapses of the ith neuron in the layer k-1. Also in FIG.4D, the multiplication circuit 212 is shown configured to provide an output equal to 30 / 2 ∙ . / 01^. For instance, the illustrated multiplication circuit 212 may be configured to provideoutput to a multiplication circuit (not shown) (e.g., as part of a sum of outputs from multiple synapses of the neuron) that implements the jth synapse in the next layer k+1, such as via an activation circuit of the integrated circuit (not shown) and / or a processor (e.g., 110, which may perform activation).

[0107] In some embodiments, the multiplication circuit 212 may be configured to multiply an input, from a multiplication circuit implementing a next layer of the network, by a programmable scalar value to produce an output for another multiplication circuit implementing a previous layer of the network. For example, in FIG.4D, the multiplication circuit 212 is shown configuredto receive an input +20. For instance, as described above, the illustrated multiplication circuit 212 may be configured to implement an ith synapse of the jth neuron in the layer k of the network of FIG.4A, with the input +20propagated via a multiplication circuit (not shown) that implements the jth synapse of a neuron in the layer k+1. In some embodiments, the input +20may be propagated via a plurality of multiplication circuits (not shown) that implement the jth synapses, respectively, of a plurality of respective neurons in the layer k+1 Also in FIG.4D, the multiplication circuit 212 is shown configured to provide an output equal to 30 / 2 ∙ +20. For instance, the illustrated multiplication circuit 212 may be configured to the output to amultiplication circuit (not shown) (e.g., as part of a sum of outputs from neurons) that implements a synapse of the ith neuron in the previous layer k-1, such as via a deactivation circuit of the integrated circuit (not shown) and / or a processor (e.g., 110, which may perform deactivation).

[0108] In some embodiments, the multiplication circuit 212 may be configured to perform multiplication (e.g., forward and / or backward) that is independent of which circuit terminal receives the input and which terminal receives the output. For example, a first circuit terminal (e.g., input signal 202) may receive an input and a second circuit terminal (e.g., output signal 204) may provide the output as the input multiplied by a programmable scalar value, whereas the second circuit terminal may receive an input and the second circuit terminal may provide the output multiplied by a transpose of the programmable scalar value (e.g., when viewed as a layer of neurons).

[0109] In some embodiments, the illustrated multiplication circuit 212 may be selectable for training among an array of multiplication circuits (e.g., implementing a neural network). For example, as shown in FIG.4D, the multiplication circuit 212 is shown configured to receive a train-enable signal, which may enable updating the programmable scalar value of the multiplication circuit 212, such as by enabling writing to a memory cell storing a value that controls the programmable scalar value, enabling a programming circuit 208 coupled to the multiplication circuit to increment and / or decrement its state in response to the coincidence tracker 250, and / or swapping input and output designed circuit terminals of the multiplication circuit 212.

[0110] In some embodiments, multiplication circuits of an integrated circuit may be configured to propagate signals (e.g., Y and D in FIG.1A) to the coincidence tracker 250, which may beconfigured to determine whether to update the path control value stored in the memory cell 240 based on the signals. For example, in an example machine learning training operation, a connection weight update may be given by the following equation: (6) ∆302 / = −7+20. / 01^in the weight matrix at layer k of the neural network, . / 01^is the input the jth neuron in the layer k, +20is the back- error at thelayer k with respect to the input signal at the jth neuron, and 7 is the learning rate of the neural network. For instance, as described above, the input signal . / 01^may be propagated via a multiplication circuit implementing a synapse of the ith neuron of the previous layer k-1 (e.g., regardless of whether activation was performed onboard or outside of the integrated circuit), such as one of a plurality of multiplication circuits implementing respective synapses of the ith neuron of the previous layer k-1. The back-propagated error +20at the jth neuron of the layer k may be given by the following equation: (7) +02 = 520890"):;^2 < = 520=(.20) where 89(^0) is the derivative of the activation fu0"): 2nction applied to the output signal ^2at the layer k, equivalent to =(.20) as the deactivation function applied to the output signal .20at the layer k, and 520is a back-propagated error value from the jth synapse(s) of the layer k+1 given by the following equation: (8) 502 = ∑3 / 02^^+ / 0^^weight matrix for the layer k+1 and + / 0^^is the error signal ith neuron of the layer k+1. For instance, as described above, the back- propagated value 520may be propagated to the multiplication circuit 212 via a multiplication circuit implementing the jth synapse of a neuron of the next layer k+1 (e.g., regardless of whether deactivation was performed onboard or outside of the integrated circuit), such as one of a plurality of multiplication circuits implementing respective jth synapses of the neurons of the next layer k+1.

[0111] In some embodiments, the coincidence tracker 250 may be configured to calculate the result of equation (1) above using the signals . / 01^and +20from the previous layer k-1 and the next layer k+1, respectively. For example, the signals . / 01^and +20may be filtered into arespective pair of pulses having probabilities based on the learning rate 7 and the value of the signal . / 01^or +20, respectively. For example, the weight change of equation (1) may be derived from equation:(9) / 2applied, 3Cis a first probability constant by which theto set a probability of a first pulse (e.g., generated by a stochastic pulse generator operating at the set probability), and 3Dis a second probability constant by which the signal +20is multiplied to set a second probability of a second pulse. For instance, coincidence of the first and second pulses may be used to derive ∆3 in equation (4). In some embodiments, the values of 3Cand 3Dmay be set to satisfy the following equation: (10) 7 = −EFGAB^3C3D .coincidence tracker 250 may be configured to output a signalindicating a number of coincidences (e.g., intersections in time) between the pulses, which in turn may provide the value ∆3 / 02. For example, depending on the output Δ of the coincidence tracker 250, an adder circuit may sum to a value that triggers or does not trigger a state update (e.g., based on a predetermined state count threshold), which in turn may cause the state update circuit to write a value in the memory 140.

[0113] While the coincidence tracker 250 may be, and is shown, within the programmable multiplier 200 in FIG.4D, it should be appreciated that the coincidence tracker 250 need not be co-located with the multiplication circuit 212 and / or the integrated circuit that includes the multiplication circuit 212.

[0114] In some embodiments, the synapse 404 shown in FIG.4D may be implemented as at least a portion of an integrated circuit, with a first circuit including the multiplication circuit 212 configured to multiply a first input (e.g., . / 01^) by a first programmable scalar value (e.g., 3 / 02 ), a second circuit including another multiplication circuit (not shown, e.g.,of the previous layer k-1) configured to multiply a second input (e.g., .201^) by a second programmable scalar value (e.g., 320 / 1^), and a third circuit including or coupled to the coincidence tracker 250the first programmable scalar value (e.g., 3 / 02 ) based on a signal (e.g., . / 01^) propagated via the second circuit. In some embodiments, a fourthcircuit including a multiplication circuit (not shown, e.g., implementing a synapse of the next layer k+1) may be configured to multiply a third input (e.g., + / 0^^) by a third programmable scalar value (e.g., 320 / ^^), and the third circuit may be configured to update the first programmable scalar value based on the signal (e.g., . / 01^) propagated via the second circuit and a second signal (e.g., +20) propagated via the fourth circuit.

[0115] In some embodiments, an integrated circuit may include an array of synapses of FIG.4D implemented using respective multiplication circuits 212, each multiplication circuit 212 configured to control a programmable scalar value (e.g., implemented by a selectable impedance path) based on an output signal (e.g., . / 01^and / or +20) provided by another of the array of multiplication circuits 212 (e.g., implementing the previous and / or next layer). In some embodiments, each multiplication circuit 212 may be configured to receive the output signal e.g., . / 01^as a first output signal from a first multiplication circuit 212 (e.g., implementing a synapse of the previous layer k-1) and a second output signal (e.g., +20) from a second multiplication circuit 212 (e.g., implementing a synapse of the next layer k+1) and to generate a third output signal (e.g., 30 / 2 ∙ . / 01^) for the second multiplication circuit by propagating the first output signal (e.g., . / 01^), the multiplication circuit may be configured to control the programmable scalar value based on the first and second output signals (e.g., . / 01^and +20).

[0116] FIG.5A is a top view of a portion of an example integrated circuit 500 including an array 502 of resistor-based multiplication circuits that may be included in the system 100a, 100b, and / or 100c, according to some embodiments. FIG.5B is a top view of the portion of the example integrated circuit 500 with the first and second conductive portions 512, 522 hidden from view, according to some embodiments.

[0117] In some embodiments, the array 502 of multiplication circuits (FIG.5B) may be configured in the manner described herein for array 300 of FIG.3. For example, each multiplication circuit of the array may include a plurality of paths, each path including a switch (e.g., 320) and an impedance (e.g., 310). In the illustrated embodiment, the array 502 includes two multiplication circuits, with one multiplication circuit 503 indicated by a dashed box in FIG. 5B. The array 502 includes six unit cell circuits 530, with each illustrated multiplication circuit including a subarray of the array 502 with three unit cell circuits 530. The unit cell circuits 530are shown in FIG.5A interconnected by conductive portions 512, 522 of the integrated circuit to form multiplication circuits, as described further below.

[0118] In some embodiments, conductive portions of the integrated circuit 500 may be coupled to inputs and outputs of the integrated circuit 500 and to the multiplication circuits. For example, in FIG.5A, the integrated circuit 500 has two first conductive portions 512 respectively coupled to inputs 510a and 510b and three second conductive portions 522 all coupled to output 520. For instance, in FIG.5A, each first conductive portion 512 is shown coupled to a respective row of unit cell circuits 530 of the array 502 and each second conductive portion is shown coupled to a respective column of unit cell circuits 530 of the array 502. In the illustrated embodiment, multiplication circuit 503 is coupled to input 510b and output 520, with output 520 configured as the sum of outputs of both multiplication circuits shown in FIG.5A.

[0119] In some embodiments, each multiplication circuit may be configured to receive one or more path select signals for selecting a respective one or more switches of the circuit. For example, as shown in FIG.5A, the integrated circuit includes switch-control conductive portions 504 coupled to respective paths of the unit cell circuits 530. In the illustrated embodiment, the multiplication circuit 503 includes three paths of three respective unit cell circuits 530, each path including a resistor 532 (FIG.5B) coupled to input 510a by a first conductive portion 512 and to output 520 via a respective one of the second conductive portions 522. Also as shown, each unit cell circuit 530 includes a transistor 534 coupled to a respective switch-control conductive portion 504 and coupled between the first conductive portion 512 and the resistor 532. In some embodiments, each switch-control conductive portion 504 may be electrically isolated from one another (e.g., with little to no communicative coupling therebetween) such that each transistor 534 may receive its own individual path select signal. In contrast, in some embodiments, at least some of the first conductive portions 512 and / or second conductive portions 522 may be coupled to one another, such as shown in FIG.5A where the three illustrated second conductive portions 522 are coupled to one another to combine current signals into an output 520. It should be appreciated that, as described above in connection with FIG.3, signals could be received at the circuit terminals labeled as outputs in FIG.5A (e.g., via second conductive portions 522) and signals could be provided at the circuit terminals labeled as inputs in FIG.5A (e.g., via first conductive portions 522), such as for back-propagated signal multiplication.

[0120] In the illustrated embodiment, the transistor 534 of each unit cell has a first channel terminal (e.g., source S) coupled to a first conductive portion 512, a second channel terminal (e.g., drain D) coupled to a first end of the resistor 532, and a control terminal (e.g., gate G) coupled to the switch-control conductive portion 504, and a second end of the resistor is coupled to a second conductive portion 522. In some embodiments, the transistors 534 may be metal- oxide-semiconductor field effect transistors (MOSFETs), such as thin-film transistors (TFTs), although other transistors may be used, such as bipolar junction transistors (BJTs). In some embodiments, the resistors 532 may include meandering conductive traces that provide a fixed resistance value, although other types of resistors and / or impedances may be used. In some cases, impedances may have non-negligible inductance and / or capacitance values, whereas in other cases, impedances may be substantially entirely resistive, resulting in resistor-based multiplication circuits.

[0121] In some embodiments, the multiplication circuits of the array 502 may have a scalable structure that is reprogrammable when coupled to a memory. For example, as shown in FIGs. 5A-5B, the multiplication circuits may be formed as a subarray of unit cell circuits 530, each unit cell circuit 530 having an impedance (e.g., resistor 532) and a switch (e.g., transistor 534), with the impedance being individually configured for that unit cell circuit 530 during manufacture. In this example, interconnections between the unit cell circuits, such as first conductive portions 512 and second conductive portions 522 may be configured during manufacture to divide the unit cell circuits into subarrays (e.g., among multiplication circuits, such as 503). For instance, impedances within each multiplication circuit may have different impedance values from one another. In some embodiments, the scalar multiple value provided by each multiplication circuit may be reprogrammed by changing the values provided to each switch via the switch-control conductive portions 504.

[0122] In some embodiments, the integrated circuit 500 may have a first layer including the first conductive portions 512 and a second layer including the second conductive portions 522. For example, the first conductive portions 512 may be coupled to respective input (and / or output) terminals of the integrated circuit (not shown) and the second conductive portions 522 may be coupled to one or more output (and / or input) terminals of the integrated circuit (not shown), such as depending on whether and / or how many of the second conductive portions 522 are connected together to sum the current signals therein. In some embodiments, the array 502 of multiplicationcircuits (and / or a subarray thereof) may form at least a portion of a programmable impedance circuit. For example, at least one of the multiplication circuits may have impedances (e.g., resistor 532) coupled in parallel between an input (e.g., 510a via one of the first conductive portions 512) and an output (e.g., 520 via one of the second conductive portions 522). In some embodiments, switches (e.g., transistor 534) may be coupled in series with respective ones of the impedances between the input and the output (e.g., first and second conductive portions 512 and 522). It should be appreciated that, when signals are received at the second conductive portions 522 and provided at the first conductive portions 512, the impedances and switches are still coupled in parallel between the circuit terminals used as input and output, respectively.

[0123] In some embodiments, a layer may have multiple first conductive portions 512, such as configured to provide respective inputs 510a and 510b. For example, each first conductive portion 512 may be coupled to a respective input terminal. In some embodiments, another layer may have multiple second conductive portions 522, such as coupled together to provide output 520 to a same output terminal, or electrically isolated and configured to provide respective outputs to respective output terminals. In some embodiments, where multiple second conductive portions 522 are configured to provide respective outputs to respective output terminals, a first programmable impedance circuit (e.g., multiplication circuit 503) may be coupled between one of the first conductive portions 512 (e.g., to receive input 510a) and at least one of the second conductive portions 522 (e.g., one of the three second conductive portions 522 shown in FIG. 5A) to provide a first output, and a second programmable impedance circuit (e.g., including the top three unit cell circuits) may be coupled between one of the first conductive portions 512 (e.g., to receive input 510a) and at least one of the second conductive portions 522 (e.g., a different one of the second conductive portions 522) to provide a second output.

[0124] While FIGs.5A-5B show each row of the array coupled to the same input and each column of the array coupled to the same output, it should be appreciated that rows and / or columns may have unit cell circuits respectively coupled to multiple inputs and / or outputs. As one example, a row of an array may have a first conductive portion extending from an end of the row to the middle of the row and another first conductive portion extending from the opposite end of the row to the middle of the row. Likewise, a column of an array may have a second conductive portion extending from an end of the column to the middle of the column and anothersecond conductive portion extending from the opposite end of the column to the middle of the column.

[0125] In addition, while FIGs.5A-5B show each multiplication circuit having three unit cell circuits 530 of the array 502, a multiplication circuit may have any number of unit cell circuits, and arrays may include multiplication circuits having different numbers of unit cell circuits.

[0126] Moreover, while FIGs.5A-5B show a single transistor per unit cell circuit, it should be appreciated that alternative or additional transistors may be included per unit cell circuit. For example, at least some unit cell circuits may alternatively or additionally include a transistor configured as a row and / or column select transistor, such as with the channel coupled between the resistor and a conductive portion (e.g., in series with the illustrated transistor) and the control terminal couple to a metal portion to receive a row and / or column select signal. For instance, a row and / or column select transistor may permit inputs to the integrated circuit (e.g., from a processor 110) to include input signals and row and / or column select signals as an alternative or in addition to inputs including respective input signals for each multiplication circuit and / or unit cell circuit, permitting flexibility of operation and in implementation of the I / O interface.

[0127] FIG.6A is a perspective view of a resistor 600 that may be included in the resistor-based multiplication circuits of FIGs.5A and 5B, according to some embodiments. FIG.6B is a top view of the conductive trace 602 and electrodes 604a, 604b of the resistor 600, according to some embodiments.

[0128] In some embodiments, the resistor 600 may be used in unit cell circuits 530 of the integrated circuit 500. As shown in FIGs.6A-6B, the resistor 600 has a conductive trace 602 that meanders from a first electrode 604a to a second electrode 604b to provide resistance between a first conductive portion 610a coupled to the first electrode 604a and a second conductive portions 610b coupled to the second electrode 604b. For instance, the first conductive portion 610a may be configured to provide an input signal and the second conductive portion 610b may be configured to obtain an output signal, although in some embodiments the first and / or second electrode 604a, 604b may be coupled to a transistor that is, in turn, coupled to a conductive portion (e.g., as shown in FIGs.5A-5B). In the illustrated embodiment, the meandering conductive trace 602 may be fixed in position when manufactured to provide a fixed resistance in a unit cell of a multiplication circuit. According to various embodiments, the meandering conductive trace 602 may be formed using gold, copper, or other suitable metal, whereas infurther embodiments, the trace 602 (or like resistance-fixing component coupled between a pair of electrodes) may be formed using semiconductor material.

[0129] FIG.7 is a top view of an alternative example of a unit cell circuit 700 that may be included in the integrated circuit of FIGs.5A-5B, according to some embodiments.

[0130] In some embodiments, the unit cell circuit 700 shown in FIG.7 may be used in unit cell circuits 530 of the integrated circuit 500. As shown in FIG.7, the unit cell circuit 700 includes a plurality of resistors in series with respective transistors and sharing an electrode, according to some embodiments. The resistors shown in FIG.7 differ from the resistor 600 (FIG.6A) in that they are coupled between a plurality of transistors 734a, 734b, 734c, and 734d, respectively, and a common electrode 706.

[0131] As shown in FIG.7, the unit cell circuit 700 includes four fixed impedances in series with respective switches. For example, the unit cell circuit 700 of FIG.7 includes four conductive traces 702a, 702b, 702c, and 702d, each coupled in series with a respective transistor 734a, 734b, 734c, and 734d. In the illustrated example, each trace 702a, 702b, 702c, and 702d terminates at one end at a respective electrode 704a, 704b, 704c, 704d, which is coupled to the respective transistor 734a, 734b, 734c, and 734d. Also shown in FIG.7, each trace 702a, 702b, 702c, and 702d terminates at another end at a common electrode 706. For example, each trace 702a, 702b, 702c, and 702d may have a different fixed impedance value, such as due to different meandering trace geometries. It should be appreciated that, in some embodiments, at least some traces within a unit cell circuit may have the same fixed impedance value. Moreover, in some embodiments, when disposed in a row and / or column, unit cell circuits with the resistive structure of FIG.7 may have different fixed impedances (e.g., combinations of fixed impedances) along at least a part of each row and / or column, depending on the application.

[0132] In some embodiments, the unit cell circuit of FIG.7 may be coupled to and between one or more first conductive portions (e.g., 512) and a second conductive portion (e.g., 522). For example, channel terminals of transistors 734a, 734b, 734c, and 734d may be coupled to one first conductive portion and the common electrode 706 may be coupled to the second conductive portion, such that the series pairs of fixed impedances and transistors are coupled in parallel with one another. For instance, control terminals of transistor 734a, 734b, 734c, and 734d may be configured to receive respective signals selecting the respective trace 702a, 702b, 702c, and 702d, which may set the parallel impedance the unit cell circuit provides between the firstconductive portion and the second conductive portion. Alternatively or additionally, at least some channel terminals of transistor 734a, 734b, 734c, and 734dmay be coupled to respective first conductive portions. For instance, control terminals of transistors 734a, 734b, 734c, and 734d may be configured to receive respective signals selecting the respective trace 702a, 702b, 702c, and 702d, which may select which first conductive portion(s) to couple to. It should be appreciated that, according to various embodiments, one or more signals may be received at transistor 734a, 734b, 734c, and 734d, and / or at the common electrode 706, and / or one or more signals may be provided at transistor 734a, 734b, 734c, and 734d, and / or at the common electrode 706, depending on the application. In some cases, an integrated circuit may be reconfigurable (e.g., based on interaction with input and output terminals of the integrated circuit) to use the same unit cell circuit in either configuration, such as to perform multiplication for an inference (e.g., forward propagation) and / or training (e.g., back-propagation).

[0133] FIG.8 is a block diagram of an example unit cell circuit 800 with a multiplication path 806, an adder circuit 8081, and a state update circuit 8082, which may be included in the integrated circuit 500, according to some embodiments.

[0134] As shown in FIG.8, a unit cell circuit 800 may be combinable into a multiplication circuit (e.g., 503) by including a multiplication path 806 having a switch 820 and an impedance 810, the path 806 configured to receive a first input signal 802 at a first circuit terminal, provide a first output signal 804 at a second circuit terminal, receive a second input signal 8091 at the second circuit terminal, and provide a second output signal 8092 at the first circuit terminal.

[0135] In some embodiments, the input signal 802 may be obtained via another multiplication circuit (not shown, e.g., implementing a synapse in a previous network layer), such as for performing an inference at the output signal 804 for propagating to a yet another multiplication circuit (not shown, e.g., implementing a synapse in a next neuron layer). In some embodiments, the output signal 804 may be provided to a coincidence tracking circuit (not shown) of another multiplication circuit (not shown, e.g., implementing a synapse in the next neuron layer), such as for determining whether to update the programmable scalar value in the destination multiplication circuit. In some embodiments, the second input signal 8091 may be obtained from another multiplication circuit (not shown, e.g., implementing a synapse in the next neuron layer), such as for obtaining a back-propagated error signal to provide, as the second output signal 8092, to yet another multiplication circuit (not shown, e.g., implementing a synapse in the previousneuron layer). In some embodiments, the adder circuit 8081 may be configured to receive an indication from the coincidence tracking circuit for the multiplication circuit that includes the illustrated unit cell circuit 800 as to whether to update the memory (not shown) to which the state update circuit 8082 may be coupled for updating the programmable scalar value of the illustrated multiplication path(s) 806.

[0136] It should be appreciated that, while a single path 806 is shown in the unit cell circuit 800, any number of paths may be included, such as corresponding to the conductive traces shown in the unit cell circuit 700 of FIG.7.

[0137] FIG.9 is a block diagram of an example unit cell circuit 900 with a multiplication path 906, an adder circuit 9081, a state update circuit 9082, and a memory cell 940, which may be included in the integrated circuit 500, according to some embodiments.

[0138] As shown in FIG.9, a unit cell circuit 900 may be combinable into a multiplication circuit (e.g., 503) by including a multiplication path 906 having a switch 920 and an impedance 910, the path 906 configured to receive a first input signal 902 and provide a second output signal 904, as well as receive a second input signal 9091 and provide a second output signal 9092. In some embodiments, the first output signal 904 may be provided to a coincidence tracking circuit (not shown) of another multiplication circuit (e.g., implementing a synapse in a next neuron layer) and the second output signal 9092 may be provided to yet another multiplication circuit (not shown, e.g., implementing a synapse in a previous neuron layer). In some embodiments, the adder circuit 9081 may be configured to receive an indication from the coincidence tracking circuit for the multiplication circuit that includes the illustrated unit cell circuit 900 as to whether to update the memory cell 940 for updating the programmable scalar value of the illustrated multiplication path(s) 906. For instance, a memory may include a memory cell 940 co-located with each unit cell circuit 900, such as a bitcell and / or a group of bitcells. In some embodiments, the memory cell may be alternatively or additionally programmed with one or more values (e.g., by a processor 110) by providing write enable and write data signals to the memory cell 940, as may be used to initialize the memory cell 940 prior to training.

[0139] FIG.10 is a block diagram of an example unit cell circuit 1000 with a multiplication path 1006, an adder circuit 1081, a state update circuit 1082, a memory cell 1040, and a coincidence tracking circuit 1050, which may be included in the integrated circuit 500, according to some embodiments.

[0140] As shown in FIG.10, a unit cell circuit 1000 may be combinable into a multiplication circuit (e.g., 503) by including a multiplication path 1006 having a switch 1020 and an impedance 1010, the path 1006 configured to receive a first input signal 1002 and provide a first output signal 1004, as well as receive a second input signal 1091 and provide a second output signal 1092. In some embodiments, the first output signal 1004 may be provided to a coincidence tracking circuit (not shown) of another multiplication circuit (e.g., implementing a synapse in the next neuron layer) and the second output signal 1092 may be provided to yet another multiplication circuit (not shown, e.g., implementing a synapse in a previous neuron layer). In some embodiments, the adder circuit 1081 may be configured to receive an indication from the coincidence tracking circuit 1050 as to whether to update the memory cell 1040 for updating the programmable scalar value of the illustrated multiplication path(s) 1006. For example, as shown in FIG.10, the coincidence tracking circuit 1050 is configured to receive a first signal 1052 and a second signal 1054. For instance, the first signal 1052 may be a signal propagated from the input via a multiplication circuit implementing a synapse in a previous neuron layer and the second signal 1054 may be a signal propagated from the output via a multiplication circuit implementing a synapse in a next neuron layer. In turn, the first output signal 1004 provided from the illustrated unit cell circuit 1000 may form the basis of a first signal 1052 at a unit cell circuit of a multiplication circuit (not shown) implementing a synapse in the next neuron layer and the second output signal 1092 may form the basis of a second input signal 1054 of a unit cell circuit of a multiplication circuit (not shown) implementing a synapse in the previous neuron layer.

[0141] In some embodiments, the coincidence tracking circuit 1050 may be configured to determine whether to update a value in the memory cell 1040 for controlling the switch(es) 1020 of the unit cell circuit 1000 individually, whereas in other embodiments, a coincidence tracking circuit may be provided for each multiplication circuit (e.g., group of unit cell circuits) to control values in the memory cells 1040 that, in combination, control the switches of the unit cell circuits to produce an updated overall parallel impedance of the impedances of the unit cell circuits.

[0142] It should be appreciated that any of the illustrated unit cell circuits 800, 900, 1000 may be included in an integrated circuit (e.g., 102a) in which the memory and coincidence tracking circuit are separate from the integrated circuit, in an integrated circuit (e.g., 102b) in which the memory is included in the integrated circuit and the coincidence tracking circuit is separate from the integrated circuit, in an integrated circuit in which the memory is separate from the integratedcircuit and the coincidence tracking circuit is included in the integrated circuit, and / or in an integrated circuit (e.g., 102c) in which both the memory and coincidence tracking circuit are included in the integrated circuit.

[0143] FIG.11 is a circuit diagram of an example adder circuit 1100 that may be included in the unit cell circuit 800, 900, and / or 1000, according to some embodiments.

[0144] As shown in FIG.11, the adder circuit 1100 is configured to receive three inputs A, B, and Cinand provide two outputs SUM and Carry OUT. The adder circuit 1100 as shown includes a first exclusive OR (XOR) gate 1102 configured to receive the inputs A, B and a second XOR gate 1104 configured to receive an output of the first XOR gate 1102 and to receive the input Cin so as to output SUM. For instance, SUM may represent a binary sum of the values of inputs A, B further incorporating a carried input (e.g., from a Carry OUT output from another adder circuit). The adder circuit 1100 as shown further includes a first AND gate 1106 configured to receive the output of the first XOR gate 1102 and the input Cin, a second AND gate 1108 configured to receive the inputs A, B, and an OR gate 1110 configured to receive the outputs of the first AND gate 1106 and the second AND gate 1108 and provide the Carry OUT signal. For instance, the Carry OUT signal may represent a carried digit from SUM due to one of the inputs A, B being 1 and the input Cinbeing 1 and / or due to the inputs A, B each being 1.

[0145] In some embodiments, the adder circuit 1100 may be configured to receive an indication from a coincidence tracking circuit, such as a 2-bit (e.g., digitized) count value that the adder circuit 1100 may be configured to use to increment and / or decrement a state maintained by the adder circuit 1100 (e.g., together with a state update circuit). It should be appreciated that an adder circuit may be alternatively or additionally implemented using analog circuitry (e.g., for directly receiving an analog count value from an analog counter circuit).

[0146] FIG.12 is a circuit diagram of an example counter circuit 1200 that may be included in the coincidence tracking circuit 1050, according to some embodiments.

[0147] As shown in FIG.12, the counter circuit 1200 is configured to receive two inputs x, d, which may correspond to a first probability-filtered version of a first signal from a first multiplication circuit (e.g., implementing a synapse in a previous neuron layer) and a second probability-filtered version of a second signal from a second multiplication circuit (e.g., implementing a synapse in a next neuron layer), respectively. For instance, the first probability- filtered signal and the second probability-filtered signal may each be obtained by filtering (e.g.,multiplying) the signals by respective probability constants to set the probability of respective stochastic pulse generators, with the outputs of the pulse generators being input to the counter circuit 1200.

[0148] The counter circuit 1200 as shown includes a buffer amplifier U1 with unity-gain configured resistors R2, R3, R4, and R5 (e.g., all having the same resistance values) and a pair of diodes D1, D2 with a shunt resistor R1 coupled between and a shunt capacitor C1 following the second diode D2. In some embodiments, this configuration may be configured to count the number of coincidence events in which the pulse-filtered inputs x, d have different values. For instance, the counter circuit 1200 may be configured to buffer a difference between the inputs x, d into the capacitor C1 via the diodes D1, D2, which may be digitized and / or may trigger an analog circuit to obtain a count based on the charge of the capacitor C1. While not shown in FIG. 12, additional circuitry may be provided to discharge the capacitor C1 so as to reset the counter circuit 1200.

[0149] FIG.13 is a table 1300 of counter values that may be obtained via the counter circuit 1200 corresponding to coincident events arising from pulse-filtered signals input to the counter circuit 1200, according to some embodiments.

[0150] As shown in FIG.13, a sequence of 10 pulses (e.g., Npulse=10) may be used to count coincident events between a first signal yi (e.g., propagated via a previous layer) having a value of 0.5 and a second signal δj (e.g., propagated via a next layer) having a value of -1, where the first signal is probability filtered by multiplying its value with a probability constant Cyset to 0.5 to obtain (e.g., using a first pulse generator) a first pulse signal with a 50% likelihood of a pulse per period, and the second signal is probability filtered by multiplying its value with a probability constant Cδ set to 0.25 to obtain (e.g., using a second pulse generator) a second pulse with a 25% likelihood of a pulse per period (e.g., representing η = 1.5). In the illustrated sequence, the Cy- probability-filtered signal yi reaches a 1 value 3 times in 12 periods, resulting in a measured probability of 0.25, matching the expected probability of 0.25 (e.g., probability of Cy multiplied by value of yi). Also as illustrated, the Cδ-probability-filtered signal δjreaches a 1 value 3 times in 12 periods, matching the expected probability of 0.25 (e.g., probability of Cδ multiplied by value of δj). However, the 1 values from the Cy-filtered signal yi only coincide with the -1 values from the Cδ-filtered signal δjonce, resulting in a measured overall probability of 0.083, less than the expected overall expected coincidence probability of 0.0625.

[0151] During operation of the counter circuit 1200 throughout this sequence, the count value stored in the capacitor C1 only increases at period 5 when the Cy-filtered signal yi reaches a 1 value while the Cδ-filtered signal δj reaches a -1 value, resulting in opposite sign values at the inputs of the amplifier U1. Thus, after period 12, the counter value represents a count of 1, which may be provided to an adder circuit to potentially increment and / or decrement a state that controls a path select signal. For instance, referring to equation (4) above, a low count may indicate little to no state changes, which may indicate that no changes are needed to the programmable scalar value corresponding to the connection weight it may apply.

[0152] While several embodiments of the present disclosure have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the functions and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the present disclosure. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the teachings of the present disclosure is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the disclosure described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, the disclosure may be practiced otherwise than as specifically described and claimed. The present disclosure is directed to each individual feature, system, article, material, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, and / or methods, if such features, systems, articles, materials, and / or methods are not mutually inconsistent, is included within the scope of the present disclosure.

[0153] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0154] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Other elements mayoptionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified unless clearly indicated to the contrary. Thus, as a non-limiting example, a reference to “A and / or B,” when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A without B (optionally including elements other than B); in another embodiment, to B without A (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0155] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of” or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0156] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0157] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS 1. An integrated circuit, comprising: a first circuit configured to multiply a first input by a first programmable scalar value using a first fixed impedance; a second circuit configured to multiply a second input by a second programmable scalar value using a second fixed impedance; and a third circuit configured to update the first programmable scalar value based on a signal propagated via the second circuit.

2. The integrated circuit of claim 1, wherein the first circuit comprises a first plurality of impedance-switch pairs and the second circuit comprises a second plurality of impedance-switch pairs, each impedance-switch pair of the first plurality of impedance-switch pairs and the second plurality of impedance-switch pairs comprising a fixed impedance coupled in series with a switch, and the first plurality of impedance-switch pairs being coupled in parallel with one another and the second plurality of impedance-switch pairs being coupled in parallel with one another.

3. The integrated circuit of claim 1 or 2, further comprising: a fourth circuit configured to multiply a third input by a third programmable scalar value using a third fixed impedance, wherein the third circuit is configured to update the first programmable scalar value based on the signal propagated via the second circuit and a second signal propagated via the fourth circuit.

4. The integrated circuit of any one of claims 1 to 3, wherein the third circuit comprises an adder circuit and a state update circuit.

5. The integrated circuit of claim 4, wherein: the first circuit and the second circuit are disposed in an array of unit cell circuits, unit cell circuits of the array arranged in subarrays, each subarray configured to multiply a respective input by a respective programmable scalar value using a respective fixed impedance, the firstcircuit comprising a first subarray of the subarrays and the second circuit comprising a second subarray of the subarrays; and the third circuit comprises, at least for each subarray, an adder circuit and a state update circuit configured to update the respective programmable scalar value based on a respective signal propagated via another subarray.

6. The integrated circuit of claim 5, wherein each unit cell circuit of the first circuit is co- located with the adder circuit and the state update circuit of the third circuit.

7. The integrated circuit of any one of claims 1 to 4, wherein: the second circuit is configured to provide the signal to a counter circuit; and the third circuit is configured to obtain, from the counter circuit, a count value based on an output from the second circuit and update the first programmable scalar value based on the count value.

8. The integrated circuit of claim 7, further comprising the counter circuit.

9. The integrated circuit of claim 8, wherein: the first circuit and the second circuit are disposed in an array of unit cell circuits, unit cell circuits of the array arranged in subarrays, each subarray configured to multiply a respective input by a respective programmable scalar value using a respective fixed impedance, the first circuit comprising a first subarray of the subarrays and the second circuit comprising a second subarray of the subarrays; the third circuit comprises, co-located with each subarray, an adder circuit and a state update circuit configured to update the respective programmable scalar value based on a respective signal propagated via another subarray; and a counter circuit is co-located with each subarray, the counter circuit of the subarray is configured to receive the respective signal, and the adder circuit and the state update circuit are configured to obtain a respective count value from the counter circuit.

10. The integrated circuit of any one of claims 1 to 9, wherein:the first circuit is configured to receive a first value from a memory that sets the first programmable scalar value in the first circuit; and the third circuit is configured to store the first value in the memory used to set the first programmable scalar value in the first circuit.

11. The integrated circuit of claim 10, further comprising the memory configured to set the first programmable scalar value in the first circuit.

12. A system, comprising: the integrated circuit of any one of claims 1 to 11; and a processor configured to provide a labeled input-output pair to the integrated circuit, wherein the second circuit is configured to propagate the signal based on an input of the labeled input-output pair and / or based on an error with respect to an output of the labeled input- output pair.

13. An integrated circuit, comprising: an array of multiplication circuits, each multiplication circuit comprising: a selectable path comprising an impedance; and a state update circuit configured to control selection of the selectable path based on an output signal provided by a selectable path of another of the array of multiplication circuits.

14. The integrated circuit of claim 13, wherein: each multiplication circuit of the array of multiplication circuits is configured to: receive the output signal as a first output signal from a first multiplication circuit of the array of multiplication circuits; receive a second output signal from a second multiplication circuit of the array of multiplication circuits; and generate a third output signal for the second multiplication circuit by propagating the first output signal via the selectable path; andthe state update circuit is configured to control selection of the selectable path based on the first output signal and the second output signal.

15. The integrated circuit of claim 13 or 14, wherein: the selectable paths of at least a first subset of the array of multiplication circuits are configured to provide the output signals to respective counter circuits of at least a second subset of the array of multiplication circuits to control selection of the selectable paths of the second subset of the array of multiplication circuits; and the state update circuits of the second subset of the array of multiplication circuits are configured to control selection of the selectable paths of the second subset of the array of multiplication circuits based on a count value obtained from the respective counter circuits based on the output signals.

16. The integrated circuit of claim 15, wherein: each multiplication circuit of the first subset and the second subset of the array of multiplication circuits comprises a first circuit terminal and a second circuit terminal, with the selectable path coupled between the first circuit terminal and the second circuit terminal; and the selectable path of each of the second subset of the array of multiplication circuits is coupled between the first circuit terminal of a first multiplication circuit of the first subset and the second circuit terminal of a second multiplication circuit of the first subset.

17. The integrated circuit of claim 15, wherein each multiplication circuit of the second subset of the array of multiplication circuits further comprises an adder circuit coupled to an input of the state update circuit and configured to receive the count value from the counter circuit.

18. The integrated circuit of claim 15 or 17, wherein each multiplication circuit of the second subset of the array of multiplication circuits further comprises the counter circuit.

19. The integrated circuit of any one of claims 15 to 18, wherein:the state update circuits of the second subset of the array of multiplication circuits are configured to control respective values stored in a memory; and the selectable paths of the second subset of the array of multiplication circuits are configured to be selected based on the respective values stored in the memory.

20. The integrated circuit of claim 19, wherein each multiplication circuit further comprises, for each selectable path of the multiplication circuit, a respective memory cell of the memory, the respective memory cell configured to store the respective value.

21. The integrated circuit of any one of claims 13 to 20, wherein the selectable path of each multiplication circuit further comprises a switch coupled in series with the impedance.

22. The integrated circuit of claim 21, wherein a subset of the array of multiplication circuits comprise a plurality of selectable paths coupled in parallel, each of the plurality of selectable paths comprising an impedance.

23. A system, comprising: the integrated circuit of any one of claims 15 to 20; and a processor configured to provide a labeled input and a labeled output to the integrated circuit, wherein: the selectable paths of the first subset of the array of multiplication circuits are configured to: generate the output signal based on a propagation, through at least a portion of the array, of the labeled input and / or a propagation, through at least a portion of the array, of an error signal indicating a difference between an output of the array and the labeled output; and the state update circuits of the second subset of the array of multiplication circuits are configured to: control selection of the selectable path based on a coincidence between the output signal and the error signal using the state update circuit.

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