Wiring substrate and preparation method therefor, light-emitting substrate, and display apparatus

Abstract

A wiring substrate, provided with a functional region and a peripheral region located on at least one side of the functional region. The wiring substrate comprises: a base provided with a first surface; a plurality of signal lines located on the first surface and located in the functional region, the plurality of signal lines being arranged at intervals in a first direction and extending in a second direction, and the first direction intersecting with the second direction; and a plurality of dummy conductive patterns located on the first surface, at least part of the dummy conductive patterns being located in the peripheral region, and the dummy conductive patterns being insulated from the plurality of signal lines.

Description

Wiring substrate and manufacturing method thereof, light-emitting substrate, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a wiring substrate and a preparation method thereof, a light-emitting substrate, and a display device. Background Art

[0002] Light-emitting diodes (LEDs), submillimeter light-emitting diodes (Mini LEDs), or micro light-emitting diodes (Micro LEDs) are self-luminous components. Mini LEDs range in size from approximately 80μm to 500μm, while Micro LEDs are smaller than 80μm.

[0003] The above-mentioned types of LEDs can be used in the backlight modules of passive display panels. By densely distributing a large number of LEDs and coordinating with regional dimming technology, better brightness uniformity and higher color contrast can be achieved within a smaller mixing distance, thereby achieving ultra-thin, high color rendering, and power-saving terminal products.

[0004] Summary of the Invention

[0005] In one aspect, a wiring substrate is provided. The wiring substrate has a functional area and a peripheral area located on at least one side of the functional area. The wiring substrate includes a substrate, a plurality of signal lines, and a plurality of dummy conductive patterns. The substrate has a first surface; a plurality of signal lines located on the first surface and located in the functional area; the plurality of signal lines are spaced apart along a first direction and extend along a second direction; the first direction and the second direction intersect; a plurality of dummy conductive patterns are located on the first surface, with at least some of the dummy conductive patterns located in the peripheral area; the dummy conductive patterns are insulated from the plurality of signal lines.

[0006] In some embodiments, the width of the dummy conductive pattern located in the peripheral region is positively correlated with the width of the peripheral region.

[0007] In some embodiments, the minimum distance between the dummy conductive pattern located in the peripheral area and the signal line is in the range of 0.5 mm to 1.5 mm.

[0008] In some embodiments, the peripheral region surrounds the functional region; the width of the dummy conductive pattern located in the peripheral region and on opposite sides of the functional region along the first direction is greater than the width of the dummy conductive pattern located in the peripheral region and on opposite sides of the functional region along the second direction.

[0009] In some embodiments, a dummy conductive pattern is disposed between two adjacent signal lines, and the dummy conductive pattern is insulated from the two adjacent signal lines.

[0010] In some embodiments, the width of the dummy conductive pattern located between the two adjacent signal lines is positively correlated with the distance between the two adjacent signal lines.

[0011] In some embodiments, the peripheral area includes a first peripheral area located on one side of the functional area, and the first peripheral area and the functional area are spaced apart along the second direction; the wiring substrate also includes: a plurality of pad units located on the first surface and in the functional area, the pad unit including a plurality of device pad groups; a plurality of connecting lines located on the first surface and in the functional area; the connecting lines include a first connecting line and a second connecting line, the pad unit and the signal line are configured to be connected through the first connecting line; the plurality of device pad groups in the same pad unit are configured to be connected through the second connecting line; the plurality of signal lines include a ground signal line, and the end of the ground signal line away from the first peripheral area is flush with the connecting line of the plurality of connecting lines away from the peripheral area.

[0012] In some embodiments, the wiring substrate further includes: a ring-shaped electrostatic release line, located on the first surface and surrounding the functional area; the ring-shaped electrostatic release line includes a first electrostatic release sub-segment, a second electrostatic release sub-segment and a third electrostatic release sub-segment electrically connected in sequence, the first electrostatic release sub-segment and the third electrostatic release sub-segment are located on opposite sides of the functional area along the first direction, and the second electrostatic release sub-segment is located on a side of the functional area away from the first peripheral area; the distance between the second electrostatic release sub-segment and the connecting line is in the range of: 0.2mm to 0.5mm.

[0013] In some embodiments, the width of the annular electrostatic release line is positively correlated with the width of the peripheral area.

[0014] In some embodiments, the second connecting line includes a connecting sub-segment between any two adjacent device pad groups within the same pad unit, wherein the connecting sub-segment connects the two adjacent device pad groups; a dummy conductive pattern is provided on at least one side of the connecting sub-segment, and the dummy conductive pattern is parallel to the extension direction of the adjacent connecting sub-segment.

[0015] In some embodiments, in the same second connecting line, a dummy conductive pattern is provided on the same side of any two adjacent connecting sub-segments, and the two dummy conductive patterns on one side of the two adjacent connecting sub-segments are connected to each other; the overall extension direction of the two dummy conductive patterns extends along the overall direction of the two adjacent connecting sub-segments.

[0016] In some embodiments, the distance between the dummy conductive pattern and the adjacent first connecting line ranges from 0.2 mm to 0.5 mm.

[0017] In some embodiments, the multiple connecting sub-segments include: multiple first connecting sub-segments, and a second connecting sub-segment located between two adjacent first connecting sub-segments; the first connecting sub-segment extends along the second direction, and the second connecting sub-segment extends along the first direction; the multiple dummy conductive patterns include: multiple first dummy conductive patterns and multiple second dummy conductive patterns; the first dummy conductive portion extends along the second direction, and the second dummy conductive portion extends along the first direction; in the same second connecting line, at least one first dummy conductive portion is arranged between at least some adjacent first connecting sub-segments, and along the first direction, the adjacent first connecting sub-segments and the at least one first dummy conductive portion are arranged at equal intervals; and / or, at least one second dummy conductive portion is arranged between at least some adjacent second connecting sub-segments, and along the second direction, the adjacent second connecting sub-segments and the at least one second dummy conductive portion are arranged at equal intervals.

[0018] In some embodiments, the first peripheral area includes a first blank area, a binding area, and a second blank area arranged in sequence along the first direction; part of the dummy conductive pattern is arranged in the first blank area; and / or part of the dummy conductive pattern is arranged in the second blank area.

[0019] In some embodiments, the wiring substrate further includes: a plurality of alignment patterns located on the first surface; at least part of the alignment patterns are located in the first blank area and the second blank area, and the dummy conductive pattern is staggered with the alignment patterns.

[0020] In some embodiments, the wiring substrate further includes: a nickel-gold layer located on a side of the device pad group away from the substrate.

[0021] In another aspect, a method for preparing a wiring substrate is provided. The wiring substrate comprises a functional area and a peripheral area located on at least one side of the functional area. The method comprises: providing a substrate having a first surface; using a common patterning process, simultaneously forming a plurality of signal lines and a plurality of dummy conductive patterns on the first surface; the plurality of signal lines are arranged in a spaced relationship along a first direction and extend along a second direction; the first direction and the second direction intersect; at least some of the dummy conductive patterns are located in the peripheral area; and the dummy conductive patterns are insulated from the plurality of signal lines.

[0022] In some embodiments, the same patterning process is used to synchronously form multiple signal lines and the multiple dummy conductive patterns on the first surface, including: forming a seed layer on the first surface; forming a photoresist layer on the seed layer; the photoresist layer uses negative photoresist, and the photoresist layer has multiple first openings and multiple second openings, the first openings correspond to the signal lines to be formed, and the second openings correspond to the dummy conductive patterns to be formed; using an electroplating process, the signal lines are formed in the first openings, and the dummy conductive patterns are synchronously formed in the second openings; stripping the photoresist to expose part of the seed layer at the corresponding position of the stripped photoresist; using the signal lines and the dummy conductive patterns as masks, etching the seed layer to remove the part of the seed layer corresponding to the position of the photoresist.

[0023] In another aspect, a light-emitting substrate is provided, comprising a wiring substrate and a plurality of light-emitting devices. The wiring substrate is any of the wiring substrates described above. The plurality of light-emitting devices are disposed on the wiring substrate.

[0024] In another aspect, a display device is provided, comprising a light-emitting substrate and a display panel. The light-emitting substrate is any of the light-emitting substrates described above. The display panel is located on the light-emitting side of the light-emitting substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual dimensions or methods of the products involved in the embodiments of the present disclosure.

[0026] FIG1 is a structural diagram of a display device according to some embodiments;

[0027] FIG2 is another structural diagram of a display device according to some embodiments;

[0028] FIG3 is another structural diagram of a display device according to some embodiments;

[0029] FIG4 is a top view of a wiring substrate according to some embodiments;

[0030] FIG5 is another top view of a wiring substrate according to some embodiments;

[0031] FIG6 is another structural diagram of a wiring substrate according to some embodiments;

[0032] FIG7 is another structural diagram of a wiring substrate according to some embodiments;

[0033] FIG8 is another top view of a wiring substrate according to some embodiments;

[0034] FIG9 is another top view of a wiring substrate according to some embodiments;

[0035] FIG10 is another top view of a wiring substrate according to some embodiments;

[0036] FIG11 is another top view of a wiring substrate according to some embodiments;

[0037] FIG12 is another top view of a wiring substrate according to some embodiments;

[0038] FIG13 is another top view of a wiring substrate according to some embodiments;

[0039] FIG14 is another top view of a wiring substrate according to some embodiments;

[0040] FIG15 is another top view of a wiring substrate according to some embodiments;

[0041] FIG16 is a partial enlarged view of a wiring substrate according to some embodiments;

[0042] FIG17 is another top view of a wiring substrate according to some embodiments;

[0043] FIG18 is another partially enlarged view of a wiring substrate according to some embodiments;

[0044] FIG19 is another partial enlarged view of a wiring substrate according to some embodiments;

[0045] FIG20 is another top view of a wiring substrate according to some embodiments;

[0046] FIG21 is another partial enlarged view of a wiring substrate according to some embodiments;

[0047] FIG22 is another partial enlarged view of a wiring substrate according to some embodiments;

[0048] FIG23 is another top view of a wiring substrate according to some embodiments;

[0049] FIG24 is another top view of a wiring substrate according to some embodiments;

[0050] FIG25 is another top view of a wiring substrate according to some embodiments;

[0051] FIG26 is another top view of a wiring substrate according to some embodiments;

[0052] FIG27 is another top view of a wiring substrate according to some embodiments;

[0053] FIG28 is another top view of a wiring substrate according to some embodiments;

[0054] FIG29 is another top view of a wiring substrate according to some embodiments;

[0055] FIG30 is another partial enlarged view of a wiring substrate according to some embodiments;

[0056] FIG31 is another partial enlarged view of a wiring substrate according to some embodiments;

[0057] FIG32 is another partial enlarged view of the wiring substrate according to some embodiments;

[0058] FIG33 is another partial enlarged view of a wiring substrate according to some embodiments;

[0059] FIG34 is another partial enlarged view of the wiring substrate according to some embodiments;

[0060] FIG35 is another partial enlarged view of a wiring substrate according to some embodiments;

[0061] FIG36 is another partial enlarged view of a wiring substrate according to some embodiments;

[0062] FIG37 is another partial enlarged view of a wiring substrate according to some embodiments;

[0063] FIG38 is another partial enlarged view of a wiring substrate according to some embodiments;

[0064] FIG39 is another partial enlarged view of a wiring substrate according to some embodiments;

[0065] FIG40 is another partial enlarged view of a wiring substrate according to some embodiments;

[0066] FIG41 is another top view of a wiring substrate according to some embodiments;

[0067] FIG42 is another top view of a wiring substrate according to some embodiments;

[0068] FIG43 is another top view of a wiring substrate according to some embodiments;

[0069] FIG44 is another top view of a wiring substrate according to some embodiments;

[0070] FIG45 is another top view of a wiring substrate according to some embodiments;

[0071] FIG46 is another top view of a wiring substrate according to some embodiments;

[0072] FIG47 is another partial enlarged view of a wiring substrate according to some embodiments;

[0073] FIG48 is another partial enlarged view of a wiring substrate according to some embodiments;

[0074] FIG49 is another top view of a wiring substrate according to some embodiments;

[0075] FIG50 is another top view of a wiring substrate according to some embodiments;

[0076] FIG51 is another partial enlarged view of a wiring substrate according to some embodiments;

[0077] FIG52 is a partial enlarged view of a wiring substrate in the related art;

[0078] FIG53 is another partial enlarged view of a wiring substrate according to some embodiments;

[0079] 54A to 54N are comparative diagrams of a first experiment according to some embodiments;

[0080] FIG55 is a line graph of a first experiment according to some embodiments;

[0081] 56A to 56N are comparative diagrams of a second experiment according to some embodiments;

[0082] FIG57 is a line graph of a second experiment according to some embodiments;

[0083] FIG58 is a flow chart of a method for preparing a wiring substrate according to some embodiments;

[0084] 59A to 59B are structural diagrams corresponding to steps in a method for preparing a wiring substrate according to some embodiments;

[0085] FIG60 is another flow chart of a method for preparing a wiring substrate according to some embodiments;

[0086] FIG61 is another structural diagram corresponding to each step in the method for preparing a wiring substrate according to some embodiments;

[0087] 62A and 62B are another structural diagram corresponding to each step in the method for preparing a wiring substrate according to some embodiments;

[0088] FIG63 is another structural diagram corresponding to each step in the method for preparing a wiring substrate according to some embodiments;

[0089] FIG64 is another structural diagram corresponding to each step in the method for preparing a wiring substrate according to some embodiments;

[0090] 65A to 65C are another structural diagram corresponding to each step in the method for preparing a wiring substrate according to some embodiments;

[0091] FIG66 is a structural diagram of a motherboard substrate according to some embodiments;

[0092] FIG67 is a structural diagram of a mask according to some embodiments;

[0093] FIG68 is another partial enlarged view of a wiring substrate according to some embodiments;

[0094] FIG69 is a structural diagram of a first alignment pattern and a dummy conductive block according to some embodiments;

[0095] FIG70 is a structural diagram of a correction alignment pattern and a dummy conductive block according to some embodiments;

[0096] FIG71 is a structural diagram of cutting alignment patterns and dummy conductive blocks according to some embodiments;

[0097] FIG72 is a structural diagram of a second alignment pattern and a dummy conductive block according to some embodiments;

[0098] FIG73 is a structural diagram of a baffle alignment pattern and a dummy conductive block according to some embodiments;

[0099] FIG74 is a structural diagram of an alignment pattern according to some embodiments;

[0100] FIG75 is another structural diagram of an alignment pattern according to some embodiments;

[0101] FIG76 is another structural diagram of an alignment pattern according to some embodiments;

[0102] FIG77 is a structural diagram of a wiring substrate during processing according to some embodiments;

[0103] FIG78 is another structural diagram of a wiring substrate during processing according to some embodiments;

[0104] FIG79 is another structural diagram of a wiring substrate during processing according to some embodiments;

[0105] FIG80 is another structural diagram of a wiring substrate during processing according to some embodiments;

[0106] FIG81 is another structural diagram of a wiring substrate during processing according to some embodiments;

[0107] FIG82 is another structural diagram of a wiring substrate during processing according to some embodiments;

[0108] FIG83 is another structural diagram of a wiring substrate during processing according to some embodiments;

[0109] FIG84 is another partial enlarged view of a wiring substrate according to some embodiments;

[0110] FIG85 is a diagram of a third experimental structure according to some embodiments;

[0111] FIG86 is a diagram of a third experimental configuration according to some embodiments;

[0112] FIG87 is a histogram according to some embodiments;

[0113] Figure 88 is another bar graph according to some embodiments. DETAILED DESCRIPTION

[0114] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0115] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0116] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0117] When describing some embodiments, the terms "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0118] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0119] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0120] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0121] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0122] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0123] Some embodiments of the present disclosure provide a display device. The display device can be any display device that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the display device of the embodiments can be implemented in a variety of electronic devices or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0124] Exemplarily, the display device is a passive display panel, and specifically may be a liquid crystal display (LCD).

[0125] In this case, as shown in FIG. 1 , in some embodiments, the display device 001 includes a light-emitting substrate 01 and a display panel 02 , and the display panel 02 is located on the light-emitting side of the light-emitting substrate 01 .

[0126] The light-emitting substrate 01 is used to form a backlight module, providing backlight for the display panel 02. For example, the backlight provided by the light-emitting substrate 01 can be white light or blue light, which is not specifically limited in this disclosure. The light-emitting side of the light-emitting substrate 01 refers to the side of the light-emitting substrate 01 that emits light.

[0127] Display panel 02 is used to display images. As shown in Figure 2 , display panel 02 includes an array substrate 021, a color filter substrate 022, and a liquid crystal layer 023. Array substrate 021 is located on the light-emitting side of light-emitting substrate 01. Color filter substrate 022 is located on the side of array substrate 021 away from light-emitting substrate 01. Liquid crystal layer 023 is located between array substrate 021 and color filter substrate 022.

[0128] The array substrate 021 may include a plurality of transistors and a plurality of pixel electrodes, and the plurality of transistors may be arranged in an array shape. The plurality of transistors are electrically connected to the plurality of pixel electrodes in a one-to-one correspondence, and the transistors are used to transmit pixel voltages to the corresponding pixel electrodes.

[0129] In addition, the color filter substrate 022 may include a variety of color filters. For example, if the backlight provided by the light-emitting substrate 01 is white light, the color filters may include a red filter, a green filter, and a blue filter. The red filter allows only red light to pass through the incident light, the green filter allows only green light to pass through the incident light, and the blue filter allows only blue light to pass through the incident light. For another example, if the backlight provided by the light-emitting substrate 01 is blue light, the color filters may also include a red filter and a green filter.

[0130] The liquid crystal layer 023 includes a plurality of liquid crystal molecules. For example, an electric field may be formed between the pixel electrode and the common electrode, and the liquid crystal molecules may be deflected under the action of the electric field.

[0131] Exemplarily, the display panel 02 further includes a common electrode. The common electrode can receive a common voltage. The common electrode can be disposed in the color filter substrate 022 or in the array substrate 021, and this disclosure does not specifically limit this.

[0132] Through the above arrangement, when the display device 001 is in operation, the light-emitting substrate 01 can emit light, and then the light will sequentially pass through the array substrate 021, the liquid crystal layer 023 and the color filter substrate 022, and finally realize image display.

[0133] Specifically, when light strikes the liquid crystal layer 023, the liquid crystal molecules are deflected by the electric field formed between the pixel electrode and the common electrode, thereby changing the amount of light passing through the liquid crystal molecules so that the light emitted after passing through the liquid crystal molecules reaches a preset brightness. Then, as the light passes through the color filter substrate 022, it passes through different color filters and emits different colors of light, such as red, blue, and green. These various colors of light interact with each other to achieve display.

[0134] In some embodiments, as shown in FIG3 , the light-emitting substrate 01 of the present disclosure includes a wiring substrate 1 and a plurality of light-emitting devices 2, wherein the plurality of light-emitting devices 2 are disposed on the wiring substrate 1. The wiring substrate 1 serves as a carrier for the light-emitting devices 2. While carrying the light-emitting devices 2, it also provides circuit connections for the light-emitting devices 2 to ensure that the light-emitting devices 2 can function normally.

[0135] The light-emitting device 2 may be a Micro LED or a Mini LED.

[0136] In some embodiments, as shown in FIG. 4 and FIG. 5 , the wiring substrate 1 includes a substrate 11 and a plurality of signal lines 12 .

[0137] In some examples, the substrate 11 may be a substrate 11 formed of an inorganic material, or a substrate 11 formed of an organic material, or a substrate 11 formed by stacking organic and inorganic materials.

[0138] For example, the substrate 11 may be made of glass materials such as soda-lime glass, quartz glass, and sapphire glass, or may be made of metal materials such as stainless steel, aluminum, and nickel.

[0139] Exemplarily, the material of the substrate 11 can also be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0140] The substrate 11 has a first surface S. A plurality of signal lines 12 are located on the first surface S. The plurality of signal lines 12 are spaced apart along a first direction X and extend along a second direction Y. The first direction X intersects the second direction Y. The light-emitting device 2 is electrically connected to the signal lines 12 (e.g., indirectly), and the signal lines 12 can provide corresponding electrical signals to the light-emitting device 2.

[0141] The angle between the first direction X and the second direction Y may be 80°, 85°, 90° or 95°.

[0142] In some examples, as shown in FIG4 , the wiring substrate 1 includes a functional area 1a and a peripheral area 1b, with the peripheral area 1b located on at least one side of the functional area 1a. FIG4 illustrates an example in which the peripheral area 1b surrounds the functional area 1a. It is understood that in other examples, the peripheral area 1b may be located on only one, two, or three sides of the functional area 1a. The signal line 12 is located in the functional area 1a.

[0143] The functional area 1a may have various shapes, such as a rectangle or a circle. For the sake of illustration, the following uses the rectangular shape of the functional area 1a as an example.

[0144] It should be noted that at least a portion of the peripheral area 1 b may be separated from the functional area 1 a through a cutting process during the preparation of the wiring substrate 1 .

[0145] For example, when a plurality of wiring substrates 1 are formed on one motherboard substrate, the peripheral region 1 b is located on one side of the functional region 1 a of the wiring substrate 1 , or between the peripheral region 1 b and the functional regions 1 a of two wiring substrates 1 .

[0146] For example, as shown in FIG4 , the peripheral area 1b is provided with at least one binding area 1c. The number of binding areas 1c can be one or more. In the case where there are multiple binding areas 1c, the multiple binding areas 1c are located on the same side of the functional area 1a.

[0147] Exemplarily, at least one binding area 1c and the functional area 1a are spaced apart along the second direction Y. The binding area 1c is a region for binding the wiring substrate to an external circuit (such as a flexible printed circuit board).

[0148] It can be understood that the wiring substrate 1 includes signal lines that transmit different types of signals. As shown in Figure 4, in some wiring substrates 1, two adjacent signal lines 12 can be a first signal line VLED and an addressing signal line 12A; or, two adjacent signal lines 12 can also be an addressing signal line 12A and a first voltage line VCC1; or, two adjacent signal lines 12 can also be a first voltage line VCC1 and a ground signal line GND; or, two adjacent signal lines 12 can also be a ground signal line GND and a feedback signal line FB.

[0149] As shown in Figure 5, in some other wiring substrates 1, two adjacent signal lines 12 can be the first signal line VLED and the second voltage line VCC2; or, two adjacent signal lines 12 can be the second voltage line VCC2 and the data signal line DL; or, two adjacent signal lines 12 can also be the data signal line DL and the addressing signal line 12A; or, two adjacent signal lines 12 can also be the addressing signal line 12A and the ground signal line GND; or, two adjacent signal lines 12 can also be the ground signal line GND and the feedback signal line FB.

[0150] When an electrical signal is transmitted in the signal line 12, the signal will be lost due to the resistance of the signal line 12. The greater the resistance of the signal line 12, the greater the loss per unit length of the signal line 12, and the greater the power consumption. Therefore, in actual production, it is necessary to reduce the resistance of the signal line 12 as much as possible. In some examples, the material of the signal line 12 may include copper, silver, aluminum, etc. According to the resistance calculation formula:

[0151] Wherein, R represents the resistance of the signal line 12 ; ρ represents the resistivity of the material of the signal line 12 ; l represents the length of the signal line 12 ; and s1 represents the cross-sectional area of ​​the signal line 12 .

[0152] It can be seen that the resistance of signal line 12 is related to the resistivity of the material of signal line 12, the length of signal line 12, and the cross-sectional area perpendicular to signal line 12. Once the product dimensions are determined, the length of signal line 12 is also determined accordingly. Once the material used for signal line 12 is determined, its resistivity is also a fixed value. Therefore, the only variable affecting the resistance of signal line 12 is the cross-sectional area of ​​signal line 12. The larger the cross-sectional area of ​​signal line 12, the lower the resistance of signal line 12; the smaller the cross-sectional area of ​​signal line 12, the higher the resistance of signal line 12.

[0153] The cross-sectional area of ​​the signal line 12 is related to the line width and thickness of the signal line 12. Since the wiring space on the wiring substrate 1 is limited and there is a minimum safe distance between two adjacent signal lines 12, the line width of the signal line 12 is difficult to change. Therefore, the variable that affects the resistance of the signal line 12 is basically the line thickness of the signal line 12, that is, the thickness of the signal line 12. The thicker the signal line 12, the lower the resistance of the signal line 12; the thinner the signal line 12, the higher the resistance of the signal line 12.

[0154] Therefore, based on the above analysis, it can be seen that when designing and preparing the signal line 12, it is necessary to increase the thickness of the signal line 12 as much as possible to reduce the resistance of the signal line 12, reduce signal loss, and reduce power loss.

[0155] The signal line 12 can be formed by various processes.

[0156] In some cases, a first copper layer can be formed on the substrate 11 through a sputtering process, and then a photoresist is coated on the first copper layer to form a first photoresist layer. The first photoresist layer is then exposed and developed to form a plurality of first openings in the first photoresist layer. The developed first photoresist layer is then used as a mask to etch away portions of the first copper layer corresponding to the first openings, and then the first photoresist layer is stripped off to form the signal line 12. However, the thickness of the signal line 12 formed by the sputtering process is generally less than or equal to 3.6 μm, and therefore cannot well meet the requirement of a high thickness for the signal line 12, and it is difficult to meet the requirement of a low resistance for the signal line 12.

[0157] In other cases, an electroplating process can be used to form the signal line 12 on the substrate 11. The electroplating process is a technology that obtains a metal coating on the substrate by reducing the metal ions at the cathode through the migration of positive and negative ions in an electrolyte solution containing metal ions under the action of an external electric field. For example, when the metal ions in the electrolyte solution are copper ions, the metal coating obtained is a copper film layer. The electrolyte solution is stored in a holding tank of the electroplating equipment, and the holding tank is also provided with an anode structure. When the electroplating process is performed, a carrier loaded with the substrate is placed in the holding tank, and the carrier and the anode structure are arranged relative to each other, the carrier is connected to the negative output terminal of the power supply, and the negative output terminal of the power supply is electrically connected to the seed layer on the substrate. The anode structure is connected to the positive output terminal of the power supply, thereby forming an electric field between the anode structure and the substrate, thereby causing the metal ions in the electrolyte to adhere to the substrate to form a metal coating of a specific thickness. The electroplating process can produce signal lines 12 with a wider range of optional thicknesses, for example, greater than or equal to 6 μm, and thus can well meet the demand for high-thickness signal lines 12 and ensure low resistance requirements for the signal lines 12 .

[0158] In the specific implementation of the electroplating process, there are two routes.

[0159] The first route: first, a second copper layer (also called a seed layer) is formed on the substrate 11 by a sputtering process, and the thickness of the second copper layer ranges from 0.1μm to 0.3μm. Then, the substrate 11 is placed in an electrolyte solution, and the second copper layer is clamped by a clamp. The second copper layer is energized to electroplate and deposit a third copper layer on the second copper layer. The thickness of the third copper layer is greater than or equal to 6μm. Then, a photoresist is coated on the third copper layer to form a second photoresist layer, and the second photoresist layer is exposed and developed to form multiple second openings on the second photoresist layer. Then, the developed second photoresist layer is used as a mask to etch the portion of the second copper layer and the third copper layer corresponding to the second opening, and then the second photoresist layer is peeled off to form a signal line 12. However, due to the large combined thickness of the second and third copper layers, etching them takes a long time, resulting in excessive etching bias, reduced productivity, and difficulty meeting mass production requirements. Therefore, high-speed etching solutions are generally used to etch the second and third copper layers. However, high-speed etching solutions are relatively expensive, which increases etching costs.

[0160] The second route: first, a seed layer 16 is formed on the substrate 11 through a sputtering process. The seed layer 16 can be a stacked structure consisting of a molybdenum niobium (MoNb) layer and a third copper layer. The molybdenum niobium layer is located between the third copper layer and the substrate 11, wherein the thickness of the molybdenum niobium layer is about 300 angstroms, and the thickness of the third copper layer ranges from 0.3μm to 1.0μm. Then, photoresist is coated on the seed layer 16 to form a third photoresist layer. Then, the third photoresist layer is exposed and developed to form multiple openings (for example, the first opening 171 below) on the third photoresist layer. Then, copper (thickness greater than or equal to 6μm) is electroplated in the first opening 171 to form a wiring sub-pattern 12Z in the first opening 171. Then, the third photoresist layer is stripped off, and the seed layer 16 is etched using the wiring sub-pattern 12Z as a mask, so that the wiring sub-pattern 12Z and the portion of the seed layer 16 below the wiring sub-pattern 12Z form the signal line 12.

[0161] Specifically, the seed layer 16 is first clamped by a carrier to negatively charge the seed layer 16, and the substrate 11 is placed in the electrolyte solution in the holding tank, and the copper block in the electrolyte solution is positively charged. In this way, the copper ions on the metal copper block will undergo an oxidation reaction and be converted into copper ions and enter the electrolyte solution. Under the action of the electric field force between the cathode and the anode, the copper ions move into the first opening 171 and are reduced to copper element and deposited in the first opening 171.

[0162] In this process route, the target of the etching process is the seed layer 16, and the thickness of the seed layer 16 is much less than 6 μm, so the etching cost and etching bias can be reduced. Therefore, the second process route can effectively reduce costs compared to the first process route.

[0163] Furthermore, the thickness uniformity of the signal line 12 in the second electroplating process is studied from two aspects.

[0164] On the one hand, during the electroplating process, the bottom surface area of ​​different signal lines to be plated (the surface of the signal line to be plated opposite to the first surface S of the substrate 11) is different due to reasons such as the line width of the signal line to be plated. Therefore, in different unit area regions of the first surface S, the ratio of the bottom surface area of ​​the signal line to be plated to the unit area is different. The bottom surface area of ​​the signal line to be plated in some unit area regions accounts for a large proportion, and the bottom surface area of ​​the signal line to be plated in some unit area regions accounts for a small proportion. In this way, during the electroplating process, according to the relationship between the current density, the current, and the cross-sectional area of ​​the signal line to be plated in the direction perpendicular to the current, that is, J=I1 / s2·····(2)

[0165] Wherein, J represents the current density. I1 represents the current along the thickness direction of the signal line to be plated. The value of I1 can be controlled by the equipment, that is, I1 can be a constant value. s2 represents the cross-sectional area of ​​the signal line to be plated along the direction perpendicular to its thickness (the bottom surface area of ​​the signal line to be plated). The signal line to be plated refers to the intermediate form of the signal line 12 during the process of forming a signal line 12 of a specific thickness in a specific area through an electroplating process.

[0166] It can be seen that during the electroplating process, the larger the bottom surface area of ​​the signal line to be plated per unit area, the smaller the current density on the signal line to be plated. Similarly, the smaller the bottom surface area of ​​the signal line to be plated per unit area, the greater the current density on the signal line to be plated. Since current density is proportional to electroplating efficiency, the greater the current density, the higher the electroplating efficiency and the thicker the signal line 12; the smaller the current density, the lower the electroplating efficiency and the thinner the signal line 12.

[0167] In summary, the difference in bottom surface area of ​​the signal lines to be plated in different unit area regions will affect the difference in current density on the signal lines to be plated in different unit area regions, and affect the thickness uniformity between the signal lines 12 in different unit area regions finally formed.

[0168] The inventors also used the Butler-Volmer equation to verify that the current density on the signal line to be plated during the electroplating process is affected by the ratio of the bottom surface area of ​​the signal line to be plated per unit area. The inventors concluded that the difference in the bottom area of ​​the signal line to be plated per unit area affects the uniformity of the thickness of the signal line 12.

[0169] Specifically, the Butler-Volmer equation:

[0170] or,

[0171] According to formula (3) and formula (4), formula (5) can be obtained: η=EE eq ·····(5)

[0172] Among them, i loc Represents the current density of the signal line to be plated, in A / m 2 ; i0 represents the exchange current density; η represents the activation overpotential of the metal ions in the electrolyte solution; E eq represents: the equilibrium potential of metal ions in the electrolyte solution; T represents the thermodynamic temperature; α a represents the charge transfer coefficient in the cathode direction; α crepresents the charge transfer coefficient in the anode direction; z represents the number of electrons involved in the electrode reaction process; F represents the Faraday constant; R represents the gas constant; and E represents the potential of the seed layer 16 and the signal line to be plated.

[0173] In the actual electroplating process, the i0 and α can be adjusted by debugging the electroplating equipment and controlling the electroplating process. a , z, F, R and T values. loc The value of η is only related to the value of η.

[0174] Since the value of η and E and E eq Related, and E eq The value of is also a constant, and the potential of the electrolyte solution is 0.34 V. Therefore, the value of η is only related to E. Combined with the actual electroplating process, we can know formula (6):

[0175] Substituting formula (6) into formula (5) yields formula (7):

[0176] in, represents the potential difference between the surface of the signal line to be plated away from the seed layer 16 and the seed layer 16; Represents the potential of the electrolyte solution.

[0177] From formula (7), we can see that the value of η is mainly affected by and The impact of as well as The numerical values ​​of .

[0178] Among them, by studying the specific electroplating process, the following formula (8) can be obtained:

[0179] Where σ represents the conductivity of the electrolyte solution; L bath W bath represents the product of the length and width of the receiving groove; x represents the distance between the seed layer 16 and the anode copper metal; I tot represents the current flowing into the seed layer 16; Represents the potential of the seed layer 16 and the signal line to be plated; Represents the electrode potential of the copper electroplating solution.

[0180] Combined with the above formula (8), it can be seen that the value of σ can be controlled by adjusting the components and / or the ratio of the electrolyte solution, and I can be controlled by adjusting the current flowing into the seed layer 16. totThe value of x can be controlled by adjusting the distance between the seed layer 16 and the anode structure, and the size of the holding groove determines L bath W bath The value of , therefore, The value can be adjusted to a fixed value.

[0181] Therefore, it can be concluded that the value of η is only related, Represents the potential of the seed layer 16 and the signal line to be plated. Since the thickness of the signal line to be plated is constantly changing during the electroplating process, the potential of the signal line to be plated will also change. The value of will also change.

[0182] The following is For the convenience of research, two signal lines to be plated with different bottom areas are selected in the unit area of ​​different regions. Among them, the structure shown in FIG6 is the first signal line to be plated 12B, and the structure shown in FIG7 is the second signal line to be plated 12C. value, and the second signal line to be plated and the seed layer 16 The photoresist layer 17 has an opening, and after the electroplating process is performed, a signal line is formed in the opening.

[0183] For the first signal line to be plated, it can be seen that the potential difference between the surface of the first signal line to be plated away from the seed layer 16 and the seed layer 16 is

[0184] in, represents the electric potential on the surface of the first signal line 12B to be plated, which is away from the seed layer 16 . represents the potential on the seed layer 16 .

[0185] According to the relationship between potential difference, resistance and current:

[0186] Among them, R0 represents the resistance of the seed layer 16, and R0 is a constant value. R1 represents the resistance of the first signal line to be plated. The value is related to the resistance of the first signal line to be plated.

[0187] For the second signal line to be plated, it can be seen that the potential difference between the surface of the second signal line to be plated away from the seed layer 16 and the seed layer 16 is

[0188] in, represents the potential on the surface of the second signal line 12C to be plated, which is away from the seed layer 16 . represents the potential on the seed layer 16 .

[0189] According to the relationship between potential difference, resistance and current:

[0190] Among them, R0 represents the resistance of the seed layer 16, R0 is a constant value, and R2 represents the resistance of the second signal line to be plated. The value is related to the resistance of the second signal line to be plated.

[0191] Since R=ρl / S·····(13)

[0192] Among them, R represents the resistance of the conductor (the first signal line to be plated or the second signal line to be plated); ρ represents the resistivity of the conductor; l represents the length of the conductor (the dimension from left to right in Figure 6 or Figure 7); S represents the cross-sectional area of ​​the conductor perpendicular to the length direction.

[0193] Substituting formula (13) into formula (10) yields formula (14).

[0194] Wherein, S1 represents the cross-sectional area (bottom area) of the first signal line to be plated perpendicular to the length direction. Combining formula (14) and formula (4), it can be concluded that the size of the bottom area of ​​the first signal line to be plated will affect the current density on the first signal line to be plated.

[0195] Similarly, by substituting formula (13) into formula (12), we can obtain formula (15).

[0196] Wherein, S2 represents the cross-sectional area (bottom area) of the second signal line to be plated perpendicular to the length direction. Combining formula (15) and formula (4), it can be concluded that the size of the bottom area of ​​the second signal line to be plated will affect the current density on the second signal line to be plated.

[0197] On this basis, the difference in potential difference between the first signal line to be plated and the second signal line to be plated can be obtained by subtracting formula (14) from formula (15):

[0198] Combining formula (16) and formula (4), it can be seen that the difference between the potential on the first signal line to be plated and the potential on the second signal line to be plated is affected by the difference between the bottom area of ​​the first signal line to be plated and the bottom area of ​​the second signal line to be plated. According to formulas (4) and (7), it can be seen that the potential on the first signal line to be plated will affect the current density on the first signal line to be plated, and the potential on the second signal line to be plated will affect the current density on the second signal line to be plated. Therefore, the difference between the bottom area of ​​the first signal line to be plated and the bottom area of ​​the second signal line to be plated will affect the difference between the current density on the first signal line to be plated and the current density on the second signal line to be plated.

[0199] On this basis, the uniformity of the current density of the signal lines to be plated (the first signal line to be plated and the second signal line to be plated) can be calculated by formula (17).

[0200] Among them, Unif(i loc ) represents the uniformity of the current density on the signal lines to be plated (the first signal line to be plated and the second signal line to be plated); Max(i loc ) represents the current density at the point with the largest current density among the selected test points on the signal line to be plated; Min(i loc ) represents the current density at the point with the smallest current density among the selected test points on the signal line to be plated; I avg Represents the average value of the current density of all selected test points on the signal line to be plated.

[0201] It can be seen from this that the uniformity of the current density on the first signal line to be plated and the current density on the second signal line to be plated will be affected by the difference between the current density on the first signal line to be plated and the current density on the second signal line to be plated. The greater the difference between the current density on the first signal line to be plated and the current density on the second signal line to be plated, the worse the uniformity of the current density on the first signal line to be plated and the current density on the second signal line to be plated. The smaller the difference between the current density on the first signal line to be plated and the current density on the second signal line to be plated, the better the uniformity of the current density on the first signal line to be plated and the current density on the second signal line to be plated.

[0202] On this basis, it can be concluded that the difference between the bottom area of ​​the first signal line to be plated and the bottom area of ​​the second signal line to be plated will affect the uniformity of the current density on the first signal line to be plated and the current density on the second signal line to be plated. The greater the difference between the bottom area of ​​the first signal line to be plated and the bottom area of ​​the second signal line to be plated, the worse the uniformity of the current density on the first signal line to be plated and the current density on the second signal line to be plated, and the worse the thickness uniformity of the different signal lines 12 formed after the final electroplating is completed. The smaller the difference between the bottom area of ​​the first signal line to be plated and the bottom area of ​​the second signal line to be plated, the better the uniformity of the current density on the first signal line to be plated and the current density on the second signal line to be plated, and the better the thickness uniformity of the different signal lines 12 formed after the final electroplating is completed.

[0203] Combining the above two inferences, it can be concluded that, within a unit area, the greater the difference between the bottom area of ​​the first signal line to be plated and the bottom area of ​​the second signal line to be plated, the worse the thickness uniformity between the different signal lines 12 finally formed; the smaller the difference between the bottom area of ​​the first signal line to be plated and the bottom area of ​​the second signal line to be plated, the better the thickness uniformity between the different signal lines 12 finally formed.

[0204] Based on this, as shown in FIG5 , the wiring substrate 1 provided by the present disclosure further includes a plurality of dummy conductive patterns 13 , which are located on the first surface S of the substrate. At least some of the plurality of dummy conductive patterns 13 are provided on the same layer as the plurality of signal lines 12 ; a dummy conductive pattern 13 is provided between two adjacent signal lines 12 , and the dummy conductive pattern 13 is insulated from the adjacent signal lines 12 . The light-emitting device 2 is connected to the signal lines 12 .

[0205] Through the above arrangement, during the process of forming the signal line 12 using the electroplating process, the dummy conductive pattern 13 is simultaneously formed. By properly setting the position of the dummy conductive pattern to be plated and the number of the dummy conductive patterns 13 to be plated, if the bottom areas of two adjacent signal lines to be plated differ greatly within a unit area, the dummy conductive patterns to be plated can be set to make the current density on the two adjacent signal lines to be plated close, the electroplating efficiency close, and ultimately the thickness between the two adjacent signal lines 12 close, thereby improving the thickness uniformity between the two adjacent signal lines 12.

[0206] The dummy conductive pattern to be plated refers to an intermediate form of the dummy conductive pattern 13 during the process of forming the dummy conductive pattern 13 with a specific thickness in a specific area through an electroplating process.

[0207] It is understood that the material of the dummy conductive pattern 13 should be consistent with the material of the signal line 12. For example, the material of the signal line 12 and the dummy conductive pattern 13 are both copper.

[0208] In some examples, before forming the dummy conductive pattern 13 by electroplating, it is necessary to perform exposure and development operations on the third photoresist layer using a mask to form a second opening, so as to form the dummy conductive pattern 13 in the second opening.

[0209] In some examples, the dummy conductive pattern 13 is insulated from two adjacent signal lines 12, which may mean that the dummy conductive pattern 13 does not contact the two adjacent signal lines 12. Of course, any other suitable insulation methods are not excluded.

[0210] Exemplarily, a dummy conductive pattern 13 is provided between at least two adjacent signal lines 12 having different line widths. The "two adjacent signal lines 12 having different line widths" may refer to an adjacent first signal line VLED and an addressing signal line 12A, an adjacent addressing signal line 12A and a first voltage line VCC1, an adjacent first voltage line VCC1 and a ground signal line GND, an adjacent ground signal line GND and a feedback signal line FB, and the like.

[0211] For example, as shown in the wiring substrate 1 of Fig. 5 , a dummy conductive pattern 13 is provided between the adjacent first signal line VLED and the second voltage line VCC2, wherein the first signal line VLED and the second voltage line VCC2 have different line widths.

[0212] In some embodiments, the width of the dummy conductive pattern 13 located between two adjacent signal lines 12 is positively correlated with the distance between the two adjacent signal lines 12. That is, the width of the dummy conductive pattern 13 located between two adjacent signal lines 12 changes as the distance between the two adjacent signal lines 12 changes. Specifically, the width of the dummy conductive pattern 13 located between two adjacent signal lines 12 increases as the distance between the two adjacent signal lines 12 increases, and decreases as the distance between the two adjacent signal lines 12 decreases.

[0213] Therefore, when the distance between two adjacent signal lines 12 is different, the blank area between the two adjacent signal lines 12 is filled by adjusting the width of the virtual conductive pattern 13, so that the bottom area ratios in the respective areas of different signal lines 12 are close, thereby making the current density on different signal lines 12 close, and the electroplating efficiency close, so as to finally make the thickness between different signal lines 12 close, so as to improve the thickness uniformity between different signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0214] In some embodiments, as shown in FIG. 68 , at least a portion of the dummy conductive pattern 13 is located in the peripheral region 1 b ; the dummy conductive pattern 13 is insulated from the plurality of signal lines 12 .

[0215] It is understandable that, compared to the functional area 1a, the peripheral area 1b has fewer metal conductors (e.g., signal lines 12) and a larger blank area (i.e., an area without metal conductors). Within the area encompassing the peripheral area 1b and the location of the signal line 12 (e.g., the first signal line VLED) near the peripheral area 1b, the bottom area of ​​the metal pattern to be plated accounts for a relatively small proportion. Consequently, when the signal line 12 (e.g., the first signal line VLED) is electroplated, the signal line 12 (e.g., the first signal line VLED) near the peripheral area 1b is thicker than the other signal lines 12, thereby affecting the overall conductive performance of the wiring substrate 1.

[0216] In the embodiment of the present disclosure, a dummy conductive pattern 13 is provided in the peripheral area 1b, so that the bottom area ratio of the metal wire in the area jointly constituted by the peripheral area 1b and the position of the signal line 12 (for example, the first signal line VLED) near the peripheral area 1b is increased, so that the bottom area ratio of the metal pattern to be plated (including the signal line 12, the dummy conductive pattern 13 and the connecting line 15) in the respective areas of the signal line 12 near the peripheral area 1b and other signal lines 12 is close, and the difference in wiring environment between the signal line 12 near the peripheral area 1b and other signal lines 12 is reduced, so that the current density on the signal line 12 near the peripheral area 1b and other signal lines 12 is close, and the electroplating efficiency is close, so that the thickness between the signal line 12 near the peripheral area 1b and other signal lines 12 is finally close, so as to improve the thickness uniformity between two adjacent signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0217] In some embodiments, the width of the dummy conductive pattern 13 located in the peripheral region 1 b is positively correlated with the width of the peripheral region 1 b .

[0218] That is, the width of the dummy conductive pattern 13 located in the peripheral region 1b varies with the width of the peripheral region 1b. Specifically, the width of the dummy conductive pattern 13 located in the peripheral region 1b increases with the width of the peripheral region 1b, and decreases with the width of the peripheral region 1b.

[0219] Therefore, when the width of the peripheral area 1b is different, by adjusting the width of the virtual conductive pattern 13 located in the peripheral area 1b, the bottom area ratio of the signal line 12 close to the peripheral area 1b in the area jointly constituted by the peripheral area 1b and the position of the signal line 12 close to the peripheral area 1b (for example, the first signal line VLED) is close to the bottom area ratio of the metal pattern to be plated in the area where other signal lines 12 are located, so that the current density on the signal line 12 close to the peripheral area 1b and other signal lines 12 is close, and the electroplating efficiency is close, so that the thickness between the signal line 12 close to the peripheral area 1b and other signal lines 12 is finally close, so as to improve the thickness uniformity between two adjacent signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0220] In some embodiments, the minimum distance between the dummy conductive pattern 13 located in the peripheral area 1b and the signal line 12 ranges from 0.5 mm to 1.5 mm. For example, the minimum distance between the dummy conductive pattern 13 located in the peripheral area 1b and the signal line 12 can be 0.5 mm, 0.7 mm, 0.9 mm, 1.2 mm, 1.5 mm, etc. The embodiments of the present disclosure are not limited to this.

[0221] This can prevent the distance between the dummy conductive pattern 13 and the signal line 12 from being too small, thereby reducing the risk of electrostatic discharge (ESD) between the two and ensuring the normal operation of the signal line 12. On the other hand, it can also prevent the distance between the dummy conductive pattern 13 and the signal line 12 from being too large, thereby ensuring the accompanying plating effect of the dummy conductive pattern 13.

[0222] In some embodiments, as shown in FIG. 4 , the peripheral region 1 b surrounds the functional region 1 a .

[0223] Exemplarily, the width of the dummy conductive patterns located in the peripheral area 1b and on opposite sides of the functional area 1a along the first direction X is greater than the width of the dummy conductive patterns located in the peripheral area 1b and on opposite sides of the functional area 1a along the second direction Y.

[0224] For example, the width of the dummy conductive pattern located in the peripheral area 1b and on opposite sides of the functional area 1a along the first direction X is 3 mm, and the width of the dummy conductive pattern located in the peripheral area 1b and on opposite sides of the functional area 1a along the second direction Y is 2 mm.

[0225] It can be understood that the density of the metal wires on two opposite sides of the functional area 1 a along the first direction X is smaller than the density of the metal wires on two opposite sides of the functional area 1 a along the second direction Y.

[0226] In this embodiment, by making the width of the dummy conductive pattern located in the peripheral area 1b and on the opposite sides of the functional area 1a along the first direction X greater than the width of the dummy conductive pattern located in the peripheral area 1b and on the opposite sides of the functional area 1a along the second direction Y, the signal lines 12 located on the opposite sides of the functional area 1a along the first direction X and the signal lines 12 located on the opposite sides of the functional area 1a along the second direction Y have a bottom area ratio of the metal pattern to be plated (including the signal line 12, the dummy conductive pattern 13 and the connecting line 15) in their respective areas close to each other, so that the thickness of the signal lines 12 located on the opposite sides of the functional area 1a along the first direction X and the signal lines 12 located on the opposite sides of the functional area 1a along the second direction Y are close to each other, so as to improve the thickness uniformity between the signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0227] It is understood that, in addition to the plurality of signal lines 12 mentioned above, the first surface S of the substrate 11 also has a plurality of connecting lines 15 for connecting the light-emitting device 2 and the signal lines 12. The connecting lines 15 and the signal lines 12 cooperate with each other to realize signal transmission and ensure the normal operation of the light-emitting device 2.

[0228] In some embodiments, as shown in FIG8 , the wiring substrate 1 of the present disclosure further includes a plurality of pad units 14 and a plurality of connecting lines 15 . The plurality of pad units 14 are located on the first surface S, and the pad unit 14 includes a plurality of device pad groups 141 . The plurality of connecting lines 15 are located on the first surface S and within the functional area 1 a . The connecting lines 15 include a plurality of first connecting lines 151 and a second connecting line 152 . The pad unit 14 and the signal line 12 are configured to be connected via the first connecting lines 151 . The plurality of device pad groups 141 in the same pad unit 14 are configured to be connected via the second connecting lines 152 . The plurality of connecting lines 15 are arranged in a plurality of columns. One light-emitting device 2 is connected to one device pad group 141 .

[0229] Through the setting of the connecting line 15 and the device pad group 141, the signal can be transmitted between the signal line 12, the first connecting line 151, and the second connecting line 152. When the signal passes through the second connecting line 152, the signal can be transmitted to the light-emitting device 2 through the device pad group 141 to achieve control of the light-emitting device 2.

[0230] For example, the number of device pad groups 141 in a pad unit 14 may be four, six, or nine, which is set according to specific needs.

[0231] Among them, multiple device pad groups 141 within a pad unit 14 can be connected to each other in series. Alternatively, multiple device pad groups 141 within a pad unit 14 can be connected to each other in parallel. Alternatively, multiple device pad groups 141 within a pad unit 14 can be connected to each other in series and parallel. In this disclosure, multiple device pad groups 141 within a pad unit 14 are connected to each other in series as an example.

[0232] Furthermore, the plurality of device pad groups 141 within a pad unit 14 are arranged in an array in an n*m manner. For example, as shown in FIG8 , when the pad unit 14 includes four device pad groups 141, the four device pad groups 141 are arranged in an array in a 2*2 manner. For another example, as shown in FIG9 , when the pad unit 14 includes six device pad groups 141, the six device pad groups 141 are arranged in an array in a 2*3 manner. For another example, as shown in FIG10 , when the pad unit 14 includes nine device pad groups 141, the nine device pad groups 141 are arranged in an array in a 3*3 manner.

[0233] Furthermore, the arrangement of the multiple device pad groups 141 in a pad unit 14 is the same. Among them, each device pad group 141 includes the same number of pads, and the arrangement of the pads in different device pad groups 141 is the same. For example, as shown in Figure 8, in the pad unit 14, each device pad group 141 includes an anode pad P1 and a cathode pad N1, and the anode pad P1 and the cathode pad N1 are arranged at intervals along the first direction X. For another example, as shown in Figure 10, in the pad unit 14, each device pad group 141 includes an anode pad P1 and a cathode pad N1, and the anode pad P1 and the cathode pad N1 are arranged at intervals along the second direction Y.

[0234] It should be explained that the pad unit 14 and the signal line 12 are configured to be connected through the first connection line 151, which may mean that the pad unit 14 is connected to the first signal line VLED through the first connection line 151, or the pad unit 14 is connected to the addressing signal line 12A through the first connection line 151, as shown in Figure 8.

[0235] Specifically, as shown in FIG8 , one connection line 15 includes two first connection lines 151, which are respectively a first sub-segment 151A and a second sub-segment 151B. The input end of the first sub-segment 151A is connected to the first signal line VLED, and the output end of the first sub-segment 151A is connected to the pad unit 14. The input end of the second sub-segment 151B is connected to the pad unit 14, and the output end of the second sub-segment 151B is connected to the addressing signal line 12A.

[0236] It is understood that the input end of the first sub-segment 151A and the input end of the second sub-segment 151B refer to signal input ends, and the output end of the first sub-segment 151A and the output end of the second sub-segment 151B refer to signal output ends. The signal is transmitted from the first signal line VLED to the addressing signal line 12A.

[0237] 8 , the wiring substrate 1 of the present disclosure further includes a plurality of driver ICs disposed on the first surface S. The driver ICs are arranged in a plurality of columns along the first direction X and in a plurality of rows along the second direction Y.

[0238] One driver chip IC can control one pad unit 14 or multiple pad units 14. The specific selection can be made according to the type of the driver chip IC.

[0239] Furthermore, the pad unit 14 includes an input end and an output end. The input end of the pad unit 14 is connected to the first signal line VLED, and the output end of the pad unit 14 is connected to the driver chip IC. In a pad unit 14, the device pad group 141 closest to the driver chip IC among the multiple device pad groups 141 connected in series serves as the starting device pad group 141. One pad in the starting device pad group 141 serves as the output end of the pad unit 14 and is electrically connected to the driver chip IC. Starting from the starting device pad group 141, all device pad groups 141 in the pad unit 14 are connected in series, and the last device pad group 141 is directly connected to the first signal line VLED.

[0240] For example, as shown in Figure 8, for the case where a pad unit 14 includes four device pad groups 141, a driver chip IC can control one pad unit 14, or control multiple pad units 14 at the same time. In the relevant embodiments and drawings of the present disclosure regarding a pad unit 14 including four device pad groups 141, one driver chip IC is used as an example to describe and illustrate the case.

[0241] For example, as shown in FIG8 , the driver chip IC can be connected to the address signal line 12A, the first voltage line VCC1, and the ground signal line GND. The first voltage line VCC1 can simultaneously provide a power signal and a data signal to the driver chip IC. The ground signal line GND is used to ground the driver chip IC.

[0242] The addressing signal line 12A includes multiple addressing signal sub-segments 12A1. In a column of driver chips, any two adjacent driver chip ICs are electrically connected through an addressing signal sub-segment 12A1. The last driver chip IC in a column of driver chip ICs is connected to one end of the feedback signal line FB through an addressing signal sub-segment 12A1, and the other end of the feedback signal line FB extends into the binding area 1c.

[0243] It can be understood that multiple light-emitting devices 2 are connected in series through multiple device pad groups 141 in a pad unit 14 and multiple second connecting lines 152. One end of the multiple light-emitting devices 2 connected in series is connected to the first signal line VLED through the first sub-segment 151A, and the other end of the multiple light-emitting devices 2 connected in series can be directly connected to the driver chip IC through the second sub-segment 151B; or, the other end of the multiple light-emitting devices 2 connected in series can also be connected to the addressing signal line 12A through the second sub-segment 151B.

[0244] For example, one driver chip IC can control one pad unit 14, or as shown in FIG9 , can control multiple pad units 14 simultaneously; one pad unit 14 can include multiple device pad groups 141. In the embodiments and drawings of this disclosure in which one pad unit 14 includes six or nine device pad groups 141, one driver chip IC is used as an example to describe and illustrate four pad units 14.

[0245] In this case, as shown in FIG9 , the driver chip IC is connected to the address signal line 12A, the second voltage line VCC2, the data signal line DL, and the ground signal line GND. The ground signal line GND is used to ground the driver chip IC; the second voltage line VCC2 is used to provide a power signal to the driver chip IC; and the data signal line DL provides a data signal to the driver chip IC.

[0246] In a column of driver chips, any two adjacent driver chip ICs are electrically connected through an addressing signal sub-segment 12A1. The last driver chip IC in a column of driver chip ICs is connected to one end of the feedback signal line FB through an addressing signal sub-segment 12A1, and the other end of the feedback signal line FB extends into the binding area 1c.

[0247] At this time, multiple light-emitting devices 2 are connected in series through multiple device pad groups 141 in a pad unit 14 and multiple second connecting lines 152. One end of the multiple light-emitting devices 2 connected in series is connected to the first signal line VLED through the first sub-segment 151A, and the other end of the multiple light-emitting devices 2 connected in series can be directly connected to the driver chip IC through the second sub-segment 151B.

[0248] The connecting wire 15 is also formed by an electroplating process, so the thickness uniformity also needs to be considered during the electroplating process.

[0249] Based on this, as shown in FIG8 , along the second direction Y, a dummy conductive pattern 13 is provided between two adjacent connection lines 15 in the same column, and the dummy conductive pattern 13 is insulated from the connection line 15 .

[0250] It is understandable that different connecting wires 15 have different wiring spaces on the wiring substrate. Therefore, during the electroplating process, the electric field density at the locations of different connecting wires 15 is different, resulting in uneven thickness between different connecting wires 15.

[0251] Through the above-mentioned arrangement, in the process of forming the connecting wire 15 by the electroplating process, the dummy conductive pattern 13 is simultaneously formed. In the case where there is a difference in the space between two adjacent connecting wires 15 to be plated on the wiring substrate, by reasonably setting the position of the dummy conductive pattern 13 to be plated and the number of the dummy conductive patterns 13 to be plated, the bottom area ratio of the metal pattern to be plated (including the signal line 12, the dummy conductive pattern 13 and the connecting wire 15) in the respective regions of the two connecting wires 15 to be plated is close, thereby making the current density on the two adjacent connecting wires 15 to be plated close, the electroplating efficiency close, and ultimately making the thickness between the two adjacent connecting wires 15 close, thereby improving the thickness uniformity between the two adjacent connecting wires 15, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0252] The connecting wire 15 to be plated refers to an intermediate form of the connecting wire 15 during the process of forming the connecting wire 15 with a specific thickness in a specific area through an electroplating process.

[0253] In some examples, the connection line 15 and the signal line 12 are provided in the same layer, that is, the connection line 15 and the signal line 12 are located in the same conductive layer, and the connection line 15 and the signal line 12 are formed simultaneously by a single electroplating process.

[0254] It can be understood that the width of the connecting line 15 is smaller than that of the signal line 12. During the electroplating process to form the connecting line 15 and the signal line 12, the density of metal ions is higher at the location where the signal line 12 is formed, and the deposition rate of metal ions is faster.

[0255] In this embodiment, by setting a virtual conductive pattern 13 between two adjacent connecting lines 15, the density of metal ions at the positions of the two adjacent connecting lines 15 to be plated is increased during the electroplating process, so that the current density on the connecting line 15 to be plated and the signal line 12 to be plated are close, and the electroplating efficiency is close, so that the thickness between the connecting line 15 and the signal line 12 is finally close, so as to improve the thickness uniformity between the connecting line 15 and the signal line 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0256] Furthermore, when the connecting lines 15 and the signal lines 12 are arranged in the same layer, the dummy conductive pattern 13 can be located between two adjacent signal lines 12 and between two adjacent connecting lines 15. This can improve the thickness uniformity between the connecting lines 15 and the thickness uniformity between the connecting lines 15 and the signal lines 12.

[0257] For example, when a driver chip IC controls a pad unit 14 and a pad unit 14 includes four device pad groups 141 , the dummy conductive pattern 13 can be located between the first signal line VLED and the addressing signal line 12A, or between two adjacent connection lines 15 .

[0258] For another example, in the case where a driver chip IC controls four pad units 14 and a pad unit 14 includes six or nine device pad groups 141, the virtual conductive pattern 13 can be located both between the first signal line VLED and the second voltage line VCC2, and between two adjacent connection lines 15.

[0259] A pad unit 14 includes multiple device pad groups 141. As shown in FIG9 , a connecting sub-segment 152A is used to electrically connect multiple device pad groups 141 in pairs (including in series or in parallel). That is, the two ends of the connecting sub-segment 152A are respectively connected to two different device pad groups 141 in the same pad unit 14. Multiple connecting sub-segments 152A in the same pad unit 14 constitute a second connecting line 152.

[0260] It should be noted that an insulating layer is formed on the side of the connecting line 15 and the signal line 12 away from the substrate 11. This insulating layer is used to isolate the connecting line 15 and the signal line 12 from water and oxygen. The insulating layer has multiple vias, which expose a portion of the connecting line 15 or also expose a portion of the signal line 12. The portions of two adjacent connecting sub-segments 152A exposed by the vias constitute the device pad group 141.

[0261] To facilitate understanding of how connecting sub-segment 152A connects two device pad groups 141, as shown in FIG8 , the two device pad groups 141, respectively connected to the two ends of the same connecting sub-segment 152A, are named first device pad group 141A and second device pad group 141B. First device pad group 141A includes anode pad P1 and cathode pad N1, and second device pad group 141B includes anode pad P1 and second cathode pad N1. At this point, connecting sub-segment 152A connecting two adjacent device pad groups 141 means that one end of connecting sub-segment 152A is connected to anode pad P1 of second device pad group 141B, and the other end of connecting sub-segment 152A is connected to cathode pad N1 of first device pad group 141A.

[0262] Since the wiring environments of the multiple connecting sub-segments 152A included in a second connecting line 152 may be different, the problem of poor thickness uniformity may occur between different connecting sub-segments 152A during the process of electroplating to form different connecting sub-segments 152A.

[0263] Based on this, as shown in FIG. 9 , in some embodiments, at least a portion of the dummy conductive pattern 13 is located within a region surrounded by the same second connecting line 152 .

[0264] In this way, during the process of forming the plurality of connecting sub-segments 152A using the electroplating process, dummy conductive patterns 13 are also simultaneously formed within the region enclosed by the second connecting lines 152. By appropriately setting the positions of the dummy conductive patterns 13 to be plated and the number of the dummy conductive patterns 13 to be plated as needed, the electric field distribution at the locations of the different connecting sub-segments 152A to be plated is relatively uniform during the electroplating process, resulting in relatively uniform thicknesses across the different connecting sub-segments 152A, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0265] The connecting sub-segment 152A to be plated refers to the intermediate form of the connecting sub-segment 152A during the process of forming the connecting sub-segment 152A with a specific thickness in a specific area through an electroplating process.

[0266] In order to meet the arrangement requirements of multiple device pad groups 141 in the same pad unit 14, the multiple connecting sub-segments 152A generally have two directions. The first type of connecting sub-segments 152A extend along the first direction X, and the second type of connecting sub-segments 152A extend along the second direction Y.

[0267] In some embodiments, as shown in FIG. 47 and FIG. 48 , a dummy conductive pattern 13 is provided on at least one side of the connecting sub-segment 152A, and the extending direction of the dummy conductive pattern 13 is parallel to the adjacent connecting sub-segment 152A.

[0268] It should be noted that "parallel" includes absolute parallelism and approximately parallelism, wherein the acceptable deviation range of approximately parallelism may be, for example, within 5°. Specifically in this embodiment, the dummy conductive pattern 13 and its adjacent connecting sub-segment 152A extend in substantially the same direction at all locations.

[0269] In this embodiment, a dummy conductive pattern 13 is provided on at least one side of the connecting sub-segment 152A, and the blank area on at least one side of the connecting sub-segment 152A is filled, thereby increasing the proportion of the metal pattern to be plated in the blank area of ​​the connecting sub-segment 152A and the connecting sub-segment 152A, thereby improving the thickness uniformity of the connecting line 15 and other conductive patterns (for example, the signal line 12).

[0270] Furthermore, the direction of the dummy conductive pattern 13 is consistent or substantially consistent with the outline or direction of the adjacent connecting sub-segment 152A, which can ensure the consistency of the plating effect of the dummy conductive pattern 13 at different positions of the connecting sub-segment 152A, and further improve the uniformity of the thickness of the connecting sub-segment 152A itself.

[0271] In some embodiments, as shown in Figures 47 and 48, in the same second connecting line 152, a dummy conductive pattern 13 is provided on the same side of any two adjacent connecting sub-segments, and the two dummy conductive patterns 13 on one side of two adjacent connecting sub-segments 152A are connected to each other; the overall extension direction of the two dummy conductive patterns 13 extends along the overall direction of the two adjacent connecting sub-segments 152A.

[0272] Therefore, the multiple dummy conductive patterns 13 located on the same side of the second connecting line 152 are connected to each other, and the directions of the multiple dummy conductive patterns 13 are consistent or substantially consistent with the outline or direction of the second connecting line 152, which can ensure the consistency of the plating effect of the dummy conductive pattern 13 on different positions of the second connecting line 152, and further improve the uniformity of the thickness of the second connecting line 152 itself.

[0273] In some embodiments, as shown in FIG9 , the plurality of connecting sub-segments 152A include a plurality of first connecting sub-segments B01 and a second connecting sub-segment B02 located between two adjacent first connecting sub-segments B01 ; the first connecting sub-segments B01 extend along the second direction Y, and the second connecting sub-segments B02 extend along the first direction X.

[0274] The first connecting sub-segment B01 is used to connect two device pad groups 141 spaced apart along the second direction Y in the same pad unit 14 ; the second connecting sub-segment B02 is used to connect two device pad groups 141 spaced apart along the first direction X in the same pad unit 14 .

[0275] In this way, while connecting two adjacent device pad groups 141, the tortuous direction of the second connecting line 152 can save space in the functional area 1a in the first direction X, so that more dense device pad groups 141 can be arranged in the limited space above the substrate 11 to connect more light-emitting devices 2.

[0276] It can be understood that, depending on the number of device pad groups 141 in a pad unit 14 , the number and arrangement of the first connecting sub-segments B01 and the second connecting sub-segments B02 included in the second connecting line 152 are also different.

[0277] For example, as shown in FIG8 , when the four device pad groups 141 in a pad unit 14 are arranged in a 2*2 array, the second connection line 152 includes two first connection sub-segments B01 and one second connection sub-segment B02 , and the second connection line 152 has a “U”-shaped structure.

[0278] 9 , when the six device pad groups 141 in a pad unit 14 are arranged in a 2*3 array, the second connection line 152 includes three first connection sub-segments B01 and two second connection sub-segments B02. The second connection line 152 has an "S"-shaped structure.

[0279] As another example, as shown in FIG10 , in a pad unit 14 , nine device pad groups 141 are arranged in a 3*3 array. The second connection line 152 includes three first connection sub-segments B01 and two second connection sub-segments B02. The second connection line 152 has an "S"-shaped structure. In this case, each first connection sub-segment B01 includes a first segment B1-1 and a second segment B1-2 arranged from top to bottom, and a device pad group 141 located between the first segment B1-1 and the second segment B1-2. The device pad group 141 is connected to the first segment B1-1 and the second segment B1-2, respectively.

[0280] Furthermore, it should be noted that the fact that the first connecting sub-segment B01 extends along the second direction Y does not necessarily mean that the first connecting sub-segment B01 is a strictly straight segment extending only along the second direction Y. The first connecting sub-segment B01 may also be a zigzag segment extending entirely along the second direction Y. Similarly, the fact that the second connecting sub-segment B02 extends along the first direction X does not necessarily mean that the second connecting sub-segment B02 is a strictly straight segment extending only along the first direction X. The second connecting sub-segment B02 may also be a zigzag segment extending entirely along the first direction X. This design is primarily intended to facilitate the connection of two adjacent device pad groups 141 using the first connecting sub-segment B01 and the second connecting sub-segment B02.

[0281] The following describes the specific forms of the first connecting sub-segment B01 and the second connecting sub-segment B02 for the case where one pad unit 14 includes four, six, or nine device pad groups 141 .

[0282] For ease of description, the positive direction of the first direction X is defined as the right direction, the negative direction of the first direction X is defined as the left direction, the positive direction of the second direction Y is defined as the upper direction, and the negative direction of the second direction Y is defined as the lower direction.

[0283] For the case where a pad unit 14 includes four device pad groups 141, illustratively, as shown in FIG8 , in a pad unit 14, the left and right first connecting sub-segments B01 are used to connect two device pad groups 141 spaced apart in the second direction Y. Each of the first connecting sub-segments B01 includes a first straight segment B11, a first inclined segment B12, and a second straight segment B13 connected sequentially from top to bottom, wherein the first straight segment B11 extends along the second direction Y, and the second straight segment B13 extends along the second direction Y. For the left first connecting sub-segment B01, the first straight segment B11 is located to the left of the second straight segment B13, the upper end of the first straight segment B11 is connected to the device pad group 141, and the lower end of the second straight segment B13 is connected to the device pad group 141. For the right first connecting sub-segment B01, the first straight segment B11 is located to the right of the second straight segment B13.

[0284] The second connecting sub-segment B02 is used to connect two device pad groups 141 spaced apart in the first direction X. The second connecting sub-segment B02 is a line segment extending along the first direction X.

[0285] For the case where a pad unit 14 includes six device pad groups 141, as shown in Figure 9, due to the different relative positional relationships between the pad unit 14 and the driver chip IC, the morphologies of the multiple first connecting sub-segments B01 and the multiple second connecting sub-segments B02 in the pad unit 14 are not consistent.

[0286] For a pad unit 14 located on the upper side of the driver chip IC, the first connecting sub-segment B01 is used to connect two device pad groups 141 spaced apart in the second direction Y. There are three first connecting sub-segments B01 spaced apart along the first direction X. The middle first connecting sub-segment B01 is a line segment extending along the second direction Y. The first connecting sub-segments B01 on both sides respectively include a third straight segment B14, a fourth straight segment B15, a second inclined segment B16, a fifth straight segment B17, and a sixth straight segment B18, connected sequentially from top to bottom. The third straight segment B14 extends along the first direction, the fourth straight segment B15 extends along the second direction, the fifth straight segment B17 extends along the second direction, and the sixth straight segment B18 extends along the first direction. The fourth straight segment B15 is located to the right of the fifth straight segment B17. The left end of the third straight segment B14 is connected to the device pad group 141, and the right end of the sixth straight segment B18 is connected to the device pad group 141. The second connecting sub-segment B02 is used to connect two device pad groups 141 spaced apart in the first direction X. Both the upper and lower second connecting sub-segments B02 include a seventh straight segment B19, a third inclined segment B20, and an eighth straight segment B21, which are sequentially connected from left to right. The seventh straight segment B19 is located above the eighth straight segment B21. The left end of the seventh straight segment B19 is connected to the device pad group 141, and the right end of the eighth straight segment B21 is connected to the device pad group 141.

[0287] For a pad unit 14 located below the driver chip IC, as shown in FIG9 , a first connecting sub-segment B01 is used to connect two device pad groups 141 spaced apart in the second direction Y. There are three first connecting sub-segments B01 spaced apart along the first direction X. The middle first connecting sub-segment B01 includes, from top to bottom, a ninth straight segment B22, a tenth straight segment B23, a fourth inclined segment B24, an eleventh straight segment B25, and a twelfth straight segment B26. The ninth straight segment B22 extends along the first direction, the tenth straight segment B23 extends along the second direction, the eleventh straight segment B25 extends along the second direction, and the twelfth straight segment B26 extends along the first direction. The tenth straight segment B23 is located to the right of the eleventh straight segment B25. The left end of the ninth straight segment B22 is connected to the device pad group 141, and the right end of the twelfth straight segment B26 is connected to the device pad group 141. As for the first connecting sub-segments B01 on both sides, they are line segments extending along the second direction Y respectively.

[0288] The second connecting sub-segment B02 is used to connect two device pad groups 141 spaced apart in the first direction X. Both the upper and lower second connecting sub-segments B02 include a thirteenth straight segment B27, a fifth inclined segment B28, and a fourteenth straight segment B29, sequentially connected from left to right. The thirteenth straight segment B27 is located above the fourteenth straight segment B29. The left end of the thirteenth straight segment B27 is connected to the device pad group 141, and the right end of the fourth straight segment B15 is connected to the device pad group 141.

[0289] When a pad unit 14 includes nine device pad groups 141 , the shapes of the multiple first connecting sub-segments B01 and the second connecting sub-segments B02 in the pad unit 14 are not consistent due to the different relative positional relationships between the pad unit 14 and the driver chip IC.

[0290] In the pad unit 14 located above the driver chip IC, the first connecting sub-segment B01 is used to connect to the device pad group 141 spaced apart in the second direction Y. There are three first connecting sub-segments B01 spaced apart along the first direction X. The first segment B1-1 and the second segment B1-2 in the middle first connecting sub-segment B01 respectively comprise a first connecting segment B30, a second connecting segment B31, a third connecting segment B32, a fourth connecting segment B33, and a fifth connecting segment B34, which are sequentially connected from top to bottom. The first connecting segment B30, the third connecting segment B32, and the fourth connecting segment B33 extend along the first direction X, while the second connecting segment B31 and the fifth connecting segment B34 extend along the second direction Y. The second connecting segment B31 is located to the left of the fourth connecting segment B33. The right end of the first connecting segment B30 is connected to the device pad group 141, and the left end of the fifth connecting segment B34 is connected to the device pad group 141.

[0291] As for the first segment B1 - 1 and the second segment B1 - 2 in the first connecting sub-segment B01 on both sides, they are respectively line segments extending along the second direction Y.

[0292] The second connecting sub-segment B02 is used to connect two device pad groups 141 spaced apart in the first direction X. The upper and lower second connecting sub-segments B02 each include a sixth connecting segment B35, a sixth inclined segment B36, and a seventh connecting segment B37, sequentially connected from left to right. The sixth connecting segment B35 and the seventh connecting segment B37 both extend along the first direction, with the sixth connecting segment B35 located below the seventh connecting segment B37. The left end of the sixth connecting segment B35 is connected to the device pad group 141, and the right end of the seventh connecting segment B37 is connected to the device pad group 141.

[0293] In the pad unit 14 located below the driver chip IC, the first connecting sub-segments B01 are used to connect to the device pad groups 141 spaced apart in the second direction Y. There are three first connecting sub-segments B01 spaced apart along the first direction X. The first segment B1-1 and the second segment B1-2 in the middle first connecting sub-segment B01 are both line segments extending along the second direction Y. The first segment B1-1 and the second segment B1-2 in the side first connecting sub-segments B01 respectively include an eighth connecting segment B38, a ninth connecting segment B39, a tenth connecting segment B40, an eleventh connecting segment B41, and a twelfth connecting segment B42, which are connected in sequence. The eighth connecting segment B38, the tenth connecting segment B40, and the twelfth connecting segment B42 extend along the first direction X, and the ninth connecting segment B39 and the eleventh connecting segment B41 extend along the second direction Y. The right end of the eighth connecting segment B38 is connected to the device pad group 141, and the left end of the twelfth connecting segment B42 is connected to the device pad group 141. The ninth connecting segment B39 is located on the left side of the eleventh connecting segment B41.

[0294] The second connecting sub-segment B02 is used to connect two device pad groups 141 spaced apart in the first direction X. The upper and lower second connecting sub-segments B02 respectively include a thirteenth connecting segment B43, a seventh inclined segment B44, and a fourteenth connecting segment B45, connected sequentially from left to right. The thirteenth connecting segment B43 and the fourteenth connecting segment B45 extend along the first direction, with the thirteenth connecting segment B43 located below the fourteenth connecting segment B45. The left end of the thirteenth connecting segment B43 is connected to the device pad group 141, and the right end of the fourteenth connecting segment B45 is connected to the device pad group 141.

[0295] Based on the fact that the plurality of connecting sub-segments 152A include the first connecting sub-segment B01 and the second connecting sub-segment B02, there are various locations for the dummy conductive pattern 13. The specific locations of the dummy conductive pattern 13 are described below.

[0296] In a possible implementation, as shown in FIG. 10 , along the first direction X, the dummy conductive pattern 13 is located between two adjacent first connection sub-segments B01 in the same second connection line 152 .

[0297] In this way, during the electroplating process of forming two adjacent first connecting sub-segments B01 in the same second connecting line 152, dummy conductive patterns 13 are simultaneously formed. The dummy conductive patterns 13 to be plated are positioned at appropriate locations and a suitable number of dummy conductive patterns 13 to be plated are provided as needed. This ensures that, during the electroplating process, the electric field at the locations of the different first connecting sub-segments B01 to be plated is uniformly distributed, resulting in a relatively uniform thickness of the different first connecting sub-segments B01. This improves the yield of the wiring substrate 1 and ensures the reliability of the wiring substrate 1.

[0298] The first connecting sub-segment B01 to be plated refers to an intermediate form of the first connecting sub-segment B01 during the process of forming the first connecting sub-segment B01 with a specific thickness in a specific area through an electroplating process.

[0299] In another possible implementation, as shown in FIG. 11 , along the second direction Y, the dummy conductive pattern 13 is located between adjacent second connecting sub-segments B02 and first connecting lines 151 .

[0300] In this way, during the electroplating process to form the adjacent second connecting sub-segment B02 and first connecting line 151, the dummy conductive pattern 13 is simultaneously formed. The dummy conductive patterns 13 to be plated are positioned at appropriate locations as needed, and an appropriate number of dummy conductive patterns 13 to be plated are provided as needed. This ensures that, during the electroplating process, the electric field at the locations where the second connecting sub-segment B02 to be plated and the first connecting line 151 to be plated are uniformly distributed. This results in relatively uniform thicknesses of the formed second connecting sub-segment B02 and first connecting line 151, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0301] It is understandable that, along the second direction Y, adjacent second connecting sub-segments B02 and first connecting lines 151 may be located on the same connecting line 15 . Alternatively, adjacent second connecting sub-segments B02 and first connecting lines 151 may also be located on two adjacent connecting lines 15 .

[0302] The second connecting sub-segment B02 to be plated refers to the intermediate form of the second connecting sub-segment B02 during the process of forming the second connecting sub-segment B02 with a specific thickness in a specific area through the electroplating process. The first connecting wire 151 to be plated refers to the intermediate form of the first connecting wire 151 during the process of forming the first connecting wire 151 with a specific thickness in a specific area through the electroplating process.

[0303] In another possible implementation, as shown in FIG12 , along the first direction X, the dummy conductive pattern 13 is located between two adjacent first connecting sub-segments B01 in the same second connecting line 152 . Furthermore, along the second direction Y, the dummy conductive pattern 13 is located between adjacent second connecting sub-segments B02 and the first connecting line 151 .

[0304] It should be explained that, along the first direction X, the dummy conductive pattern 13 is located between two adjacent second connecting sub-segments B02 in the same second connecting line 152, which means that the dummy conductive pattern 13 is located between the extension lines of the two adjacent second connecting sub-segments B02 in the same second connecting line 152. Similarly, along the second direction Y, the dummy conductive pattern 13 is located between adjacent second connecting sub-segments B02 and the first connecting line 151, which means that the dummy conductive pattern 13 is located between the extension lines of the adjacent second connecting sub-segments B02 and the extension lines of the first connecting line 151.

[0305] In some examples, as shown in FIG12 , along the first direction X, the dummy conductive pattern 13 is located between two adjacent first connecting sub-segments B01 in the same second connecting line 152. Furthermore, along the second direction, the dummy conductive pattern 13 is located between adjacent second connecting sub-segments B02 and the first connecting line 151. The adjacent second connecting sub-segments B02 and the first connecting line 151 belong to the same connecting line 15.

[0306] In other examples, as shown in FIG13 , along the first direction, the dummy conductive pattern 13 is located between two adjacent first connecting sub-segments B01 of the same second connecting line 152. Furthermore, along the second direction, the dummy conductive pattern 13 is located between adjacent second connecting sub-segments B02 and first connecting lines 151, and adjacent second connecting sub-segments B02 and first connecting lines 151 are respectively located on adjacent connecting lines 15.

[0307] In this way, during the electroplating process of forming two adjacent first connecting sub-segments B01, and the adjacent second connecting sub-segment B02 and first connecting line 151, dummy conductive patterns 13 are simultaneously formed. The positions and number of dummy conductive patterns 13 to be plated can be appropriately set as needed, so that during the electroplating process, the electric field distribution at the locations where the second connecting sub-segments B02 to be plated, the first connecting line 151 to be plated, and the first connecting line 151 to be plated are relatively uniform, resulting in relatively uniform thickness of the second connecting sub-segments B02, the first connecting line 151, and the first connecting line 151, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0308] According to different requirements, the dummy conductive pattern 13 may have different shapes. For example, the dummy conductive pattern 13 may include at least one dummy conductive portion 131 .

[0309] On this basis, in some embodiments, multiple signal lines 12, multiple connecting lines 15, and dummy conductive parts 131 are provided in the same layer. That is, multiple signal lines 12, multiple connecting lines 15, and at least one dummy conductive part 131 can be formed at one time through a single electroplating process.

[0310] In this way, the dummy conductive portion 131 can make the current density on two adjacent signal lines 12 to be plated and two adjacent connecting lines 15 to be plated close to each other, thereby improving the thickness uniformity between the two adjacent signal lines 12 and two adjacent connecting lines 15.

[0311] In this case, as shown in FIG. 14 , in some embodiments, when a plurality of dummy conductive portions 131 are provided between two adjacent first connecting sub-segments B01 , at least two of the dummy conductive portions 131 are insulated from each other.

[0312] The dummy conductive portion 131 may be disposed in various ways. The following describes the disposition of the dummy conductive portion 131 in detail for the case where the dummy conductive pattern 13 is located between two adjacent first connecting sub-segments B01 in the same second connecting line 152 .

[0313] In some embodiments, as shown in FIG14 , along the first direction X, at least one first dummy conductive portion 13A is disposed between at least partially two adjacent first connecting sub-segments B01 in the same second connecting line 152 ; the first dummy conductive portion 13A extends along the second direction Y. Along the first direction X, two adjacent first connecting sub-segments B01 and the first dummy conductive portion 13A are disposed at equal intervals.

[0314] As a result, during the electroplating process, the first dummy conductive portion 13A to be plated can make the current density on two adjacent first connecting sub-segments B01 to be plated closer, thus making the electroplating efficiency closer, and ultimately making the thickness between the two adjacent first connecting sub-segments B01 closer, thereby improving the thickness uniformity between the two adjacent first connecting sub-segments B01. In addition, because the two adjacent first connecting sub-segments B01 and the first dummy conductive portion 13A are arranged at equal intervals, when manufacturing the mask, the shielding patterns corresponding to the two adjacent first connecting sub-segments B01 and the shielding patterns corresponding to the first dummy conductive portion 13A on the mask are also arranged at equal intervals. This regular arrangement of multiple shielding patterns facilitates mask manufacturing.

[0315] It can be understood that the first dummy conductive portion 13A to be plated refers to an intermediate form of the first dummy conductive portion 13A during the process of forming the first dummy conductive portion 13A with a specific thickness in a specific area through an electroplating process.

[0316] It should be explained that the first dummy conductive portion 13A and the dummy conductive portion 131 have the same function and are only distinguished by name.

[0317] The number of the first dummy conductive parts 13A can be one, two, three, four or five.

[0318] It should be explained that the dummy conductive pattern 13 is located between two adjacent first connecting sub-segments B01 in the same second connecting line 152 in the following two cases.

[0319] In the first case, along the first direction X, two adjacent first connecting sub-segments B01 and first dummy conductive portions 13A do not overlap.

[0320] In the second case, as shown in FIG14 , along the first direction X, the projections of two adjacent first connecting sub-segments B01 and the first dummy conductive portion 13A in the second direction Y at least partially overlap. It should be noted that, herein, "the projections of two adjacent first connecting sub-segments B01 and the first dummy conductive portion 13A in the second direction Y at least partially overlap" includes two cases: the projection of the first connecting sub-segment B01 in the second direction Y partially overlaps with the projection of the first dummy conductive portion 13A in the second direction Y; and the projection of the first connecting sub-segment B01 in the second direction Y completely overlaps with the projection of the first dummy conductive portion 13A in the second direction Y.

[0321] In this case, the distance between the first connecting sub-segment B01 and the first dummy conductive portion 13A is closer. In this way, during the electroplating process, the first dummy conductive portion 13A to be plated can better divert the current to the one with higher current density on the two adjacent first connecting sub-segments B01 to be plated, thereby making the electroplating efficiency between adjacent first connecting sub-segments B01 closer. After the electroplating is completed, the thickness of adjacent first connecting sub-segments B01 is closer, and the thickness uniformity between adjacent first connecting sub-segments B01 is better.

[0322] In other embodiments, as shown in FIG16 , along the first direction X, the dummy conductive pattern 13 located between two adjacent first connecting sub-segments B01 in the same second connecting line 152 includes at least one fifth dummy conductive portion 13E, and the fifth dummy conductive portion 13E extends along the second direction; along the first direction, the fifth dummy conductive portions 13E of adjacent first connecting sub-segments B01 are arranged in sequence at intervals and at unequal intervals.

[0323] In this way, the fifth dummy conductive portion 13E to be plated can also be used to reduce the current with higher current density on the two adjacent first connecting sub-segments B01 to be plated, so that the current density on the two adjacent first connecting sub-segments B01 to be plated is close, and the electroplating efficiency is close, thereby improving the thickness uniformity of the two adjacent first connecting sub-segments B01.

[0324] The fifth dummy conductive portion 13E to be plated refers to an intermediate form of the fifth dummy conductive portion 13E during the process of forming the fifth dummy conductive portion 13E with a specific thickness in a specific area through an electroplating process.

[0325] In some examples, between two adjacent first connecting sub-segments B01 , the number of the fifth dummy conductive portions 13E may be one, two, or more.

[0326] Exemplarily, for a column of connecting lines 15 on the left, there are two fifth dummy conductive portions 13E between two adjacent first connecting sub-segments B01. As shown in FIG16 , along the first direction X, the distance between the fifth dummy conductive portion 13E on the left and the first connecting sub-segment B01 on the left is smaller than the distance between the two adjacent fifth dummy conductive portions 13E, and the distance between the fifth dummy conductive portion 13E on the right and the first connecting sub-segment B01 on the right is smaller than the distance between the two adjacent fifth dummy conductive portions 13E.

[0327] Along the first direction X, the distance between the fifth dummy conductive portion 13E on the left and the first connecting sub-segment B01 on the left may be equal to the distance between the fifth dummy conductive portion 13E on the right and the first connecting sub-segment B01 on the right.

[0328] Of course, the distance between the fifth dummy conductive portion 13E on the left and the first connecting sub-segment B01 on the left may be unequal to the distance between the fifth dummy conductive portion 13E on the right and the first connecting sub-segment B01 on the right.

[0329] In some embodiments, the distance between the dummy conductive pattern 13 and the adjacent first connection line 151 ranges from 0.2 mm to 0.5 mm. For example, the distance between the dummy conductive pattern 13 and the adjacent first connection line 151 can be 0.2 mm, 0.25 mm, 0.3 mm, 0.4 mm, or 0.5 mm.

[0330] Within this range, on the one hand, the distance between the dummy conductive pattern 13 and the first connecting line 151 can be prevented from being too small, thereby reducing the risk of electrostatic discharge (ESD) between the two and ensuring the normal operation of the first connecting line 151. On the other hand, the distance between the dummy conductive pattern 13 and the first connecting line 151 can be prevented from being too large, thereby ensuring the accompanying plating effect of the first dummy conductive pattern 13.

[0331] 16 , the distance between the fifth dummy conductive portion 13E on the left and the first connecting sub-segment B01 on the left is in the range of 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.25 mm, 0.3 mm, 0.4 mm, or 0.5 mm.

[0332] 16 , the distance between the fifth dummy conductive portion 13E on the right and the first connecting sub-segment B01 on the right ranges from 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.25 mm, 0.3 mm, 0.4 mm, or 0.5 mm.

[0333] Within this range, on the one hand, the distance between the fifth dummy conductive portion 13E and the first connecting sub-segment B01 can be prevented from being too small, reducing the risk of electrostatic discharge (ESD) between the two and ensuring the normal operation of the first connecting sub-segment B01. On the other hand, the distance between the fifth dummy conductive portion 13E and the first connecting sub-segment B01 can be prevented from being too large, thereby ensuring the accompanying plating effect of the fifth dummy conductive portion 13E.

[0334] Alternatively, the fifth dummy conductive portion 13E may be a line segment extending along the second direction. Alternatively, based on the shape of the first connecting sub-segment B01, the fifth dummy conductive portion 13E may have the same shape as the first connecting sub-segment B01, i.e., the two may be conformal. The following describes the specific configuration of the fifth dummy conductive portion 13E for cases where one pad unit 14 includes four device pad groups 141, six device pad groups 141, and nine device pad groups 141.

[0335] For example, when a pad unit 14 includes four device pad groups 141 , as shown in FIG16 , the first arrangement of the fifth dummy conductive portion 13E in the left column of connection lines 15 is that the fifth dummy conductive portion 13E is a line segment extending along the second direction.

[0336] Alternatively, as shown in FIG16 , in a second configuration of the fifth dummy conductive portion 13E in the right column of connecting wires 15, the fifth dummy conductive portion 13E on the left aligns with the first connecting sub-segment B01 on the left, and the fifth dummy conductive portion 13E on the right aligns with the first connecting sub-segment B01 on the right. That is, along the second direction, the fifth dummy conductive portion 13E on the left includes a first straight dummy sub-segment E1, a first inclined dummy sub-segment E2, and a second straight dummy sub-segment E3, which are sequentially connected from top to bottom. The first straight dummy sub-segment E1 on the left is parallel to the first straight segment B11 on the left, the first inclined dummy sub-segment E2 on the left is parallel to the first inclined segment B12 on the left, and the second straight dummy sub-segment E3 on the right is parallel to the second straight segment B13 on the right.

[0337] Exemplarily, as shown in FIG. 17 , when one pad unit 14 includes six device pad groups 141 , one arrangement of the fifth dummy conductive portion 13E is that the fifth dummy conductive portion 13E is a line segment extending along the second direction.

[0338] 18 , another configuration of the fifth dummy conductive portion 13E is to have the fifth dummy conductive portion 13E aligned with the first connecting sub-segment B01. The following example illustrates the alignment of the fifth dummy conductive portion 13E with the first connecting sub-segment B01.

[0339] For example, along the second direction, in a pad unit 14 located on the upper side of the driver chip IC, for the middle first connecting sub-segment B01, along the first direction, the two fifth dummy conductive portions 13E located on both sides of the first connecting sub-segment B01 are both line segments extending along the second direction.

[0340] As shown in Figure 17, for both the left and right first connecting sub-segments B01, the fifth dummy conductive portion 13E includes a third straight dummy sub-segment E4, a second inclined dummy sub-segment E5, and a fourth straight dummy sub-segment E6, connected sequentially from top to bottom. The third straight dummy sub-segment E4 is parallel to the fourth straight segment B15, the second inclined dummy sub-segment E5 is parallel to the second inclined segment B16, and the fourth straight dummy sub-segment E6 is parallel to the fifth straight segment B17.

[0341] For another example, along the second direction, as shown in Figures 17 and 19, in a pad unit 14 located below the driver chip IC, for the middle first connecting sub-segment B01, as shown in Figure 19, along the first direction, the two fifth dummy conductive portions 13E located on either side of the first connecting sub-segment B01 each include a fifth straight dummy sub-segment E7, a third inclined dummy sub-segment E8, and a sixth straight dummy sub-segment E9, sequentially connected from top to bottom. The fifth straight dummy sub-segment E7 is parallel to the tenth straight segment B23, the third inclined dummy sub-segment E8 is parallel to the fourth inclined segment B24, and the sixth straight dummy sub-segment E9 is parallel to the eleventh straight segment B25.

[0342] As for the first connecting sub-segments B01 on the left and right sides, the fifth dummy conductive portions 13E are both line segments extending along the second direction.

[0343] For example, when a pad unit 14 includes nine device pad groups 141 , as shown in FIG20 , in the left column of connecting wires 15 , one configuration of the fifth dummy conductive portion 13E is that the fifth dummy conductive portion 13E is a line segment extending along the second direction.

[0344] Alternatively, as shown in FIG21 , another configuration of the fifth dummy conductive portion 13E is that the fifth dummy conductive portion 13E and the first connecting sub-segment B01 are aligned along the second direction. The alignment of the fifth dummy conductive portion 13E and the first connecting sub-segment B01 is described in detail below.

[0345] For example, as shown in FIG. 20 and FIG. 21 , along the second direction, in a pad unit 14 located above the driver chip IC.

[0346] For the first segment B1-1 (upper side) and the second segment B1-2 in the middle first connecting sub-segment B01, along the first direction, the two fifth dummy conductive portions 13E located on both sides of the first connecting sub-segment B01 include, in order from top to bottom, a first connecting dummy sub-portion E10, a second connecting dummy sub-portion E11, a third connecting dummy sub-portion E12, a fourth connecting dummy sub-portion E13, a fifth connecting dummy sub-portion E14, a sixth connecting dummy sub-portion E15, a seventh connecting dummy sub-portion E16, and an eighth connecting dummy sub-portion E17. Specifically, for the first segment B1-1 in the first connecting sub-segment B01, the first connecting dummy sub-portion E10 is parallel to the second connecting segment B31, the second connecting dummy sub-portion E11 is parallel to the third connecting segment B32, the third connecting dummy sub-portion E12 is parallel to the fourth connecting segment B33, and the fourth connecting dummy sub-portion E13 is parallel to the fifth connecting segment B34. For the second segment B1-2 in the first connecting sub-segment B01, the fifth connecting dummy sub-portion E14 is parallel to the first connecting segment B30, the sixth connecting dummy sub-portion E15 is parallel to the second connecting segment B31, the seventh connecting dummy sub-portion E16 is parallel to the third connecting segment B32, and the eighth connecting dummy sub-portion E17 is parallel to the fourth connecting segment B33.

[0347] On this basis, as shown in FIG. 21 , illustratively, the fourth connection dummy sub-portion E13 and the fifth connection dummy sub-portion E14 are connected together at their adjacent ends.

[0348] As for the first connecting sub-segments B01 on the left and right sides, the fifth dummy conductive portions 13E are both line segments extending along the second direction.

[0349] For another example, along the second direction, in a pad unit 14 located below the driver chip IC.

[0350] For the middle first connecting sub-segment B01 , as shown in FIG22 , along the first direction, the two fifth dummy conductive portions 13E located on both sides of the first connecting sub-segment B01 are both line segments extending along the second direction.

[0351] For the first segment B1-1 (upper side) and the second segment B1-2 (lower side) in the first connecting sub-segment B01 on the left and right sides, the fifth dummy conductive portion 13E for accompanying plating the two segments includes, respectively, a ninth connecting dummy sub-portion E18, a tenth connecting dummy sub-portion E19, an eleventh connecting dummy sub-portion E20, a twelfth connecting dummy sub-portion E21, a thirteenth connecting dummy sub-portion E22, a fourteenth connecting dummy sub-portion E23, a fifteenth connecting dummy sub-portion E24, and a sixteenth connecting dummy sub-portion E25, which are sequentially connected from top to bottom. The ninth connecting dummy sub-portion E18 is parallel to the ninth connecting segment B39, the tenth connecting dummy sub-portion E19 is parallel to the tenth connecting segment B40, the eleventh connecting dummy sub-portion E20 is parallel to the eleventh connecting segment B41, and the twelfth connecting dummy sub-portion E21 is parallel to the twelfth connecting segment B42. The thirteenth connecting dummy sub-portion E22 is parallel to the eighth connecting segment B38, the fourteenth connecting dummy sub-portion E23 is parallel to the ninth connecting segment B39, the fifteenth connecting dummy sub-portion E24 is parallel to the tenth connecting segment B40, and the sixteenth connecting dummy sub-portion E25 is parallel to the eleventh connecting segment B41.

[0352] On this basis, as shown in FIG. 22 , illustratively, the ends of the twelfth connection dummy sub-portion E21 and the thirteenth connection dummy sub-portion E22 that are close to each other may be connected together.

[0353] Next, the arrangement of the dummy conductive pattern 13 is described in detail for the case where the dummy conductive pattern 13 is located between the adjacent second connecting sub-segment B02 and the first connecting line 151 , and the adjacent second connecting sub-segment B02 and the first connecting line 151 belong to two adjacent connecting lines 15 .

[0354] In some embodiments, as shown in FIG15 and FIG23 , the dummy conductive pattern 13 includes at least one second dummy conductive portion 13B; the second dummy conductive portion 13B extends along the second direction Y. Along the second direction Y, when the dummy conductive pattern 13 is located between adjacent second connecting sub-segments B02 and first connecting lines 151, and the adjacent second connecting sub-segments B02 and first connecting lines 151 are respectively two adjacent connecting lines 15, the second dummy conductive portion 13B is provided between the adjacent second connecting sub-segments B02 and first connecting lines 151. Along the first direction X, the second dummy conductive portions 13B are provided at equal intervals between two adjacent signal lines 12.

[0355] Thus, during the electroplating process, by providing the second dummy conductive portion 13B to be plated, and arranging the second dummy conductive portion 13B at equal intervals between two adjacent signal lines 12, the current density on the two adjacent signal lines 12 to be plated can be made close, and the electroplating efficiency can be made close, so that the thickness between the two adjacent signal lines 12 can be made close, thereby improving the thickness uniformity between the two adjacent signal lines 12. In addition, because the two adjacent signal lines 12 and the second dummy conductive portion 13B are arranged at equal intervals, when manufacturing the mask, the shielding patterns corresponding to the two adjacent signal lines 12 and the shielding patterns corresponding to the second dummy conductive portion 13B on the mask are also arranged at equal intervals. Such a regular arrangement of multiple shielding patterns can facilitate the manufacture of the mask.

[0356] The second dummy conductive portion 13B to be plated refers to an intermediate form of the second dummy conductive portion 13B during the process of forming the second dummy conductive portion 13B with a specific thickness in a specific area through an electroplating process.

[0357] In addition, the number of the second dummy conductive parts 13B can be one, two, or more.

[0358] It can be understood that, in the case where a driver chip IC drives a pad unit 14, for example, a pad unit 14 includes four device pad groups 141. As mentioned above, along the first direction X, the two adjacent signal lines 12 and the second virtual conductive portion 13B, the two adjacent signal lines 12 in the equally spaced arrangement refer to the first signal line VLED and the address signal line 12A. Since the address signal line 12A includes a plurality of addressing signal sub-segments 12A1 arranged along the second direction, the two adjacent signal lines 12 can be understood as the first signal line VLED and the addressing signal sub-segment 12A1.

[0359] On this basis, as shown in FIG23 , for layout requirements, the addressing signal sub-segment 12A1 needs to be bent when connected to the driver chip IC. In this case, the distance between two adjacent signal lines 12 refers to the minimum distance between the first signal line VLED and the addressing signal line 12A.

[0360] For example, if a driver chip IC drives four pad units 14, for example, a pad unit 14 includes six device pad groups 141. As mentioned above, along the first direction X, two adjacent signal lines 12 and second dummy conductive portions 13B are equally spaced, and the two adjacent signal lines 12 are the first signal line VLED and the first voltage line VCC1. For another example, if a pad unit 14 includes nine device pad groups 141, the two adjacent signal lines 12 are the first signal line VLED and the second voltage line VCC2.

[0361] In some examples, as shown in FIG. 23 , the second dummy conductive portion 13B and the projection of the first connecting sub-segment B01 in the second direction Y are at least partially staggered.

[0362] It should be noted that, here, “the projection of the second dummy conductive portion 13B and the first connecting sub-segment B01 in the second direction Y are at least partially staggered” includes two situations: the projection of the second dummy conductive portion 13B and the first connecting sub-segment B01 in the second direction Y are staggered, the projection of the second dummy conductive portion 13B and the first connecting sub-segment B01 in the second direction Y are staggered and partially overlapped, and the projection of the second dummy conductive portion 13B and the first connecting sub-segment B01 in the second direction Y are partially staggered.

[0363] In this way, when the second dummy conductive portion 13B and the first connecting sub-segment B01 are located in the same conductive layer, during the process of electroplating the second dummy conductive portion 13B and the first connecting sub-segment B01, mutual interference between the first connecting sub-segment B01 to be plated and the second dummy conductive portion 13B to be plated can be avoided, so as to ensure that the first connecting sub-segment B01 and the second dummy conductive portion 13B are insulated from each other after being formed.

[0364] In other embodiments, as shown in Figure 24, along the first direction X, when the dummy conductive pattern 13 is located between the adjacent second connecting sub-segment B02 and the first connecting line 151, and the adjacent second connecting sub-segment B02 and the first connecting line 151 respectively belong to two adjacent connecting lines 15, the dummy conductive pattern 13 includes at least one sixth dummy conductive portion 13F, and the sixth dummy conductive portion 13F extends along the second direction Y; along the first direction X, adjacent signal lines 12 and the sixth dummy conductive portions 13F are arranged in sequence at intervals and are set at unequal intervals.

[0365] In this way, the sixth dummy conductive part 13F to be plated can also be used to divert the current on the one with higher current density between the two adjacent signal lines to be plated, so that the current density on the two adjacent signal lines to be plated is close, and the electroplating efficiency is close, thereby improving the thickness uniformity of the two adjacent signal lines 12.

[0366] The sixth dummy conductive portion 13F to be plated refers to an intermediate form of the sixth dummy conductive portion 13F during the process of forming the sixth dummy conductive portion 13F with a specific thickness in a specific area through an electroplating process.

[0367] In some examples, between adjacent second connection sub-segments B02 and first connection lines 151 , the number of sixth dummy conductive portions 13F may be one, two, or more.

[0368] For example, in the case where a pad unit 14 includes four device pad groups 141, there are two sixth dummy conductive parts 13F between the adjacent second connecting sub-segment B02 and the first connecting line 151. As shown in FIG24 , along the first direction, the distance between the sixth dummy conductive part 13F on the left and the signal line 12 (first signal line VLED) on the left is smaller than the distance between the two adjacent sixth dummy conductive parts 13F, and the distance between the sixth dummy conductive part 13F on the right and the addressing signal line 12A on the right is smaller than the distance between the two adjacent sixth dummy conductive parts 13F.

[0369] Along the first direction, the distance between the sixth dummy conductive portion 13F on the left and the signal line 12 (first signal line VLED) on the left may be equal to the distance between the sixth dummy conductive portion 13F on the right and the addressing signal line 12A on the right.

[0370] Of course, the distance between the sixth dummy conductive portion 13F on the left and the signal line 12 (first signal line VLED) on the left may be unequal to the distance between the sixth dummy conductive portion 13F on the right and the addressing signal line 12A on the right.

[0371] Exemplarily, the distance between the left sixth dummy conductive portion 13F and the left signal line 12 (first signal line VLED) ranges from 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.23 mm, 0.3 mm, 0.4 mm, or 0.5 mm.

[0372] Exemplarily, the distance between the sixth dummy conductive portion 13F on the right side and the address signal line 12A on the right side ranges from 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.23 mm, 0.3 mm, 0.4 mm, or 0.5 mm.

[0373] Within this range, on the one hand, the distance between the sixth dummy conductive portion 13F and the signal line 12 can be prevented from being too small, thereby reducing the risk of electrostatic discharge (ESD) between the two and ensuring the normal operation of the signal line 12. On the other hand, the distance between the sixth dummy conductive portion 13F and the signal line 12 can be prevented from being too large, thereby ensuring the accompanying plating effect of the sixth dummy conductive portion 13F.

[0374] The following describes in detail the arrangement of the dummy conductive pattern 13 in the case where the dummy conductive pattern 13 is located between two adjacent second connecting sub-segments B02 and the first connecting line 151 , and the adjacent second connecting sub-segments B02 and the first connecting line 151 belong to two adjacent connecting lines 15 .

[0375] In some embodiments, as shown in FIG25 , along the second direction Y, when the dummy conductive pattern 13 is located between adjacent second connecting sub-segments B02 and first connecting lines 151, and the adjacent second connecting sub-segments B02 and first connecting lines 15 respectively belong to two adjacent connecting lines 15, the dummy conductive pattern 13 further includes at least one third dummy conductive portion 13C; the third dummy conductive portion 13C extends along the first direction X. Along the second direction Y, adjacent second connecting sub-segments B02, first connecting lines 151, and third dummy conductive portions 13C are arranged at equal intervals.

[0376] As a result, during the electroplating process, the third dummy conductive portion 13C to be plated can make the current density on the adjacent second connecting sub-segments B02 and the first connecting line 151 approach, thus approaching the electroplating efficiency, and ultimately making the thickness between the adjacent second connecting sub-segments B02 and the first connecting line 151 approach, thereby improving the thickness uniformity between the adjacent second connecting sub-segments B02 and the first connecting line 151. In addition, because the adjacent second connecting sub-segments B02, the first connecting line 151, and the third dummy conductive portion 13C are arranged at equal intervals, when manufacturing the mask, the shielding patterns corresponding to the adjacent second connecting sub-segments B02 and the first connecting line 151, as well as the shielding patterns corresponding to the third dummy conductive portion 13C, are also arranged at equal intervals. This regular arrangement of multiple shielding patterns can facilitate the manufacture of the mask.

[0377] It can be understood that the third dummy conductive portion 13C to be plated refers to an intermediate form of the third dummy conductive portion 13C during the process of forming the third dummy conductive portion 13C with a specific thickness in a specific area through an electroplating process.

[0378] It should be noted that when the dummy conductive pattern 13 is located between the adjacent second connecting sub-segment B02 and the first connecting line 151, and the adjacent second connecting sub-segment B02 and the first connecting line 151 are respectively two adjacent connecting lines 15, there are two possible scenarios. In the first scenario, the projections of the dummy conductive pattern 13, the second connecting sub-segment B02, and the first connecting line 151 in the first direction X at least partially overlap. In the second scenario, the projections of the dummy conductive pattern 13, the second connecting sub-segment B02, and the first connecting line 151 in the first direction X do not overlap.

[0379] The number of the third dummy conductive parts 13C can be one, two, or more.

[0380] In other embodiments, as shown in FIG26 , along the second direction Y, when the dummy conductive pattern 13 is located between two adjacent second connecting sub-segments B02 and the first connecting line 151 , and the adjacent second connecting sub-segments B02 and the first connecting line 151 respectively belong to two adjacent connecting lines 15 , the dummy conductive pattern 13 further includes at least one seventh dummy conductive portion 13G; the seventh dummy conductive portion 13G extends along the first direction X. Along the second direction Y, adjacent second connecting sub-segments B02 and the first connecting line 151 and the seventh dummy conductive portion 13G are arranged at unequal intervals.

[0381] In this way, the seventh dummy conductive portion 13G to be plated can also be used to divert the current with higher current density on the adjacent second connecting sub-segment to be plated B02 and the first connecting line to be plated 151, so that the current density on the adjacent second connecting sub-segment to be plated B02 and the first connecting line to be plated 151 is close, and the electroplating efficiency is close, thereby improving the thickness uniformity of the adjacent second connecting sub-segment B02 and the first connecting line 151.

[0382] The seventh dummy conductive portion 13G to be plated refers to an intermediate form of the seventh dummy conductive portion 13G during the process of forming the seventh dummy conductive portion 13G with a specific thickness in a specific area through an electroplating process.

[0383] In addition, the number of the seventh dummy conductive portions 13G may be one, two, or more.

[0384] For example, as shown in FIG27 , when a pad unit 14 includes four device pad groups 141, two seventh dummy conductive portions 13G1 and 13G2 are provided. The seventh dummy conductive portion 13G1 is located above the seventh dummy conductive portion 13G2. The adjacent second connecting sub-segments B02 are equidistant from the first connecting line 151 and the seventh dummy conductive portion 13G1. The seventh dummy conductive portion 13G2 is located close to the second connecting sub-segment B02 and is spaced from the second connecting sub-segment B02 by a distance of 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.23 mm, 0.35 mm, 0.4 mm, or 0.5 mm.

[0385] The following describes in detail the arrangement of the dummy conductive pattern 13 when the dummy conductive pattern 13 is located between the adjacent second connecting sub-segment B02 and the first connecting line 151 , and the second connecting sub-segment B02 and the first connecting line 151 belong to the same connecting line 15 .

[0386] In some embodiments, as shown in FIG28 , along the second direction Y, when the dummy conductive pattern 13 is located between the adjacent second connecting sub-segment B02 and the first connecting line 151 , and the second connecting sub-segment B02 and the first connecting line 151 belong to the same connecting line 15 , the dummy conductive pattern 13 further includes at least one fourth dummy conductive portion 13D; the fourth dummy conductive portion 13D extends along the first direction X. Along the second direction Y, the second connecting sub-segment B02, the first connecting line 151, and the fourth dummy conductive portion 13D are arranged at equal intervals.

[0387] As a result, during the electroplating process, the fourth dummy conductive portion 13D to be plated can make the current density on the adjacent second connecting sub-segments B02 and the first connecting line 151 close, and the electroplating efficiency close, ultimately making the thickness between the adjacent second connecting sub-segments B02 and the first connecting line 151 close, thereby improving the thickness uniformity between the adjacent second connecting sub-segments B02 and the first connecting line 151. In addition, because the adjacent second connecting sub-segments B02, the first connecting line 151, and the fourth dummy conductive portion 13D are arranged at equal intervals, when manufacturing the mask, the shielding patterns on the mask corresponding to the adjacent second connecting sub-segments B02 and the first connecting line 151, as well as the shielding patterns corresponding to the fourth dummy conductive portion 13D, are also arranged at equal intervals. This regular arrangement of multiple shielding patterns can facilitate the manufacture of the mask.

[0388] It can be understood that the fourth dummy conductive portion 13D to be plated refers to an intermediate form of the fourth dummy conductive portion 13D during the process of forming the fourth dummy conductive portion 13D with a specific thickness in a specific area through an electroplating process.

[0389] It should be noted that the phrase "the dummy conductive pattern 13 is located between the adjacent second connecting sub-segment B02 and the first connecting line 151" means that the dummy conductive pattern 13 is located between the extension line of the adjacent second connecting sub-segment B02 and the extension line of the first connecting line 151. This specifically includes two situations: in the first situation, the dummy conductive pattern 13 at least partially overlaps with the second connecting sub-segment B02 and the first connecting line 151 along the second direction; in the second situation, the dummy conductive pattern 13 does not overlap with the second connecting sub-segment B02 and the first connecting line 151 along the second direction.

[0390] The number of the fourth dummy conductive portions 13D may be one, two, or more, etc. FIG28 shows that there are two fourth dummy conductive portions 13D provided between the adjacent second connecting sub-segments B02 and the first connecting line 151 .

[0391] In other embodiments, as shown in FIG29 , along the second direction Y, when the dummy conductive pattern 13 is located between the adjacent second connecting sub-segment B02 and the first connecting line 151 , and the second connecting sub-segment B02 and the first connecting line 151 belong to the same connecting line 15 , the dummy conductive pattern 13 further includes at least one eighth dummy conductive portion 13H; the eighth dummy conductive portion 13H extends along the first direction X. Along the second direction Y, the second connecting sub-segment B02, the first connecting line 151, and the eighth dummy conductive portion 13H are arranged at unequal intervals.

[0392] In this way, the eighth dummy conductive part 13H to be plated can make the current density on the adjacent second connecting sub-segments B02 and the first connecting line 151 close, and the electroplating efficiency close, so as to ultimately make the thickness between the adjacent second connecting sub-segments B02 and the first connecting line 151 close, so as to improve the thickness uniformity between the adjacent second connecting sub-segments B02 and the first connecting line 151.

[0393] The eighth dummy conductive portion 13H to be plated refers to an intermediate form of the eighth dummy conductive portion 13H during the process of forming the eighth dummy conductive portion 13H with a specific thickness in a specific area through an electroplating process.

[0394] In some examples, between adjacent second connection sub-segments B02 and first connection lines 151 , the number of eighth dummy conductive portions 13H may be one, two, or more.

[0395] 29 , when a pad unit 14 includes four device pad groups 141, there is one eighth dummy conductive portion 13H between adjacent second connection sub-segments B02 and first connection lines 151. Within the same pad unit 14, along the second direction, the distance between the eighth dummy conductive portion 13H and the second connection sub-segment B02 is smaller than the distance between the eighth dummy conductive portion 13H and the first connection line 151.

[0396] Exemplarily, the distance between the eighth dummy conductive portion 13H and the second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.23 mm, 0.35 mm, 0.45 mm, or 0.5 mm.

[0397] For example, when a pad unit 14 includes six device pad groups 141, as shown in FIG30 , there is one eighth dummy conductive portion 13H between the adjacent left second connecting sub-segment B02 and the first connecting line 151. Within the same pad unit 14, along the second direction, the distance between the eighth dummy conductive portion 13H and the left second connecting sub-segment B02 is smaller than the distance between the eighth dummy conductive portion 13H and the first connecting line 151.

[0398] Exemplarily, the distance between the eighth dummy conductive portion 13H and the second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.23 mm, 0.35 mm, 0.45 mm, or 0.5 mm.

[0399] It should be explained that, in this case, the eighth dummy conductive portion 13H can have two different forms.

[0400] In the first type, the eighth dummy conductive portion 13H is a line segment extending along the first direction.

[0401] The second type, for a pad unit 14 on the upper or lower side of the driver chip IC, as shown in FIG30 , is that the eighth dummy conductive portion 13H includes a seventh straight dummy sub-portion H1, a fourth inclined dummy sub-portion H2, and an eighth straight dummy sub-portion H3, which are sequentially connected from left to right. The seventh straight dummy sub-portion H1 is parallel to the seventh straight segment B19, the fourth inclined dummy sub-portion H2 is parallel to the third inclined segment B20, and the eighth straight dummy sub-portion H3 is parallel to the eighth straight segment B21. The seventh straight dummy sub-portion H1 is located above the eighth straight dummy sub-portion H3.

[0402] For example, one pad unit 14 includes nine device pad groups 141 .

[0403] For example, for a pad unit 14 on the upper side of the driver chip IC, as shown in FIG31 , three eighth dummy conductive portions 13H1, 13H2, and 13H3 are provided between the adjacent second connecting sub-segment B02 on the left and the first connecting line 151. The three eighth dummy conductive portions 13H1, 13H2, and 13H3 are arranged in sequence from top to bottom.

[0404] The eighth dummy conductive portion 13H1 is a line segment extending along the first direction and is located between the third connecting segment B32 and the fifth connecting segment B34 in the first segment B1-1. The eighth dummy conductive portion 13H2 is a line segment extending along the first direction and is located between the third connecting segment B32 and the fifth connecting segment B34 in the second segment B1-2, along the second direction. The eighth dummy conductive portion 13H3 is located between the eighth dummy conductive portion 13H2 and the second connecting sub-segment B02. Alternatively, the eighth dummy conductive portion 13H3 can be a line segment extending along the first direction. Alternatively, as shown in FIG. 32 , the eighth dummy conductive portion 13H3 can include a ninth straight dummy sub-segment H4, a fifth inclined dummy sub-segment H5, and a tenth straight dummy sub-segment H6, sequentially connected from left to right. The ninth straight dummy sub-portion H4 is parallel to the sixth connecting segment B35 , the fifth inclined dummy sub-portion H5 is parallel to the sixth inclined segment B36 , and the tenth straight dummy sub-portion H6 is parallel to the seventh connecting segment B37 .

[0405] Along the second direction, the third connecting segment B32 and the fifth connecting segment B34 in the first segment B1-1, and the eighth dummy conductive portion 13H1, are arranged at equal intervals. And / or, the third connecting segment B32 and the fifth connecting segment B34 in the second segment B1-2, and the eighth dummy conductive portion 13H2, are arranged at equal intervals.

[0406] In addition, along the second direction, the distance between the eighth dummy conductive portion 13H3 and the second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, the distance may be 0.2 mm, 0.22 mm, 0.35 mm, 0.45 mm, or 0.5 mm.

[0407] For a pad unit 14 on the upper side of the driver chip IC, three eighth dummy conductive portions 13H4, 13H5, and 13H6 are provided between the adjacent second connecting sub-segment B02 and the first connecting line 151 on the right side, as shown in FIG32 . The eighth dummy conductive portion 13H4 may be a line segment extending along the first direction. Alternatively, as shown in FIG32 , the eighth dummy conductive portion 13H4 may include an eleventh straight dummy sub-segment H7, a sixth inclined dummy sub-segment H8, and a twelfth straight dummy sub-segment H9, sequentially connected from left to right. The eleventh straight dummy sub-segment H7 is parallel to the sixth connecting segment B35, the sixth inclined dummy sub-segment H8 is parallel to the sixth inclined segment B36, and the twelfth straight dummy sub-segment H9 is parallel to the seventh connecting segment B37. The eleventh straight dummy sub-segment H7 is located below the twelfth straight dummy sub-segment H9. The eighth dummy conductive portion 13H5 is located between the first connecting segment B30 and the third connecting segment B32 in the first segment B1-1. The eighth dummy conductive portion 13H6 is located between the first connecting segment B30 and the third connecting segment B32 in the second segment B1-2.

[0408] Along the second direction, the first connecting segment B30 and the third connecting segment B32 in the first segment B1-1, and the eighth dummy conductive portion 13H5 are arranged at equal intervals. And / or, the first connecting segment B30 and the third connecting segment B32 in the second segment B1-2, and the eighth dummy conductive portion 13H6 are arranged at equal intervals.

[0409] In addition, along the second direction, the distance between the eighth dummy conductive portion 13H4 and the second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, the distance may be 0.2 mm, 0.22 mm, 0.36 mm, 0.45 mm, or 0.5 mm.

[0410] For another example, in a pad unit 14 on the lower side of the driver chip IC, as shown in FIG33 , three eighth dummy conductive portions 13H7, 13H8, and 13H9 are provided between the adjacent second connecting sub-segment B02 on the left and the first connecting line 151. The three eighth dummy conductive portions 13H7, 13H8, and 13H9 are arranged in sequence from top to bottom.

[0411] As shown in FIG33 , the eighth dummy conductive portion 13H7 can be a line segment extending along the first direction X. Alternatively, as shown in FIG34 , the eighth dummy conductive portion 13H7 can include a thirteenth straight dummy sub-portion H10, a seventh inclined dummy sub-portion H11, and a fourteenth straight dummy sub-portion H12, sequentially connected from left to right. The thirteenth straight dummy sub-portion H10 is parallel to the sixth connecting segment B35, the seventh inclined dummy sub-portion H11 is parallel to the sixth inclined segment B36, and the fourteenth straight dummy sub-portion H12 is parallel to the seventh connecting segment B37. The thirteenth straight dummy sub-portion H10 is located below the fourteenth straight dummy sub-portion H12. The eighth dummy conductive portion 13H8 is located between the eighth connecting segment B38 and the tenth connecting segment B40 on the first segment B1-1. The eighth dummy conductive portion 13H9 is located between the eighth connecting segment B38 and the tenth connecting segment B40 on the second segment B1-2. The eighth dummy conductive portion 13H8 and the eighth dummy conductive portion 13H9 may be line segments extending along the first direction X.

[0412] Along the second direction, the eighth connecting segment B38 and the tenth connecting segment B40 in the first segment B1-1, and the eighth dummy conductive portion 13H8, are arranged at equal intervals. And / or, the eighth connecting segment B38 and the tenth connecting segment B40 in the second segment B1-2, and the eighth dummy conductive portion 13H9, are arranged at equal intervals.

[0413] In addition, along the second direction, the minimum distance between the eighth dummy conductive portion 13H7 and the second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, 0.2 mm, 0.22 mm, 0.36 mm, 0.45 mm, or 0.5 mm.

[0414] For a pad unit 14 on the lower side of the driver chip IC, as shown in FIG34 , three eighth dummy conductive portions 13H10, 13H11, and 13H12 are provided between the adjacent second connecting sub-segment B02 and the first connecting line 151 on the right side. The three eighth dummy conductive portions 13H10, 13H11, and 13H12 are arranged sequentially from top to bottom.

[0415] The eighth dummy conductive portion 13H10 is a line segment extending along the first direction and is located between the tenth connecting segment B40 and the twelfth connecting segment B42 on the first segment B1-1. The eighth dummy conductive portion 13H11 is located between the tenth connecting segment B40 and the twelfth connecting segment B42 in the second segment B1-2. The eighth dummy conductive portion 13H12 is located between the eighth dummy conductive portion 13H11 and the second connecting sub-segment B02. The eighth dummy conductive portion 13H12 can be a line segment extending along the first direction. Alternatively, as shown in FIG34 , the eighth dummy conductive portion 13H12 can include a fifteenth straight dummy sub-segment H13, an eighth inclined dummy sub-segment H14, and a sixteenth straight dummy sub-segment H15, which are sequentially connected from left to right. The fifteenth straight dummy sub-portion H13 is parallel to the thirteenth connecting segment B43 , the eighth inclined dummy sub-portion H14 is parallel to the seventh inclined segment B44 , and the sixteenth straight dummy sub-portion H15 is parallel to the fourteenth connecting segment B45 .

[0416] Along the second direction, the tenth connecting segment B40 and the twelfth connecting segment B42 in the first segment B1-1, and the eighth dummy conductive portion 13H10 are arranged at equal intervals. And / or, the tenth connecting segment B40 and the twelfth connecting segment B42 in the second segment B1-2, and the eighth dummy conductive portion 13H11 are arranged at equal intervals.

[0417] In addition, along the second direction, the distance between the eighth dummy conductive portion 13H12 and the second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, the distance may be 0.2 mm, 0.22 mm, 0.35 mm, 0.45 mm, or 0.5 mm.

[0418] In some examples, as shown in FIG35 , the signal line 12 and the connection line 15 are provided on the same conductive layer. Along the first direction, the eighth dummy conductive portion 13H is located between the adjacent first signal line VLED and the first connection sub-segment B01. Along the second direction, the distance between the eighth dummy conductive portion 13H and the first connection line 151 is greater than the distance between the eighth dummy conductive portion 13H and the first connection sub-segment B01.

[0419] In the second direction, the distance between the eighth dummy conductive portion 13H and the first connection line 151 ranges from 0.2 mm to 0.5 mm. For example, the distance may be 0.2 mm, 0.22 mm, 0.35 mm, 0.45 mm, or 0.5 mm.

[0420] In addition to being disposed at the positions mentioned in the above embodiments, the dummy conductive patterns 13 may also be disposed at other positions. The following describes the disposition of other dummy conductive patterns 13 by taking the case where a pad unit 14 includes six device pad groups 141 or nine device pad groups 141 as an example.

[0421] For the case where one pad unit 14 includes six device pad groups 141 .

[0422] In some embodiments, along the second direction, a region between the upper and lower connecting lines 15 adjacent to the driver chip IC is subjected to accompanying plating design.

[0423] In some embodiments, as shown in FIG36 , at least one second dummy conductive portion 13B is provided between at least some adjacent second connecting sub-segments B02 , and along the second direction Y, adjacent second connecting sub-segments B02 and at least one second dummy conductive portion 13B are arranged at equal intervals.

[0424] Adjacent second connecting sub-segments B02 may belong to different connecting lines 15 , as shown in FIG. 36 .

[0425] For example, the number of the second dummy conductive portions 13B between adjacent second connecting sub-segments B02 may be one, two, or more, which is not limited in the embodiments of the present disclosure.

[0426] Thus, during the electroplating process, by providing the second dummy conductive portion 13B between adjacent second connecting sub-segments B02, the current density on the two adjacent second connecting sub-segments B02 to be plated can be made similar, and the electroplating efficiency can be made similar, ultimately making the thickness between the two adjacent second connecting sub-segments B02 closer, thereby improving the thickness uniformity between the two adjacent second connecting sub-segments B02. In addition, because the two adjacent second connecting sub-segments B02 and the second dummy conductive portion 13B are arranged at equal intervals, when manufacturing the mask plate, the shielding patterns corresponding to the two adjacent second connecting sub-segments B02 and the shielding patterns corresponding to the second dummy conductive portion 13B on the mask plate are also arranged at equal intervals. This regular arrangement of multiple shielding patterns facilitates the manufacture of the mask plate.

[0427] In other examples, as shown in FIG36 , the dummy conductive pattern 13 is disposed between two adjacent second connecting sub-segments B02, and the two adjacent second connecting sub-segments B02 belong to two adjacent second connecting lines 152. Along the second direction Y, the two adjacent second connecting sub-segments B02 and the dummy conductive pattern 13 between the two adjacent second connecting sub-segments B02 are arranged at unequal intervals.

[0428] For example, the dummy conductive pattern 13 further includes at least one ninth dummy conductive portion 13I, which extends along the first direction X. Along the second direction Y, two adjacent second connecting sub-segments B02 and the ninth dummy conductive portion 13I are arranged at unequal intervals.

[0429] In this way, the ninth dummy conductive portion 13I to be plated can make the current density on the two adjacent second connecting sub-segments B02 close, the electroplating efficiency close, and ultimately make the thickness between the two adjacent second connecting sub-segments B02 close, thereby improving the thickness uniformity between the two adjacent second connecting sub-segments B02.

[0430] The ninth dummy conductive portion 13I to be plated refers to an intermediate form of the ninth dummy conductive portion 13I during the process of forming the ninth dummy conductive portion 13I with a specific thickness in a specific area through an electroplating process.

[0431] In some examples, between two adjacent second connecting sub-segments B02 , the number of the ninth dummy conductive portions 13I may be one, two, or more.

[0432] 36 , three ninth dummy conductive portions 13I1 , 13I2 , and 13I3 are provided between two adjacent second connection sub-segments B02 . The three ninth dummy conductive portions 13I1 , 13I2 , and 13I3 are sequentially spaced from top to bottom.

[0433] The ninth dummy conductive portion 13I1 may be a line segment extending along the first direction. Alternatively, as shown in FIG37 , the ninth dummy conductive portion 13I1 may include a seventeenth straight dummy sub-portion I1, a ninth inclined dummy sub-portion I2, and an eighteenth straight dummy sub-portion I3, sequentially connected from left to right. The seventeenth straight dummy sub-portion I1 is parallel to the seventh straight segment B19 on the upper side, the ninth inclined dummy sub-portion I2 is parallel to the third inclined segment B20 on the upper side, and the eighteenth straight dummy sub-portion I3 is parallel to the eighth straight segment B21 on the upper side. The seventeenth straight dummy sub-portion I1 is located above the eighteenth straight dummy sub-portion I3.

[0434] The ninth dummy conductive portion 13I2 is a line segment extending along the first direction. The ninth dummy conductive portion 13I3 may be a line segment extending along the first direction. Alternatively, as shown in FIG37 , the ninth dummy conductive portion 13I3 may include a nineteenth straight dummy sub-portion I4, a tenth inclined dummy sub-portion I5, and a twentieth straight dummy sub-portion I6, which are sequentially spaced from left to right. The nineteenth straight dummy sub-portion I4 is parallel to the seventh straight segment B19 on the lower side, the tenth inclined dummy sub-portion I5 is parallel to the third inclined segment B20 on the lower side, and the twentieth straight dummy sub-portion I6 is parallel to the eighth straight segment B21 on the lower side.

[0435] Exemplarily, along the second direction, the distance between the ninth dummy conductive portion 13I2 and the ninth dummy conductive portion 13I1 is equal to the distance between the ninth dummy conductive portion 13I2 and the ninth dummy conductive portion 13I3 .

[0436] In addition, along the second direction, the distance between the ninth dummy conductive portion 13I1 and the upper second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, 0.2 mm, 0.22 mm, 0.35 mm, 0.44 mm, or 0.5 mm.

[0437] Along the second direction, the distance between the ninth dummy conductive portion 13I3 and the lower second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, 0.2 mm, 0.22 mm, 0.35 mm, 0.43 mm, or 0.5 mm.

[0438] For the case where one pad unit 14 includes nine device pad groups 141 .

[0439] In some embodiments, a co-plating design is implemented within the upper and lower connecting lines 15 adjacent to the driver IC along the second direction. As shown in Figure 38 , a dummy conductive pattern 13 is disposed between two adjacent second connecting sub-segments B02, which belong to two adjacent second connecting lines 152. The dummy conductive pattern 13 also includes at least one tenth dummy conductive portion 13J; the tenth dummy conductive portion 13J extends along the first direction X. Along the second direction Y, the two adjacent second connecting sub-segments B02 and the tenth dummy conductive portion 13J are arranged at unequal intervals.

[0440] In this way, the tenth dummy conductive portion 13J to be plated can make the current density on the two adjacent second connecting sub-segments B02 close, and the electroplating efficiency close, so as to ultimately make the thickness between the two adjacent second connecting sub-segments B02 close, thereby improving the thickness uniformity between the two adjacent second connecting sub-segments B02.

[0441] The tenth dummy conductive portion 13J to be plated refers to an intermediate form of the tenth dummy conductive portion 13J during the process of forming the tenth dummy conductive portion 13J with a specific thickness in a specific area through an electroplating process.

[0442] In some examples, between two adjacent second connecting sub-segments B02 , the number of the tenth dummy conductive portions 13J may be one, two, or more.

[0443] 38 , three tenth dummy conductive portions 13J1, 13J2, and 13J3 are disposed between two adjacent second connecting sub-segments B02, where the two adjacent second connecting sub-segments B02 belong to two adjacent second connecting lines 152. The three tenth dummy conductive portions 13J1, 13J2, and 13J3 are sequentially spaced from top to bottom.

[0444] The tenth dummy conductive portion 13J1 may be a line segment extending along the first direction. Alternatively, as shown in FIG39 , the tenth dummy conductive portion 13J1 may include a twenty-first straight dummy sub-portion J1, an eleventh inclined dummy sub-portion J2, and a twenty-second straight dummy sub-portion J3, which are sequentially connected from left to right. The twenty-first straight dummy sub-portion J1 is parallel to the sixth connecting segment B35 on the upper side, the eleventh inclined dummy sub-portion J2 is parallel to the sixth inclined segment B36 on the upper side, and the twenty-second straight dummy sub-portion J3 is parallel to the seventh connecting segment B37 on the upper side. The twenty-first straight dummy sub-portion J1 is located below the twenty-second straight dummy sub-portion J3.

[0445] The tenth dummy conductive portion 13J2 is a line segment extending along the first direction. The tenth dummy conductive portion 13J2 can be a line segment extending along the first direction. Alternatively, as shown in FIG39 , the tenth dummy conductive portion 13J3 can also include a twenty-third straight dummy sub-portion J4, a twelfth inclined dummy sub-portion J5, and a twenty-fourth straight dummy sub-portion J6, which are sequentially spaced from left to right. The twenty-third straight dummy sub-portion J4 is parallel to the sixth connecting segment B35 on the lower side, the twelfth inclined dummy sub-portion J5 is parallel to the twelfth inclined dummy sub-portion J5 on the lower side, and the twenty-fourth straight dummy sub-portion J6 is parallel to the seventh connecting segment B37 on the lower side.

[0446] Exemplarily, along the second direction Y, the distance between the tenth dummy conductive portion 13J2 and the tenth dummy conductive portion 13J1 is equal to the distance between the tenth dummy conductive portion 13J2 and the tenth dummy conductive portion 13J3 .

[0447] In addition, along the second direction, the minimum distance between the tenth dummy conductive portion 13J1 and the upper second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, 0.2 mm, 0.22 mm, 0.35 mm, 0.44 mm, or 0.5 mm.

[0448] Along the second direction, the distance between the tenth dummy conductive portion 13J3 and the lower second connecting sub-segment B02 ranges from 0.2 mm to 0.5 mm, for example, 0.2 mm, 0.22 mm, 0.35 mm, 0.43 mm, or 0.5 mm.

[0449] In some embodiments, as shown in FIG40 , the signal line 12 and the connecting line 15 are located on the same conductive layer, and along the second direction, a co-plating design is performed on the upper and lower connecting lines 15 adjacent to the driver chip IC.

[0450] Along the first direction, the dummy conductive pattern 13 is located between the adjacent signal line 12 (i.e., the first signal line VLED) and the first connecting sub-segment B01. The dummy conductive pattern 13 includes an eleventh dummy conductive portion 13K. The eleventh dummy conductive portion 13K extends along the second direction. Along the first direction, the distance between the eleventh dummy conductive portion 13K and the signal line 12 is greater than the distance between the eleventh dummy conductive portion 13K and the first connecting sub-segment B01.

[0451] The eleventh dummy conductive portion 13K to be plated refers to an intermediate form of the eleventh dummy conductive portion 13K during the process of forming the eleventh dummy conductive portion 13K with a specific thickness in a specific area through an electroplating process.

[0452] In addition, the distance between the eleventh dummy conductive portion 13K and the first connecting sub-segment B01 ranges from 0.2 mm to 0.5 mm, for example, the distance may be 0.2 mm, 0.22 mm, 0.35 mm, 0.44 mm, or 0.5 mm.

[0453] In some examples, as shown in FIG. 40 , for one pad unit 14 of the driver chip IC (eg, the pad unit 14 on the upper side), the eleventh dummy conductive portion 13K may be a line segment extending along the second direction.

[0454] In other examples, as shown in FIG40 , for one pad unit 14 of the driver chip IC (eg, the pad unit 14 on the lower side), the extending direction of the eleventh dummy conductive portion 13K is consistent with the extending direction of the adjacent first connecting sub-segment B01 .

[0455] The first dummy conductive portion 13A, the second dummy conductive portion 13B, the third dummy conductive portion 13C, the fourth dummy conductive portion 13D, the fifth dummy conductive portion 13E, the sixth dummy conductive portion 13F, the seventh dummy conductive portion 13G, the eighth dummy conductive portion 13H, the ninth dummy conductive portion 13I, the tenth dummy conductive portion 13J and the eleventh dummy conductive portion 13K mentioned above can be provided not only separately but also in combination with each other. C. At least two of the fourth dummy conductive part 13D, the fifth dummy conductive part 13E, the sixth dummy conductive part 13F, the seventh dummy conductive part 13G, the eighth dummy conductive part 13H, the ninth dummy conductive part 13I, the tenth dummy conductive part 13J and the eleventh dummy conductive part 13K are set at the same time, and the connecting line 15 and the signal line 12 are set on the same conductive layer. The specific plating situation of a pad unit 14 including four device pad groups 141, six device pad groups 141 or nine device pad groups 141 is introduced.

[0456] In the case where one pad unit 14 includes four device pad groups 141 .

[0457] In the first embodiment, as shown in FIG41 , a first dummy conductive portion 13A and a third dummy conductive portion 13C are provided simultaneously between two adjacent connecting lines 15 along the second direction, and the number of first dummy conductive portion 13A and third dummy conductive portion 13C is one. The lower end of first dummy conductive portion 13A is connected to the right end of third dummy conductive portion 13C, and first dummy conductive portion 13A and third dummy conductive portion 13C form an "L" shape.

[0458] In a second embodiment, as shown in FIG42 , along the second direction, between two adjacent connection lines 15, a first dummy conductive portion 13A, a second dummy conductive portion 13B, a third dummy conductive portion 13C, and a fourth dummy conductive portion 13D are simultaneously provided. The number of each of the first dummy conductive portion 13A, the second dummy conductive portion 13B, the third dummy conductive portion 13C, and the fourth dummy conductive portion 13D is two. The fourth dummy conductive portion 13D is located between the two first dummy conductive portions 13A. The second dummy conductive portion 13B is located between the two adjacent third dummy conductive portions 13C.

[0459] The upper end of the first dummy conductive portion 13A on the left is connected to the left end of the fourth dummy conductive portion 13D on the upper side, the lower end of the first dummy conductive portion 13A on the left is connected to the right end of the third dummy conductive portion 13C on the upper side, the upper end of the first dummy conductive portion 13A on the right is connected to the right end of the fourth dummy conductive portion 13D on the upper side, the lower end of the first dummy conductive portion 13A on the right is connected to the upper end of the second dummy conductive portion 13B on the right side, and the fourth dummy conductive portion 13D on the lower side is connected. The left end of the fourth dummy conductive part 13D on the lower side is connected to the first dummy conductive part 13A on the right side, the left end of the third dummy conductive part 13C on the upper side is connected to the upper end of the second dummy conductive part 13B on the left side, the third dummy conductive part 13C on the lower side is connected to the lower end of the second dummy conductive part 13B on the left side, and the lower end of the second dummy conductive part 13B on the right side is connected to the right end of the third dummy conductive part 13C on the lower side.

[0460] In a third embodiment, as shown in FIG43 , along the second direction, between two adjacent connecting lines 15 , the first dummy conductive part 13A, the sixth dummy conductive part 13F, the seventh dummy conductive part 13G, and the eighth dummy conductive part 13H are provided simultaneously, and the number of the first dummy conductive part 13A, the sixth dummy conductive part 13F, and the seventh dummy conductive part 13G are two each, and the number of the eighth dummy conductive part 13H is one.

[0461] The eighth dummy conductive portion 13H is located between the two first dummy conductive portions 13A, and the two sixth dummy conductive portions 13F are located below the two first dummy conductive portions 13A. The extension direction of the left sixth dummy conductive portion 13F is consistent with the extension direction of the left first dummy conductive portion 13A, and the extension direction of the right sixth dummy conductive portion 13F is consistent with the extension direction of the right first dummy conductive portion 13A. The seventh dummy conductive portion 13G1 is located to the left of the left sixth dummy conductive portion 13F, and the seventh dummy conductive portion 13G2 is located below the sixth dummy conductive portion 13F. The left end of the eighth dummy conductive portion 13H is connected to the upper end of the left first dummy conductive portion 13A, and the right end of the eighth dummy conductive portion 13H is connected to the upper end of the right first dummy conductive portion 13A. The upper end of the sixth dummy conductive portion 13F on the left is connected to the lower end of the first dummy conductive portion 13A on the left, and the lower end of the sixth dummy conductive portion 13F on the left is connected to the seventh dummy conductive portion 13G2. The upper end of the sixth dummy conductive portion 13F on the right is connected to the lower end of the first dummy conductive portion 13A on the right, and the lower end of the sixth dummy conductive portion 13F on the right is connected to the seventh dummy conductive portion 13G2. The right end of the seventh dummy conductive portion 13G1 is connected to the sixth dummy conductive portion 13F on the left, and the lower end of the sixth dummy conductive portion 13F on the left is connected to the seventh dummy conductive portion 13G2.

[0462] In a fourth embodiment, as shown in FIG44 , a first dummy conductive portion 13A, a third dummy conductive portion 13C, a fourth dummy conductive portion 13D, and a sixth dummy conductive portion 13F are simultaneously provided between two adjacent connecting lines 15 along the second direction. Two first dummy conductive portions 13A, two third dummy conductive portions 13C, two fourth dummy conductive portions 13D, and two sixth dummy conductive portions 13F are provided. The two fourth dummy conductive portions 13D are provided between the two adjacent first dummy conductive portions 13A. The sixth dummy conductive portion 13F is provided below the first dummy conductive portion 13A. The extension direction of the left sixth dummy conductive portion 13F is consistent with the extension direction of the left first dummy conductive portion 13A, and the extension direction of the right sixth dummy conductive portion 13F is consistent with the extension direction of the right first dummy conductive portion 13A. Two third dummy conductive portions 13C are provided to the left of the left sixth dummy conductive portion 13F.

[0463] The left end of the upper fourth dummy conductive portion 13D is connected to the upper end of the left first dummy conductive portion 13A, and the right end of the upper fourth dummy conductive portion 13D is connected to the upper end of the right first dummy conductive portion 13A. The left end of the lower fourth dummy conductive portion 13D is connected to the left first dummy conductive portion 13A, and the right end of the lower fourth dummy conductive portion 13D is connected to the right first dummy conductive portion 13A. The lower end of the left first dummy conductive portion 13A is connected to the upper end of the left sixth dummy conductive portion 13F, and the lower end of the right first dummy conductive portion 13A is connected to the upper end of the right sixth dummy conductive portion 13F. The right end of the upper third dummy conductive portion 13C is connected to the left sixth dummy conductive portion 13F, and the right end of the lower third dummy conductive portion 13C is connected to the lower end of the left sixth dummy conductive portion 13F.

[0464] In a fifth embodiment, as shown in FIG45 , a fifth dummy conductive portion 13E, a sixth dummy conductive portion 13F, a seventh dummy conductive portion 13G, and an eighth dummy conductive portion 13H are provided simultaneously between two adjacent connecting lines 15 along the second direction. There are two fifth dummy conductive portions 13E, two sixth dummy conductive portions 13F, and two seventh dummy conductive portions 13G, respectively. There is one eighth dummy conductive portion 13H. The two sixth dummy conductive portions 13F are respectively a sixth dummy conductive portion 13F1 and a sixth dummy conductive portion 13F2; and the two seventh dummy conductive portions 13G are respectively a seventh dummy conductive portion 13G1 and a seventh dummy conductive portion 13G2.

[0465] Eighth dummy conductive portion 13H is disposed between two fifth dummy conductive portions 13E, and two sixth dummy conductive portions 13F are disposed below fifth dummy conductive portion 13E. Sixth dummy conductive portion 13F on the left extends in the same direction as fifth dummy conductive portion 13E on the left, and sixth dummy conductive portion 13F on the right extends in the same direction as fifth dummy conductive portion 13E on the right. Seventh dummy conductive portion 13G1 is disposed to the left of sixth dummy conductive portion 13F on the left, and seventh dummy conductive portion 13G2 is disposed below sixth dummy conductive portion 13F. The left end of eighth dummy conductive portion 13H is connected to the upper end of fifth dummy conductive portion 13E on the left, and the right end of eighth dummy conductive portion 13H is connected to the upper end of fifth dummy conductive portion 13E on the right. The upper end of the sixth dummy conductive portion 13F on the left is connected to the lower end of the fifth dummy conductive portion 13E on the left, and the upper end of the sixth dummy conductive portion 13F on the right is connected to the lower end of the fifth dummy conductive portion 13E on the right. The right end of the seventh dummy conductive portion 13G2 is connected to the lower end of the fifth dummy conductive portion 13E on the right, and the lower end of the fifth dummy conductive portion 13E on the left is connected to the seventh dummy conductive portion 13G2.

[0466] In this case, as shown in Figure 46, along the second direction Y, the distance between the lower end of the sixth dummy conductive part 13F1 and the upper end of the sixth dummy conductive part 13F2 can be greater than or equal to 0.2 mm (at the position of the dotted box in Figure 46). In this way, the two fifth dummy conductive parts 13E, the two sixth dummy conductive parts 13F and the eighth dummy conductive part 13H can be prevented from forming a closed loop, and residual charges can be avoided on the two fifth dummy conductive parts 13E, the two sixth dummy conductive parts 13F and the eighth dummy conductive part 13H after electroplating, thereby avoiding electrostatic discharge (ESD) phenomenon, so as to ensure that the first connecting sub-segment B01, the second connecting sub-segment B02, the first connecting line 151 and the signal line 12 around the two fifth dummy conductive parts 13E, the two sixth dummy conductive parts 13F and the eighth dummy conductive part 13H can work normally.

[0467] In the case where a pad unit 14 includes six device pad groups 141, the accompanying plating of two adjacent connecting lines 15 on the upper and lower sides of the driver chip IC is described below.

[0468] In the sixth embodiment, as shown in FIG. 47 , a first dummy conductive portion 13A, a fifth dummy conductive portion 13E, a sixth dummy conductive portion 13F, a seventh dummy conductive portion 13G, an eighth dummy conductive portion 13H, and a ninth dummy conductive portion 13I are provided on the wiring substrate.

[0469] Among them, four first dummy conductive parts 13A1, 13A2, 13A3 and 13A4 are provided on the wiring substrate 1; eight fifth dummy conductive parts 13E1, 13E2, 13E3, 13E4, 13E5, 13E6, 13E7 and 13E8 are provided on the wiring substrate 1; two sixth dummy conductive parts 13F are provided on the wiring substrate 1; three seventh dummy conductive parts 13G1, 13G2 and 13G3 are provided on the wiring substrate 1; four eighth dummy conductive parts 13H are provided on the wiring substrate 1, and the number is 13H13, 13H14, 13H15 and 13H16; three ninth dummy conductive parts 13I1, 13I2 and 13I3 are provided on the wiring substrate 1.

[0470] As shown in FIG47 , for connection line 15 located on the upper side of driver chip IC, first dummy conductive portion 13A1, fifth dummy conductive portion 13E1, fifth dummy conductive portion 13E2, and eighth dummy conductive portion 13H13 are disposed between adjacent first connecting sub-segments B01 on the left side. Fifth dummy conductive portion 13E1 is located to the left of fifth dummy conductive portion 13E2, and eighth dummy conductive portion 13H13 is located between fifth and fifth dummy conductive portions 13E1 and 13E2. The left end of eighth dummy conductive portion 13H13 is connected to the lower end of fifth dummy conductive portion 13E1, and the right end of eighth dummy conductive portion 13H13 is connected to the lower end of fifth dummy conductive portion 13E2. First dummy conductive portion 13A1 is located between fifth and fifth dummy conductive portions 13E1 and 13E2, with the lower end of first dummy conductive portion 13A1 spaced from eighth dummy conductive portion 13H13.

[0471] First dummy conductive portion 13A2, fifth dummy conductive portion 13E3, fifth dummy conductive portion 13E4, and eighth dummy conductive portion 13H14 are disposed between the right-side adjacent second connecting sub-segment B02. Fifth dummy conductive portion 13E3 is located to the left of fifth dummy conductive portion 13E4, and eighth dummy conductive portion 13H14 is located between fifth and fifth dummy conductive portions 13E3 and 13E4. The upper end of fifth dummy conductive portion 13E3 is connected to the left end of eighth dummy conductive portion 13H13, and the upper end of fifth dummy conductive portion 13E4 is connected to the right end of eighth dummy conductive portion 13H13. First dummy conductive portion 13A2 is located between fifth and fifth dummy conductive portions 13E3 and 13E4, with the upper end of first dummy conductive portion 13A2 spaced from eighth dummy conductive portion 13H14.

[0472] For the connection line 15 located on the bottom side of the driver chip IC, the first dummy conductive portion 13A3, the fifth dummy conductive portion 13E5, the fifth dummy conductive portion 13E6, and the eighth dummy conductive portion 13H15 are located between the adjacent second connecting sub-segments B02 on the left side. The fifth dummy conductive portion 13E5 is located to the left of the fifth dummy conductive portion 13E6, and the eighth dummy conductive portion 13H15 is located between the fifth and fifth dummy conductive portions 13E5 and 13E6. The left end of the eighth dummy conductive portion 13H15 is connected to the upper end of the fifth dummy conductive portion 13E5, and the right end of the eighth dummy conductive portion 13H15 is connected to the upper end of the fifth dummy conductive portion 13E6. The first dummy conductive portion 13A3 is located between the fifth and fifth dummy conductive portions 13E5 and 13E6, and the upper end of the first dummy conductive portion 13A3 is spaced apart from the eighth dummy conductive portion 13H15.

[0473] First dummy conductive portion 13A4, fifth dummy conductive portion 13E7, fifth dummy conductive portion 13E8, and eighth dummy conductive portion 13H16 are located between the adjacent second connecting sub-segment B02 on the right side. Fifth dummy conductive portion 13E7 is located to the right of fifth dummy conductive portion 13E8, and eighth dummy conductive portion 13H16 is located between fifth dummy conductive portion 13E7 and fifth dummy conductive portion 13E8. The left end of eighth dummy conductive portion 13H16 is connected to the lower end of fifth dummy conductive portion 13E7, and the right end of eighth dummy conductive portion 13H16 is connected to the lower end of fifth dummy conductive portion 13E8. First dummy conductive portion 13A4 is located between fifth dummy conductive portion 13E7 and fifth dummy conductive portion 13E8, with the lower end of first dummy conductive portion 13A4 spaced apart from the eighth dummy conductive portion.

[0474] Three seventh dummy conductive portions 13G are located to the left of sixth dummy conductive portion 13F on the left. The right end of seventh dummy conductive portion 13G1 is connected to the lower end of fifth dummy conductive portion 13E3, the right end of seventh dummy conductive portion 13G2 is connected to sixth dummy conductive portion 13F on the left, and the right end of seventh dummy conductive portion 13G3 is connected to the upper end of fifth dummy conductive portion 13E7. Sixth dummy conductive portion 13F on the left extends in the same direction as first dummy conductive portion 13A2 and is connected to the upper end of first dummy conductive portion 13A4. The upper end of sixth dummy conductive portion 13F on the left is connected to the lower end of first dummy conductive portion 13A2, and the lower end of sixth dummy conductive portion 13F on the left is connected to the upper end of first dummy conductive portion 13A4. The extension direction of sixth dummy conductive portion 13F on the right side is consistent with the extension direction of fifth dummy conductive portion 13E4 and the extension direction of fifth dummy conductive portion 13E8. The upper end of sixth dummy conductive portion 13F on the right side is connected to the lower end of fifth dummy conductive portion 13E4, and the lower end of sixth dummy conductive portion 13F on the right side is connected to the upper end of fifth dummy conductive portion 13E8.

[0475] In the case where a pad unit 14 includes nine device pad groups 141, the accompanying plating of two adjacent connecting wires 15 located immediately above and below the driver chip IC will be described.

[0476] In the seventh embodiment, as shown in FIG. 48 , the first dummy conductive portion 13A, the fifth dummy conductive portion 13E, the eighth dummy conductive portion 13H, the tenth dummy conductive portion 13J, and the eleventh dummy conductive portion 13K are provided simultaneously.

[0477] There are four first dummy conductive portions 13A, eight fifth dummy conductive portions 13E, fourteen eighth dummy conductive portions 13H, three tenth dummy conductive portions 13J, and two eleventh dummy conductive portions 13K.

[0478] The fifth dummy conductive portion 13E is aligned with the first connecting sub-segment B01. The eighth dummy conductive portion 13H is a line segment extending along the first direction. The tenth dummy conductive portion 13J is a line segment extending along the first direction. The eleventh dummy conductive portion 13K is aligned with the first connecting sub-segment B01.

[0479] For a connection line 15 on the upper side of the driver chip IC, the right end of the eighth dummy conductive portion 13H on the left is connected to the upper end of the eleventh dummy conductive portion 13K on the left. The lower end of the eleventh dummy conductive portion 13K is connected to the left end of the tenth dummy conductive portion 13J1. From left to right along the first direction X, the lower end of the first fifth dummy conductive portion 13E is connected to the left end of the eighth dummy conductive portion 13H3, the lower end of the second fifth dummy conductive portion 13E is connected to the right end of the eighth dummy conductive portion 13H3, the upper end of the third fifth dummy conductive portion 13E is connected to the left end of the eighth dummy conductive portion 13H4, and the lower end of the third fifth dummy conductive portion 13E is connected to the right end of the tenth dummy conductive portion 13J1. The upper end of the fourth fifth dummy conductive portion 13E is connected to the right end of the eighth dummy conductive portion 13H4. The lower end of the first dummy conductive portion 13A on the right side extends to intersect with the tenth dummy conductive portion 13J2 .

[0480] For a connection line 15 on the bottom side of the driver chip IC, the right end of the eighth dummy conductive portion 13H on the left is connected to the lower end of the eleventh dummy conductive portion 13K on the left. The upper end of the eleventh dummy conductive portion 13K on the left is connected to the left end of the tenth dummy conductive portion 13J2. From left to right along the first direction, the upper end of the first fifth dummy conductive portion 13E is connected to the eighth dummy conductive portion 13H7, and the right end of the eighth dummy conductive portion 13H7 is connected to the upper end of the second fifth dummy conductive portion 13E. The upper end of the third fifth dummy conductive portion 13E is connected to the right end of the tenth dummy conductive portion 13J2, and the lower end of the third fifth dummy conductive portion 13E is connected to the left end of the eighth dummy conductive portion 13H12. The lower end of the fourth fifth dummy conductive portion 13E is connected to the right end of the eighth dummy conductive portion 13H12. The upper end of the first dummy conductive portion 13A on the right side extends to intersect with the tenth dummy conductive portion 13J2 .

[0481] The connection of the fourth fifth dummy conductive portion 13E above the driver chip IC is connected to the upper end of the fourth fifth dummy conductive portion 13E below the driver chip IC.

[0482] To verify the thickness uniformity of different points on different second connecting lines 152 after different dummy conductive portions 131 are provided, the following study examines the thickness uniformity of the twelve connecting sub-segments 152A, four second connecting lines 152 selected from a wiring substrate 1, each of which includes three connecting sub-segments 152A. For details, please refer to the data in Tables 1 to 4 below. The plating time can be set to achieve the designed thickness of 9 μm for the connecting sub-segments 152A.

[0483] Table 1 below represents experimental data when the dummy conductive portion 131 is not provided.

[0484] Table 1

[0485] A01 to A012 in Table 1 are shown in FIG49 , respectively, and A01 to A012 represent the midpoint position of the connecting sub-segment 152A in which they are located.

[0486] According to the data in Table 1, the average thickness of the twelve positions A01 to A012 can be calculated to be 11.5 μm. On this basis, the thickness uniformity of the twelve positions A01 to A012 can be calculated to be 12.0%.

[0487] The following formula shows the calculation formula of uniformity.

[0488] Among them, Unif(t loc ) represents the uniformity value, Max(t loc ) represents the maximum thickness, Min(t loc ) represents the minimum thickness, t avg Represents the average thickness.

[0489] The following Table 2 represents experimental data when the dummy conductive portion 131 mentioned in the first embodiment is set as shown in FIG. 41 .

[0490] Table 2

[0491] Based on the data in Table 2, the average thickness at locations A11 to A112 is calculated to be 10.7 μm. Based on this, the thickness uniformity at locations A11 to A112 is calculated to be 7.4%. For the specific calculation formula, refer to Formula 16 above.

[0492] Table 3 below represents experimental data when the dummy conductive portion 131 mentioned in the second embodiment is provided as shown in FIG. 42 .

[0493] Table 3

[0494] Based on the data in Table 3, the average thickness at locations A21 through A212 is calculated to be 9.3 μm. Based on this, the thickness uniformity at locations A21 through A212 is calculated to be 10.8%. For the specific calculation formula, refer to Formula 16 above.

[0495] The following Table 4 represents experimental data when the dummy conductive portion 131 mentioned in the third embodiment is set as shown in FIG. 43 .

[0496] Table 4

[0497] Based on the data in Table 4, the average thickness at locations A31 to A312 is calculated to be 9.1 μm. Based on this, the thickness uniformity at locations A31 to A312 is calculated to be 8.9%. For the specific calculation formula, refer to Formula 16 above.

[0498] Combining the experimental data in Tables 1 to 4, it can be concluded that the thickness uniformity values ​​corresponding to Table 2 are smaller than those corresponding to Table 4, which are smaller than those corresponding to Table 3, and which are smaller than those corresponding to Table 1. Therefore, the embodiment corresponding to Table 2 is the most effective in improving thickness uniformity, i.e., the first embodiment. However, since the average thickness value in Table 2 is 10.7 μm, which is significantly different from the theoretical thickness value of 9 μm, it consumes more copper material and is more expensive. In contrast, the thickness uniformity values ​​and average thickness values ​​corresponding to Table 4 are not only smaller, but the average thickness value of 9.1 μm is also close to the theoretical thickness value of 9 μm. Therefore, the embodiment corresponding to Table 4 achieves the best plating effect.

[0499] In addition, by adopting the accompanying plating solution in the third embodiment, the proportion of the metal pattern to be plated on the first surface S can be controlled to be less than 30%, thereby saving materials and reducing production costs.

[0500] It is understandable that after the signal line 12 extends from the functional area 1a to the binding area 1c, it needs to be bound to the binding pin 18 in the binding area 1c to achieve normal signal transmission.

[0501] Specifically, in some embodiments, as shown in Figure 49, the wiring substrate 1 in the present disclosure also includes a plurality of binding pins 18, which are arranged on the first surface S and located in the binding area 1c. The signal line 12 extends to one end within the binding area 1c and is connected to the binding pin 18 to ensure smooth transmission of the signal line 12.

[0502] In some embodiments, as shown in FIG. 49 , the wiring substrate 1 provided by the present disclosure further includes a ring-shaped electrostatic release line 12D, which is disposed on the first surface S and surrounds the functional area 1 a.

[0503] The electrostatic discharge line 12D includes a first electrostatic discharge sub-segment 12D1, a second electrostatic discharge sub-segment 12D2, and a third electrostatic discharge sub-segment 12D3, which are electrically connected in sequence. The first electrostatic discharge sub-segment 12D1 and the third electrostatic discharge sub-segment 12D3 are located on opposite sides of the functional area 1a along the first direction X, and the second electrostatic discharge sub-segment 12D2 is located on the side of the functional area 1a away from the binding area 1c. The end of the first electrostatic discharge sub-segment 12D1 away from the second electrostatic discharge sub-segment 12D2 extends into the binding area 1c and is electrically connected to the binding pin 18. The end of the third electrostatic discharge sub-segment 12D3 away from the second electrostatic discharge sub-segment 12D2 extends into the binding area 1c and should be electrically connected to the binding pin 18.

[0504] Through the setting of the annular electrostatic release line 12D, the annular electrostatic release line 12D can conduct the static electricity in the functional area 1a to the pins in the binding area 1c, thereby avoiding the accumulation of static electricity in the functional area 1a, and avoiding the damage to the light-emitting device 2 or the driver chip IC after the static electricity accumulates to a certain level, so as to ensure the normal operation of the light-emitting device 2 and improve the preparation yield of the wiring substrate 1.

[0505] For example, as shown in Figure 49, the first electrostatic discharge sub-segment 12D1 includes a first vertical sub-segment 12D11, a first horizontal sub-segment 12D12, and a second vertical sub-segment 12D13, which are connected in sequence. The first vertical sub-segment 12D11 and the second vertical sub-segment 12D13 extend along the second direction, while the first horizontal sub-segment 12D12 extends along the first direction. The upper end of the first vertical sub-segment 12D11 is connected to the left end of the second electrostatic discharge sub-segment 12D2. The end of the first horizontal sub-segment 12D12, which is away from the first horizontal sub-segment 12D12, extends into the binding area 1c and is connected to the binding pin 18.

[0506] For example, as shown in Figure 49, the third ESD sub-segment 12D3 includes a third vertical sub-segment 12D31, a second horizontal sub-segment 12D32, and a fourth vertical sub-segment 12D33, which are sequentially connected. The third vertical sub-segment 12D31 and the fourth vertical sub-segment 12D33 extend along the second direction, while the second horizontal sub-segment 12D32 extends along the first direction. The upper end of the third vertical sub-segment 12D31 is connected to the right end of the second ESD sub-segment 12D2, and the lower end of the fourth vertical sub-segment 12D33 extends into the binding area 1c and is connected to the binding pin 18.

[0507] In some examples, as shown in FIG. 49 , the peripheral region 1b includes a first peripheral region 1b1 , the first peripheral region 1b1 includes at least one binding region 1c and at least one blank region, and the at least one binding region 1c and the at least one blank region are arranged sequentially along the first direction X or the second direction Y.

[0508] The number of blank areas can be one or more. For example, as shown in FIG49 , the first peripheral area 1b1 includes a binding area 1c and two blank areas located on both sides of the binding area 1c. The two blank areas are a first blank area 1d1 and a second blank area 1d2.

[0509] Along the first direction X, the first blank area 1d1, the binding area 1c, and the second blank area 1d2 are arranged in sequence. The first and second blank areas 1d1, 1d2 are of similar size in the first direction, and the binding pins 18 are located within the binding area 1c. This ensures symmetry in the connections of the signal lines 12 on either side of the binding area 1c, facilitating signal transmission.

[0510] During actual production, the binding pins 18 are also electroplated together with the signal lines 12. Since the binding pins 18 are primarily concentrated in the binding area 1c, with a first blank area 1d1 and a second blank area 1d2 on either side of the binding area 1c, the current density on the plated binding pins 18 is relatively high during the electroplating process, resulting in a relatively high electroplating thickness per unit time. This can affect the uniformity of the thickness of the multiple binding pins 18, as well as the uniformity of the thickness between the multiple binding pins 18 and the connecting lines 15 and signal lines 12 in the functional area 1a.

[0511] Based on this, in some embodiments, as shown in FIG50 , a portion of the dummy conductive pattern 13 is disposed in the first blank area 1d1. This allows the dummy conductive pattern 13 to be formed simultaneously with the electroplating process to form the binding pins 18. This increases the proportion of metal patterns to be plated per unit area within the first peripheral area 1b1, resulting in similar current densities and electroplating efficiencies across the plurality of binding pins 18 to be plated, ultimately resulting in similar thicknesses across all binding pins 18, thereby improving thickness uniformity across the binding pins 18.

[0512] In some embodiments, as shown in FIG50 , a portion of the dummy conductive pattern 13 is disposed in the second blank area 1d2 . This allows the dummy conductive pattern 13 to be formed simultaneously with the electroplating process to form the binding pins 18 . This increases the proportion of metal patterns to be plated per unit area within the first peripheral region 1b1 , resulting in similar current densities and electroplating efficiencies across the plurality of binding pins 18 to be plated, ultimately resulting in similar thicknesses across all binding pins 18 , thereby improving thickness uniformity across the binding pins 18 .

[0513] In some embodiments, as shown in FIG50 , dummy conductive patterns 13 are provided in both the first blank area 1d1 and the second blank area 1d2. Thus, during the electroplating process to form the binding pins 18, the dummy conductive patterns 13 are simultaneously formed, thereby increasing the proportion of metal patterns to be plated per unit area within the first peripheral area 1b1, making the current density on the multiple binding pins 18 to be plated similar, and the electroplating efficiency similar, ultimately making the thickness of all the binding pins 18 similar, thereby improving the thickness uniformity among the binding pins 18.

[0514] In addition, for the first blank area 1d1, setting a dummy conductive pattern 13 can increase the proportion of the metal pattern to be plated per unit area, reduce the edge effect caused by the existence of the first blank area 1d1, and reduce the plating rate of the first horizontal sub-segment 12D12 during the electroplating process, increase the thickness difference between the first horizontal sub-segment 12D12 and other signal lines 12, connecting lines 15, and binding pins 18 around it, so as to improve uniformity.

[0515] For the second blank area 1d2, setting a dummy conductive pattern 13 can increase the proportion of the metal pattern to be plated per unit area, reduce the edge effect caused by the existence of the second blank area 1d2, and reduce the plating rate of the second horizontal sub-segment 12D32 during the electroplating process, increase the thickness difference between the second horizontal sub-segment 12D32 and other signal lines 12, connecting lines 15, and binding pins 18 around it, so as to improve uniformity.

[0516] In some examples, the dummy conductive pattern 13 located in the first blank area 1 d 1 includes a plurality of first dummy pins 132 . The first dummy pins 132 extend along the second direction Y, and the plurality of first dummy pins 132 are arranged at intervals along the first direction X.

[0517] Exemplarily, the width of the first binding pin 18 , that is, the dimension along the first direction X, may range from 5 mm to 7 mm. For example, the width of the first binding pin 18 is 5.0 mm, 5.3 mm, 5.6 mm, 6.0 mm, 6.2 mm or 7 mm.

[0518] Illustratively, in the second direction Y, the distance between the upper end of the first dummy pin 132 and the first horizontal sub-segment 12D12 ranges from 0.2 mm to 0.3 mm. For example, the distance between the upper end of the first dummy pin 132 and the first horizontal sub-segment 12D12 is 0.2 mm, 0.22 mm, 0.24 mm, 0.26 mm, or 0.30 mm.

[0519] In some examples, the dummy conductive pattern 13 located in the second blank area 1 d 2 includes a plurality of second dummy pins 133 . The second dummy pins 133 extend along the second direction Y, and the plurality of second dummy pins 133 are arranged at intervals along the first direction X.

[0520] Illustratively, the distance between the upper end of the second dummy pin 133 and the second horizontal sub-segment 12D32 is in the range of 0.2 to 0.3 mm along the second direction Y. For example, the distance between the upper end of the second dummy pin 133 and the second horizontal sub-segment 12D32 is 0.2 mm, 0.23 mm, 0.25 mm, 0.28 mm, or 0.30 mm.

[0521] In some embodiments, the wiring substrate 1 further includes a plurality of alignment patterns 19 .

[0522] In some examples, to ensure the accuracy of the placement of the binding pins 18, a binding alignment pattern 19 may be provided in the first peripheral region 1b1, as shown in FIG51. For example, the binding alignment pattern 19 may be in the shape of a cross to facilitate positioning of the binding pins 18 for electroplating.

[0523] In some examples, as shown in FIG. 51 , part of the bonding alignment pattern 19 is disposed in the first blank area 1 d 1 and the second blank area 1 d 2 , so as to avoid interference of the bonding alignment pattern with the bonding pins 18 .

[0524] When the dummy conductive pattern 13 is provided in both the first blank area 1d1 and the second blank area 1d2, some of the binding alignment patterns 19 are staggered with the dummy conductive pattern 13, thereby avoiding interference between the setting position of the dummy conductive pattern 13 and the setting position of the binding alignment pattern.

[0525] 51 , a first clearance area 1d11 is provided in the first blank area 1d1. The bonding alignment pattern 19 is provided in the first clearance area 1d11, and the dummy conductive pattern 13 is provided outside the first clearance area 1d11.

[0526] Exemplarily, the first clearance area 1d11 may be rectangular, and the binding alignment pattern is disposed at the center of the square first clearance area 1d11.

[0527] Exemplarily, the distance between the outline of the first clearance area 1d11 and the nearest edge of the binding alignment pattern is about 0.5 mm.

[0528] In some embodiments, as shown in FIG52 and FIG53 , in order to better improve the thickness uniformity of the connecting wires 15 and the signal wires 12 on the wiring substrate 1 , the positions of some of the signal wires 12 and the connecting wires 15 are adjusted.

[0529] For example, as shown in FIG52 , in the related art, in the second direction, the distance between the second connecting sub-segment B02 farthest from the first peripheral area 1b1 and the second electrostatic release sub-segment 12D2 is relatively large, which will cause a large blank area between the feedback signal line FB and the second electrostatic release sub-segment 12D2, thereby affecting the thickness uniformity between the signal line 12 and the connecting line 15 as a whole.

[0530] Based on the above problems, as shown in Figure 53, the present disclosure adjusts the positions of the feedback signal line FB and the ground signal line GND. In the second direction, the end of the ground signal line GND away from the first peripheral area 1b1 is flush with the connecting line 15 away from the first peripheral area 1b1 among the multiple connecting lines 15.

[0531] For example, in the second direction, the ground signal line GND and the feedback signal line FB extend away from the first peripheral area 1b1, such that the upper end of the ground signal line GND is flush with the second connecting sub-segment B02, and the feedback signal line FB is partially located between the ground signal line GND and the second electrostatic discharge sub-segment 12D2. This fills the blank area between the ground signal line GND and the second electrostatic discharge sub-segment 12D2, increasing the proportion of the metal pattern to be plated per unit area in the blank area and improving the overall thickness uniformity of the connecting line 15 and the signal line 12.

[0532] In some embodiments, as shown in FIG53 , the distance between the second electrostatic discharge sub-segment 12D2 and the connecting line 15 ranges from 0.2 mm to 0.5 mm. For example, the distance between the second electrostatic discharge sub-segment 12D2 and the connecting line 15 can be 0.2 mm, 0.25 mm, 0.3 mm, 0.4 mm, or 0.5 mm.

[0533] For example, the second electrostatic release sub-segment 12D2 may be moved downward in the second direction Y so that the distance between the second electrostatic release sub-segment 12D2 and the uppermost second connecting sub-segment B02 is maintained between 0.2 mm and 0.5 mm.

[0534] Within this range, the distance between the second ESD sub-segment 12D2 and the connecting line 15 can be prevented from being too small, reducing the risk of electrostatic discharge (ESD) between the two and ensuring the normal operation of the connecting line 15. Furthermore, by ensuring that the distance between the second ESD sub-segment 12D2 and the connecting line 15 is within a certain range, the second ESD sub-segment 12D2 can also play a certain role in accompanying plating, thereby improving the thickness uniformity between the connecting line 15 and the signal line 12.

[0535] To verify that the provision of dummy conductive patterns 13 improves the uniformity of the thickness of signal lines 12, connecting lines 15, and binding pins 18, the following study examines the provision of dummy conductive patterns 13 from two perspectives during the initial design phase, assuming that signal lines 12 and connecting lines 15 are located on the same conductive layer.

[0536] First, as shown in Figures 54A to 54N, the dummy conductive pattern 13 includes a dummy conductive portion 131, and the influence of the distance between the dummy conductive portion 131 and the signal line 12 or the connecting line 15 or the binding pin 18 on the uniformity of the signal line 12 or the connecting line 15 is explored.

[0537] The width of the dummy conductive portion 131 was set to 3 μm, and the theoretical thickness of the dummy conductive portion 131 and the conductor to be plated (at least one of the signal line 12, the connecting line 15, and the binding pin 18) was set to 5 μm. The following study investigated the uniformity of the distance between the dummy conductive portion 131 and the conductor to be plated across different conductors.

[0538] It can be understood that the width of the dummy conductive portion 131 refers to a dimension perpendicular to the extension direction of the dummy conductive portion 131 .

[0539] As shown in Figures 54A, 54C, and 54N, the abscissa in each figure represents the dimension of substrate 11 along the first direction X, and the ordinate represents the dimension of substrate 11 along the second direction Y. Each rectangle in the figure represents an area, each of which contains a conductor to be plated. Dummy conductive portions 131 are provided in the blank areas at both ends of the conductors to be plated. Each figure shows five thickness distribution areas spaced apart along the first direction X. A film thickness meter is used to measure the conductors to be plated within each thickness distribution area to determine their respective thicknesses, ultimately yielding a thickness distribution.

[0540] In addition, FIG54B shows a commonly used electroplating equipment model, and FIG54B shows the flow and distribution of metal ions (such as copper ions) in the electrolyte solution during the electroplating process. The electroplating equipment 100 includes an anode 110, and the substrate 1' to be plated is placed in a receiving tank 120 of the electroplating equipment 100 and is arranged relative to the anode 110. The negative output terminal of the power supply is electrically connected to the seed layer on the substrate 1' to be plated, and the anode 110 is connected to the positive output terminal of the power supply, thereby forming an electric field between the anode 110 and the substrate 1' to be plated, and the electric field line distribution is directed from the anode 110 to the substrate 1' to be plated.

[0541] As shown in Figure 54B, the electric field lines in the middle area are distributed relatively sparsely, and the electric field lines on the edge side are distributed denser than those in the middle. Therefore, as the electroplating proceeds, the wires to be plated (for example, at least one of the signal line 12, the connecting line 15, and the binding pin 18) at the edge where the electric field lines are densely distributed are plated thicker, while the wires to be plated (for example, at least one of the signal line 12, the connecting line 15, and the binding pin 18) at the middle where the electric field lines are sparsely distributed are plated thinner, resulting in the problem of poor electroplating uniformity.

[0542] 54A represents the thickness distribution of the conductor to be plated in the five thickness distribution areas when the dummy conductive portion 131 is not provided.

[0543] Figures 54C and 54D are a set of comparative experiments. Figure 54C shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 54D shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the distance between the dummy conductive portion 131 and the conductor to be plated is 0.5 mm.

[0544] Figures 54E and 54F are a set of comparative experiments. Figure 54E shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 54F shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the distance between the dummy conductive portion 131 and the conductor to be plated is 1 mm.

[0545] Figures 54G and 54H are a set of comparative experiments. Figure 54G shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 54H shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the distance between the dummy conductive portion 131 and the conductor to be plated is 1.5 mm.

[0546] Figures 54I and 54J are a set of comparative experiments. Figure 54I shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 54J shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the distance between the dummy conductive portion 131 and the conductor to be plated is 2 mm.

[0547] Figures 54K and 54L are a set of comparative experiments. Figure 54K shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 54L shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the distance between the dummy conductive portion 131 and the conductor to be plated is 2.5 mm.

[0548] Figures 54M and 54N are a set of comparative experiments. Figure 54M shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 54N shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the distance between the dummy conductive portion 131 and the conductor to be plated is 3 mm.

[0549] Combining the thickness distribution of the conductors to be plated in Figures 54A and 54C to 54N above, and taking values ​​for calculation, the data in Table 5 below can be obtained.

[0550] Table 5

[0551] Combining the data in Table 5 above, a line graph is produced, as shown in Figure 55. The graph shows that as the distance between the conductor to be plated and the dummy conductive portion 131 decreases, the thickness uniformity of the conductor to be plated gradually improves. When the distance between the dummy conductive portion 131 and the conductor to be plated is 0.5 μm, the conductor thickness uniformity is optimal.

[0552] Secondly, as shown in Figures 56A to 56N, the dummy conductive pattern 13 includes a dummy conductive portion 131, and the influence of the width change of the dummy conductive portion 131 itself on the uniformity of the signal line 12 or the connecting line 15 is explored.

[0553] The distance between the conductor to be plated and the dummy conductive portion 131 is set to 0.5 mm. The theoretical thickness of the dummy conductive portion 131 and the conductor to be plated (at least one of the signal line 12, the connecting wire 15, and the binding pin 18) to be plated is 5 μm. The following study investigates the effect of varying the width of the dummy conductive portion 131 on the uniformity of the plated conductors.

[0554] As shown in Figures 56A, 56C, and 56N, the abscissa in each figure represents the dimension of substrate 11 along the first direction, and the ordinate represents the dimension of substrate 11 along the second direction. Each rectangle in the figure represents an area, and each area contains a conductor to be plated. Dummy conductive portions 131 are provided in the blank areas at both ends of the conductors to be plated. Each figure shows five thickness distribution areas spaced apart along the first direction. A film thickness meter is used to measure the conductors to be plated within each thickness distribution area to determine their respective thicknesses, ultimately yielding a thickness distribution.

[0555] In addition, a commonly used electroplating equipment model is shown in Figure 56B, and Figure 56B shows the flow and distribution of metal ions (such as copper ions) in the electrolyte solution during the electroplating process. The electroplating equipment 100 includes an anode 110, and the substrate 1' to be plated is placed in a receiving tank 120 of the electroplating equipment 100 and is arranged relative to the anode 110. The negative output terminal of the power supply is electrically connected to the seed layer on the substrate 1' to be plated, and the anode 110 is connected to the positive output terminal of the power supply, thereby forming an electric field between the anode 110 and the substrate 1' to be plated, and the electric field line distribution is directed from the anode 110 to the substrate 1' to be plated.

[0556] 56A represents the thickness distribution of the conductor to be plated in the five thickness distribution areas when the dummy conductive portion 131 is not provided.

[0557] Figures 56C and 56D are a set of comparative experiments. Figure 56C shows the thickness distribution of the conductor to be plated in the five thickness distribution areas when the dummy conductive portion 131 is not provided. Figure 56D shows the thickness distribution of the conductor to be plated in the five thickness distribution areas when the width of the dummy conductive portion 131 itself is 0.5 mm.

[0558] Figures 56E and 56F are a set of comparative experiments. Figure 56E shows the thickness distribution of the conductor to be plated in the five thickness distribution areas when the dummy conductive portion 131 is not provided. Figure 56F shows the thickness distribution of the conductor to be plated in the five thickness distribution areas when the width of the dummy conductive portion 131 itself is 1 mm.

[0559] Figures 56G and 56H are a set of comparative experiments. Figure 56G shows the thickness distribution of the conductor to be plated in the five thickness distribution areas when the dummy conductive portion 131 is not provided. Figure 56H shows the thickness distribution of the conductor to be plated in the five thickness distribution areas when the width of the dummy conductive portion 131 itself is 2 mm.

[0560] Figures 56I and 56J are a set of comparative experiments. Figure 56I shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 56J shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the width of the dummy conductive portion 131 itself is 4 mm.

[0561] Figures 56K and 56L are a set of comparative experiments. Figure 56K shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when no dummy conductive portion 131 is provided. Figure 56L shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the width of the dummy conductive portion 131 itself is 6 mm.

[0562] Figures 56M and 56N are a set of comparative experiments. Figure 56M shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the dummy conductive portion 131 is not provided. Figure 56N shows the thickness distribution of the conductor to be plated within the five thickness distribution zones when the width of the dummy conductive portion 131 itself is 8 mm.

[0563] Combining the thickness distribution of the conductors to be plated in Figures 56A and 56C to 56N above, and performing calculations based on the values, the data in Table 6 below can be obtained.

[0564] Table 6

[0565] Combining the data in Table 6 above, we can produce the line graph shown in Figure 57. The graph shows that as the width of the conductor to be plated gradually increases, the thickness uniformity of the conductor to be plated gradually improves. When the width of the dummy conductive portion 131 is 4 μm, the thickness uniformity of the conductor to be plated is optimal.

[0566] On the other hand, the present disclosure also provides a method for preparing a wiring substrate 1 , as shown in FIG58 , the method includes S100 to S200 .

[0567] S100: As shown in FIG59A, a substrate 11 having a first surface S is provided.

[0568] For example, the substrate 11 may be made of glass materials such as soda-lime glass, quartz glass, and sapphire glass, or may be made of metal materials such as stainless steel, aluminum, and nickel.

[0569] S200: As shown in FIG59B , a plurality of signal lines 12 and a plurality of dummy conductive patterns 13 are simultaneously formed on the first surface S using the same patterning process; the plurality of signal lines 12 are spaced apart along a first direction X and extend along a second direction Y; the first direction X and the second direction Y intersect; a dummy conductive pattern 13 is provided between two adjacent signal lines 12, and the dummy conductive pattern 13 is insulated from the two adjacent signal lines 12.

[0570] In some examples, the angle between the first direction and the second direction may be 85°, 90°, or 95°.

[0571] Through the above-mentioned arrangement, in the process of forming the signal line 12 by the electroplating process, the dummy conductive pattern 13 is simultaneously formed. When the bottom areas of two adjacent signal lines 12 to be plated are different (that is, when the wiring environments of the two signal lines 12 to be plated are different), by reasonably setting the positions of the dummy conductive patterns 13 to be plated and the number of the dummy conductive patterns 13 to be plated, the bottom area ratios of the metal patterns to be plated (including the signal line 12, the dummy conductive pattern 13 and the connecting line 15) in the respective areas of the two signal lines 12 to be plated are close, thereby making the current density on the two adjacent signal lines 12 to be plated close, the electroplating efficiency close, and finally making the thickness between the two adjacent signal lines 12 close, so as to improve the thickness uniformity between the two adjacent signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0572] In other embodiments, as shown in FIG. 60 , the present disclosure further provides a method for preparing a wiring substrate 1 , which includes steps a100 to a200 .

[0573] a100: providing a substrate 11 having a first surface S.

[0574] For example, the substrate 11 may be made of glass materials such as soda-lime glass, quartz glass, and sapphire glass, or may be made of metal materials such as stainless steel, aluminum, and nickel.

[0575] a200: Using the same patterning process, multiple signal lines 12 and multiple dummy conductive patterns 13 are simultaneously formed on the first surface S; the multiple signal lines 12 are arranged in a first direction X and extend in a second direction Y; the first direction X and the second direction Y intersect; at least a portion of the plated dummy conductive patterns 13 are located in the peripheral area 1b, and the dummy conductive patterns 13 are insulated from two adjacent signal lines 12.

[0576] Through the above-mentioned arrangement, in the process of forming the signal line 12 by the electroplating process, a dummy conductive pattern 13 is simultaneously formed in the peripheral area 1b, thereby increasing the bottom area ratio of the metal wire in the area jointly constituted by the peripheral area 1b and the position of the signal line 12 (for example, the first signal line VLED) near the peripheral area 1b, so that the bottom area ratio of the metal pattern to be plated (including the signal line 12, the dummy conductive pattern 13 and the connecting line 15) of the signal line 12 near the peripheral area 1b and other signal lines 12 in their respective areas is close, reducing the difference in wiring environment between the signal line 12 near the peripheral area 1b and other signal lines 12, thereby making the current density on the signal line 12 near the peripheral area 1b and other signal lines 12 close, and the electroplating efficiency close, so that the thickness between the signal line 12 near the peripheral area 1b and other signal lines 12 is finally close, so as to improve the thickness uniformity between two adjacent signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0577] In some embodiments, S200 : using the same patterning process to simultaneously form a plurality of signal lines 12 and a plurality of dummy conductive patterns 13 on the first surface S, including S210 to S230 .

[0578] S210: As shown in FIG60 and FIG61 , a seed layer 16 is formed on the first surface S;

[0579] In some examples, the seed layer 16 includes a molybdenum-niobium layer and a seed copper layer, wherein the molybdenum-niobium layer is located between the seed copper layer and the substrate. The molybdenum-niobium layer and the seed copper layer are sequentially formed on the first surface S.

[0580] The thickness of the molybdenum-niobium layer is about 300 angstroms, and the thickness of the seed copper layer ranges from 0.3 μm to 1.0 μm. For example, the thickness of the seed copper layer can be 0.3 μm, 0.35 μm, 0.4 μm, 0.5 μm or 1.0 μm.

[0581] For example, the molybdenum-niobium layer and the seed copper layer may be sequentially formed on the substrate by a sputtering process.

[0582] In some examples, the step of forming the seed layer 16 on the first surface S includes S211 - S212 .

[0583] S211: As shown in FIG62A , a buffer layer 20 is formed on the first surface S.

[0584] For example, before forming the buffer layer 20 on the first surface S, the substrate 11 may be cleaned to remove impurities such as dust on the substrate 11 to ensure the smoothness of the subsequent buffer layer 20 .

[0585] Illustratively, the thickness of the buffer layer 20 ranges from 1200 angstroms to 4000 angstroms. For example, the thickness of the buffer layer 20 may be 1200 angstroms, 1400 angstroms, 2000 angstroms, 2500 angstroms, or 4000 angstroms.

[0586] S212 : As shown in FIG. 62B , a seed layer 16 is formed on the buffer layer 20 .

[0587] The buffer layer 20 has a buffering effect. When the substrate 11 is impacted, the buffer layer 20 can absorb the impact force, thereby protecting the seed layer 16 from damage.

[0588] S220: As shown in Figures 60 and 63, a photoresist layer 17 is formed on the seed layer 16, and the photoresist layer adopts negative photoresist; the photoresist layer 17 has a plurality of first openings 171 and a plurality of second openings 172, the first openings 171 correspond to the signal lines 12 to be formed, and the second openings 172 correspond to the dummy conductive patterns 13 to be formed.

[0589] In some examples, a photoresist may be coated on the seed layer 16 through a coating process to form a photoresist layer 17. To help the photoresist cure, the photoresist may be baked through a baking process after coating.

[0590] The thickness of the photoresist layer 17 may be greater than or equal to 7 μm. For example, the thickness of the photoresist layer 17 may be 7 μm, 8 μm, 9 μm, etc. The specific thickness is determined according to the thickness of the signal line 12 and the dummy conductive pattern 13 .

[0591] In some examples, after forming the photoresist layer 17 on the seed layer 16 , the photoresist layer 17 is patterned by performing exposure and development processes on the photoresist layer 17 to form a plurality of first openings 171 and a plurality of second openings 172 on the photoresist layer 17 .

[0592] For example, the photoresist can be a negative photoresist. Thus, after exposing and developing the photoresist layer 17, multiple photoresist layers with inverted trapezoidal cross-sections are formed. Thus, after electroplating, the formed connecting wires 15, signal wires 12, and dummy conductive patterns 13 have a positive trapezoidal cross-section. Subsequently, after etching the seed layer 16, the formed signal wires 12 and dummy conductive patterns 13 will not have the gap R shown in FIG. 78 , thereby ensuring the service life of the connecting wires 15 and signal wires 12.

[0593] S230: As shown in Figures 60 and 64, an electroplating process is used to form a signal line 12 in the first opening 171, and simultaneously form a dummy conductive pattern 13 in the second opening 172. In some examples, S230 specifically includes steps S231 to S233.

[0594] S231 : As shown in FIG. 65A , a routing sub-pattern 12Z is ​​formed in the first opening 171 by using an electroplating process, and a dummy conductive sub-pattern 13Z is simultaneously formed in the second opening 172 .

[0595] S232: As shown in FIG65B , the photoresist is stripped off to expose a portion of the seed layer 16 at a position corresponding to the stripped photoresist.

[0596] S233: As shown in FIG65C , the exposed portion of the seed layer 16 is etched so that the routing sub-pattern 12Z and the portion of the seed layer 16 thereunder form the signal line 12, and the dummy conductive sub-pattern 13Z and the portion of the seed layer 16 thereunder form the dummy conductive pattern 13.

[0597] For example, when etching the exposed portion of the seed layer 16, the etching time needs to be controlled. Generally, the etching time needs to be appropriately increased, and the actual etching time is 30% to 50% longer than the theoretical etching time. This can achieve over-etching of the seed layer 16 to completely remove the portion of the seed layer 16 that needs to be removed, thereby avoiding short circuits between multiple signal lines 12.

[0598] For example, when the thickness of the molybdenum-niobium layer is 300 angstroms and the thickness of the third copper layer is 0.3 μm, etching generally takes about 60 seconds.

[0599] Through the process flow of S210 to S230 above, in the process of forming the signal line 12 by the electroplating process, a dummy conductive pattern 13 is simultaneously formed. When the bottom areas of two adjacent signal lines 12 to be plated are different (that is, when the wiring environments of the two signal lines 12 to be plated are different), by reasonably setting the positions of the dummy conductive patterns 13 to be plated and the number of the dummy conductive patterns 13 to be plated, the bottom area ratios of the metal patterns to be plated (including the signal line 12, the dummy conductive patterns 13 and the connecting lines 15) of the two signal lines 12 to be plated in their respective areas are close to each other, thereby making the current density on the two adjacent signal lines 12 to be plated close to each other, and the electroplating efficiency close to each other, so as to finally make the thickness between the two adjacent signal lines 12 close to each other, so as to improve the thickness uniformity between the two adjacent signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0600] In actual production, multiple wiring substrates 1 are produced in the same batch. For example, as shown in FIG66 , a motherboard substrate 002 is divided into multiple processing areas 003, which are arranged in an array. Within each processing area 003 are multiple signal lines 12, multiple dummy conductive patterns 13, multiple pad units 14, and multiple connecting lines 15. The motherboard substrate 002 is then cut to separate each processing area 003 from the motherboard substrate 002, thereby independently forming multiple wiring substrates 1. This ensures efficient production.

[0601] In some examples, as shown in FIG. 66 , six processing regions 003 are divided on one motherboard substrate 002 , and the six processing regions 003 are arranged in three rows and two columns.

[0602] In other examples, as shown in FIG67 , twenty-four processing areas 003 may be divided on a motherboard substrate 002 , and the twenty-four processing areas 003 are arranged in six rows and four columns.

[0603] On this basis, the accompanying plating situation in the intermediate process is introduced for the case where a motherboard substrate 002 has multiple processing areas 003.

[0604] In some embodiments, as shown in FIG68 , an annular process edge area U is formed along the edge of the processing area 003. A dummy conductive pattern 13 is provided in the process edge area U. The dummy conductive pattern 13 includes a plurality of dummy conductive blocks 134 spaced apart (spaced at intervals of hundreds of microns, such as no greater than 100 μm) along the circumference of the process edge area U. By providing the dummy conductive pattern 13 in the process edge area U, the dummy conductive pattern 13 can improve the problem of thicker signal lines 12 and connecting lines 15 near the process edge area U in the processing area 003, thereby improving the thickness uniformity of the connecting lines 15, signal lines 12, and binding patterns throughout the processing area 003. In addition, the dummy conductive pattern 13 located in the process edge area U is composed of a plurality of dummy conductive blocks 134. Therefore, during the electroplating process, the adhesion between the dummy conductive blocks 134 and the motherboard substrate 002 can be ensured, thereby preventing the dummy conductive blocks 134 from falling off.

[0605] Exemplarily, the width of the dummy conductive block 134 ranges from 2 mm to 5 mm. The width of the dummy conductive block 134 refers to a dimension parallel to the first surface S and perpendicular to the extending direction of the dummy conductive block 134 .

[0606] For example, the width of the dummy conductive block 134 may be 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, or 5 mm.

[0607] Exemplarily, the distance between each two adjacent dummy conductive blocks 134 ranges from 0.1 mm to 0.3 mm. For example, the distance between each two adjacent dummy conductive blocks 134 is 0.1 mm, 0.13 mm, 0.15 mm, 0.17 mm, 0.2 mm, or 0.3 mm.

[0608] Exemplarily, the length of the dummy conductive block 134 ranges from 10 mm to 20 mm. For example, the length of the dummy conductive block 134 can be 10 mm, 12 mm, 15 mm, 17 mm, or 20 mm.

[0609] The length of the dummy conductive block 134 refers to the size of the dummy conductive block 134 along the circumference of the processing area 003 .

[0610] In order to ensure the smooth completion of the intermediate process, as shown in Figure 68, a plurality of alignment patterns are provided outside the processing area 003. The alignment patterns are used to assist in completing the production of the wiring substrate 1.

[0611] Exemplarily, as shown in FIG69 , the first alignment pattern 004 is provided in the process edge area U. A plurality of first openings are provided on the dummy conductive block 134 , and the first alignment pattern 004 is provided in the first openings.

[0612] Exemplarily, the first alignment pattern 004 includes a first "cross-shaped" pattern and a first square pattern. The first opening portion is a square structure. The first "cross-shaped" pattern is arranged in one first opening portion and is located at the center position. The first square pattern is arranged in another first opening portion and is arranged at the center position of the first opening portion.

[0613] For example, the distance d between the first square pattern and the adjacent edge of the first opening may be 500 μm.

[0614] Exemplarily, as shown in FIG70 , a TP alignment pattern is shown. The TP alignment pattern 005 is disposed in the process edge area U. A plurality of second openings are disposed on the dummy conductive block 134 , and the TP alignment pattern 005 is disposed in the second openings.

[0615] Specifically, the correction alignment pattern 005 includes two second square patterns. The second opening portion is a square structure, and the two second square patterns are respectively disposed in one second opening portion.

[0616] For example, the distance d between the second square pattern and the adjacent edge of the second opening may be 500 μm.

[0617] For example, as shown in FIG. 71 , a cutting alignment pattern is shown. The cutting alignment pattern 006 is disposed in the process edge region U. A plurality of third openings are disposed on the dummy conductive block 134 , and the cutting alignment pattern 006 is disposed within the third openings.

[0618] Specifically, the cutting alignment pattern 006 includes a second "cross-shaped" pattern, the third opening portion is a square structure, and the second "cross-shaped" pattern is arranged in one of the third opening portions.

[0619] For example, the distance between the third rectangular pattern and the adjacent edge of the third opening may be 500 μm.

[0620] Exemplarily, as shown in FIG72 , there are multiple second alignment patterns 007 , at least one second alignment pattern 007 is set in the process edge area U, and there is a fourth opening portion on the dummy conductive block 134 , and the second alignment pattern 007 is set in the fourth opening portion.

[0621] For example, FIG73 shows a baffle alignment pattern 008. Multiple baffle alignment patterns 008 are provided, and are located on the side of the process edge zone U away from the processing area 003. During the electroplating process, to ensure thickness uniformity between the baffle alignment pattern 008 and the connecting wires 15 and signal wires 12, a dummy conductive pattern 13 is also provided on the side of the process edge zone U away from the processing area 003. The dummy conductive pattern 13 includes a dummy conductive block 134. Four fifth openings are defined in the dummy conductive block 134. The fifth openings are polygonal, and at least one baffle alignment pattern 008 is provided in each of the fifth openings. The dummy conductive blocks 134 provide accompanying plating for the baffle alignment pattern 008, ensuring thickness uniformity between the baffle alignment pattern 008 and the connecting wires 15 and signal wires 12 during the electroplating process.

[0622] In order to more clearly understand which factors affect the appearance of the alignment pattern during the electroplating process, the following simulation experiment is used to explore the experimental results.

[0623] As shown in Figure 74, the five "cross-shaped" patterns in the first row of the figure are openings corresponding to the alignment patterns formed after etching the photoresist layer 17. The five "cross-shaped" patterns in the second row and the five "cross-shaped" patterns in the third row are the appearances of the alignment patterns formed after electroplating. The five "cross-shaped" patterns in the fourth row, the five "cross-shaped" patterns in the fifth row, the five "cross-shaped" patterns in the sixth row, and the five "cross-shaped" patterns in the seventh row are the appearances of the alignment patterns formed after etching the seed layer 16. It can be concluded from the figure that as the width of the alignment pattern increases, the morphology of the alignment pattern becomes clearer, but there is still the problem of unclear morphology of the alignment pattern.

[0624] On this basis, a dummy conductive pattern 13 is again set around the alignment pattern, and the dummy conductive pattern 13 is used to reduce the electroplating rate of the alignment pattern and improve the morphology of the alignment pattern. As shown in Figure 75, the morphology of the electroplating pattern after the electroplating is completed. The three alignment patterns in the first row are the morphologies of the alignment pattern when the dummy conductive pattern 13 is not set. The three alignment patterns in the second row are the morphologies of the alignment pattern when the dummy conductive pattern 13 is set and the width of the dummy conductive pattern 13 is 2 mm. The three alignment patterns in the third row are the morphologies of the alignment pattern when the dummy conductive pattern 13 is set and the width of the dummy conductive pattern 13 is 5 mm. The three alignment patterns in the fourth row are the morphologies of the alignment pattern when the dummy conductive pattern 13 is set and the width of the dummy conductive pattern 13 is 8 mm.

[0625] The width of the dummy conductive pattern 13 refers to the dimension of the dummy conductive block 134 perpendicular to the extending direction thereof when the dummy conductive pattern 13 includes the dummy conductive block 134 .

[0626] On this basis, as shown in Figure 76, the morphology of the alignment pattern corresponding to Figure 75 after the seed layer 16 is etched. Figure 76 shows the morphology of the alignment pattern corresponding to Figure 75 after the seed layer 16 is etched. The three alignment patterns in the first row are the morphologies of the alignment patterns when the dummy conductive pattern 13 is not set. The three alignment patterns in the second row are the morphologies of the alignment patterns when the dummy conductive pattern 13 is set and the width of the dummy conductive pattern 13 is 2 mm. The three alignment patterns in the third row are the morphologies of the alignment patterns when the dummy conductive pattern 13 is set and the width of the dummy conductive pattern 13 is 5 mm. The three alignment patterns in the fourth row are the morphologies of the alignment patterns when the dummy conductive pattern 13 is set and the width of the dummy conductive pattern 13 is 8 mm. According to the morphology comparison in the above figures, it can be seen that as the width of the dummy conductive block 134 increases, the morphology of the alignment pattern becomes clearer.

[0627] In order to more clearly understand the actual manufacturing process of the display device 001 in the present disclosure, the actual manufacturing process of the display device 001 is described below based on the case where the connecting lines 15 and the signal lines 12 are located in the same conductive layer.

[0628] A motherboard substrate 002 is provided and cleaned to remove dust and other impurities thereon. The motherboard substrate 002 has a first surface S, on which a buffer layer 20 is disposed. A seed layer 16 is formed on the buffer layer 20 using a sputtering process. A photoresist is coated on the seed layer 16 to form a photoresist layer 17. The photoresist layer 17 is exposed to light, developed, and other processes to form a plurality of first openings 171, a plurality of second openings 172, a plurality of third openings, a plurality of first opening portions, a plurality of second opening portions, a plurality of third opening portions, a plurality of fourth opening portions, and a plurality of fifth opening portions on the photoresist layer 17. Electroplating is then performed to form routing sub-patterns 12Z within the first openings 171, dummy conductive sub-patterns within the second openings 172, connecting sub-lines and solder sub-units within the third openings, and corresponding alignment patterns within the first, second, third, fourth, and fifth openings. The seed layer 16 is then etched so that the routing sub-pattern 12Z and the portion of the seed layer 16 beneath it form the signal line 12, the connecting sub-line and the portion of the seed layer 16 beneath it form the connecting line 15, and the pad sub-unit and the portion of the seed layer 16 beneath it form the pad unit 14. The motherboard substrate 002 is then precisely cut along the first annular cutting line 009 outside the process edge area U using the cutting alignment pattern 006, leaving the process edge area U and the processing area 003. The first annular cutting line 009 surrounds the process edge area U.

[0629] A photosensitive white ink material is then applied to the sides of the signal lines 12 and the connecting lines 15 facing away from the first surface S. After the photosensitive white ink material solidifies, a photosensitive white ink layer is formed over the signal lines 12 and the connecting lines 15. The photosensitive white ink layer is then exposed and developed to form a plurality of fourth openings in the photosensitive white ink layer. The fourth openings correspond to the positions of the pad units 14, exposing the pad units 14. A thermosetting white ink material is then applied around the fourth openings to reduce their area.

[0630] In some embodiments, the wiring substrate 1 further includes a nickel-gold layer located on a side of the device pad group 141 away from the substrate 11. This layer is used to protect the device pad group 141 from oxidation and also facilitates subsequent fixing of the device pad group 141 to components such as the light-emitting device 2 by reflow soldering.

[0631] At this time, after the above steps, a nickel-gold layer is then formed on the surface of the area of ​​the pad unit 14 exposed by the fourth opening. After the nickel-gold layer is formed, the necessary electrical performance tests are performed on the nickel-gold layer to ensure the normal setting of the nickel-gold layer. Then, the pad unit 14 is fixedly connected to the light-emitting device 2 and the driver chip IC through a reflow soldering process. Then, the connection between the light-emitting device 2 and the driver chip IC and the pad unit 14 is tested, and the light-emitting device 2 and the driver chip IC with poor connection are located and reworked. Furthermore, a protective structure can be provided for the light-emitting device 2 and / or the driver chip IC.

[0632] Next, motherboard substrate 002 is cut along a second circular cutting line 0010 between process edge region U and processing region 003 to remove process edge region U, leaving only processing region 003. The flexible printed circuit board is then bonded to the binding pins 18 within the bonding region 1c and subjected to an aging process to produce light-emitting substrate 01. Display panel 02 is then positioned on the light-emitting surface of light-emitting substrate 01, and a support portion is provided between light-emitting substrate 01 and display panel 02 to support the display panel 02, thereby forming display device 001. Finally, display device 001 undergoes a factory inspection. Second circular cutting line 0010 encircles processing region 003.

[0633] In actual production, when coating the photoresist on the motherboard substrate 002, both positive photoresist and negative photoresist can be used.

[0634] For example, as shown in Figures 77 to 79, for positive photoresist, after the photoresist layer 17 is exposed and developed, a plurality of photoresist retaining walls 173 with a regular trapezoidal cross-section will be formed, and the angle H of the regular trapezoidal bottom angle ranges from 80° to 90°. A first opening 171, a second opening 172, a third opening, a first opening portion, a second opening portion, a third opening portion, a fourth opening portion or a fifth opening portion will be formed between each adjacent two photoresist retaining walls 173. Then, a routing sub-pattern 12Z, a dummy conductive sub-pattern 13Z, and the like are formed by electroplating in the first opening 171, the second opening 172, the third opening, the first opening portion, the second opening portion, the third opening portion, the fourth opening portion, or the fifth opening portion. However, because the photoresist retaining wall 173 has a regular trapezoidal cross-section, after electroplating, a gap R, as shown in FIG78 , appears between the routing sub-pattern 12Z and the dummy conductive sub-pattern 13Z and the photoresist retaining wall 173, near the first surface S. After the photoresist retaining wall 173 is removed and the seed layer 16 is etched, the gap R becomes larger, as shown in region R' in FIG79 . This can affect the service life of the connecting line 15 or the signal line 12.

[0635] For another example, as shown in Figures 80 to 82, for negative photolithography, after exposing and developing the photoresist layer 17, multiple photoresist retaining walls 173 with inverted trapezoidal cross-sections are formed. As shown in Figure 81, the angle O of the bottom angle of the inverted trapezoid is approximately 102°. Thus, after electroplating, the routing sub-pattern 12Z and the dummy conductive sub-pattern 13Z have a right trapezoidal cross-section, as shown in Figure 82. After the seed layer 16 is subsequently etched, the resulting signal line 12 and dummy conductive pattern 13 will not have gaps, thereby ensuring the service life of the connecting line 15 and the signal line 12.

[0636] In addition, as shown in Figure 83, during the production process, since it is necessary to use a clamp to clamp the first electrode area 0011 and the second electrode area 0012 on the substrate 11 and make the clamp contact with the seed layer 16, when the photoresist layer 17 is exposed and developed, it is necessary to remove part of the photoresist located in the first electrode area 0011 and the second electrode area 0012 so that the clamp can contact with the seed layer 16.

[0637] During the exposure and development process, a mask plate is required. In the electroplating scheme, the photoresist on the seed layer 16 is a positive photoresist. Therefore, when designing the mask plate, the positions on the mask plate where no shielding pattern is set correspond to the positions of the signal line 12, the connecting line 15, the binding pattern, etc.

[0638] Since the motherboard substrate 002 has multiple processing areas 003, multiple wiring substrates 1 can be formed at one time. However, during the exposure and development process of the photoresist layer 17, the size of the mask is only sufficient to process the photoresist layer 17 in one processing area 003 at a time. As shown in FIG83 , when exposing and developing a portion of the photoresist layer 17 in one processing area 003, the exposure and development process is also performed on the middle area 0013 of the motherboard substrate 002, thus exposing the seed layer 16 in the middle area 0013. In the subsequent electroplating process, a copper layer will also be electroplated and deposited in the middle area 0013, resulting in unnecessary waste. In addition, when the motherboard substrate 002 is cut, it is also easy to cause the motherboard substrate 002 to break.

[0639] Based on this, when using the mask plate for processing, it is necessary to use a baffle to block part of the photoresist layer 17 corresponding to the middle area 0013 to avoid exposure and development of the photoresist layer 17 in the middle area 0013, to avoid light reduction and decomposition of the photoresist layer 17 in the middle area 0013, and to avoid electroplating a layer of copper in the middle area 0013, so as to reduce the waste of copper material and ensure smooth cutting of the motherboard substrate 002 to avoid breakage of the motherboard substrate 002.

[0640] Exemplarily, the size of the first electrode area 0011 along the first direction ranges from 20 mm to 25 mm. For example, the size of the first electrode area 0011 in the first direction is 20 mm, 22 mm, 23 mm, 24 mm, or 25 mm.

[0641] Exemplarily, the size of the middle area 0013 along the first direction ranges from 20 mm to 25 mm. For example, the size of the middle area 0013 in the first direction is 20 mm, 21 mm, 23 mm, 24 mm or 25 mm.

[0642] In some embodiments, the width of the annular electrostatic discharge line 12D is positively correlated with the width of the peripheral region 1 b .

[0643] That is, the width of the loop-shaped electrostatic discharge line 12D changes with the width of the peripheral area 1b. Specifically, the width of the loop-shaped electrostatic discharge line 12D increases with the width of the peripheral area 1b, and decreases with the width of the peripheral area 1b.

[0644] Therefore, when the width of the peripheral area 1b is different, by adjusting the width of the annular electrostatic release line 12D, the bottom area ratio of the signal line 12 close to the peripheral area 1b in the area jointly formed by the peripheral area 1b and the signal line 12 close to the peripheral area 1b (for example, the first signal line VLED) is close to the bottom area ratio of the metal pattern to be plated in the area where other signal lines 12 are located, so that the current density on the signal line 12 close to the peripheral area 1b and other signal lines 12 is close, and the electroplating efficiency is close, so that the thickness between the signal line 12 close to the peripheral area 1b and other signal lines 12 is finally close, so as to improve the thickness uniformity between two adjacent signal lines 12, thereby improving the yield of the wiring substrate 1 and ensuring the reliability of the wiring substrate 1.

[0645] In some embodiments, as shown in FIG84 , the first vertical sub-segment 12D11 is widened by 77 μm along the negative direction of the first direction, so that the distance between the first vertical sub-segment 12D11 and the second annular cutting line 0010 is 0.6 mm. This allows the first vertical sub-segment 12D11 to also function as a dummy conductive pattern 13, thereby improving the thickness uniformity of the connecting wires 15, signal wires 12, and binding pins 18.

[0646] In order to better understand the role of the dummy conductive pattern 13 in the preparation process of the wiring substrate 1, the following experimental demonstration is conducted again to prove that the setting of the dummy conductive pattern 13 can improve the thickness uniformity of the connecting line 15, the signal line 12, the binding pattern, the alignment pattern, etc.

[0647] For example, when six processing areas 003 are provided on a motherboard substrate 002 and arranged in three rows and two columns, the thickness uniformity of the conductive wire to be plated at different locations within the processing area 003 was studied with varying distances between the dummy conductive portion 131 and the conductive wire to be plated. The data shown in Tables 7 to 9 below were obtained.

[0648] Table 7

[0649] As shown in FIG85 , lines 1 to 7 represent the division of the short side (vertical side) of substrate 11, and the distance between two adjacent lines is 5 mm. When the distance between dummy conductive portion 131 and the conductor to be plated is 0.76 mm, lines 1 to 7 intersect with the conductor to be plated on substrate 11, and a point is selected from each of the intersections of lines 1 to 7 with the conductor to be plated, thereby obtaining seven values. The maximum value of these seven values ​​is 9.2 μm, and the minimum value is 8.7 μm. The average value of these seven values ​​is calculated to be 9.0 mm. Based on this, the film thickness uniformity is calculated to be 2.8%.

[0650] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 2 mm, lines 1 to 7 intersect with the wire to be plated on the substrate 11 respectively, and a point is selected from each of the intersection lines of lines 1 to 7 with the wire to be plated, that is, 7 values ​​are obtained. The maximum value of the 7 values ​​is 8.7 μm, and the minimum value is 7.9 μm. The average value of the 7 numbers is calculated to be 8.4. On this basis, the film thickness uniformity of the wire to be plated is calculated to be 4.8%.

[0651] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 5 mm, lines 1 to 7 intersect with the wire to be plated on the substrate 11 respectively, and a point is selected from each of the intersection lines of lines 1 to 7 with the wire to be plated, that is, 7 values ​​are obtained. The maximum value of the 7 values ​​is 9.8 μm, and the minimum value is 8.6 μm. The average value of the 7 numbers is calculated to be 8.4. On this basis, the film thickness uniformity of the wire to be plated is calculated to be 6.5%.

[0652] Combined with the above data, it can be seen that as the distance between the conductor to be plated and the dummy conductive portion 131 decreases, the uniformity of the conductor to be plated decreases from 6.5% to 2.8%. Moreover, when the distance between the dummy conductive portion 131 and the conductor to be plated is 0.76 μm, the thickness value at the point where the outermost line intersects the conductor to be plated is not the maximum value, and the edge effect during the electroplating process is also reduced.

[0653] Table 8

[0654] As shown in FIG86 , lines 1 to 7 represent the division of the long side (horizontal side) of substrate 11, and the distance between two adjacent lines is 5 mm. When the distance between dummy conductive portion 131 and the conductor to be plated is 0.6 mm, lines 1 to 7 intersect with the conductor to be plated on substrate 11. A point is selected from each of the intersections of lines 1 to 7 with the conductor to be plated, resulting in seven values. The maximum value of these seven values ​​is 9.9 μm, and the minimum value is 9.4 μm. The average of these seven values ​​is calculated to be 9.6. Based on this, the film thickness uniformity is calculated to be 2.6%.

[0655] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 2 mm, lines 1 to 7 intersect with the wire to be plated on the substrate 11 respectively, and a point is selected from each of the intersection lines of lines 1 to 7 with the wire to be plated, that is, 7 values ​​are obtained. The maximum value of the 7 values ​​is 10.2 μm, and the minimum value is 9.3 μm. The average value of the 7 numbers is calculated to be 9.6. On this basis, the film thickness uniformity of the wire to be plated is calculated to be 4.6%.

[0656] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 4 mm, lines 1 to 7 intersect with the wire to be plated on the substrate 11 respectively, and a point is selected from each of the intersection lines of lines 1 to 7 with the wire to be plated, that is, 7 values ​​are obtained. The maximum value of the 7 values ​​is 9.0 μm, and the minimum value is 8.4 μm. The average value of the 7 numbers is calculated to be 8.6. On this basis, the film thickness uniformity of the wire to be plated is calculated to be 3.4%.

[0657] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 7 mm, lines 1 to 7 respectively intersect with the wire to be plated on the substrate 11, and a point is selected from each of the intersection lines of lines 1 to 7 with the wire to be plated, that is, 7 values ​​are obtained. The maximum value of the 7 values ​​is 10.1 μm, and the minimum value is 8.4 μm. The average value of the 7 numbers is calculated to be 9.0. On this basis, the film thickness uniformity of the wire to be plated is calculated to be 9.2%.

[0658] Combining the above data, we can see that as the distance between the conductor to be plated and the dummy conductive portion 131 decreases, the uniformity of the conductor to be plated decreases from 9.2% to 2.6%. Furthermore, when the distance between the dummy conductive portion 131 and the conductor to be plated is 0.6 μm, the thickness value at the point where the outermost line intersects the conductor to be plated is not the maximum value, and the edge effect during the electroplating process is also reduced.

[0659] Table 9

[0660] As shown in Figure 85, lines 1 through 7 represent the divisions of the peripheral region 1b of substrate 11, with the distance between adjacent lines being 5 mm. When the distance between dummy conductive portion 131 and the conductor to be plated is 0.6 mm, each of lines 1 through 7 intersects with the conductor to be plated on substrate 11. Seven values ​​are obtained by selecting a point from each of the intersections of lines 1 through 7 with the conductor to be plated. The maximum value of these seven values ​​is 7.3 μm, and the minimum value is 6.7 μm. The average of these seven values ​​is calculated to be 7.1, and based on this, the film thickness uniformity is calculated to be 4.3%.

[0661] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 2 mm, each of lines 1 to 7 intersects with the wire to be plated on the substrate 11, and a point is selected from the positions where lines 1 to 7 intersect with the wire to be plated, so as to obtain 7 values. The maximum value of the 7 values ​​is 7.4 μm, and the minimum value is 6.7 μm. The average value of the 7 numbers is calculated to be 7.1. On this basis, the uniformity of the film thickness of the wire to be plated is calculated to be 5.0%.

[0662] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 4 mm, lines 1 to 7 intersect with the wire to be plated on the substrate 11 respectively, and a point is selected from each of the intersection lines of lines 1 to 7 with the wire to be plated, that is, 7 values ​​are obtained. The maximum value of the 7 values ​​is 7.0 μm, and the minimum value is 6.4 μm. The average value of the 7 numbers is calculated to be 6.7. On this basis, the film thickness uniformity of the wire to be plated is calculated to be 4.5%.

[0663] Similarly, when the distance between the dummy conductive portion 131 and the wire to be plated is 7 mm, lines 1 to 7 respectively intersect with the wire to be plated on the substrate 11, and a point is selected from each of the intersection lines of lines 1 to 7 with the wire to be plated, that is, 7 values ​​are obtained. The maximum value of the 7 values ​​is 6.8 μm, and the minimum value is 5.9 μm. The average value of the 7 numbers is calculated to be 9.0. On this basis, the film thickness uniformity of the wire to be plated is calculated to be 7.1%.

[0664] From the above data, it can be seen that as the distance between the conductor to be plated and the dummy conductive portion 131 decreases, the uniformity of the conductor to be plated decreases from 7.1% to 4.3%.

[0665] Combining the data in Tables 7 to 9 above, it can be seen that as the distance between the dummy conductive portion 131 and the wire to be plated decreases, the thickness uniformity of the wire to be plated increases.

[0666] As shown in FIG67 , when a motherboard substrate 002 is arranged with six rows and four columns, totaling twenty-four processing areas 003, and the left edge of the processing area 003 in the first column is 5 cm away from the left edge of the motherboard substrate 002, the distance between the processing areas 003 in the second column and the processing areas 003 in the third column is 7 cm, and the right edge of the processing area 003 in the fourth column is 5 cm away from the right edge of the processing areas 003 in the fourth column, the thickness uniformity of the wires to be plated on the entire motherboard substrate 002 is studied to obtain a bar chart as shown in FIG88 .

[0667] From left to right, the first bar graph represents the case where the dummy conductive part 131 is not set. At this time, the thickness uniformity of the wire to be plated is 30.58%. The second bar graph represents the case where the distance between the wire to be plated and the dummy conductive part 131 is 4mm, and the width of the dummy conductive part 131 itself is 1.0mm. The thickness uniformity of the wire to be plated is 17.53%. The third bar graph represents the case where the distance between the wire to be plated and the dummy conductive part 131 is 6mm, and the width of the dummy conductive part 131 itself is 0.5mm. The thickness uniformity of the wire to be plated is 10.87%. The fourth bar graph represents the case where the distance between the wire to be plated and the dummy conductive part 131 is 10mm, and the width of the dummy conductive part 131 itself is 0.5mm. The thickness uniformity of the wire to be plated is 13.95%. The fifth bar graph represents a case where the distance between the conductor to be plated and the dummy conductive portion 131 is 2 mm, and the width of the dummy conductive portion 131 is 0.5 mm. The thickness uniformity of the conductor to be plated is 22.69%. The sixth bar graph represents a case where the distance between the conductor to be plated and the dummy conductive portion 131 is 4 mm, and the width of the dummy conductive portion 131 is 0.5 mm. The thickness uniformity of the conductor to be plated is 21.74%. The seventh bar graph represents a case where the distance between the conductor to be plated and the dummy conductive portion 131 is 4 mm, and the width of the dummy conductive portion 131 is 1.5 mm. The thickness uniformity of the conductor to be plated is 22.12%. The eighth bar graph represents a case where the distance between the conductor to be plated and the dummy conductive portion 131 is 8 mm, and the width of the dummy conductive portion 131 is 0.5 mm. The thickness uniformity of the conductor to be plated is 19.23%.

[0668] From the above experimental results, it can be seen that for the wires to be plated in the first column of processing areas 003 and the wires to be plated in the fourth column of processing areas 003, the thickness uniformity of the wires to be plated is best when the distance between the wires to be plated and the dummy conductive portion 131 is 6 mm and the width of the dummy conductive portion 131 itself is 0.5 mm.

[0669] Furthermore, the first columnar graph, the second columnar graph, the third columnar graph, and the fourth columnar graph all represent accompanying plating performed in an area with a blank width of 5 cm. The fifth columnar graph, the sixth columnar graph, the seventh columnar graph, and the eighth columnar graph all represent accompanying plating performed in an area with a blank width of 7 cm. It should be noted that the blank width refers to the width of the position where the metal wire (signal wire 12 and connecting wire 15) is not set. It can be seen from the above experimental results that the larger the blank position, the larger the width of the required dummy conductive pattern, and the better the thickness uniformity of the wire to be plated.

[0670] For the wires to be plated in the second column processing area 003 and the wires to be plated in the third column processing area 003, the thickness uniformity of the wires to be plated is best when the distance between the wires to be plated and the dummy conductive portion 131 is 8 mm and the width of the dummy conductive portion 131 itself is 0.5 mm.

[0671] Next, the authors investigated whether to include a dummy conductive pattern and the difference between the actual thickness of the conductor to be plated and the theoretical thickness. The theoretical thickness of the conductor to be plated was set to 5 μm, as shown in Figure 87. From left to right, the first bar graph represents the case where the dummy conductive portion 131 is not included. In this case, the actual thickness of the conductor to be plated is 7.46 μm. The second bar graph represents the case where the distance between the conductor to be plated and the dummy conductive portion 131 is 4 mm, and the width of the dummy conductive portion 131 is 1.0 mm. The actual thickness of the conductor to be plated is 5.36 μm. The third bar graph represents the case where the distance between the conductor to be plated and the dummy conductive portion 131 is 6 mm, and the width of the dummy conductive portion 131 is 0.5 mm. The actual thickness of the conductor to be plated is 4.69 μm. The fourth bar graph represents the case where the distance between the conductor to be plated and the dummy conductive portion 131 is 10 mm, and the width of the dummy conductive portion 131 is 0.5 mm. The actual thickness of the conductor to be plated is 4.16 μm. The fifth bar graph represents the case where the distance between the wire to be plated and the dummy conductive portion 131 is 2 mm, the width of the dummy conductive portion 131 itself is 0.5 mm, and the actual thickness of the wire to be plated is 6.99 μm. The sixth bar graph represents the case where the distance between the wire to be plated and the dummy conductive portion 131 is 4 mm, the width of the dummy conductive portion 131 itself is 0.5 mm, and the actual thickness of the wire to be plated is 6.48 μm. The seventh bar graph represents the case where the distance between the wire to be plated and the dummy conductive portion 131 is 4 mm, the width of the dummy conductive portion 131 itself is 1.5 mm, and the actual thickness of the wire to be plated is 6.5 μm. The eighth bar graph represents the case where the distance between the wire to be plated and the dummy conductive portion 131 is 8 mm, the width of the dummy conductive portion 131 itself is 0.5 mm, and the actual thickness of the wire to be plated is 5.24 μm.

[0672] From the above experimental comparison, it can be seen that for the wires to be plated in the first column of processing areas 003 and the wires to be plated in the fourth column of processing areas 003, when the distance between the wires to be plated and the dummy conductive portion 131 is 4 mm and the width of the dummy conductive portion 131 itself is 1.0 mm, the actual thickness of the wires to be plated is closest to the theoretical thickness of the wires to be plated.

[0673] Furthermore, the first columnar graph, the second columnar graph, the third columnar graph, and the fourth columnar graph all represent accompanying plating performed in an area with a blank width of 5 cm. The fifth columnar graph, the sixth columnar graph, the seventh columnar graph, and the eighth columnar graph all represent accompanying plating performed in an area with a blank width of 7 cm. It should be noted that the blank width refers to the width of the position where the metal wire (signal wire 12 and connecting wire 15) is not set. It can be seen from the above experimental results that the larger the blank position, the larger the width of the required dummy conductive pattern, and the better the thickness uniformity of the wire to be plated.

[0674] For the wires to be plated in the second column processing area 003 and the wires to be plated in the third column processing area 003, when the distance between the wires to be plated and the dummy conductive portion 131 is 8 mm and the width of the dummy conductive portion 131 itself is 0.5 mm, the actual thickness of the wires to be plated is closest to the theoretical thickness of the wires to be plated.

[0675] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A wiring substrate having a functional area and a peripheral area located on at least one side of the functional area; the wiring substrate includes: A substrate having a first surface; A plurality of signal lines located on the first surface and in the functional area; The plurality of signal lines are arranged at intervals in a first direction and extend in a second direction; the first direction and the second direction intersect; A plurality of dummy conductive patterns located on the first surface, and at least some of the dummy conductive patterns are located in the peripheral area; The dummy conductive patterns are insulated from the plurality of signal lines.

2. The wiring substrate according to claim 1, wherein, The width of the dummy conductive pattern located in the peripheral area is positively correlated with the width of the peripheral area.

3. The wiring substrate according to claim 1 or 2, wherein The range of the minimum distance between the dummy conductive pattern located in the peripheral area and the signal line is: 0.5 mm to 1.5 mm.

4. The wiring substrate according to any one of claims 1 to 3, wherein, The peripheral area surrounds the functional area; The width of the dummy conductive pattern located in the peripheral area and on the opposite sides of the functional area along the first direction is greater than the width of the dummy conductive pattern located in the peripheral area and on the opposite sides of the functional area along the second direction.

5. The wiring substrate according to any one of claims 1 to 4, wherein, A dummy conductive pattern is provided between some adjacent two signal lines, and the dummy conductive pattern is insulated from the adjacent two signal lines.

6. The wiring substrate according to claim 5, wherein, The width of the dummy conductive pattern located between the adjacent two signal lines is positively correlated with the distance between the adjacent two signal lines.

7. The wiring substrate according to any one of claims 1 to 6, wherein, The peripheral area includes a first peripheral area located on one side of the functional area, and the first peripheral area and the functional area are arranged at intervals in the second direction; the wiring substrate further includes: A plurality of pad units located on the first surface and in the functional area, and the pad unit includes a plurality of device pad groups; A plurality of connection lines located on the first surface and in the functional area; the connection lines include a first connection line and a second connection line, and the pad unit and the signal line are configured to be connected through the first connection line; the plurality of device pad groups in the same pad unit are configured to be connected through the second connection line; The plurality of signal lines include a ground signal line, and one end of the ground signal line far from the first peripheral area is flush with the connection line far from the peripheral area among the plurality of connection lines.

8. The wiring substrate according to claim 7, further including: A ring-shaped electrostatic discharge line located on the first surface and surrounding the functional area; The ring-shaped electrostatic discharge line includes a first electrostatic discharge sub-segment, a second electrostatic discharge sub-segment, and a third electrostatic discharge sub-segment that are electrically connected in sequence. The first static Electrostatic discharge sub-segment and the third electrostatic discharge sub-segment are located on the opposite sides of the functional area along the first direction, and the second electrostatic discharge sub-segment is located on the side of the functional area far from the first peripheral area; The range of the distance between the second electrostatic discharge sub-segment and the connection line is: 0.2 mm to 0.5 mm.

9. The wiring substrate according to claim 8, wherein, The width of the ring-shaped electrostatic discharge line is positively correlated with the width of the peripheral area.

10. The wiring substrate according to any one of claims 7 to 9, wherein, The second connecting line includes a connecting sub-segment located between any two adjacent device pad groups in the same pad unit, and the connecting sub-segment connects the two adjacent device pad groups; a dummy conductive pattern is provided on at least one side of the connecting sub-segment, and the dummy conductive pattern is parallel to the extension direction of the adjacent connecting sub-segment.

11. The wiring substrate according to claim 10, wherein: In the same second connecting line, a dummy conductive pattern is respectively provided on the same side of any two adjacent connecting sub-segments, and the two dummy conductive patterns on one side of the two adjacent connecting sub-segments are connected to each other; The overall extension direction of the two dummy conductive patterns extends along the overall direction of the two adjacent connecting sub-segments.

12. The wiring substrate according to claim 11, wherein, The distance between the dummy conductive pattern and the adjacent first connecting line ranges from 0.2 mm to 0.5 mm.

13. The wiring substrate according to claim 11 or 12, wherein, The plurality of connecting sub-segments include: a plurality of first connecting sub-segments, and a second connecting sub-segment located between two adjacent first connecting sub-segments; the first connecting sub-segment extends along the second direction, and the second connecting sub-segment extends along the first direction; The plurality of dummy conductive patterns include: a plurality of first dummy conductive patterns and a plurality of second dummy conductive patterns; the first dummy conductive portion extends along the second direction, and the second dummy conductive portion extends along the first direction; In the same second connecting line, at least one first dummy conductive portion is arranged between at least some adjacent first connecting sub-segments, and along the first direction, the adjacent first connecting sub-segments and the at least one first dummy conductive portion are arranged at equal intervals; and / or, At least one second dummy conductive portion is disposed between at least some of the adjacent second connecting sub-segments, and along the second direction, the adjacent second connecting sub-segments and the at least one second dummy conductive portion are disposed at equal intervals.

14. The wiring substrate according to any one of claims 7 to 13, wherein, The first peripheral area includes a first blank area, a binding area, and a second blank area arranged in sequence along the first direction; Part of the dummy conductive pattern is disposed in the first blank area; and / or, Part of the dummy conductive pattern is disposed in the second blank area.

15. The wiring substrate according to claim 14, further comprising: A plurality of alignment patterns are located on the first surface; at least part of the alignment patterns are located in the first blank area and the second blank area, and the dummy conductive patterns are staggered with the alignment patterns.

16. The wiring substrate according to any one of claims 5 to 15 further comprises: The nickel-gold layer is located on a side of the device pad group away from the substrate.

17. A method for preparing a wiring substrate, the wiring substrate comprising a functional area and a peripheral area located on at least one side of the functional area; the method comprising: providing a substrate having a first surface; Using the same patterning process, a plurality of signal lines and a plurality of dummy conductive patterns are simultaneously formed on the first surface; The plurality of signal lines are arranged at intervals along a first direction and extend along a second direction; the first direction and the second direction intersect; At least part of the dummy conductive pattern is located in the peripheral area; the dummy conductive pattern is insulated from the plurality of signal lines.

18. The preparation method according to claim 17, wherein, The method of using the same patterning process to simultaneously form a plurality of signal lines and the plurality of dummy conductive patterns on the first surface comprises: forming a seed layer on the first surface; A photoresist layer is formed on the seed layer; the photoresist layer uses a negative photoresist, and the photoresist layer has a plurality of first openings and a plurality of second openings. The first openings correspond to signal lines to be formed, and the second openings correspond to the dummy conductive patterns to be formed; Using an electroplating process, the signal lines are formed in the first openings, and the dummy conductive patterns are simultaneously formed in the second openings; The photoresist is stripped to expose a part of the seed layer corresponding to the position where the stripped photoresist is located; Using the signal lines and the dummy conductive patterns as masks, the seed layer is etched to remove a part of the seed layer corresponding to the position of the photoresist.

19. A light-emitting substrate, comprising: A wiring substrate, which is the wiring substrate according to any one of claims 1 to 16; A plurality of light-emitting devices, which are arranged on the wiring substrate.

20. A display device, comprising: A light-emitting substrate, which is the light-emitting substrate according to claim 19; A display panel, which is located on the light-emitting side of the light-emitting substrate.

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