Thin film transistor, sensor, display panel, and display panel manufacturing method

Abstract

Embodiments of the present application provide a thin film transistor, and a sensor, a display panel and a display device comprising the thin film transistor. The thin film transistor comprises: a substrate; a semiconductor layer located above the substrate; and a gate layer located on the side of the semiconductor layer facing away from the substrate, wherein the gate layer comprises a transparent conductive layer. The thin film transistor further comprises a first insulating layer located on the side of the semiconductor layer facing away from the substrate, the first insulating layer comprises a first opening, the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the transparent conductive layer extends along at least part of the inner wall of the first opening. The thin film transistor provided by the embodiments of the present application can be used as an important component of a sensor to achieve effective sensing of ambient light, and can also be applied to a display device to achieve true integration of a light sensor and the display device, reducing the size of the display device; moreover, the thin film transistor can be manufactured synchronously with other elements of the display device, reducing the overall cost of the display device.

Description

Thin film transistor, sensor, display panel, and display panel manufacturing method Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a thin film transistor, a sensor including the thin film transistor, a display panel, a display device, and a method for manufacturing a display panel. Background Art

[0002] Thin-film transistors (TFTs) are commonly used electronic components in various display devices. They are the primary components of both the gate driver circuits that provide gate scanning signals and the pixel circuits that drive each pixel in the display device to emit light. With the rapid development of display panel technology, smart panels with rich functionality are becoming an inevitable market trend. For example, various sensors, such as photosensors, fingerprint sensors, and distance sensors, can be integrated into a display panel to achieve an integrated, all-in-one design and enhance the display panel's additional functionality. By integrating photosensors into a display device, the display device can automatically detect ambient light levels and adjust screen brightness. However, in conventional display panels or display devices, sensors such as photosensors are present within the display device as separate modules or units. These separate sensor units or sensor modules often need to be purchased separately and then installed within the display device, increasing the cost of the display device and hindering its size reduction.

[0003] Summary of the Invention

[0004] The present application provides a thin-film transistor (TFT), comprising: a substrate; a semiconductor layer located above the substrate; and a gate layer located on a side of the semiconductor layer facing away from the substrate, the gate layer comprising a transparent conductive layer. The TFT also comprises a first insulating layer located on a side of the semiconductor layer facing away from the substrate, the first insulating layer comprising a first opening, the orthographic projection of the first opening on the substrate at least partially overlapping the orthographic projection of the semiconductor layer on the substrate, wherein the transparent conductive layer extends along at least a portion of an inner wall of the first opening.

[0005] In some embodiments, the thin film transistor also includes a first insulating layer located on the side of the semiconductor layer facing away from the substrate, the first insulating layer includes a first opening, the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the transparent conductive layer extends along at least a portion of the inner wall of the first opening.

[0006] In some embodiments, the thin film transistor further includes a second insulating layer located on a side of the first insulating layer away from the semiconductor layer, the second insulating layer including a second opening connected to the first opening, wherein the transparent conductive layer further extends along at least a portion of an inner wall of the second opening.

[0007] In some embodiments, an orthographic projection of the second opening on the substrate covers an orthographic projection of the first opening on the substrate, and an orthographic projection of the transparent conductive layer on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer on the substrate.

[0008] In some embodiments, the gate layer also includes a gate metal layer, the first insulating layer covers the gate metal layer, the gate metal layer includes a third opening, the first opening is connected to the third opening, and the transparent conductive layer also extends along at least a portion of the inner wall of the third opening and is in direct contact with the gate metal layer.

[0009] In some embodiments, the gate layer further includes a gate metal layer, the gate metal layer includes a third opening, and the transparent conductive layer extends along at least a portion of an inner wall of the third opening to directly contact the gate metal layer.

[0010] In some embodiments, the semiconductor layer includes a central doping region and an edge doping region surrounding the central doping region, the doping ions in the central doping region are different from the doping ions in the edge doping region, and the orthographic projection of the gate metal layer including the third opening on the substrate coincides with the orthographic projection of the central doping region on the substrate.

[0011] In some embodiments, the third opening, the second opening, and the first opening integrally form a gate opening, and the transparent conductive layer extends along an inner wall of the gate opening to cover the gate opening.

[0012] In some embodiments, the thin film transistor further includes a gate insulating layer located between the semiconductor layer and the gate layer, and the third opening exposes the gate insulating layer so that the transparent conductive layer is in direct contact with the gate insulating layer.

[0013] In some embodiments, the thin film transistor further includes a source and a drain, wherein the source and the drain are located on a surface of the first insulating layer facing away from the substrate, and the source and the drain are respectively electrically connected to the edge doping region of the semiconductor layer.

[0014] In some embodiments, the semiconductor layer includes a central doping region and an edge doping region surrounding the central doping region, the doping ions in the central doping region are different from the doping ions in the edge doping region, and the orthographic projection of the first opening on the substrate coincides with the orthographic projection of the central doping region on the substrate.

[0015] In some embodiments, the thin film transistor further includes a light blocking layer located on a side of the semiconductor layer facing the substrate, and an orthographic projection of the light blocking layer on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer on the substrate.

[0016] In some embodiments, the light shielding layer includes a conductive material, and the light shielding layer and the transparent conductive layer are electrically connected to each other.

[0017] In some embodiments, the thin film transistor also includes an electrical connection layer on the surface of the first insulating layer facing away from the substrate, the transparent conductive layer extends to the outside of the first opening, the first insulating layer includes a first conductive via, and the transparent conductive layer is electrically connected to the light blocking layer at least via the electrical connection layer and the first conductive via.

[0018] In some embodiments, the thin film transistor also includes a gate insulating layer located between the semiconductor layer and the gate layer, wherein the second insulating layer includes an external via located outside the second opening, and the transparent conductive layer is electrically connected to the electrical connection layer via the external via, wherein the thin film transistor also includes a buffer layer located between the semiconductor layer and the light blocking layer, the buffer layer and the gate insulating layer respectively include a second conductive via and a third conductive via connected to the first conductive via, and the electrical connection layer is electrically connected to the light blocking layer via the first conductive via, the second conductive via and the third conductive via.

[0019] In some embodiments, the electrical connection layer includes the same material as the source and drain electrodes.

[0020] In some embodiments, a diameter of an orthographic projection of the third opening on the substrate is between 2 micrometers and 5 micrometers.

[0021] In some embodiments, the gate metal layer includes a gate metal material layer located on at least one side of the third opening, and a diameter of an orthographic projection of the gate metal material layer on the substrate is 1 / 8 to 1 / 6 of a diameter of an orthographic projection of the third opening on the substrate.

[0022] Another embodiment of the present application provides a sensor, which includes at least one thin film transistor as described in any of the aforementioned embodiments.

[0023] In some embodiments, the sensor includes thin film transistors as described in any of the aforementioned embodiments that are connected in parallel, and the gate layers of the thin film transistors connected in parallel are electrically connected to each other.

[0024] Another embodiment of the present application provides a display panel including a display area and a non-display area. The display panel includes at least one thin film transistor as described in any of the aforementioned embodiments, and the thin film transistor is located in the non-display area.

[0025] In some embodiments, the display panel includes a plurality of thin film transistors as described in any of the aforementioned embodiments, and the plurality of thin film transistors as described in any of the aforementioned embodiments form N groups of thin film transistors, each group of thin film transistors includes at least two thin film transistors, and the at least two thin film transistors are connected in parallel, wherein each group of thin film transistors in the N groups of thin film transistors is configured to independently output electrical signals reflecting ambient light, and N is an integer greater than or equal to 2.

[0026] In some embodiments, the non-display area surrounds the display area, so that the non-display area includes a first non-sub-display area and a second non-sub-display area facing each other, and the display panel also includes a cover ink area at least within the first non-sub-display area, wherein the N groups of thin film transistors are located between the cover ink area and the display area.

[0027] In some embodiments, the display panel further includes a light-blocking layer above the N groups of thin film transistors, the light-blocking layer including a plurality of openings, the plurality of openings respectively exposing N-1 groups of thin film transistors in the N groups of thin film transistors, and the display panel further includes a color filter layer located in the plurality of openings.

[0028] In some embodiments, the color filter layer includes a red color resist layer, a green color resist layer, and a blue color resist layer, and the red color resist layer, the green color resist layer, and the blue color resist layer respectively cover different groups of thin film transistors in the N-1 group of thin film crystals.

[0029] In some embodiments, the display panel also includes a controller located in the second non-sub-display area, and the controller is electrically connected to the N groups of thin film transistors via signal lines, wherein the non-display area also includes a third non-sub-display area and a fourth non-sub-display area that are opposite to each other, and the signal line extends from the controller through at least one of the third non-sub-display area and the fourth non-sub-display area and is electrically connected to the N groups of thin film transistors.

[0030] Yet another embodiment of the present application provides a display device, comprising the display panel described in the above embodiment.

[0031] Another embodiment of the present application provides a method for manufacturing a display panel, which includes a substrate, and the method includes: manufacturing a semiconductor material layer on the substrate; manufacturing a gate insulating layer and a gate metal layer on the semiconductor material layer, wherein the gate metal layer is located on the side of the gate insulating layer facing away from the substrate; ion-doping the semiconductor material layer to obtain a semiconductor layer; at least partially removing the gate metal layer to expose the gate insulating layer; and forming a transparent conductive layer on the gate insulating layer.

[0032] In some embodiments, the display panel includes a pixel electrode in the display area, and the method further includes: forming the transparent conductive layer in a process of forming the pixel electrode.

[0033] These and other advantages of the application will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Embodiments of the present application will now be described in more detail and with reference to the accompanying drawings, in which:

[0035] FIG1 illustrates a partial cross-sectional view of a thin film transistor provided according to a comparative embodiment of the present application;

[0036] FIG2 schematically shows a partial top perspective view of a thin film transistor according to an embodiment of the present application;

[0037] FIG3 is a partial cross-sectional view of the thin film transistor taken along the dotted line A1-A2 in FIG2;

[0038] FIG4 a schematically shows a partial cross-sectional view of a thin film transistor according to another embodiment of the present application;

[0039] FIG4 b schematically shows a partial cross-sectional view of a thin film transistor according to another embodiment of the present application;

[0040] FIG5 schematically shows a partial top perspective view of a thin film transistor according to yet another embodiment of the present application;

[0041] FIG6 is a partial cross-sectional view of the thin film transistor taken along the dotted line B1-B2 in FIG5;

[0042] FIG7 schematically shows a partial top perspective view of a display panel including the thin film transistor shown in FIG6 ;

[0043] FIG8 shows a partial schematic cross-sectional view of a dual-gate thin film transistor;

[0044] FIG. 9 illustrates a current-voltage curve corresponding to the thin film transistor shown in FIG. 4 a .

[0045] 10 and 11 respectively illustrate a plan view and a cross-sectional view of a thin film transistor according to an embodiment of the present application;

[0046] FIG12 illustrates some steps involved in a method for manufacturing a display panel according to an embodiment of the present application;

[0047] FIG13 illustrates the process of removing the gate metal layer and forming a transparent conductive layer;

[0048] FIG14 illustrates a plan view of a display panel according to an embodiment of the present application, in which a boundary between a display area and a non-display area and some elements in the non-display area are identified;

[0049] FIG15 illustrates a connection diagram of a plurality of thin film transistors located in a non-display area of ​​a display panel and serving as light sensors;

[0050] 16 illustrates a partially enlarged top plan view of a non-display area of ​​a display panel, in which the boundaries between the region where multiple thin film transistors serving as light sensors are located, the display region, and the cover ink region are identified. DETAILED DESCRIPTION

[0051] The following description provides specific details of various embodiments of the present application so that those skilled in the art can fully understand and implement the various embodiments of the present application. In some cases, this application does not illustrate or describe in detail some structures or functions well known in the art to avoid these unnecessary descriptions from obscuring the description of the embodiments of the present application. The technical solutions of the present application can be embodied in many different forms and purposes and should not be limited to the embodiments set forth herein. These embodiments are provided to make the technical solutions of the present application clear and complete, but the embodiments do not limit the scope of protection of this patent application.

[0052] Here, some of the terms involved in the embodiments of the present application are first explained to facilitate understanding by those skilled in the art.

[0053] FIG1 schematically illustrates a partial cross-sectional view of a thin film transistor according to a comparative embodiment of the present application. As shown in FIG1 , the thin film transistor may include a substrate SB, a buffer layer BF, a gate G, a source S, a drain D, a gate insulating layer GI, an interlayer insulating layer ILD, a planarization layer PLN, and a passivation layer PVX. The gate insulating layer GI prevents direct contact between the gate G and the semiconductor layer SE. The gate G typically comprises an opaque metal material such as molybdenum (Mo) or platinum.

[0054] Unlike the thin film transistor provided in the comparative embodiment shown in FIG1 , the thin film transistor according to the embodiment of the present application includes a substrate, a semiconductor layer located above the substrate, and a gate layer located on the side of the semiconductor layer facing away from the substrate, and the gate layer includes a transparent conductive layer. Since the gate layer includes a transparent conductive layer, external ambient light can reach the semiconductor layer of the thin film transistor at least via the transparent conductive layer, so that the semiconductor layer is exposed to light and generates leakage current, resulting in a change in the current flowing through the thin film transistor. Moreover, this current change is more obvious when the thin film transistor is in the off state (cut-off state). Therefore, by detecting the current change when the thin film transistor is in the off state, it is possible to detect the change in light in the environment in which the thin film transistor is located. The thin film transistor provided in the embodiment of the present application can be used as an important component of a sensor to achieve effective sensing of ambient light. It can also be used in display devices to achieve true integration of light sensors and display devices, reduce the volume of the display device, and achieve synchronous production with other components of the display device, thereby reducing the overall cost of the display device.

[0055] Below, embodiments of the thin-film transistor proposed in this application are further described using more specific examples. Figure 2 schematically illustrates a partial top perspective view of a thin-film transistor according to one embodiment of the present application, and Figure 3 is a partial cross-sectional view of the thin-film transistor taken along dashed line A1-A2 in Figure 2 . As shown in Figures 2 and 3 , the thin-film transistor includes a substrate SB, a semiconductor layer SE located above the substrate SB, and a gate layer GT located on the side of the semiconductor SE layer facing away from the substrate SB. The gate layer GT includes a transparent conductive layer. In some embodiments, the semiconductor layer SE may include low-temperature polycrystalline silicon (LTPS). That is, the active layer of the thin-film transistor is formed using LTPS material, forming a LTPS TFT. Compared to the fabrication process of amorphous silicon thin-film transistors, the fabrication process of LTPS TFTs adds laser crystallization and ion implantation to convert the amorphous silicon thin film into polycrystalline silicon, thereby significantly improving electron mobility. Using LTPS TFTs as pixel driver elements in display devices can increase the brightness of the display device and reduce power consumption. In some embodiments, the transparent conductive layer may include a transparent conductive material such as ITO (indium tin oxide). In the example of Figure 2, instead of an opaque metal material, a transparent ITO conductive layer is used as the gate of the thin film transistor, which allows the semiconductor layer SE below the gate layer to receive and sense external light, thereby creating the necessary conditions for the thin film transistor to have a light sensing function, and realizing a thin film transistor with a photosensitivity function. It can be understood that the materials of the semiconductor layer and the transparent conductive layer described above are only exemplary, and materials with similar properties to the above-mentioned low-temperature polycrystalline silicon or indium tin oxide can be used to make the semiconductor layer or the gate layer respectively. This application does not impose any restrictions on the materials for making the substrate, and the substrate can be made of appropriate metal materials or insulating materials.

[0056] As shown in FIG3 , according to some embodiments of the present application, the thin film transistor further comprises a first insulating layer IN1 located on a side of the semiconductor layer SE facing away from the substrate SB. The first insulating layer IN1 comprises a first opening, the orthographic projection of the first opening on the substrate SB at least partially overlapping the orthographic projection of the semiconductor layer SE on the substrate SE, and the transparent conductive layer GT extends along at least a portion of the inner wall of the first opening. According to another embodiment of the present application, the thin film transistor further comprises a second insulating layer IN2 located on a side of the first insulating layer IN1 facing away from the semiconductor layer. The second insulating layer IN2 comprises a second opening communicating with the first opening, and the transparent conductive layer further extends along at least a portion of the inner wall of the second opening. This embodiment can be further illustrated with reference to FIG3 , which shows the second insulating layer IN2 comprising a second opening, the first opening communicating with the second opening, and the transparent conductive layer GT extending along at least a portion of the inner wall of the first and second openings.

[0057] Furthermore, in some embodiments, the orthographic projection of the second opening in the second insulating layer IN2 on the substrate SB overlaps the orthographic projection of the first opening in the first insulating layer IN1 on the substrate SB, and the orthographic projection of the transparent conductive layer GT on the substrate at least partially overlaps the orthographic projection of the semiconductor layer SE on the substrate SB. This can also be understood from the cross-sectional view shown in FIG3 , in which the horizontal dimension of the cross-section of the second opening in the second insulating layer IN2 is greater than the horizontal dimension of the cross-section of the first opening in the first insulating layer IN1.

[0058] For the sake of simplicity, Figure 3 does not show the source and drain of the thin film transistor. In the top perspective view shown in Figure 2, the strip-shaped areas marked with S and D are illustrated as the source and drain of the thin film transistor. The source electrode S is electrically connected to the semiconductor layer SE via the via CNT1, and the drain electrode D is electrically connected to the semiconductor layer SE via the via CNT2. Figure 2 schematically shows three vias CNT1 and three vias CNT2, and the vias CNT1 and CNT2 at least penetrate the gate insulating layer GI but are not connected to the gate layer GT. Figure 2 also shows a first opening OP in the first insulating layer and a second insulating layer IN2. The transparent conductive layer can extend along the inner wall of the first opening in the first insulating layer and the second opening in the second insulating layer to the outside of the second opening of the second insulating layer.

[0059] According to other embodiments of the present application, in addition to the transparent conductive layer, the gate layer of the thin film transistor may further include a gate metal layer. The gate metal layer includes a third opening, and the transparent conductive layer extends along at least a portion of the inner wall of the third opening and directly contacts the gate metal layer. The gate metal layer may include any conventional opaque conductive metal, such as the aforementioned metal molybdenum or molybdenum oxide.

[0060] Figure 4a illustrates a partial cross-sectional view of a thin-film transistor provided according to some embodiments of the present application. As shown in Figure 4a, the gate layer of the thin-film transistor includes a transparent conductive layer GT and a gate metal layer GM. A first insulating layer IN1 covers the gate metal layer GM. The gate metal layer includes a third opening. The first opening in the first insulating layer IN1 communicates with the third opening in the gate metal layer. The transparent conductive layer covers at least a portion of the inner wall of the third opening in the gate metal layer GM and is in direct contact with the gate metal layer GM. In other words, in this embodiment, the gate layer of the thin-film transistor is composed of both a transparent conductive layer and a gate metal layer. The direct contact between the transparent conductive layer and the gate metal layer is not limited to the example shown in Figure 4a; the third opening in the gate metal layer GM can have any cross-sectional profile. As will be explained further below, the gate metal layer can be a metal material layer left over from the processing required to manufacture the thin-film transistor. For example, a semiconductor material layer and a molybdenum (Mo) metal layer can be pre-formed above a substrate, and an ion doping process can be performed on the semiconductor material layer to form the aforementioned semiconductor layer. In some embodiments, the semiconductor material layer comprises low-temperature polysilicon doped with boron ions. On this basis, the above-mentioned first insulating layer and / or second insulating layer can be formed above the semiconductor layer and the molybdenum metal layer. The first opening in the first insulating layer and the second opening in the second insulating layer can expose at least a portion of the molybdenum metal layer. As a result, at least a portion of the molybdenum metal layer can be removed by an etching process, and the portion of the molybdenum metal layer that is not removed can be regarded as the above-mentioned gate metal layer. The formation of the gate metal layer will be further described in detail in the embodiment of the method for manufacturing a display panel discussed below.

[0061] According to some embodiments of the present application, the semiconductor layer of the thin film transistor includes a central doping region and an edge doping region surrounding the central doping region, the doping ions of the central doping region are different from the doping ions of the edge doping region, and the orthographic projection of the third opening in the gate metal layer on the substrate at least partially overlaps with the orthographic projection of the central doping region on the substrate. Continuing to refer to Figure 4a, the semiconductor layer includes a central doping region C0 and edge doping regions C1 and C2 surrounding the central doping region. In some embodiments, the central doping region C0 and the edge doping regions C1 and C2 are doped with ions of different elements. For example, the central doping region C0 may be doped with boron ions, while the edge doping regions C1 and C2 are both doped with boron ions and phosphorus ions. Furthermore, the central doping region C0 is a heavily doped region, and the edge doping regions C1 and C2 are lightly doped regions, that is, the ion doping concentration of the central doping region C0 is higher than the ion doping concentration of the edge doping regions C1 and C2. The orthographic projection of the third opening in the gate metal layer on the substrate at least partially overlaps with the orthographic projection of the central doped region on the substrate. Correspondingly, the orthographic projection of the transparent conductive layer in direct contact with the gate metal layer on the substrate at least partially overlaps with the orthographic projection of the central doped region on the substrate, thereby facilitating the positive influence of the voltage change on the gate layer on the movement of ions in the semiconductor layer, thereby ensuring the good performance of the thin film transistor.

[0062] In the embodiment of Figure 4a, the orthographic projection of the first opening in the first insulating layer IN1 on the substrate SB covers the orthographic projection of the third opening in the gate metal layer GM on the substrate. Furthermore, as shown in Figure 4a, in some embodiments, the third opening in the gate metal layer, the second opening in the second insulating layer IN2, and the first opening in the first insulating layer IN1 form a gate opening as a whole, and the transparent conductive layer GT in the gate layer extends along the inner wall of the gate opening to cover the gate opening. In some embodiments, the orthographic projection of the gate metal layer GM including the third opening on the substrate SB coincides with the orthographic projection of the central doped region C0 on the substrate SB. The "coincidence" mentioned herein means that the boundaries of the regions where the two projections are located are roughly the same, and does not mean that the regions where the two projections are located completely overlap. Furthermore, when the cross-section of the gate metal layer GM in a vertical direction perpendicular to the substrate is an irregular pattern, the coincidence of the orthographic projection of the gate metal layer GM on the substrate SB and the orthographic projection of the central doped region C0 on the substrate SB includes any of the following situations: the orthographic projection of the upper surface of the gate metal layer GM facing away from the substrate SB on the substrate is substantially consistent with the orthographic projection of the central doped region C0 on the substrate SB; the orthographic projection of the lower surface of the gate metal layer GM facing the substrate SB on the substrate is substantially consistent with the orthographic projection of the central doped region C0 on the substrate SB; and the outer boundary of the orthographic projection of the side surface of the gate metal layer GM between the upper and lower surfaces on the substrate is substantially consistent with the outer boundary of the orthographic projection of the central doped region C0 on the substrate SB. When ion doping is performed on the semiconductor material layer, the gate metal layer GM before etching can block ions intended for doping into the edge doped regions C1 and C2 from entering or being doped into the central doped region C0. Accordingly, the coverage area of ​​the gate metal layer GM and the coverage area of ​​the formed central doped region C0 can be substantially consistent. In some embodiments, the diameter of the orthographic projection of the third opening in the gate metal layer on the substrate is between 2 μm and 5 μm. The diameter mentioned here refers to the length of the shortest line segment connecting two points on the boundary of the orthographic projection of the third opening on the substrate and passing through the center point of the orthographic projection of the third opening on the substrate. Referring to the embodiments of Figures 2 and 4a, the diameter of the orthographic projection of the third opening in the gate metal layer on the substrate is the width d1 of the transparent conductive layer GT distributed on the bottom surface of the third opening in the width direction perpendicular to its length extension direction, and the above-mentioned width d1 is 3.5 μm. In addition, it can be understood that Figures 3 and 4a do not show the entire structure of the thin film transistor. For example, the thin film transistor may also include a passivation layer located on the side of the transparent conductive layer facing away from the substrate to protect the thin film transistor.

[0063] In some embodiments, the gate metal layer includes a gate metal material layer located on at least one side of the third opening, and the diameter of the orthographic projection of the gate metal material layer on the substrate is 1 / 8 to 1 / 6 of the diameter of the orthographic projection of the third opening on the substrate. Similarly, the diameter mentioned in this paragraph refers to the length of the shortest line segment connecting two points on the boundary of the orthographic projection of the gate metal material layer on the substrate and passing through the center point of the orthographic projection of the gate metal material layer on the substrate. Referring to the embodiments of Figures 2 and 4a, gate metal material layers are distributed on both sides of the third opening. The diameter of the orthographic projection of each gate metal material layer on the substrate is the width d2 of the gate metal material distributed on the gate insulating layer GI in the width direction perpendicular to its length extension direction, and the above-mentioned width d2 is approximately 0.5μm.

[0064] As shown in Figure 4a, a gate insulating layer GI is located between the semiconductor layer and the gate layer to isolate the gate layer from the semiconductor layer. A third opening in the gate metal layer GM exposes the gate insulating layer GI, allowing the transparent conductive layer GT to directly contact the gate insulating layer GI. Furthermore, although not shown in Figure 4a, the thin film transistor further includes a source and a drain. The source and drain may be located on a surface of the first insulating layer facing away from the substrate, and the source and drain are electrically connected to edge doped regions C1 and C2 of the semiconductor layer, respectively.

[0065] As previously mentioned, in some embodiments, the semiconductor layer includes a central doped region and an edge doped region surrounding the central doped region, and the gate metal layer GM may be completely removed. In this case, as shown in FIG4 b , the orthographic projection of the first opening in the first insulating layer IN1 on the substrate SB may coincide with the orthographic projection of the central doped region C0 on the substrate SB. Similarly, the term "coincidence" here means that the boundaries of the regions where the two projections are located are substantially consistent, and does not mean that the regions where the two projections are located completely overlap. In addition, when the cross-section of the first opening in the first insulating layer IN1 in a vertical direction perpendicular to the substrate is an irregular shape, the orthographic projection of the first opening on the substrate SB may coincide with the orthographic projection of the central doped region C0 on the substrate SB, including any of the following situations: the orthographic projection of the bottom surface of the first opening on the substrate is substantially consistent with the orthographic projection of the central doped region C0 on the substrate SB; the outer boundary of the orthographic projection of the sidewall of the first opening adjacent to the bottom surface on the substrate is substantially consistent with the outer boundary of the orthographic projection of the central doped region C0 on the substrate SB.

[0066] The main structure of the thin-film transistor provided by another embodiment of the present application is described below with reference to Figures 5 and 6. The structure of the thin-film transistor shown in Figure 6 is substantially the same as that of the thin-film transistor shown in Figure 4a, except that the thin-film transistor shown in Figure 6 further includes a light-blocking layer LS located on the side of the semiconductor layer SE facing the substrate SB, and the orthographic projection of the light-blocking layer LS on the substrate SB at least partially overlaps with the orthographic projection of the semiconductor layer SE on the substrate SE. Figure 6 also shows a buffer layer BF between the light-blocking layer LS and the semiconductor layer SE. The light-blocking layer LS may include a conductor or non-conductor material having light-blocking properties. The light-blocking layer LS can block light that may enter the thin-film transistor from the lower side of the substrate SB shown in Figure 6, thereby avoiding or reducing interference of light from other light sources with the light-sensing function of the thin-film transistor. In another embodiment, the light-blocking layer LS may also have light-reflecting properties. For example, light incident on the thin film transistor from above can reach the semiconductor layer SE through structures such as the transparent conductive layer GT. Some of the light may still continue to pass through the semiconductor layer SE and reach the light blocking layer LS. The light blocking layer LS can reflect the light incident from above back to the semiconductor layer SE, thereby helping to enhance the photosensitivity of the semiconductor layer SE.

[0067] Figure 6 is a partial top perspective view of a thin-film transistor corresponding to the cross-sectional view shown in Figure 5 . The cross-sectional view shown in Figure 6 can be considered to be taken along the dashed line B1-B2 shown in Figure 5 . Figure 5 actually shows a partial top perspective view of two thin-film transistors. The third opening in the gate metal layer and the vias used to connect the source S or drain D of the thin-film transistor to the semiconductor layer are collectively labeled CNT. As can be seen in Figure 5 , the transparent conductive layer GT in the gate layer is separated from the source S and drain D of the thin-film transistor. The transparent conductive layer GT extends horizontally along the elongated region but does not approach the source S and drain D. In Figure 5 , the source S or drain D of each thin-film transistor is electrically connected to the semiconductor layer via three conductive vias CNT. Furthermore, the sources of the two thin-film transistors shown in Figure 5 are electrically connected to each other, and the drains of the two thin-film transistors are electrically connected to each other. The two thin-film transistors may share the same transparent conductive layer GT. That is, the orthographic projection of the transparent conductive layer GT on the substrate at least partially overlaps with the orthographic projection of the semiconductor layers of the two thin-film transistors on the substrate. The extension length of the transparent conductive layer GT shown in FIG5 in the horizontal direction (x direction in FIG5 ) is not less than the sum of the dimensions of the semiconductor layers of the two thin film transistors in the horizontal direction. Therefore, the two thin film transistors shown in FIG5 actually form a parallel connection, and they can be controlled by the same signal. For two thin film transistors connected in parallel, they can have their own light blocking layer LS. As shown in FIG5 , the light blocking layer LS of each thin film transistor can extend close to the area where the source and drain are located, that is, the positive projection of the light blocking layer LS on the substrate can completely cover and exceed the positive projection of the corresponding transparent conductive layer on the substrate. The light blocking layers LS for the two thin film transistors can be separated from each other or formed as one. In other embodiments, more thin film transistors can share the same transparent conductive layer GT to achieve parallel connection of more thin film transistors.

[0068] According to another embodiment of the present application, the light blocking layer in the thin film transistor may include a conductive material, and the light blocking layer and the transparent conductive layer are electrically connected to each other. Since the light blocking layer and the transparent conductive layer are electrically connected to each other, the thin film transistor has the same potential when it is in operation. In other words, in this case, the light blocking layer plays a light blocking role on the one hand, and on the other hand, the light blocking layer actually forms part of the gate structure of the thin film transistor, thereby obtaining a dual-gate thin film transistor. By using this dual-gate thin film transistor, the current change when the thin film transistor is in the off state can be better sensed, thereby improving the sensitivity of detecting changes in light in the environment in which the thin film transistor is located.

[0069] According to some embodiments of the present application, the thin film transistor also includes an electrical connection layer on the surface of the first insulating layer facing away from the substrate, the transparent conductive layer extends to the outside of the first opening, the first insulating layer includes a first conductive via, and the transparent conductive layer is electrically connected to the light blocking layer at least via the electrical connection layer and the first conductive via.

[0070] In order to achieve mutual electrical connection between the light blocking layer and the transparent conductive layer, technicians in this field can make different designs according to the application scenarios of the thin-film transistor. This application does not impose any restrictions on this. The following is a schematic illustration of the implementation method of mutual electrical connection between the light blocking layer and the transparent conductive layer by applying thin-film transistors to display panels.

[0071] Figure 7 schematically illustrates a partial top perspective view of a display panel including the thin-film transistor described in the above-described embodiment. Figure 7 illustrates a single thin-film transistor and its surrounding connection structure. As shown in Figure 7 , similar to the embodiments shown in Figures 5 or 2 , the source electrode S and drain electrode D of the thin-film transistor are electrically connected to the semiconductor layer via three vias, respectively. In Figure 7 , one of the vias electrically connecting the drain electrode D to the semiconductor layer is labeled CNTb. In the embodiment of Figure 7 , a transparent conductive layer, which is part of the gate layer of the thin-film transistor, extends horizontally (in the x-direction in Figure 7 ) from the region between the source and drain electrodes to the left in the left region of Figure 7 . The material of the transparent conductive layer then extends vertically (in the y-direction in Figure 7 ) to form the large dotted-line region shown in Figure 7 . In some embodiments, the transparent conductive layer may be made of indium tin oxide (ITO). Figure 7 also illustrates an L-shaped dotted-line region that overlaps with the large dotted-line region (transparent conductive layer). This L-shaped dotted-line region is an example of the aforementioned electrical connection layer region. The area where the electrical connection layer area and the transparent conductive layer area overlap each other includes a via PLN, which passes through the second insulating layer and is located outside the second opening of the second insulating layer. It may be referred to as an external via PLN in this article. In some embodiments, the electrical connection layer may be formed on the surface of the first insulating layer facing away from the substrate and covered by the second insulating layer. The external via formed in the second insulating layer may expose the electrical connection layer, so that the transparent conductive layer may extend to the external via PLN and connect to the electrical connection layer. In some embodiments, the thin film transistor also includes a buffer layer between the semiconductor layer and the light blocking layer, and the buffer layer and the gate insulating layer respectively include a second conductive via and a third conductive via that are connected to the first conductive via in the first insulating layer. The electrical connection layer is electrically connected to the light blocking layer via the first conductive via, the second conductive via, and the third conductive via. In this way, electrical connection between the light blocking layer and the transparent conductive layer is achieved, forming a dual-gate thin film transistor.

[0072] FIG7 illustrates an example of a first conductive via, a second conductive via, and a third conductive via that are interconnected. In the plan view shown in FIG7 , the first conductive via, the second conductive via, and the third conductive via are illustrated as CNTa. Of course, the thin film transistor may include multiple such conductive vias CNTa. FIG8 shows a partial schematic cross-sectional view of a dual-gate thin film transistor. The cross-sectional view shown in the right half of FIG8 is obtained along the dotted line c1-c2 in FIG7 , which is similar to the cross-sectional view of the thin film transistor shown in FIG6 . The left half of FIG8 illustrates a composite view of the partial cross-sectional views obtained along the dotted line e1-e2 and the dotted line d1-d2 in FIG7 . In FIG8 , the transparent conductive layer is still labeled GT, which corresponds to the ITO in FIG7 . In the example of FIG7 , the electrical connection layer EL is roughly L-shaped. For simplicity, the electrical connection layer EL is simplified as a small conductive layer on the first insulating layer IN1 because FIG8 is mainly used to illustrate the electrical connection between the light blocking layer LS and the transparent conductive layer GT. Combining Figures 7 and 8 , it can be understood that the area where the light-blocking layer LS extends above the substrate exceeds the area where the semiconductor layer SE extends on the substrate. However, the light-blocking layer LS does not extend to the transparent conductive layer indicated by the large dashed-line area in Figure 7 . Therefore, the light-blocking layer is electrically connected to the transparent conductive layer via an L-shaped electrical connection layer that overlaps the transparent conductive layer. In Figure 7 , the L-shaped electrical connection layer is insulated from the drain electrode D and source electrode S of the thin-film transistor.

[0073] In some embodiments, the electrical connection layer EL includes the same material as the source and drain of the thin film transistor. The source or drain may include a metal material such as titanium, and accordingly, the electrical connection layer EL may be made on the first insulating layer IN1 based on the same process as the source and drain. In addition, the electrical connection layer including the same material as the source or drain can reduce the overall resistance on the connection line of the two gates of the dual-gate thin film transistor (one of which mainly includes a transparent conductive layer and the other mainly includes a light blocking layer). The planar schematic diagram shown in Figure 7 can also be further extended and replicated in the vertical direction, that is, a plurality of thin film transistors can continue to be formed above or below the thin film transistor shown in Figure 7, and the gates of these thin film transistors can be electrically connected to each other via the transparent conductive layer shown in the rectangular dotted box in Figure 7, thereby forming a plurality of dual-gate thin film transistors connected in parallel.

[0074] Figure 9 illustrates the current-voltage curve corresponding to the thin film transistor shown in Figure 4a. The abscissa in Figure 9 represents the voltage Vg applied to the gate layer of the thin film transistor, and the ordinate represents the current Id flowing through the drain of the thin film transistor. The darker curve in Figure 9 represents the current-voltage characteristic curve of the thin film transistor in a darker environment, and the lighter curve represents the current-voltage characteristic curve of the thin film transistor in a brighter environment. It can be seen from Figure 9 that under the influence of external ambient light, the leakage current when the thin film transistor is in the off state (cut-off state) is significantly increased. Therefore, the thin film transistor provided in the embodiment of the present application has a strong photosensitivity characteristic.

[0075] Accordingly, another embodiment of the present application provides a sensor comprising at least one thin film transistor as described in any of the aforementioned embodiments. Utilizing the light-sensitive properties of the thin film transistors proposed in the embodiments of the present application, the sensor can sense changes in ambient light.

[0076] In some embodiments, the sensor may include multiple thin-film transistors (TFTs) described above, connected in parallel, with their gate layers electrically connected to one another. That is, the sources of the TFTs are electrically connected together, the drains of the TFTs are electrically connected together, and the gate layers of the TFTs are controlled by the same control signal. This allows the sensor to detect larger changes in leakage current based on changes in ambient light, improving the sensor's ability to sense changes in ambient light.

[0077] In some embodiments, the thin-film transistors described in the above embodiments can be applied to display panels, thereby detecting changes in ambient light based on the light-sensitive properties of the thin-film transistors. Based on these changes in ambient light, the display brightness of the display panel can be appropriately controlled, thereby improving the user experience of using the display device in different environments. In some embodiments, the display panel includes a display area and a non-display area peripheral to the display area. The display panel includes a thin-film transistor as described in any of the above embodiments, and the thin-film transistor can be located in the non-display area. In this way, the thin-film transistor located in the non-display area can act as a light-sensing element of the display panel, thereby providing a light-sensing signal to the controller of the display panel.

[0078] Another embodiment of the present application provides a display device, which includes the display panel described in the above embodiment. The display panel mentioned herein refers to a factory display product with basic image display function, and the display device refers to any form of display product that can be used by users and includes a display panel. Compared with the display panel, the display device may include components that are not directly related to the display function. For example, the display device may not have a frame, while the display device may include a frame for supporting or including a display panel. The display device includes any electronic device with a display function. Examples of display devices include but are not limited to various types of computers, televisions, watches, car displays, etc.

[0079] In some embodiments, the display device is a liquid crystal display including a backlight source. When a thin film transistor in a non-display area of ​​the liquid crystal display senses a change in ambient light, it can provide a light sensing signal to a controller of the liquid crystal display, whereby the controller can adaptively adjust the brightness of the display screen of the liquid crystal display based on the light sensing signal. For example, when the liquid crystal display is transferred from a darker indoor environment to an outdoor environment with stronger ambient light, the thin film transistor can generate a larger leakage current signal, which is provided to the controller. The controller then controls the backlight source to enhance the luminous intensity based on the leakage current signal, thereby improving the screen display brightness of the liquid crystal display, improving the user's viewing experience of the liquid crystal display under strong outdoor ambient light, and enhancing the user experience of the liquid crystal display.

[0080] Figures 10 and 11 illustrate a planar image and a cross-sectional image of a thin film transistor according to an embodiment of the present application, respectively. The images shown in Figures 10 and 11 were obtained using a scanning electron microscope (SEM). The roughly rectangular gray area presented in the center of Figure 10 corresponds to the area of ​​the transparent conductive layer in the gate layer of the thin film transistor. In the cross-sectional image shown in Figure 11, a transparent conductive layer ITO and a gate metal layer in contact with the transparent conductive layer ITO are shown. The gate metal layer includes molybdenum, and the gate metal layer is labeled Mo in Figure 11. The gate metal layer Mo can be a metal material layer left over from the processing required for the process of manufacturing the thin film transistor.

[0081] As shown in FIG12 , another embodiment of the present application provides a method for manufacturing a display panel, the display panel including a substrate, the method including: S1201, forming a semiconductor material layer on the substrate; S1202, forming a gate insulating layer and a gate metal layer on the semiconductor material layer, the gate metal layer being located on a side of the gate insulating layer facing away from the substrate; S1203, ion doping the semiconductor material layer to obtain a semiconductor layer; S1204, at least partially removing the gate metal layer to expose the gate insulating layer; and S1205, forming a transparent conductive layer on the gate insulating layer. In some embodiments, the semiconductor material layer in step S1201 includes low-temperature polysilicon. In some embodiments, ion doping can be performed on the low-temperature polysilicon material to dope boron ions into the low-temperature polysilicon, that is, the semiconductor material layer includes low-temperature polysilicon doped with boron ions. The gate metal layer manufactured in step S1202 may include a molybdenum metal layer. In step S1203, an ion doping process can be used to ion-dope the semiconductor material layer to obtain a semiconductor layer, such that the central and edge regions of the semiconductor layer are doped with ions of different elements. For example, the central doped region is doped with boron ions, while the edge doped region is doped with boron ions and phosphorus ions. Specifically, a phosphorus ion doping process can be performed on the semiconductor material layer. During this process, the gate metal layer produced can block phosphorus ions from entering the region covered by the gate metal layer, so that phosphorus ions can only be doped into the region of the semiconductor material layer not covered by the gate metal layer. As a result, the region of the semiconductor layer corresponding to the gate metal layer is doped only with boron ions, while the remaining regions of the semiconductor layer are doped with boron ions and phosphorus ions. Accordingly, the central doped region of the semiconductor layer substantially corresponds to the region covered by the gate metal layer. In step S1204, a wet etching process can be used to at least partially remove the gate metal layer to expose the gate insulating layer. The etchant that can be used in the wet etching process can include, for example, nitric acid, acetic acid, or phosphoric acid. In step S1205, a transparent conductive layer is formed on the exposed gate insulating layer.

[0082] In some embodiments, after the gate metal layer and the semiconductor layer are formed, an insulating layer covering the gate metal layer and the semiconductor layer (for example, the aforementioned first insulating layer IN1 and second insulating layer IN2) may be formed. Then, in the above-mentioned step S1204, the gate metal layer is at least partially removed by etching to expose the gate insulating layer. Figure 13 schematically illustrates the process of forming a transparent conductive layer after removing the gate metal layer by a wet etching process. Figure 13 only shows a portion of the insulating layer at the position of the gate metal layer GM. In the process of manufacturing the display panel, the gate metal layer GM can be formed in the same process as the structures in other areas of the display panel. For example, the gate metal layer GM can be formed in the same process as the gate of the pixel switch in the display area of ​​the display panel, and the gate line for transmitting the control signal to the pixel switch in the patterning process for the same gate metal film. The formed first insulating layer IN1 and second insulating layer IN2 can cover the gate of the pixel switch and the gate line for transmitting the control signal to the pixel switch to protect the gate line and the gate of the pixel switch. Therefore, as shown in FIG13 , after forming the first insulating layer IN1 and the second insulating layer IN2, a first opening is formed in the first insulating layer, a second opening is formed in the second insulating layer, and a third opening is formed in the gate metal layer through an etching process. The first opening, the second opening, and the third opening are interconnected and expose at least a portion of the gate insulating layer. Thus, a transparent conductive layer GT can be formed on the exposed gate insulating layer GI. The gate metal layer GM may not be completely removed, but may leave a portion of the gate metal material. The transparent conductive layer formed thereafter may be in direct contact with the remaining gate metal layer. Of course, under ideal process conditions, the gate metal layer can be completely removed. In this way, the gate layer of the formed thin-film transistor only includes the transparent conductive layer material. Because the gate layer includes the transparent conductive layer, external ambient light can reach the semiconductor layer of the thin-film transistor at least through the transparent conductive layer, causing the semiconductor layer to be exposed to light and generate leakage current, resulting in a change in the current flowing through the thin-film transistor. Thus, manufacturing a display panel based on the method provided in this embodiment allows the resulting display panel to integrate a thin-film transistor with a light-sensitive function. This light-sensitive thin-film transistor can replace other specialized light sensors, thereby achieving true integration of the light sensor and the display panel, which is beneficial for reducing the size of the display panel. Furthermore, compared with existing display panel manufacturing processes, the above-described display panel manufacturing process only adds an etching process for the gate metal layer and does not increase the number of masks required for the display panel manufacturing process, thereby controlling the cost of manufacturing the display device.

[0083] According to some embodiments of the present application, the display panel includes a pixel electrode in the display area, and the method for manufacturing the display panel may include: forming the transparent conductive layer in the process of forming the pixel electrode. The pixel electrode here can be, for example, the pixel electrode of each pixel area on the array substrate of the liquid crystal display, and the pixel electrode can form an electric field with the common electrode to control the deflection of the liquid crystal. Forming the transparent conductive layer in the process of forming the pixel electrode means that the pixel electrode in the display area and the transparent conductive layer of the thin film transistor in the non-display area can be based on the same material and formed in the same composition process. For example, the pixel electrode and the transparent conductive layer are both formed of indium tin oxide material. Thereby, the process of manufacturing a display device including a thin film transistor with a light sensing function can be simplified, and at the same time, the light sensor element can be truly integrated inside the display device.

[0084] In addition, the other layer structures of the thin film transistor can correspond to the layer structures of the switching devices for driving the pixels to emit light in the display area of ​​the display panel, respectively. Therefore, the other layer structures of the thin film transistor can be manufactured in the same process as the layer structures corresponding to the switching devices in the display area. For example, the gate metal layer can be formed in the same process as the gate of the thin film transistor in the display area of ​​the display panel or the gate line connected to the gate. Therefore, based on the method for manufacturing a display panel provided by the embodiment of the present disclosure, a thin film transistor with photosensitive characteristics can be manufactured in the non-display area of ​​the display panel, and based on the thin film transistor with photosensitive characteristics, a detection of ambient light can be formed, thereby making the light sensor in the form of a non-chip inside the display panel, realizing the true integration of the light sensor and the display device, which is conducive to reducing the volume of the display device, and does not lead to an increase in the number of masks required for the process of manufacturing the display panel, thereby controlling the cost of manufacturing the display device.

[0085] As mentioned above, a thin film transistor as described in any of the aforementioned embodiments can be made in the non-display area of ​​the display panel. In this way, the thin film transistor located in the non-display area can act as a light sensing element of the display panel, thereby providing a light sensing signal to the controller of the display panel. In some embodiments, the display panel includes a plurality of thin film transistors as described in any of the aforementioned embodiments, and these transistors can form N groups of thin film transistors, each group of thin film transistors includes at least two thin film transistors, and the at least two thin film transistors are connected in parallel, wherein each group of thin film transistors in the N groups of thin film transistors is configured to independently output an electrical signal reflecting ambient light (i.e., the leakage current mentioned above), and N is an integer greater than or equal to 2. The following is further explained by taking the aforementioned multiple thin film transistors to form four groups of thin film transistors as an example. As shown in Figures 14 and 15, multiple thin film transistors form four groups of thin film transistors, and these four groups of thin film transistors are represented as R, G, B and D respectively. Each group of transistors includes two thin film transistors connected in parallel to each other. In other embodiments, the above-mentioned multiple thin film transistors can form more groups of thin film transistors, and each group of transistors can include more than three thin film transistors connected in parallel to each other. In the example of FIG15 , two adjacent groups of transistors can share the same control signal line and thus be controlled by the same control signal. For example, the gates of each thin-film transistor in thin-film transistor group R and thin-film transistor group G are electrically connected to control terminal G1, and the gates of each thin-film transistor in thin-film transistor group B and thin-film transistor group D are electrically connected to control terminal G2. This reduces the number of control signal lines and the space occupied. DR, DG, DB, and DD in FIG15 correspond to the drains of different thin-film transistors and also serve as the sensing current output terminals of the aforementioned four groups of thin-film transistors. That is, each group of thin-film transistors outputs a corresponding leakage current from terminals DR, DG, DB, and DD, respectively, when exposed to external light. S1 and S2 in FIG15 correspond to the sources of different thin-film transistors and also serve as the voltage input terminals of the aforementioned four groups of thin-film transistors. In FIG15 , two adjacent groups of transistors can share the same input voltage connection line. For example, the source of each thin-film transistor in thin-film transistor group R and thin-film transistor group G is electrically connected to voltage input terminal S1, and the source of each thin-film transistor in thin-film transistor group B and thin-film transistor group D is electrically connected to voltage input terminal S2. This reduces the number and space occupied by input voltage connection lines for transmitting input voltages. The voltages received by voltage input terminals S1 and S2 can be set based on the actual power supply voltage of the display panel. For example, the voltages received by voltage input terminals S1 and S2 can be 3V, 6V, or 9V, etc.The control terminals G1 and G2 mentioned above can also be set according to the specific type of thin film transistor. For example, the voltage of the control signal provided from the control terminals G1 and G2 can be -2V to 0V, and the characteristics of the cutoff region of the IV characteristic curve of the thin film transistor can be captured by adjusting the voltage of the control signal.

[0086] Continuing with FIG. 14 , the non-display area of ​​the display panel surrounds the display area AA (the annular area indicated by the dotted line in FIG. 14 ), such that the non-display area includes a first non-sub-display area NA1 and a second non-sub-display area NA2 that face each other, and a third non-sub-display area NA3 and a fourth non-sub-display area NA4 that face each other. In some embodiments, the display panel further includes a cover plate ink area at least within the first non-sub-display area NA1, with the N groups of thin-film transistors located between the cover plate ink area and the display area AA. The cover plate ink area is a region of the cover plate of the display panel in which ink material is formed. The ink within the cover plate ink area protects the display panel screen from scratches and wear, while also enhancing the aesthetics of the display panel.

[0087] Figure 16 illustrates a partially enlarged view of the first non-sub-display area NA1 shown in Figure 14 . The area containing the N thin-film transistors is shown in a grid format in Figure 16 and labeled SEN. The lower boundary of the cover ink area within the first non-sub-display area NA1 is labeled CG, and the boundary between the display area AA and the first non-sub-display area NA1 is labeled UA, i.e., the upper boundary of the display area AA. As shown in Figure 16 , the N thin-film transistors SE are located between the cover ink area and the display area. There is a certain gap between the area SE containing the N thin-film transistors and the upper boundary UA of the display area AA, as well as the lower boundary CG of the cover ink area. In some implementations, the vertical distance a3 between the lower boundary CG of the cover plate ink zone and the upper boundary UA of the display area AA is approximately 0.25 mm. The region where the N sets of thin-film transistors are located can be formed into a long strip shape. The vertical distance a1 between the upper edge of the long strip region SE and the lower boundary CG of the cover plate ink zone is approximately 0.13 mm, and the vertical distance a2 between the upper edge of the long strip region SE and the upper boundary UA of the display area AA is approximately 0.12 mm. As a result, the N sets of thin-film transistors acting as light sensors can reduce the space occupied by the display area while being protected from the influence of the ink material in the cover plate ink zone, thereby effectively sensing changes in ambient light.

[0088] According to some embodiments of the present application, the display panel further includes a light-blocking layer located above the N groups of thin film transistors, the light-blocking layer including a plurality of openings, the plurality of openings respectively exposing the N-1 groups of thin film transistors in the N groups of thin film transistors, and the display panel further includes a color filter layer located in the plurality of openings. As shown in FIG15 , the light-blocking layer BM includes a plurality of openings, the number of openings corresponding to N-1, so as to respectively expose the N-1 groups of thin film transistors in the N groups of thin film transistors. In FIG15 , the light-blocking layer BM includes openings corresponding to the thin film transistor groups R, G, and B, and a color filter layer can be formed in these openings, that is, the thin film transistor groups R, G, and B are covered by the color filter layer, while the thin film transistor group D is covered by the light-blocking layer. The light-blocking layer mainly includes an opaque material to block ambient light from reaching a group of thin film transistors in the N groups of thin film transistors. In the embodiment of FIG15 , the light-blocking layer is formed of the same material as a conventional black matrix in a display device. Furthermore, during the manufacturing process of the display panel, a black matrix material layer can be first formed above the thin-film transistor groups R, G, B, and D. Then, openings are formed in the black matrix material layer corresponding to the thin-film transistor groups R, G, and B. The color filter layer can fill the openings in the black matrix material layer, thereby allowing the color filter layer to cover the thin-film transistor groups R, G, and B. During operation of the display panel, the electrical signal output by the group of thin-film transistors covered by the light-blocking layer changes relatively little, which can serve as a reference signal. The electrical signals output by the remaining thin-film transistor groups in the N groups of thin-film transistors can be compared with this reference signal, thereby generating multiple corresponding electrical signal differences. Based on these differences, changes in the ambient light environment in which the display panel is located can be determined. For example, the thin-film transistor groups R, G, and B shown in FIG15 can each output corresponding leakage currents based on the received ambient light. These leakage currents can be compared with the leakage current output by thin-film transistor group D to obtain three leakage current differences. When the average value of the three leakage current differences exceeds the threshold, it is determined that the ambient light of the display panel has changed significantly, and then the display brightness of the display panel is appropriately controlled based on the change in ambient light, thereby improving the user experience of using the display device in different environments.

[0089] The color filter layer covering the thin-film transistor groups R, G, and B includes a red color-resistance layer, a green color-resistance layer, and a blue color-resistance layer. The red, green, and blue color-resistance layers respectively cover different groups of thin-film transistors in the N-1 group of thin-film transistors. For example, as shown in FIG15 , the red color-resistance layer covers the thin-film transistor group R, the green color-resistance layer covers the thin-film transistor group G, and the blue color-resistance layer covers the thin-film transistor group B. The red, green, and blue color-resistance layers can filter ambient light, so that the external light received by the thin-film transistor groups R, G, and B primarily includes red light, green light, and blue light, respectively. This improves the accuracy of the thin-film transistor groups R, G, and B in sensing changes in external ambient light.

[0090] It is understood that the N groups of thin-film transistors acting as light sensors can be controlled by a corresponding controller, which can be located in the non-display area of ​​the display panel. As shown in Figure 14, the display panel also includes a controller IC located in the second non-sub-display area NA2. The controller IC is electrically connected to the N groups of thin-film transistors via signal lines SL. The non-display area of ​​the display panel also includes a third non-sub-display area NA3 and a fourth non-sub-display area NA4 that face each other. The signal line extends from the controller IC through at least one of the third non-sub-display area NA3 and the fourth non-sub-display area NA4 to electrically connect to the N groups of thin-film transistors. Figure 14 illustrates the signal line SL extending through the third non-sub-display area NA3 and the fourth non-sub-display area NA4. However, in other embodiments, the signal line SL may be provided only in the third non-sub-display area NA3 or the fourth non-sub-display area NA4.

[0091] It will be understood that although the terms "first," "second," and "third" may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms and only represent distinctions in terms of name. In addition, the "electrical connection" mentioned herein includes "direct connection" or "indirect connection." Although the technical solutions of the present application have been described in conjunction with some embodiments, the scope of protection of the present application is not limited to the specific forms set forth herein, and the scope of the present application is defined by the appended claims.

Claims

1. A thin film transistor, characterized in that: The thin film transistor includes: substrate; a semiconductor layer located above the substrate; and a gate layer located on a side of the semiconductor layer facing away from the substrate, wherein the gate layer comprises a transparent conductive layer, The thin film transistor further includes a first insulating layer located on the side of the semiconductor layer facing away from the substrate, the first insulating layer includes a first opening, the orthographic projection of the first opening on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the transparent conductive layer extends along at least a portion of the inner wall of the first opening.

2. The thin film transistor according to claim 1, wherein the thin film transistor further comprises a second insulating layer located on a side of the first insulating layer facing away from the semiconductor layer, the second insulating layer comprising a second opening connected to the first opening, wherein the transparent conductive layer further extends along at least a portion of an inner wall of the second opening.

3. The thin film transistor according to claim 2, wherein the orthographic projection of the second opening on the substrate covers the orthographic projection of the first opening on the substrate, and the orthographic projection of the transparent conductive layer on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate.

4. The thin film transistor according to claim 3, wherein the gate layer further includes a gate metal layer, the first insulating layer covers the gate metal layer, the gate metal layer includes a third opening, the first opening is connected to the third opening, and the transparent conductive layer further extends along at least a portion of an inner wall of the third opening and is in direct contact with the gate metal layer.

5. The thin film transistor according to claim 4, wherein the semiconductor layer includes a central doping region and an edge doping region surrounding the central doping region, the doping ions in the central doping region are different from the doping ions in the edge doping region, and the orthographic projection of the gate metal layer including the third opening on the substrate coincides with the orthographic projection of the central doping region on the substrate. 6 . The thin film transistor according to claim 4 , wherein the third opening, the second opening, and the first opening integrally form a gate opening, and the transparent conductive layer extends along an inner wall of the gate opening to cover the gate opening.

7. The thin film transistor according to claim 5, wherein the thin film transistor further comprises a source and a drain, the source and the drain being located on a surface of the first insulating layer facing away from the substrate, and the source and the drain being electrically connected to edge doped regions of the semiconductor layer, respectively.

8. The thin film transistor according to claim 1, wherein the semiconductor layer includes a central doping region and an edge doping region surrounding the central doping region, the doping ions in the central doping region are different from the doping ions in the edge doping region, and the orthographic projection of the first opening on the substrate coincides with the orthographic projection of the central doping region on the substrate.

9. The thin film transistor according to claim 2, wherein the thin film transistor further comprises a light blocking layer located on a side of the semiconductor layer facing the substrate, and an orthographic projection of the light blocking layer on the substrate at least partially overlaps with an orthographic projection of the semiconductor layer on the substrate.

10. The thin film transistor according to 9, wherein the light blocking layer comprises a conductive material, and the light blocking layer and the transparent conductive layer are electrically connected to each other.

11. According to the thin film transistor described in 10, the thin film transistor also includes an electrical connection layer on the surface of the first insulating layer facing away from the substrate, the transparent conductive layer extends to the outside of the first opening, the first insulating layer includes a first conductive via, and the transparent conductive layer is electrically connected to the light blocking layer at least via the electrical connection layer and the first conductive via.

12. The thin film transistor according to claim 11 , wherein the thin film transistor further comprises a gate insulating layer located between the semiconductor layer and the gate layer, wherein the second insulating layer comprises an external via hole located outside the second opening, and the transparent conductive layer is electrically connected to the electrical connection layer via the external via hole. The thin film transistor further includes a buffer layer between the semiconductor layer and the light blocking layer, the buffer layer and the gate insulation layer respectively include a second conductive via and a third conductive via connected to the first conductive via, and the electrical connection layer is electrically connected to the light blocking layer via the first conductive via, the second conductive via and the third conductive via. 13 . The thin film transistor according to claim 11 , wherein the electrical connection layer comprises the same material as a source electrode and a drain electrode of the thin film transistor. 14 . The thin film transistor according to claim 6 , wherein a diameter of an orthographic projection of the third opening on the substrate is between 2 μm and 5 μm.

15. The thin film transistor according to claim 14, wherein the gate metal layer comprises a gate metal material layer located on at least one side of the third opening, wherein a diameter of an orthographic projection of the gate metal material layer on the substrate is 1 / 8 to 1 / 6 of a diameter of an orthographic projection of the third opening on the substrate.

16. A sensor, characterized in that: The sensor comprises at least one thin film transistor according to any one of claims 1-15.

17. The sensor according to 16, wherein the sensor comprises a plurality of thin film transistors according to any one of claims 1 to 15 connected in parallel with each other, and gate layers of the thin film transistors connected in parallel with each other are electrically connected with each other.

18. A display panel comprising a display area and a non-display area, characterized in that: The display panel includes at least one thin film transistor according to any one of claims 1 to 15, and the thin film transistor is located in the non-display area.

19. The display panel according to claim 18, wherein the display panel comprises a plurality of thin film transistors according to any one of claims 1 to 15, and the plurality of thin film transistors according to any one of claims 1 to 15 form N groups of thin film transistors, each group of thin film transistors comprises at least two thin film transistors, and the at least two thin film transistors are connected in parallel, wherein each group of thin film transistors in the N groups of thin film transistors is configured to independently output an electrical signal reflecting ambient light, and N is an integer greater than or equal to 2.

20. The display panel according to claim 19, wherein the non-display area surrounds the display area so that the non-display area includes a first non-sub-display area and a second non-sub-display area facing each other, and the display panel further includes a cover ink area at least within the first non-sub-display area, wherein the N groups of thin film transistors are located between the cover ink area and the display area.

21. The display panel according to claim 19, wherein the display panel further comprises a light-blocking layer above the N groups of thin film transistors, wherein the light-blocking layer comprises a plurality of openings, the plurality of openings respectively exposing N-1 groups of thin film transistors in the N groups of thin film transistors, and the display panel further comprises a color filter layer located in the plurality of openings.

22. The display panel according to claim 21, wherein the color filter layer comprises a red color resist layer, a green color resist layer, and a blue color resist layer, and the red color resist layer, the green color resist layer, and the blue color resist layer respectively cover different groups of thin film transistors in the N-1 group of thin film crystals.

23. A display panel according to claim 20, wherein the display panel further comprises a controller located in the second non-sub-display area, the controller being electrically connected to the N groups of thin film transistors via signal lines, wherein the non-display area further comprises a third non-sub-display area and a fourth non-sub-display area directly opposite each other, the signal line extending from the controller through at least one of the third non-sub-display area and the fourth non-sub-display area and being electrically connected to the N groups of thin film transistors.

24. A method for manufacturing a display panel, the display panel comprising a substrate, the method comprising: forming a semiconductor material layer on the substrate; forming a gate insulating layer and a gate metal layer on the semiconductor material layer, wherein the gate metal layer is located on a side of the gate insulating layer facing away from the substrate; performing ion doping on the semiconductor material layer to obtain a semiconductor layer; at least partially removing the gate metal layer to expose the gate insulating layer; as well as A transparent conductive layer is formed on the gate insulating layer.

25. The method according to claim 24, wherein the display panel comprises a pixel electrode in the display area, the method further comprising: The transparent conductive layer is formed in the process of forming the pixel electrode.

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