Lower electrode system, semiconductor process device and control method

Abstract

The present application provides a lower electrode system, a semiconductor process device and a control method. The system comprises a bearing apparatus and an ejector pin apparatus, wherein the ejector pin apparatus is used to lift a wafer on the bearing apparatus or place a wafer onto the bearing apparatus, and further comprises a grounding apparatus; the grounding apparatus comprises a grounding circuit, a grounding switch and a control unit, wherein the grounding circuit is electrically connected to a lower electrode in the bearing apparatus by means of the grounding switch and is used for grounding the lower electrode when the grounding switch is closed; and the control unit is used for controlling the grounding switch to be open in respond to the starting of a semiconductor process, and controlling the grounding switch to be closed in response to the ending of the semiconductor process, wherein the ending of the semiconductor process comprises: a plasma generation stage ends, and the ejector pin apparatus lifts the wafer on the bearing apparatus. The scheme can improve the wafer repetition transmission precision, and ensures that an AWC result meets requirements.

Description

Lower electrode system, semiconductor process equipment and control method Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a lower electrode system, semiconductor process equipment, and a control method. Background Art

[0002] In advanced semiconductor edge etching equipment, the etcher etches the edge of the wafer after completing process steps such as photolithography, desmearing, deposition, or etching, removing edge polymer to reduce defects in subsequent process flows and improve product yield. In edge etching equipment, the wafer is usually placed on a carrier within the process chamber. During the edge etching process, due to the DC bias phenomenon, the wafer and the lower electrode in the carrier are both negatively charged. If the accumulated charge cannot be discharged in a timely and effective manner, it will accumulate on the wafer surface, causing particle problems. The charge will also accumulate inside the lower electrode. Because the lower electrode usually has gaps and channels, for example, if the lower electrode is provided with a gas delivery channel, the accumulated charge on the lower electrode will generate a potential difference with the cooling gas flowing into the channel. If the channel space is large, there is a risk of discharge and sparking. Once a discharge and spark occurs, it often causes electrical damage or even serious damage to the lower electrode. Therefore, the lower electrode needs to be grounded to conduct away the negative charge of the lower electrode. At the same time, the wafer also needs to be grounded to conduct away the negative charge of the wafer to avoid particle and spark problems.

[0003] However, at the end of the process, the lower electrode, which has been in a grounded state, will conduct the negative charge accumulated inside the lower electrode into the ground when the RF power is turned off. At this time, the wafer on the carrier is still negatively charged, and there is a potential difference between the wafer and the lower electrode, which in turn causes electrostatic adsorption between the wafer and the lower electrode, causing the wafer to shift during the needle lifting process, resulting in the AWC (Active Wafer Centering, wafer automatic correction) result failing to meet the requirements. Summary of the Invention

[0004] This application aims to solve at least one of the technical problems existing in the prior art, and proposes a lower electrode system, semiconductor process equipment and control method, which can solve the problem of wafer deviation during the needle lifting process due to electrostatic adsorption between the wafer and the lower electrode.

[0005] To achieve the objectives of the present application, a lower electrode system is provided, which is applied to semiconductor process equipment and includes a carrier device and an ejector pin device, wherein the ejector pin device is used to lift a wafer on the carrier device or place a wafer on the carrier device, and further includes a grounding device, wherein the grounding device includes a grounding circuit, a grounding switch, and a control unit, wherein the grounding circuit is electrically connected to the lower electrode in the carrier device through the grounding switch, and is used to ground the lower electrode when the grounding switch is turned on;

[0006] The control unit is used to control the grounding switch to be disconnected in response to the start of a semiconductor process, and to control the grounding switch to be connected in response to the end of the semiconductor process; wherein the end of the semiconductor process includes: the end of the plasma generation stage, and the ejector device lifting the wafer on the carrier device.

[0007] In some embodiments, the ejector device is configured to lift the wafer on the carrier device and then ground the wafer.

[0008] In some embodiments, the ejector device is configured to be electrically connected to the grounding switch through the lower electrode, so as to ground the wafer on the ejector device when the control unit controls the grounding switch to be turned on.

[0009] In some embodiments, the ejector pin device includes a plurality of conductive ejector pins and a plurality of conductive ejector pin bellows, wherein a plurality of through holes are provided in the carrier device and are spaced apart along the circumference of the carrier device, and the plurality of ejector pins are arranged in a one-to-one correspondence and can be raised and lowered through the plurality of through holes; the plurality of ejector pin bellows are arranged in a one-to-one correspondence on the plurality of ejector pins, and the upper end of each ejector pin bellows is sealed and connected to the carrier device and is electrically conductive; the lower end of each ejector pin bellows is sealed and connected to the corresponding ejector pin and is electrically conductive.

[0010] In some embodiments, a radio frequency feeding device is further included, wherein the radio frequency feeding device is electrically connected to the lower electrode and is used to be electrically connected to a radio frequency power supply through a matcher to load radio frequency power to the lower electrode.

[0011] In some embodiments, the grounding circuit includes a circuit for connecting between the lower electrode and the ground, and a grounding resistor connected in series to the grounding circuit; the grounding switch is connected in series to the grounding circuit and is located on the side of the grounding resistor close to the lower electrode.

[0012] In some embodiments, the resistance of the grounding resistor is greater than or equal to 5 MΩ and less than or equal to 20 MΩ.

[0013] As another technical solution, the present application also provides a semiconductor process equipment, including a process chamber and the above-mentioned lower electrode system provided in the present application, at least some components of the lower electrode system are located in the process chamber.

[0014] In some embodiments, the semiconductor processing equipment includes a wafer edge etching equipment.

[0015] As another technical solution, the present application also provides a semiconductor process equipment control method, which is applied to the above-mentioned lower electrode system provided in the present application, comprising:

[0016] In response to a semiconductor process starting, controlling the ground switch to be opened;

[0017] In response to the semiconductor process being completed, controlling the ground switch to be turned on;

[0018] The semiconductor process includes: the plasma generation stage ends, and the ejector device lifts the wafer on the carrier device.

[0019] In some embodiments, before the semiconductor process begins, the process further includes:

[0020] Controlling the chamber pressure to reach a first pressure value;

[0021] In response to placing the wafer on the carrier, process gas is introduced into the process chamber, and the chamber pressure is controlled to reach a second pressure value; the second pressure value is greater than the first pressure value to form a pressure difference between the upper surface and the lower surface of the wafer, thereby fixing the wafer on the carrier.

[0022] This application has the following beneficial effects:

[0023] In the technical solutions of the lower electrode system, semiconductor process equipment, and control method provided in this application, by controlling the ground switch to be disconnected before the plasma generation phase of the semiconductor process begins, the lower electrode in the carrier device is disconnected from the ground. Therefore, during the plasma generation phase, the negative charge accumulated in the lower electrode is not discharged, and the lower electrode and the wafer accumulate negative charge simultaneously, so that the lower electrode and the wafer are both negatively charged and have substantially the same potential. This avoids a potential difference between the wafer and the lower electrode, and prevents electrostatic adsorption between the two. Consequently, when the ejector device lifts the wafer from the carrier device, the wafer is not deflected due to electrostatic adsorption, thereby effectively improving the repeatable transfer accuracy of the wafer and ensuring that the AWC (wafer automatic correction) results meet the requirements. Furthermore, after the plasma generation phase ends and the ejector device lifts the wafer from the carrier device, controlling the ground switch to be connected can ground the lower electrode, thereby allowing the accumulated charge in the lower electrode to be discharged and avoiding sparking problems within the lower electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a structural diagram of a lower electrode system and semiconductor process equipment provided in an embodiment of the present application;

[0025] FIG2 is a timing diagram of a ground switch input signal and RF power in an embodiment of the present application;

[0026] FIG3 is a state diagram of the lower electrode system provided in an embodiment of the present application during the plasma generation stage;

[0027] FIG4 is a state diagram of the lower electrode system provided by an embodiment of the present application when the ejector device holds up the wafer;

[0028] FIG5 is a state diagram of the lower electrode system provided in an embodiment of the present application when the plasma generation stage ends and the ejector pin device lifts the wafer;

[0029] FIG6 is an AWC result diagram of the related art;

[0030] FIG7 is an AWC result diagram of an embodiment of the present application;

[0031] FIG8 is a flow chart of a lower electrode system control method used in a semiconductor process equipment according to an embodiment of the present application;

[0032] FIG9 is another flow chart of a lower electrode system control method used in a semiconductor process equipment according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solution of the present application, the lower electrode system, semiconductor process equipment and control method provided by the present application are described in detail below with reference to the accompanying drawings.

[0034] Referring to FIG. 1 , a lower electrode system 100 provided in an embodiment of the present application is applied to semiconductor process equipment. The semiconductor process equipment, for example, includes a wafer edge etching apparatus as shown in FIG. 1 , for etching the edge region of a wafer 3 to remove wafer edge polymer. Of course, in practical applications, the semiconductor process equipment may also include other types of process equipment, and the present embodiment is not particularly limited thereto.

[0035] Specifically, the lower electrode system 100 includes a carrier device 1 and a ejector device 2, wherein the ejector device 2 is used to lift the wafer 3 on the carrier device 1 or place the wafer 3 on the carrier device 1, so as to cooperate with the robot arm to realize the wafer 3 taking or placing operation.

[0036] In some embodiments, the ejector device 2 includes a plurality of ejector pins 21 and a plurality of ejector bellows 22. A plurality of through-holes 23 are provided in the carrier device 1, spaced apart along the circumference of the carrier device 1. The ejector pins 21 are arranged in a one-to-one correspondence with the plurality of through-holes 23 and are arranged to be lifted and lowered through the plurality of through-holes 23. The lower end of each ejector pin 21 can pass through the bottom of the process chamber 200 of the semiconductor process equipment and extend outside the process chamber 200 to be connected to an external lifting drive source (not shown). Driven by the lifting drive source, the plurality of ejector pins 21 can be raised and lowered synchronously, so that their top ends can rise to a position above the carrying surface of the carrier device 1, thereby lifting the wafer 3 on the carrier device 1; or the top ends of the ejector pins 21 can be lowered to a position below the carrying surface of the carrier device 1, thereby placing the wafer 3 placed on the top ends of the plurality of ejector pins 21 on the carrying surface of the carrier device 1. Of course, in actual applications, the aforementioned lift drive source can also be disposed within the process chamber 200. In this case, the lower ends of the plurality of ejector pins 21 do not need to extend outside the process chamber 200 and can be connected to the lift drive source within the process chamber 200. For example, the aforementioned lift drive source comprises a plurality of drive components mounted on the carrier device 1 and connected to the plurality of ejector pins 21 in a one-to-one correspondence. Each of the plurality of drive components is configured to synchronously lift and lower one of the plurality of ejector pins 21 to which it is connected. The drive components may be, for example, a lift cylinder, an electric lift cylinder, or the like.

[0037] When the lower ends of the multiple ejector pins 21 extend outside the process chamber 200, multiple ejector bellows 22 are mounted one-to-one on the multiple ejector pins 21, and the upper end of each ejector bellows 22 is sealedly connected to the carrier device 1, for example, by welding. The lower end of each ejector bellows 22 extends outside the process chamber 200 through the through-hole 201 in the chamber bottom, which is penetrated by the ejector pin 21, and is sealedly connected to the corresponding ejector pin 21, for example, by welding. In this way, each ejector bellows 22 can seal one of the through-holes 23 in the carrier device 1. Since the upper end of this through-hole 23 is located on the supporting surface of the carrier device 1, sealing this through-hole 23 ensures the sealing of the process chamber 200 of the semiconductor process equipment. At the same time, the ejector bellows 22 also enables the ejector pins 21 to be raised and lowered. In addition, the through-hole 201 in the chamber bottom, which is penetrated by the ejector pin 21, requires additional sealing structure to ensure the sealing of the process chamber 200.

[0038] The above-mentioned supporting device 1 can have a variety of structures, for example, including a base plate 11, a chuck 12 and an interface plate 13 arranged in sequence from top to bottom. The base plate 11, the chuck 12 and the interface plate 13 are integrated together and electrically conductive. The three as a whole constitute the lower electrode. The base plate 11 is made of a conductive material, such as Al, and the upper surface of the base plate 11 is provided with a hard anodized coating 11a for supporting the wafer 3 and electrically insulating the base plate 11 from the wafer 3. The hard anodized coating 11a is, for example, Al2O3. The main body of the chuck 12 is made of a conductive material, such as Al. A temperature control channel can also be provided in the main body of the chuck 12 for conveying a temperature control medium (heating medium or cooling medium) to achieve temperature control of the lower electrode. In some embodiments, the outer peripheral surface of the chuck 12 and the outer peripheral surface of the interface plate 13 are provided with a hard anodized coating or other insulating layer to prevent the chuck 12 and the interface plate 13 from contacting the plasma. The main body of the chuck 12 can be used to electrically connect to the lower electrode RF device 400 (including a matcher 401 and an RF power supply 402). In some embodiments, the lower electrode system 100 further includes an RF feedthrough 14, which is, for example, mounted on the interface plate 13 and electrically connected to the main body of the chuck 12. The RF feedthrough 14 is used to electrically connect to the RF power supply 402 through the matcher 401. The RF power supply 402 applies RF power to the main body of the chuck 12 to excite the process gas in the process chamber 200 to form a plasma, thereby etching the wafer 3.

[0039] In addition, taking the crystal edge etching equipment as an example, the crystal edge etching equipment includes a chamber 202 and an upper electrode cover plate 203 arranged on the top of the chamber 202. The chamber 202 and the upper electrode cover plate 203 together constitute a process chamber 200. In addition, a center hole 301a is provided in the upper electrode cover plate 203. The crystal edge etching equipment also includes an upper electrode 300, a lifting drive device 302 and a top bellows 301. The lifting drive device 302 is installed on the upper electrode cover plate 203, and its drive shaft extends into the process chamber 200 through the center hole 301a and is fixedly connected to the upper electrode 300. It is used to drive the upper electrode 300 to rise and fall to adjust the vertical distance between the upper electrode 300 and the supporting device 1. For example, when performing operations such as taking or placing a wafer, the lifting drive device 302 can be controlled to drive the upper electrode 300 to rise to increase the above-mentioned vertical distance. During the process, the lift drive 302 can be controlled to drive the upper electrode 300 downward, thereby reducing the vertical distance mentioned above to meet the requirements of the edge etching process. The top bellows 301 surrounds the drive shaft of the lift drive 302 and is sealed to the upper electrode cover plate 203. It is used to seal the central hole 301a and ensure smooth lifting and lowering of the drive shaft of the lift drive 302. Of course, in actual applications, the top bellows 301 can also be replaced by other dynamic sealing components such as magnetic fluid seals.

[0040] The upper electrode 300 is used to form an electric field together with the lower electrode to excite the process gas in the process chamber 200 to form plasma. The upper electrode 300 is, for example, an upper electrode plate. The edge area of ​​the upper electrode plate is also provided with an edge gas inlet channel for introducing process gas (for etching) to the edge portion of the wafer 3. In addition, in some embodiments, a central gas inlet channel can also be provided in the central area of ​​the upper electrode plate to introduce an inert gas (such as nitrogen) into the central area of ​​the process chamber 200 to prevent plasma from entering the central area of ​​the process chamber 200. On this basis, in order to prevent plasma from etching the central area of ​​the wafer 3, a shielding component can also be provided in the central area of ​​the upper surface of the wafer 3. The shielding component is, for example, a glass plate.

[0041] When the edge portion of the wafer 3 is etched to remove the edge polymer, before the RF power supply 402 is turned on, the chamber pressure of the process chamber 200 is first controlled to a relatively low pressure range (for example, 70mTorr to 100mTorr) by vacuuming, and then the wafer 3 is placed on the hard anodized coating 11a, and process gas is introduced into the process chamber 200 to raise the chamber pressure of the process chamber 200 to a relatively high pressure range (for example, 1Torr to 3Torr). At this time, there is a pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3, that is, the pressure on the upper surface side of the wafer 3 is greater than the pressure on the lower surface side, so that the wafer 3 can be fixed on the hard anodized coating 11a. It is easy to understand that the gas in the process chamber 200 is also slowly flowing into the gap between the lower surface of the wafer 3 and the hard anodized coating 11a, causing the pressure on the lower surface of the wafer 3 to slowly increase, and the pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3 to gradually decay. However, since this is a slow process, there is sufficient time to fix the wafer 3 on the hard anodized coating 11a while the RF power supply 402 is turned on. By adjusting the above pressure range, it can be ensured that before the ejector device 2 lifts the wafer 3 on the hard anodized coating 11a, the above pressure difference decays to zero or close to zero, ensuring that the ejector device 2 can normally lift the wafer 3. From the above, it can be seen that the carrier device 1 does not need to set up an additional structure to fix the wafer 3, for example, there is no need to set up an additional electrostatic adsorption electrode such as in an electrostatic chuck, and the wafer 3 can be fixed by using only the above pressure difference.

[0042] The interface plate 13 is fixed to the bottom of the cavity 202 and is electrically insulated from the cavity 202. For example, the interface plate 13 can be electrically insulated from the cavity 202 by an insulating ring 15. The interface plate 13 is provided with a variety of interfaces with different functions, such as an RF interface for installing the RF feedthrough 14. For example, it also includes an interface for installing the ejector bellows 22. The ejector bellows 22 is inserted into this interface and its upper end is sealed to the main body of the chuck 12. In addition, through holes for the ejector 21 to pass through are correspondingly provided in the hard anodized coating 11a, the base plate 11, and the chuck 12, forming the above-mentioned through holes 23.

[0043] The lower electrode system 100 also includes a grounding device, which includes a grounding circuit, a grounding switch 102, and a control unit. The grounding circuit is electrically connected to the lower electrode in the carrier device 1 (for example, composed of a base plate 11, a chuck 12, and an interface plate 13) through the grounding switch 102, and is used to ground the lower electrode when the grounding switch 102 is turned on. The grounding circuit that realizes this function includes, for example, a circuit 101 for connecting between the lower electrode and the ground, and a grounding resistor 103 connected in series with the circuit 101; the grounding switch 102 is connected in series with the circuit 101 and is located on the side of the grounding resistor 103 close to the lower electrode. The grounding resistor 103 can slowly discharge the charge of the lower electrode when the grounding switch 102 is turned on. In addition, when the above-mentioned lower electrode radio frequency device 400 is connected in parallel with the circuit 101, the grounding resistor 103 can also prevent radio frequency leakage when the grounding switch 102 is turned on, that is, prevent radio frequency current from flowing into the ground through the circuit 101. In some embodiments, the resistance of the grounding resistor 103 ranges from 5 MΩ to 20 MΩ (inclusive), with specific examples of the resistance of the grounding resistor 103 being 5 MΩ, 10 MΩ, or 20 MΩ. The resistance of the grounding resistor 103 should not be too large, otherwise the charge discharge will be too slow, which will easily cause static electricity accumulation (the accumulation of static charge without discharge) on the lower electrode. The resistance of the grounding resistor 103 should not be too small, otherwise it will not effectively prevent RF leakage.

[0044] In some embodiments, the grounding switch 102 is, for example, a relay, so as to be able to automatically disconnect or connect upon receiving an input signal (eg, 0V or 24V in FIG. 2 ) from a control unit.

[0045] Please refer to Figure 2. The control unit is used to control the ground switch 102 to be disconnected before the plasma generation phase of the semiconductor process (i.e., the RF start phase T2-T3 in Figure 2) begins, for example, it is disconnected at the process start time T1 in Figure 2, and after the plasma generation phase ends (i.e., ends at time T3 in Figure 2) and the ejector device 2 lifts the wafer 3 on the carrier device 1 (i.e., the ejector lifting phase T3-T4 in Figure 2), the control unit is used to control the ground switch 102 to be connected, for example, it is connected at the process end time T4 in Figure 2, which is equivalent to being in the disconnected state during the RF start phase. When the lower electrode RF device 400 is turned on (i.e., time T2 in FIG2 ), RF power starts to be loaded to the lower electrode. At this time, the electric field formed between the lower electrode and the upper electrode 300 can ionize the process gas in the process chamber 200 to form plasma, thereby realizing plasma ignition. This time T2 is the beginning of the plasma generation phase. When the lower electrode RF device 400 is turned off (i.e., time T3 in FIG2 ), RF power is stopped from being loaded to the lower electrode. This time T3 is the end of the plasma generation phase. Of course, the embodiments of the present application are not limited to this. In actual applications, the method of generating plasma in the process chamber 200 can also be any other method, such as loading RF power to the upper electrode (e.g., a coil or an electrode plate) through the upper electrode RF device to ionize the process gas in the process chamber 200 to form plasma. The above-mentioned control unit can be a host computer or a slave computer.

[0046] By controlling the ground switch 102 to open before the plasma generation phase of the semiconductor process begins, the lower electrode in the carrier device 1 is disconnected from the ground. Consequently, during the plasma generation phase, the negative charge accumulated on the lower electrode is not released. Instead, the lower electrode and wafer 3 accumulate negative charge simultaneously, resulting in a negative charge on the lower electrode and a substantially equivalent potential, as shown in FIG3 . Specifically, during the plasma generation phase, the gas within the process chamber 200 is ionized by RF energy to form a plasma containing ions and electrons. Under the RF energy, the ions and electrons repeatedly accelerate and then decelerate. Because electrons are much less massive than ions, their speed is much greater than theirs, resulting in electrons accumulating on wafer 3 and exhibiting a negative polarity relative to the ground. This phenomenon is known as DC bias. Simultaneously, the plasma inevitably contacts the lower electrode through the gap (the outer surface of the substrate 11 contacts the plasma), causing the lower electrode to accumulate negative charge as well. On this basis, since the lower electrode in the carrier device 1 is disconnected from the ground before the plasma generation phase begins, the process of charge accumulation in the lower electrode and the process of charge accumulation in the wafer 3 are the same process. Due to the synchronous charge accumulation, the two achieve the same potential, thereby avoiding the potential difference between the wafer 3 and the lower electrode, and no electrostatic adsorption occurs between the two. As shown in FIG4 , when the ejector device 2 lifts the wafer 3 on the carrier device 1, the wafer 3 will not be offset due to electrostatic adsorption, thereby effectively improving the repeatable transfer accuracy of the wafer and ensuring that the AWC (wafer automatic correction) results meet the requirements. It is easy to understand that the lower electrode in the carrier device 1 must be disconnected from the ground before the plasma generation phase begins. During the plasma generation phase, or after the plasma generation phase ends, the lower electrode in the carrier device 1 cannot be disconnected from the ground, and thus the lower electrode and the wafer 3 cannot be synchronously accumulated, and thus the two cannot achieve the same potential.

[0047] On this basis, after the plasma generation stage is completed and the ejector device 2 lifts the wafer 3 on the carrier device 1, as shown in Figure 5, the grounding switch 102 is controlled to be turned on, so that the lower electrode can be grounded, so that the charge accumulated in the lower electrode can be discharged, avoiding the spark problem inside the lower electrode.

[0048] In the related art, the lower electrode is kept grounded during the plasma generation phase. In this case, the black box in Figure 6 represents the distribution range of the center position points (black dots) of multiple wafers in the related art (i.e., the AWC range, indicating the repeatability of the wafer). In the embodiment of the present application, before the plasma generation phase begins, the grounding switch 102 is controlled to be disconnected. During the plasma generation phase, the negative charge accumulated in the lower electrode will not be discharged. In this case, the black box in Figure 7 represents the distribution range of the center position points (black dots) of multiple wafers in the embodiment of the present application. Comparing the sizes of the black boxes in Figures 6 and 7, it can be seen that the AWC range of the related art is too large, while the embodiment of the present application can control the AWC range within a smaller range, thereby effectively improving the repeatability of the wafer.

[0049] In some embodiments, the ejector device 2 is configured to ground the wafer 3 after lifting it from the carrier device 1, thereby resolving the particle problem caused by the accumulated charge on the wafer 3. Furthermore, in some embodiments, the ejector device 2 is configured to be electrically connected to the grounding switch 102 via the lower electrode, so that the wafer 3 on the ejector device 2 is grounded simultaneously with the control unit controlling the grounding switch 102 to be turned on. In this way, the negative charge in the wafer 3 and the lower electrode can be discharged synchronously, thereby always avoiding the potential difference between the wafer 3 and the lower electrode, and resolving the particle problem caused by the accumulated charge on the wafer 3 and the spark problem caused by the accumulated charge on the lower electrode.

[0050] Furthermore, in some embodiments, the ejector device 2 is electrically connected to the grounding switch 102 via the lower electrode in the following manner: the ejector pins 21 and the ejector bellows 22 are both made of a conductive material, such as stainless steel. Furthermore, since the ejector pins 21 and the ejector bellows 22 are interconnected to provide electrical conduction between them, and the ejector bellows 22 is interconnected to provide electrical conduction between them and the bottom of the carrier device 1 (i.e., the lower electrode), when multiple ejector pins 21 lift the wafer 3 on the carrier device 1, when the grounding switch 102 is turned on, the negative charge in the wafer 3 is sequentially conducted to the ground via the ejector pins 21, the ejector bellows 22, the lower electrode, and the grounding circuit. Of course, in actual applications, the ejector device 2 can also be grounded in any other manner, or the wafer 3 can also be grounded in any other manner, and the embodiments of the present application are not particularly limited in this regard.

[0051] In addition, in some embodiments, the control unit is further configured to control the grounding switch 102 to be in an on state during a non-processing phase (e.g., including phases T0 to T2 and the phase after time T4) before the process begins and after the process ends. That is, during the non-processing phase, the grounding switch 102 is always in a normally closed state to conduct the negative charge in the lower electrode to the ground.

[0052] As another technical solution, an embodiment of the present application further provides a semiconductor process apparatus, comprising a process chamber 200 and a lower electrode system 100, wherein at least some components of the lower electrode system 100 are located in the process chamber 200. The lower electrode system 100 includes, for example, a carrier device 1, an ejector device 2, and a grounding device. Since the structures and functions of these devices have been described in detail in the above embodiments, they will not be repeated here.

[0053] The semiconductor process equipment includes, for example, a wafer edge etching device as shown in FIG1 , which is used to etch the edge region of the wafer 3 to remove the wafer edge polymer.

[0054] As another technical solution, the embodiment of the present application further provides a semiconductor process equipment control method, which is applied to the above-mentioned lower electrode system provided in the embodiment of the present application. As shown in FIG8 , the control method includes:

[0055] S1, in response to the start of the semiconductor process, controlling the ground switch to be disconnected;

[0056] S2, in response to the completion of the semiconductor process, controlling the ground switch to be turned on;

[0057] The semiconductor process includes the following steps: the plasma generation phase ends, and the ejector device 2 lifts the wafer on the carrier device 1 .

[0058] By controlling the grounding switch 102 to be disconnected before the plasma generation phase of the semiconductor process begins, the lower electrode in the carrier device 1 can be disconnected from the ground. Therefore, during the plasma generation phase, the negative charge accumulated in the lower electrode will not be discharged. The lower electrode and wafer 3 will accumulate negative charge simultaneously, so that the lower electrode and wafer 3 are negatively charged as a whole, and the potential is basically the same. This can avoid a potential difference between wafer 3 and the lower electrode, and no electrostatic adsorption will occur between the two. As a result, when the ejector device 2 lifts the wafer on the carrier device 1, the wafer 3 will not be deflected due to electrostatic adsorption, thereby effectively improving the repeatable transmission accuracy of wafer 3 and ensuring that the AWC (wafer automatic correction) results meet the requirements. On this basis, after the plasma generation phase ends and the ejector device 2 lifts the wafer 3 on the carrier device 1, controlling the grounding switch 102 to be connected can ground the lower electrode, thereby allowing the accumulated charge in the lower electrode to be discharged, avoiding the problem of sparking inside the lower electrode.

[0059] In some embodiments, before the semiconductor process begins, the process further includes:

[0060] S01, controlling the chamber pressure to reach a first pressure value;

[0061] S02. In response to placing the wafer 3 on the carrier 1, process gas is introduced into the process chamber 200, and the chamber pressure is controlled to reach a second pressure value; the second pressure value is greater than the first pressure value to form a pressure difference between the upper surface and the lower surface of the wafer 3, thereby fixing the wafer 3 on the carrier 1.

[0062] In some embodiments, the first pressure value ranges from 70 mTorr to 100 mTorr, for example.

[0063] In some embodiments, the second pressure value ranges from 1 Torr to 3 Torr, for example.

[0064] Before the RF power supply is turned on, the chamber pressure of the process chamber 200 is first controlled at a first pressure value by vacuuming, and then the wafer 3 is placed on the base plate 11, and process gas is introduced into the process chamber 200 to increase the chamber pressure of the process chamber 200 to a second pressure value. At this time, there is a pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3, that is, the pressure on the upper surface side of the wafer 3 is greater than the pressure on the lower surface side, so that the wafer 3 can be fixed on the base plate 11. It is easy to understand that during this process, the gas in the process chamber 200 also slowly flows into the gap between the lower surface of the wafer 3 and the base 11, causing the pressure on the side of the lower surface of the wafer 3 to slowly increase, and the pressure difference between the upper surface of the wafer 3 and the lower surface of the wafer 3 gradually decays. However, since this is a slow process, there is enough time to fix the wafer 3 on the base 11 while the RF power is turned on, and by adjusting the above-mentioned pressure range, it can be ensured that before the ejector device 2 lifts the wafer 3 on the base 11, the above-mentioned pressure difference decays to zero or close to zero, so as to ensure that the ejector device 2 can normally lift the wafer 3. From the above, it can be seen that the chuck 12 does not need to be equipped with an additional structure to fix the wafer 3, such as an electrostatic chuck, and can fix the wafer 3 only by using the above-mentioned pressure difference.

[0065] In some embodiments, as shown in FIG9 , after the above step S2, the control method further includes step S3:

[0066] S3 . After lifting the wafer 3 on the carrier device 1 , the wafer 3 on the ejector device 2 is grounded by the ejector device 2 .

[0067] Furthermore, in some embodiments, the wafer 3 on the ejector device 2 is grounded at the same time as the lower electrode is grounded. This allows the negative charges in the wafer 3 and the lower electrode to be discharged synchronously, thereby avoiding a potential difference between the wafer 3 and the lower electrode and solving the problem of particles caused by the accumulated charge on the wafer 3 and the problem of sparks caused by the accumulated charge on the lower electrode.

[0068] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present application, and such modifications and improvements are also considered to be within the scope of protection of the present application.

Claims

1. A lower electrode system is applied to semiconductor process equipment and includes a carrier device and a thimble device. The thimble device is used to lift a wafer on the carrier device or place the wafer on the carrier device. It is characterized in that, It further includes a grounding device, and the grounding device includes a grounding circuit, a grounding switch and a control unit. Wherein, the grounding circuit is electrically connected to the lower electrode in the carrier device through the grounding switch, and is used to ground the lower electrode when the grounding switch is turned on; The control unit is used to control the grounding switch to disconnect in response to the start of the semiconductor process, and control the grounding switch to turn on in response to the end of the semiconductor process; wherein, the end of the semiconductor process includes: the end of the plasma generation stage, and the thimble device lifts the wafer on the carrier device.

2. The lower electrode system according to claim 1, characterized in that The thimble device is configured to ground the wafer after lifting the wafer on the carrier device.

3. The lower electrode system according to claim 2, wherein, The thimble device is configured to be electrically connected to the grounding switch through the lower electrode, so as to ground the wafer on the thimble device while the control unit controls the grounding switch to turn on.

4. The lower electrode system according to claim 2, wherein The thimble device includes a plurality of conductive thimbles and a plurality of conductive thimble bellows. Wherein, a plurality of through holes are arranged at intervals along the circumference of the carrier device in the carrier device, and the plurality of thimbles are correspondingly and liftably inserted into the plurality of through holes; the plurality of thimble bellows are correspondingly sleeved on the plurality of thimbles, and the upper end of each thimble bellows is hermetically connected to the carrier device and electrically conductive; the lower end of each thimble bellows is hermetically connected to the corresponding thimble and electrically conductive.

5. The lower electrode system according to claim 1, characterized in that It further includes a radio frequency feeding device, and the radio frequency feeding device is electrically connected to the lower electrode, and is used to be electrically connected to a radio frequency power supply through a matcher to load radio frequency power to the lower electrode.

6. The lower electrode system according to any one of claims 1-5, characterized in that The grounding circuit includes a circuit for connecting between the lower electrode and the ground, and a grounding resistor connected in series on the grounding circuit; the grounding switch is connected in series on the grounding circuit and is located on the side of the grounding resistor close to the lower electrode.

7. The lower electrode system according to claim 6, wherein The resistance value of the grounding resistor is greater than or equal to 5 MΩ and less than or equal to 20 MΩ.

8. A semiconductor process equipment, comprising a process chamber, characterized in that, It further includes a lower electrode system according to any one of claims 1-7, and at least some components in the lower electrode system are located in the process chamber.

9. The semiconductor processing equipment according to claim 8, wherein The semiconductor process equipment includes an edge etching equipment.

10. A control method for a semiconductor process equipment, which is applied to a lower electrode system according to any one of claims 1-7, includes: Controlling the grounding switch to disconnect in response to the start of the semiconductor process; Controlling the grounding switch to turn on in response to the end of the semiconductor process; Wherein, after the semiconductor process includes: the end of the plasma generation stage, and the thimble device lifts the wafer on the carrier device.

11. The method according to claim 10, characterized in that, Before the semiconductor process starts, it further includes: Controlling the chamber pressure to reach a first pressure value; In response to placing the wafer on the carrier device, introducing a process gas into the process chamber, and controlling the chamber pressure to reach a second pressure value; the second pressure value is greater than the first pressure value, so as to form a pressure difference between the upper surface and the lower surface of the wafer, and fix the wafer on the carrier device.

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