Storage device

Abstract

The present invention provides a novel storage device. A test bit generation unit has the function of generating a test sequence from an information sequence. A storage unit has the function of storing, in a flip-flop circuit, a codeword that is constituted by the information sequence and the test sequence, and outputting the codeword as a received word. An error detection correction unit has the function of outputting an error vector which indicates the position of an error in the received word and a decoded word in which the error in the received word has been corrected. The storage unit has the function of storing the decoded word in the flip-flop circuit in accordance with the error vector, the function of writing the decoded word to a holding circuit, and the function of writing back, to the flip-flop circuit, the decoded word written in the holding circuit. The flip-flop circuit has a first transistor. The holding circuit has a second transistor. The off current of the second transistor is smaller than the off current of the first transistor.

Description

storage device

[0001] One aspect of the present invention relates to a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, systems including these devices, and driving methods or manufacturing methods thereof.

[0003] It is known that an OS transistor (a transistor including an oxide semiconductor in a channel formation region) has an extremely low off-state current. For example, Patent Document 1 discloses a low-power processing unit (such as a CPU) that utilizes the characteristic of an OS transistor having a low off-state current. Specifically, Patent Document 1 discloses a technology that enables power gating of a flip-flop mounted on an integrated circuit by incorporating a holding circuit including an OS transistor and a capacitor into the flip-flop.

[0004] JP 2016-82593 A JP 2017-135698 A International Publication No. 2023 / 180849

[0005] In computing processing units, a defect called a soft error can occur, in which a part of the data held in a flip-flop or the like is unintentionally inverted, causing malfunction. Soft errors are particularly likely to occur in environments with strong radiation, such as outer space, and lead to a decrease in reliability.

[0006] It is known that OS transistors have small variations in electrical characteristics due to radiation exposure. For example, Patent Document 2 discloses evaluation results in which a memory circuit using an OS transistor and an inverter loop using a Si transistor (a transistor including silicon in a channel formation region) are irradiated with radiation, and the evaluation results show that the memory circuit using the OS transistor is less susceptible to soft errors than the inverter loop using the Si transistor. Furthermore, Patent Document 3 discloses evaluation results showing that, when an OS transistor is irradiated with radiation, the variation in subthreshold slope, the variation in field-effect mobility, and the maintenance of an extremely small off-state current are small.

[0007] Therefore, for example, in a configuration in which a flip-flop using a Si transistor is incorporated with a holding circuit using an OS transistor, as disclosed in Patent Document 1, reliability can be improved by storing data in the holding circuit. However, in this configuration, there is a possibility that the data stored in the flip-flop may be unintentionally inverted before being stored in the holding circuit. In such a case, the unintentionally inverted data is stored in the holding circuit, resulting in a soft error.

[0008] An object of one embodiment of the present invention is to provide a highly reliable storage device.An object of one embodiment of the present invention is to provide a miniaturized storage device.An object of one embodiment of the present invention is to provide a storage device with reduced power consumption.An object of one embodiment of the present invention is to provide a storage device with increased operation speed.An object of one embodiment of the present invention is to provide a novel storage device.

[0009] Another object of one embodiment of the present invention is to provide a semiconductor device that can be used for the memory device, or to provide an arithmetic processing unit using the memory device.

[0010] The above-mentioned problem does not preclude the existence of other problems. A person skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and can extract other problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0011] (1) One aspect of the present invention is a storage device including a check bit generation unit, a memory unit, and an error detection and correction unit, the memory unit including a flip-flop circuit and a holding circuit, the check bit generation unit having a function of generating a check sequence from an information sequence, the memory unit having a function of storing a code word composed of the information sequence and the check sequence in the flip-flop circuit and outputting the code word as a received word, the error detection and correction unit having a function of outputting an error vector indicating a position of an error in the received word and a decoded word in which the error in the received word has been corrected, the memory unit having a function of storing the decoded word in the flip-flop circuit according to the error vector, a function of writing the decoded word to the holding circuit, and a function of writing the decoded word written to the holding circuit back to the flip-flop circuit, the flip-flop circuit having a first transistor, the holding circuit having a second transistor, and an off-state current of the second transistor being smaller than the off-state current of the first transistor.

[0012] (2) In the above (1), the code word may be a Hamming code.

[0013] (3) In the above (1) or (2), the change in electrical characteristics of the second transistor due to radiation exposure may be smaller than the change in electrical characteristics of the first transistor due to radiation exposure.

[0014] (4) In the above (1) or (2), the second transistor may be stacked on a layer on which the first transistor is provided.

[0015] (5) In the above (1) or (2), the first transistor may include silicon in a channel formation region, and the second transistor may include an oxide semiconductor in a channel formation region.

[0016] According to one embodiment of the present invention, a highly reliable storage device can be provided. Alternatively, according to one embodiment of the present invention, a miniaturized storage device can be provided. Alternatively, according to one embodiment of the present invention, a storage device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a storage device with increased operation speed can be provided. Alternatively, according to one embodiment of the present invention, a novel storage device can be provided.

[0017] According to one embodiment of the present invention, a semiconductor device that can be used for the memory device can be provided. Alternatively, according to one embodiment of the present invention, a processing unit including the memory device can be provided.

[0018] Note that the above effects do not preclude the existence of other effects. A person skilled in the art can naturally derive other effects from the description in this specification, drawings, claims, etc., and can extract other effects from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above effects and other effects).

[0019] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device. FIGS. 2A and 2B are circuit diagrams illustrating a configuration example of a memory device. FIG. 3 is a timing chart illustrating an operation example of the memory device. FIG. 4 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 5 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 6A is a top view illustrating a configuration example of a semiconductor device. FIGS. 6B and 6C are cross-sectional views illustrating a configuration example of a semiconductor device. FIG. 7 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 8 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 9A is a top view illustrating a configuration example of a semiconductor device. FIGS. 9B to 9D are cross-sectional views illustrating a configuration example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIG. 11A is a top view illustrating a configuration example of a semiconductor device. FIG. 11B is a perspective schematic view illustrating a configuration example of a semiconductor device. FIGS. 11C and 11D are cross-sectional views illustrating a configuration example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views illustrating a configuration example of a semiconductor device. FIG. 13 is a cross-sectional view illustrating a configuration example of a semiconductor device. FIGS. 14A to 14C are cross-sectional views illustrating a configuration example of a semiconductor device. 15A and 15B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 16A is a top view showing a configuration example of a semiconductor device. FIG. 16B is a perspective schematic view showing a configuration example of a semiconductor device. FIGS. 16C to 16E are cross-sectional views showing a configuration example of a semiconductor device. FIGS. 17A and 17B are cross-sectional views showing a configuration example of a semiconductor device. FIG. 18A is a top view showing a configuration example of a semiconductor device. FIG. 18B is a perspective schematic view showing a configuration example of a semiconductor device. FIGS. 18C to 18E are cross-sectional views showing a configuration example of a semiconductor device. FIG. 19 is a cross-sectional view showing a configuration example of a semiconductor device. FIG. 20A is a top view showing a configuration example of a semiconductor device. FIG. 20B is a perspective schematic view showing a configuration example of a semiconductor device. FIGS. 20C to 20E are cross-sectional views showing a configuration example of a semiconductor device. FIG. 21 is a diagram showing various memory devices by layer. FIG. 22 is a schematic view explaining a configuration example of a memory device. FIGS. 23A to 23H are circuit diagrams explaining a configuration example of a memory cell. 24A and 24B are schematic diagrams illustrating an example of the configuration of a display device, Fig. 25 is a cross-sectional view illustrating an example of the configuration of a display device, and Fig. 26 is a cross-sectional view illustrating an example of the configuration of a display device.Fig. 27A and Fig. 27B are circuit diagrams illustrating an example of the configuration of a semiconductor device. Fig. 28A and Fig. 28B are diagrams illustrating an example of an electronic component. Fig. 29A and Fig. 29B are diagrams illustrating an example of an electronic device. Fig. 29C to Fig. 29E are diagrams illustrating an example of a mainframe computer. Fig. 30A is a diagram illustrating an example of space equipment. Fig. 30B is a diagram illustrating an example of a storage system applicable to a data center. Fig. 30C and Fig. 30D are diagrams illustrating an example of an electronic device. Figs. 31A1 to 31A7 and Fig. 31B1 to 31B6 are diagrams illustrating electrical connections.

[0020] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. Examples of semiconductor devices include electronic circuits including semiconductor elements, chips equipped with electronic circuits, electronic components with chips housed in packages, and electronic devices equipped with electronic components. Furthermore, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, and electronic devices may themselves be semiconductor devices and may also include semiconductor devices.

[0021] The following description of the embodiments will be given with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it will be readily understood by those skilled in the art that various changes can be made to the embodiments and their details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0022] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0023] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0024] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations to facilitate understanding of the present invention and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching. However, these may not be reflected in the drawings to facilitate understanding. Furthermore, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors. However, these may not be reflected in the drawings to facilitate understanding.

[0025] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0026] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0027] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cutoff state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cutoff state," or "off state."

[0028] In this specification, the voltage between the gate and the source (gate-source) (based on the source unless otherwise specified) is sometimes referred to as the "gate voltage," the voltage between the drain and the source (drain-source) (based on the source unless otherwise specified) is sometimes referred to as the "drain voltage," and the voltage between the backgate and the source (backgate-source) (based on the source unless otherwise specified) is sometimes referred to as the "backgate voltage." Also, the current flowing between the drain and the source (positive in the direction from the drain to the source unless otherwise specified) is sometimes referred to as the "drain current." Note that, for n-channel transistors, terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" can be interchanged with terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" for p-channel transistors, as appropriate. Also, terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" for n-channel transistors can be interchanged with terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" for p-channel transistors, as appropriate.

[0029] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0030] In this specification and the like, one of the source or drain (also referred to as two input / output terminals) of a transistor may be referred to as a first terminal, and the other of the source or drain of the transistor may be referred to as a second terminal. That is, a transistor has at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. One terminal of a capacitor (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other terminal of the capacitor (also referred to as the other of the pair of terminals) may be referred to as a second terminal. One terminal of a display element may be referred to as a first terminal, and the other terminal of the display element may be referred to as a second terminal. One terminal of a liquid crystal element may be referred to as a first terminal, and the other terminal of the liquid crystal element may be referred to as a second terminal. One terminal of a light-emitting element may be referred to as a first terminal, and the other terminal of the light-emitting element may be referred to as a second terminal. One terminal of a light-receiving element may be referred to as a first terminal, and the other terminal of the light-receiving element may be referred to as a second terminal. In addition, one of the anode or cathode of the diode (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other of the anode or cathode of the diode (also referred to as the other of the pair of terminals) may be referred to as a second terminal.

[0031] Embodiment 1 A memory device according to one embodiment of the present invention will be described with reference to the drawings. At least a part of the memory device according to one embodiment of the present invention can be used for, for example, an arithmetic processing unit. In particular, it can be used for a register included in the arithmetic processing unit.

[0032] A storage device of one embodiment of the present invention has a function of storing a k-bit information sequence (also referred to as information bits) (k is an integer of 1 or more). For example, the storage device can function as a k-bit register.

[0033] Furthermore, the storage device has a function of storing an m-bit (m is an integer equal to or greater than 1) check sequence (also called check bits) in addition to the k-bit information sequence. That is, the storage device has a function of storing an n-bit (n=k+m) code word (also called code bits) composed of the k-bit information sequence and the m-bit check sequence. This allows the storage device to have a function of detecting the occurrence of an error (also called an error) in the stored code word. The storage device may also have a function of correcting an erroneous code word.

[0034] An example of the configuration of a storage device having such a function will be described later.

[0035] An error correction code can be used as the code word. For example, a Hamming code can be used as the error correction code. By using a Hamming code, it is possible to detect an error in any one bit of the code word and correct that one bit in which the error occurred. Therefore, by using a Hamming code, it is possible to correct a single-bit error.

[0036] In a Hamming code, there are n+1 (i.e., k+m+1) combinations of an n-bit codeword with no error and an error in any one bit. The amount of information in an m-bit check sequence is 2 to the mth power. Therefore, the relationship expressed by the following formula (1) must be satisfied between the number of bits k in the information sequence and the number of bits m in the check sequence.

[0037]

[0038] For example, if the information sequence is 4 bits (k=4), the check sequence is 3 bits (m=3), and the code word is 7 bits (n=7). Also, if the information sequence is 8 bits (k=8), the check sequence is 4 bits (m=4), and the code word is 12 bits (n=12). Also, if the information sequence is 16 bits (k=16), the check sequence is 5 bits (m=5), and the code word is 21 bits (n=21). Also, if the information sequence is 32 bits (k=32), the check sequence is 6 bits (m=6), and the code word is 38 bits (n=38). Also, if the information sequence is 64 bits (k=64), the check sequence is 7 bits (m=7), and the code word is 71 bits (n=71).

[0039] The error correction code may be an extended Hamming code, which is a Hamming code with one parity bit added. The use of the extended Hamming code makes it possible to correct one error (detect an error in any one bit of a codeword and correct the one bit where the error occurred) and to detect two errors (detect an error in any two bits of a codeword).

[0040] Furthermore, the error correction code may be a BCH code, a Reed-Solomon code, or the like. By using these codes, it becomes possible to correct errors of two or more bits in addition to correcting errors of one bit.

[0041] In this manner, the memory device of one embodiment of the present invention has a function of storing code words using error correction codes, and thus can be a memory device that is less susceptible to soft errors. Therefore, the reliability of the memory device and a processor using the memory device can be improved.

[0042] Here, Triple Modular Redundancy (TMR) is an example of a technology that realizes a memory device that is less susceptible to soft errors. In a memory device using TMR, the same information is stored in three memory circuits, and the result of a majority vote among them is output. As a result, even if an error occurs in one of the three memory circuits, the correct result is obtained by majority vote. However, if an error occurs in two or more of the three memory circuits, the correct result cannot be obtained. In order to achieve this effect, a memory device using TMR requires memory circuits with three times the number of bits of the information sequence.

[0043] On the other hand, as described above, the storage device of one embodiment of the present invention requires a storage circuit for an m-bit check sequence in addition to a storage circuit for a k-bit information sequence. Therefore, for example, the storage circuit required to store a 4-bit information sequence is 12 bits for TMR, but 7 bits for the storage device of one embodiment of the present invention. For example, the storage circuit required to store an 8-bit information sequence is 24 bits for TMR, but 12 bits for the storage device of one embodiment of the present invention. For example, the storage circuit required to store a 16-bit information sequence is 48 bits for TMR, but 21 bits for the storage device of one embodiment of the present invention. For example, the storage circuit required to store a 32-bit information sequence is 96 bits for TMR, but 38 bits for the storage device of one embodiment of the present invention. For example, the storage circuit required to store a 64-bit information sequence is 192 bits for TMR, but 71 bits for the storage device of one embodiment of the present invention. Thus, the storage device of one embodiment of the present invention requires fewer bits than the storage device using TMR, thereby enabling a reduction in circuit scale. Therefore, it is possible to reduce the size and power consumption of a memory device and a processor using the memory device.

[0044] <Configuration Example of Storage Device> Next, a configuration example of a storage device having the above functions will be described.

[0045] 1 is a circuit diagram illustrating an example of a configuration of a memory device 100 according to one embodiment of the present invention. As illustrated in FIG. 1, the memory device 100 includes a memory unit 101, a check bit generation unit 102, and an error detection and correction unit 103. Although not shown, the memory device 100 may also include a control unit that controls the operation of each of the memory unit 101, the check bit generation unit 102, and the error detection and correction unit 103.

[0046] The check bit generator 102 has a function of generating an m-bit check sequence from a k-bit information sequence. For example, it can generate an m-bit check sequence so that an n-bit codeword formed from the k-bit information sequence and the m-bit check sequence becomes an error-correcting code such as a Hamming code.

[0047] The memory unit 101 has a function of storing and holding an n-bit code word and outputting it as an n-bit received word. The memory unit 101 also has a function of storing and holding an n-bit decoded word corrected by the error detection and correction unit 103 in accordance with an n-bit error vector (also called an error pattern) output from the error detection and correction unit 103 and outputting it as an n-bit received word. The memory unit 101 may also have a function of backing up the n-bit decoded word.

[0048] The error detection and correction unit 103 has a function of detecting that an error has occurred in at least one bit of an n-bit received word, correcting the at least one erroneous bit, and outputting the result as an n-bit decoded word. It also has a function of outputting an n-bit error vector indicating which bit of the n-bit received word has been corrected. For example, when a Hamming code is used as the error correction code, it is possible to detect that an error has occurred in any one bit of the n-bit received word, and correct that one erroneous bit.

[0049] Wires Xc[1] through Xc[k], each having the function of transmitting a k-bit information sequence, are connected to the storage unit 101 and the check bit generation unit 102. Wires Pc[1] through Pc[m], each having the function of transmitting an m-bit check sequence, are connected to the check bit generation unit 102 and the storage unit 101. Wires Yc[1] through Yc[n], each having the function of transmitting an n-bit received word, are connected to the storage unit 101 and the error detection and correction unit 103. Wires Wc[1] through Wc[n], each having the function of transmitting an n-bit decoded word, are connected to the error detection and correction unit 103 and the storage unit 101. Wires Ec[1] through Ec[n], each having the function of transmitting an n-bit error vector, are connected to the error detection and correction unit 103 and the storage unit 101.

[0050] Therefore, a k-bit information sequence provided from outside the storage device 100 is input to the storage unit 101 and the check bit generation unit 102 via wiring Xc[1] to wiring Xc[k]. Also, an m-bit check sequence output from the check bit generation unit 102 is input to the storage unit 101 via wiring Pc[1] to wiring Pc[m]. That is, an n-bit code word composed of the k-bit information sequence and the m-bit check sequence is input to the storage unit 101. Also, an n-bit received word output from the storage unit 101 is input to the error detection and correction unit 103 via wiring Yc[1] to wiring Yc[n]. Also, an n-bit decoded word output from the error detection and correction unit 103 is input to the storage unit 101 via wiring Wc[1] to wiring Wc[n]. Furthermore, the n-bit error vector output from the error detection and correction unit 103 is input to the storage unit 101 via wiring Ec[1] to wiring Ec[n]. Of the n-bit decoded words, a k-bit decoded sequence corresponding to a k-bit information sequence may be output to the outside of the storage device 100 via wiring Wc[1] to wiring Wc[k].

[0051] In the present embodiment and the like, the code words transmitted via the wirings Xc[1] to Xc[k] and the wirings Pc[1] to Pc[m] may be referred to as code data. Furthermore, the received words transmitted via the wirings Yc[1] to Yc[n] may be referred to as retained data. Furthermore, the decoded words transmitted via the wirings Wc[1] to Wc[n] may be referred to as decoded data. Furthermore, the error vectors transmitted via the wirings Ec[1] to Ec[n] may be referred to as error signals.

[0052] The storage unit 101 includes n unit storage circuits 110 (unit storage circuits 110[1] to 110[n]).

[0053] The wiring D1 included in each of the n unit memory circuits 110 is connected to the wirings Xc[1] to Xc[k] and the wirings Pc[1] to Pc[m]. The wiring Q included in each of the n unit memory circuits 110 is connected to the wirings Yc[1] to Yc[n]. The wiring D2 included in each of the n unit memory circuits 110 is connected to the wirings Wc[1] to Wc[n]. The wiring Ec included in each of the n unit memory circuits 110 is connected to the wirings Ec[1] to Ec[n].

[0054] Therefore, the code data is applied to the wire D1, the retained data is applied to the wire Q, the decoded data is applied to the wire D2, and the error signal is applied to the wire Ec.

[0055] The unit memory circuit 110 includes a scan flip-flop circuit 120 and a backup circuit 130 .

[0056] The backup circuit 130 is connected to the scan flip-flop circuit 120 via a wiring D2. The backup circuit 130 is also connected to the scan flip-flop circuit 120 via a wiring SD.

[0057] The unit memory circuit 110 has a function of storing 1-bit information. Specifically, the unit memory circuit 110 has a function of storing and holding coded data in the scan flip-flop circuit 120 and outputting the coded data as held data. The unit memory circuit 110 also has a function of storing and holding decoded data in response to an error signal and outputting the decoded data as held data.

[0058] The unit memory circuit 110 may also have a function of storing 1-bit information even when the unit memory circuit 110 is powered off (power supply is cut off). Specifically, the unit memory circuit 110 may have a function of writing and holding decoded data in the backup circuit 130 and a function of writing the held data back to the scan flip-flop circuit 120.

[0059] The scan flip-flop circuit 120 has at least a flip-flop circuit (corresponding to a flip-flop circuit 122 described later). As the transistors constituting the scan flip-flop circuit 120, for example, Si transistors are used.

[0060] The backup circuit 130 has at least a holding circuit (corresponding to the holding circuit 131 described later), and the holding circuit has at least a switch element sw and a memory element me. The switch element sw has a function of controlling the writing of decoded data. The memory element me has a function of retaining the written decoded data. Various types of transistors can be used as the switch element sw. For example, a MOS field effect transistor, a junction field effect transistor, or a bipolar transistor can be used. For example, a capacitive element can be used as the memory element me. Furthermore, for example, a memory element using a ferroelectric material, a memory element using the magnetoresistive effect, a memory element using phase change recording technology, or a memory element using field-induced resistance change can also be used.

[0061] The backup circuit 130 may include, for example, as shown in FIG. 1, at least a transistor M31 and a capacitive element C31.

[0062] One of the source and drain of the transistor M31 is connected to one terminal of the capacitor C31. The other of the source and drain of the transistor M31 is connected to a wiring D2. The other terminal of the capacitor C31 is connected to a wiring to which an arbitrary potential is supplied.

[0063] A control unit (not shown) supplies a signal to the gate of the transistor M31 to control the conduction state of the transistor M31. In response to the signal supplied to the gate of the transistor M31, the potential of the decoded data supplied from the wiring D2 is stored and held in one terminal of the capacitance element C31. A potential based on the held potential is supplied to the wiring SD.

[0064] A specific example of the configuration of the unit memory circuit 110 will be described later.

[0065] In one embodiment of the present invention, a transistor having an off-state current smaller than that of a transistor included in the scan flip-flop circuit 120 is preferably used as a transistor included in the backup circuit 130. This allows data written to the backup circuit 130 to be held for a longer period of time, thereby enabling power gating of the memory device 100, for example. Thus, power consumption of the memory device and an arithmetic processing device including the memory device can be reduced.

[0066] Furthermore, it is preferable to use transistors having higher radiation resistance than the transistors constituting the scan flip-flop circuit 120 as the transistors constituting the backup circuit 130. For example, it is preferable to use transistors whose electrical characteristics change less due to radiation exposure than the transistors constituting the scan flip-flop circuit 120. For example, it is preferable to use transistors whose off-state current changes less due to radiation exposure than the transistors constituting the scan flip-flop circuit 120. For example, it is preferable to use transistors whose subthreshold slope changes less due to radiation exposure than the transistors constituting the scan flip-flop circuit 120. For example, it is preferable to use transistors whose field-effect mobility changes less due to radiation exposure than the transistors constituting the scan flip-flop circuit 120. For example, it is preferable to use transistors whose threshold voltage changes less due to radiation exposure than the transistors constituting the scan flip-flop circuit 120. This makes it possible to prevent data held in the backup circuit 130 from being unintentionally inverted due to the influence of radiation. Therefore, it is possible to improve the reliability of the memory device and the arithmetic processing device using the memory device.

[0067] Furthermore, it is preferable to use transistors that can be stacked on the layer in which the transistors that constitute the scan flip-flop circuit 120 are provided as the transistors that constitute the backup circuit 130. This can reduce the area overhead associated with providing the backup circuit 130. This can therefore reduce the size of the memory device and the arithmetic processing unit using the memory device. Furthermore, since the distance of the wiring connecting the backup circuit 130 and the scan flip-flop circuit 120 to each other can be shortened, the energy required for data exchange (access energy) can be reduced. This can therefore reduce the power consumption of the memory device and the arithmetic processing unit using the memory device.

[0068] For example, an OS transistor can be used as a transistor included in the backup circuit 130 .

[0069] The OS transistor has a characteristic of having an extremely small off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width in a room temperature environment is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ In the case of a Si transistor (a transistor including silicon in a channel formation region), the off-state current per 1 μm of channel width in a room temperature environment can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２ A) or less. Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude smaller than that of a Si transistor. Therefore, for example, when a wiring connected to one of the source and drain of an OS transistor is floating, charge accumulated in the wiring can be held for a long period of time. Therefore, for example, by configuring a memory cell using an OS transistor, data written to the memory cell can be stored for a long period of time.

[0070] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. The on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. On the other hand, the on-state current of a Si transistor decreases in a high-temperature environment. That is, the on-state current of an OS transistor is larger than that of a Si transistor in a high-temperature environment. Furthermore, an OS transistor can perform favorable switching operation even in an environment of 125° C. or higher and 150° C. or lower because of its large ratio of on-state current to off-state current. Therefore, a semiconductor device using an OS transistor can operate stably and with high reliability even in a high-temperature environment.

[0071] Furthermore, an OS transistor has a high withstand voltage between the source and the drain (also referred to as drain withstand voltage). Therefore, a semiconductor device including an OS transistor can operate stably and with high reliability even when driven at high voltage.

[0072] Furthermore, the electrical characteristics of an OS transistor change little due to radiation exposure. For example, as shown in Patent Document 3, the subthreshold slope of an OS transistor changes little due to radiation exposure. Furthermore, the field-effect mobility of an OS transistor changes little due to radiation exposure. Furthermore, as shown in Patent Document 3, an OS transistor can maintain an extremely small off-state current even after radiation exposure. For example, the off-state current of an OS transistor per 1 μm of channel width after radiation exposure is 1 fA (1×10 −１５ A) Below, 1aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ A) can be as follows: Therefore, a semiconductor device including an OS transistor can operate stably and have high reliability even in an environment with strong radiation such as outer space.

[0073] Furthermore, since OS transistors can be freely arranged on, for example, a silicon substrate on which Si transistors are provided, they can be easily integrated. Furthermore, since OS transistors can be manufactured using the same manufacturing equipment as Si transistors, OS transistors can be manufactured at low cost.

[0074] Therefore, by using an OS transistor as a transistor that constitutes the backup circuit 130, it is possible to achieve power saving, high reliability, miniaturization, integration, and cost reduction for a memory device and a processor using the memory device.

[0075] In one embodiment of the present invention, transistors with various structures can be used as transistors included in the memory device 100. For example, transistors with various structures can be used, such as top-gate transistors (e.g., planar transistors and staggered transistors), bottom-gate transistors (e.g., inverted planar transistors and inverted staggered transistors), dual-gate transistors (structures in which gates are arranged on both sides (e.g., above and below) of a channel formation region), FIN transistors, TRI-GATE transistors, and GAA transistors (gate-all-around transistors). Furthermore, for example, vertical transistors (transistors whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0076] A structural example of a transistor that can be used in the memory device 100 will be described in Embodiment 2 to be described later.

[0077] For example, when the memory device 100 is used in outer space, radiation reaches each transistor constituting the memory device 100 randomly. Therefore, for example, by making the distance between the unit memory circuits 110 constituting the memory device 100 greater than the range affected by radiation, the possibility of errors occurring simultaneously in two or more unit memory circuits 110 can be reduced. Therefore, for example, in the memory device 100, it is preferable to arrange the unit memory circuits 110 so that the distance between them is 1 μm or more, 2 μm or more, 3 μm or more, 5 μm or more, or 10 μm or more. In this case, the unit memory circuits 110 may be arranged randomly. Such an arrangement makes it less likely that errors will occur simultaneously in two or more unit memory circuits 110, so that a Hamming code capable of correcting a single-bit error can be used for error correction in the memory device 100.

[0078] [Operation Example] Next, an example of error correction in the storage device 100 will be described using a (7,4) Hamming code. In the (7,4) Hamming code, the code word is 7 bits (n=7), the information sequence is 4 bits (k=4), and the check sequence is 3 bits (m=3).

[0079] In a storage device 100 using a (7,4) Hamming code, a storage unit 101 has seven unit storage circuits 110. As a result, the storage unit 101 can store and hold a 7-bit code word (x1, x2, x3, x4, p1, p2, p3) obtained by adding a 3-bit check sequence (p1, p2, p3) to a 4-bit information sequence (x1, x2, x3, x4), and output it as a 7-bit received word (y1, y2, y3, y4, y5, y6, y7).

[0080] The check bit generator 102 can generate a check sequence (p1, p2, p3) from an information sequence (x1, x2, x3, x4).

[0081] At this time, the check bit generation unit 102 obtains the check matrix (p1, p2, p3) by, for example, the following calculation: Note that "mod 2" indicates the remainder when dividing by 2.

[0082] p1=(x1+x2+x3) mod 2 p2=(x2+x3+x4) mod 2 p3=(x1+x2+x4) mod 2

[0083] Even if an error occurs in any one bit of a 7-bit received word (y1, y2, y3, y4, y5, y6, y7), the error detection and correction unit 103 can output a 7-bit decoded word (w1, w2, w3, w4, w5, w6, w7) in which the erroneous bit has been corrected, and a 7-bit error vector (e1, e2, e3, e4, e5, e6, e7) indicating which bit has been corrected.

[0084] At this time, the error detection and correction unit 103 detects the position of an error from the received word (y1, y2, y3, y4, y5, y6, y7) and performs a calculation to correct the detected error.

[0085] First, for example, a 3-bit syndrome (s1, s2, s3) is obtained by the following calculation.

[0086] s1=(y1+y2+y3+y5) mod 2 s2=(y2+y3+y4+y6) mod 2 s3=(y1+y2+y4+y7) mod 2

[0087] Next, for example, an error vector (e1, e2, e3, e4, e5, e6, e7) is obtained by the following correspondence: "S(s1, s2, s3)" indicates the syndrome (s1, s2, s3), and "E(e1, e2, e3, e4, e5, e6, e7)" indicates the error vector (e1, e2, e3, e4, e5, e6, e7).

[0088] S(1,0,1)=E(1,0,0,0,0,0,0) S(1,1,1)=E(0,1,0,0,0,0,0) S(1,1,0)=E(0,0,1,0,0,0,0) S(0,1,1)=E(0,0,0,1,0,0,0) S(1,0,0)=E(0,0,0,0,1,0,0) S(0,1,0)=E(0,0,0,0,0,1,0) S(0,0,1)=E(0,0,0,0,0,0,1) S(0,0,0)=E(0,0,0,0,0,0,0)

[0089] In this case, a bit that is "1" in the error vector (e1, e2, e3, e4, e5, e6, e7) indicates that an error has occurred in the corresponding bit in the received word (y1, y2, y3, y4, y5, y6, y7).

[0090] Furthermore, the decoded words (w1, w2, w3, w4, w5, w6, w7) are obtained by the following calculations.

[0091] w1=(y1+e1) mod 2 w2=(y2+e2) mod 2 w3=(y3+e3) mod 2 w4=(y4+e4) mod 2 w5=(y5+e5) mod 2 w6=(y6+e6) mod 2 w7=(y7+e7) mod 2

[0092] If the received word (y1, y2, y3, y4, y5, y6, y7) contains a single error bit, the decoded word (w1, w2, w3, w4, w5, w6, w7) obtained by the above calculation will be equal to the code word (x1, x2, x3, x4, p1, p2, p3). Therefore, the decoded sequence (w1, w2, w3, w4) will contain the same information as the information sequence (x1, x2, x3, x4).

[0093] The memory unit 101 can correct errors in the received words (y1, y2, y3, y4, y5, y6, y7) using the decoded words (w1, w2, w3, w4, w5, w6, w7) and the error vectors (e1, e2, e3, e4, e5, e6, e7).

[0094] At this time, the memory unit 101 can store and hold the corresponding bits in the decoded words (w1, w2, w3, w4, w5, w6, w7) in the unit memory circuits 110 corresponding to the bits that are "1" in the error vector (e1, e2, e3, e4, e5, e6, e7), thereby correcting the errors in the received words (y1, y2, y3, y4, y5, y6, y7).

[0095] Here, the error correction will be explained using an example in which an information sequence (0, 1, 0, 1) is given to the storage device 100.

[0096] The check bit generator 102 generates a check matrix (1,0,0) from the information sequence (0,1,0,1). Therefore, the memory 101 stores and holds the codeword (0,1,0,1,1,0,0).

[0097] For example, if no error occurs in the received word, the error detection and correction unit 103 obtains a decoded word (0,1,0,1,1,0,0) and an error vector (0,0,0,0,0,0,0,0) from the received word (0,1,0,1,1,0,0). At this time, all of e1 to e7 in the error vector are "0", indicating that no error occurs in the received word. Furthermore, the decoded word is equal to the code word and the received word.

[0098] On the other hand, for example, if an error occurs in which y3 of the received word is inverted from "0" to "1", the error detection and correction unit 103 obtains a decoded word (0,1,0,1,1,0,0) and an error vector (0,0,1,0,0,0,0) from the received word (0,1,1,1,1,0,0). At this time, the error vector has e3 of "1", indicating that an error has occurred in y3 of the received word. Furthermore, the decoded word is equal to the code word. That is, w3 of the decoded word becomes "0", the same as x3 of the code word.

[0099] In the storage unit 101, the decoded word w3, which is "0", is stored and held in the unit storage circuit 110 corresponding to the error vector e3. As a result, the received word y3 is corrected from "1" to "0".

[0100] <Configuration Example of Unit Memory Circuit> A specific configuration example of the unit memory circuit 110 will be described.

[0101] 2A and 2B are circuit diagrams illustrating examples of the configuration of the unit memory circuit 110. FIG.

[0102] As shown in FIG. 2A, the unit memory circuit 110 includes a scan flip-flop circuit 120 and a backup circuit 130.

[0103] The scan flip-flop circuit 120 includes a selector circuit 121 and a flip-flop circuit 122. The backup circuit 130 includes a holding circuit 131 and a transistor M33. The holding circuit 131 includes a transistor M31, a transistor M32, and a capacitive element C31.

[0104] Various signals for controlling the operation of the unit memory circuit 110 are supplied to the wirings BK, RV, SE, PCK, GBK, and Ec.

[0105] These signals may be generated by a control unit (not shown) included in the storage device 100 or may be generated outside the storage device 100 .

[0106] The unit memory circuit 110 can store and hold data input from the wiring D1 or the wiring SD in the flip-flop circuit 122 in the scan flip-flop circuit 120 in synchronization with a clock signal applied to the wiring PCK, and output the data to the wiring Q. Furthermore, data input from the wiring D2 can be stored in the flip-flop circuit 122 and then held in the flip-flop circuit 122 in response to a signal applied to the wiring Ec. Furthermore, data input from the wiring D2 can be written to the holding circuit 131 in the backup circuit 130 and then held in the flip-flop circuit 122 in response to a signal applied to the wiring BK. This operation may be referred to as, for example, saving, evacuation, storing, or backup. Furthermore, data held in the holding circuit 131 can be written back to the flip-flop circuit 122 via the wiring SD in response to a signal applied to the wiring RV, and then held in the flip-flop circuit 122. This operation may be referred to as, for example, loading, restoring, or recovery.

[0107] Here, if an error occurs in the data held in the flip-flop circuit 122 (the logical value of the held data is inverted), the error detection and correction unit 103 inverts the logical value of the data output to the wiring Q and provides the wiring D2 with a signal indicating that an error has occurred, and provides the wiring Ec with a signal indicating that an error has occurred. Also, if no error occurs in the data held in the flip-flop circuit 122 (the logical value of the held data is not inverted), the error detection and correction unit 103 provides the wiring D2 with data of the same logical value as the logical value of the data output to the wiring Q and provides the wiring Ec with a signal indicating that no error has occurred.

[0108] The flip-flop circuit 122 has an input terminal D1f connected to the wiring D1, an input terminal D2f connected to the wiring D2, an output terminal Qf connected to the wiring Q, and a control terminal Ecf connected to the wiring Ec. The flip-flop circuit 122 has a function of storing and holding data input from the input terminal D1f in synchronization with a clock signal applied to the wiring PCK, and outputting the data to the output terminal Qf. The flip-flop circuit 122 also has a function of storing and holding data input from the input terminal D2f in response to a signal applied to the control terminal Ecf, and outputting the data to the output terminal Qf.

[0109] A specific example of the configuration of the flip-flop circuit 122 will be described later.

[0110] The selector circuit 121 has a function of transmitting data applied to the wiring D1 or the wiring SD to the flip-flop circuit 122 in response to a signal applied to the wiring SE. Code data is applied to the wiring D1. Data held in the holding circuit 131 in the backup circuit 130 or data input from the wiring SD_IN is applied to the wiring SD_IN. Data for a scan test is applied to the wiring SD_IN.

[0111] The selector circuit 121 may be, for example, a selector circuit available in a standard circuit library.

[0112] The backup circuit 130 can hold the state of the scan flip-flop circuit 120 in the holding circuit 131 when power gating is performed.

[0113] 2A , the holding circuit 131 is connected to each of the wiring D2 and the wiring SD. In the holding circuit 131, the terminal (wiring) connected to the wiring D2 serves as an input terminal, and the terminal (wiring) connected to the wiring SD serves as an output terminal. That is, in the unit memory circuit 110, the input terminal D2f of the flip-flop circuit 122 is connected to the input terminal of the holding circuit 131, and the input terminal D1f of the flip-flop circuit 122 is connected to the output terminal of the holding circuit 131 via the selector circuit 121.

[0114] In the holding circuit 131, one of the source or drain of the transistor M31 is connected to one terminal of the capacitance element C31. One of the source or drain of the transistor M32 is connected to one terminal of the capacitance element C31. The other terminal of the capacitance element C31 is connected to a wiring to which a constant potential is supplied. The other of the source or drain of the transistor M31 is connected to the input terminal of the holding circuit 131 (i.e., wiring D2). The other of the source or drain of the transistor M32 is connected to the output terminal of the holding circuit 131 (i.e., wiring SD). The gate of the transistor M31 is connected to wiring BK. The gate of the transistor M32 is connected to wiring RV.

[0115] In addition, in the holding circuit 131, the wiring that connects one of the source or drain of the transistor M31, one of the source or drain of the transistor M32, and one terminal of the capacitance element C31 may be referred to as wiring SN.

[0116] In the backup circuit 130, one of the source and the drain of the transistor M33 is connected to the wiring SD. The other of the source and the drain of the transistor M33 is connected to the wiring SD_IN.

[0117] The gate of the transistor M33 is connected to a line GBK, which is supplied with a signal that controls whether or not a scan test is performed.

[0118] In one embodiment of the present invention, the transistors M31, M32, and M33 can be, for example, OS transistors. OS transistors have characteristics of extremely low off-state current. Furthermore, even in a high-temperature environment, the off-state current hardly increases and the on-state current is not easily reduced.

[0119] As a result, the holding circuit 131 can hold data written to the wiring SN for a long period of time by turning off the transistors M31 and M32. For example, the holding circuit 131 can continue to hold data even when the supply of power to the scan flip-flop circuit 120 is cut off by power gating. That is, the holding circuit 131 can be used as a nonvolatile memory.

[0120] In the unit memory circuit 110, when data held in the wiring SN is written back to the flip-flop circuit 122, the potential of the data may change due to the parasitic capacitance of the wiring SD. Therefore, the capacitance of the capacitor C31 may be set to be larger than the parasitic capacitance of the wiring SD so that the amount of change in the potential of the data is smaller than, for example, the logic threshold value of the flip-flop circuit 122.

[0121] As another example of the configuration of the unit memory circuit 110, for example, a Si transistor may be used as the transistor M33.

[0122] In one embodiment of the present invention, the backup circuit 130 can be provided in the unit memory circuit 110 without changing the circuit configuration and layout of the scan flip-flop circuit 120. That is, the backup circuit 130 is a highly versatile circuit.

[0123] Furthermore, since the backup circuit 130 is stacked on the scan flip-flop circuit 120 in the unit memory circuit 110, the distance of the interconnecting wiring can be shortened. This reduces the energy required for saving and loading data (access energy). This allows for a reduction in the power consumption of the unit memory circuit 110 due to power gating.

[0124] In the unit memory circuit 110, the backup circuit 130 may have multiple holding circuits 131. This allows, for example, when a processing unit switches between multiple tasks, the state of the scan flip-flop circuit 120 for each task to be held in each of the multiple holding circuits 131. This configuration eliminates the need to exchange data for executing each task with a memory (e.g., cache memory or main memory) external to the unit memory circuit 110. This reduces the time required for task switching and the access energy required for data exchange. This improves the operating speed of the processing unit and reduces power consumption.

[0125] Next, a specific example of the configuration of the flip-flop circuit 122 will be described.

[0126] 2B , the flip-flop circuit 122 includes a switch circuit X21, a logical negation (NOT) circuit X22, a NOT circuit X23, a switch circuit X24, a switch circuit X25, a NOT circuit X26, a NOT circuit X27, a switch circuit X28, and a buffer circuit X29. The flip-flop circuit 122 may also include a selector circuit 123.

[0127] Data input from input terminal D1f is stored in a first latch having a first inverter loop composed of NOT circuits X22 and X23, and switch circuits X21 and X24. The data stored in the first latch is stored in a second latch having a second inverter loop composed of NOT circuits X26 and X27, and switch circuits X25 and X28. The data stored in the second latch is output to output terminal Qf via buffer circuit X29.

[0128] The inverting control terminal of the switch circuit X21, the non-inverting control terminal of the switch circuit X24, the non-inverting control terminal of the switch circuit X25, and the inverting control terminal of the switch circuit X28 are connected to a wiring PCKA. The non-inverting control terminal of the switch circuit X21, the inverting control terminal of the switch circuit X24, the inverting control terminal of the switch circuit X25, and the non-inverting control terminal of the switch circuit X28 are connected to a wiring PCKB. A signal having the same logical value as the signal supplied to the wiring PCK is supplied to the wiring PCKA, and a signal obtained by inverting the logical value of the signal supplied to the wiring PCK is supplied to the wiring PCKB.

[0129] With this configuration, the flip-flop circuit 122 can store and hold data input from the input terminal D1f in synchronization with the rising edge of the signal applied to the wiring PCK, and output the data to the output terminal Qf.

[0130] The flip-flop circuit 122 also has a selector circuit 123 in the second latch. The selector circuit 123 has a function of selecting, in response to a signal applied to a control terminal Ecf, whether to hold the data stored in the first latch and the second latch or to transmit data applied to a wiring D2f to the first latch and the second latch.

[0131] That is, for example, when a signal indicating that an error has occurred in the data held in the flip-flop circuit 122 is applied to the control terminal Ecf, the data input from the input terminal D2f is stored in the flip-flop circuit 122. On the other hand, when a signal indicating that no error has occurred in the data held in the flip-flop circuit 122 is applied to the control terminal Ecf, the data stored in the flip-flop circuit 122 continues to be held.

[0132] The switch circuit included in the flip-flop circuit 122 may be, for example, an analog switch circuit available in a standard circuit library. The NOT circuit may be, for example, an inverter circuit available in a standard circuit library. The buffer circuit may be, for example, a buffer circuit available in a standard circuit library. The selector circuit 123 may be, for example, a selector circuit available in a standard circuit library.

[0133] Note that one embodiment of the present invention includes a structure in which at least one of a gate, a source, and a drain of one or more transistors is not connected to anything or is connected to any wiring. Another embodiment of the present invention includes a structure in which nothing is input to one or more wirings or a structure in which any signal or potential is input to one or more wirings.

[0134] [Operation Example] Next, an operation example of the unit memory circuit 110 will be described.

[0135] Fig. 3 is a timing chart for explaining an example of the operation of the unit memory circuit 110 shown in Fig. 2A and Fig. 2B. Fig. 3 shows an example of the operation when the unit memory circuit 110 is powered off by power gating.

[0136] In the following description, the potential of a signal is referred to as potential H or potential L. The potential H is a potential that, when applied to the gate of an n-channel transistor, causes the transistor to be in a conducting state, and a potential that, when applied to the gate of a p-channel transistor, causes the transistor to be in a non-conducting state. The potential L is a potential that, when applied to the gate of an n-channel transistor, causes the transistor to be in a non-conducting state, and a potential that, when applied to the gate of a p-channel transistor, causes the transistor to be in a conducting state.

[0137] Note that the potentials H and L do not need to be the same for each of the multiple signals. The potentials H and L of each of the multiple signals may be different depending on the threshold voltage of the transistor to which the signal is applied. For example, the potentials H and L of a signal applied to the gate of a transistor included in the scan flip-flop circuit 120 may be different from those of a signal applied to the gate of a transistor included in the backup circuit 130.

[0138] In the following description of the operation, it is assumed that the same potential as the potential of the wiring Q is applied to the wiring D2, and the potential L is applied to the wiring Ec. It is also assumed that the potential L is applied to the wiring GBK.

[0139] 3 illustrates the states of signals (potential H or potential L) applied to the wirings PCK, BK, RV, and SE in each period (periods T11 to T14) of the operation. The timing chart also illustrates the states of data applied to the wirings D1, Q, SD, and SN.

[0140] The period immediately before period T11 is a period during which normal operation (Run) is performed. Period T11 is a period during which normal operation is stopped and backup (Backup) is performed. Period T12 is a period during which power gating (PG) is performed. Period T13 is a period during which recovery (Recovery) is performed. Period T14 is a period during which normal operation (Run) is resumed.

[0141] It is assumed that a clock signal is applied to the wiring PCK immediately before the period T11, and that a potential L is applied to each of the wiring BK, the wiring RV, and the wiring SE.

[0142] Therefore, in synchronization with the rising edge of the clock signal applied to the wiring PCK, the data da applied to the wiring D1 is stored in the scan flip-flop circuit 120 and output to the wiring Q. Data da is also applied to the wiring D2. The states of the data applied to the wirings SD and SN are assumed to be indefinite. In the following description, unless otherwise specified, the immediately preceding state is assumed to be maintained.

[0143] In a period T11, the clock signal applied to the line PCK is stopped.

[0144] Next, a potential H is applied to the wiring BK. Then, the data da applied to the wiring D2 is stored in the wiring SN of the holding circuit 131. After that, a potential L is applied to the wiring BK. Then, the data da stored in the wiring SN is held.

[0145] In a period T12, the supply of power to the scan flip-flop circuit 120 is cut off, that is, the power is turned off.

[0146] At this time, the data da stored in the scan flip-flop circuit 120 is lost, and the data da stored in the wiring SN of the holding circuit 131 is held.

[0147] In a period T13, the supply of power to the scan flip-flop circuit 120 is resumed, that is, the scan flip-flop circuit 120 is powered on.

[0148] Next, a potential H is applied to the wiring RV. Then, the data da held in the wiring SN of the holding circuit 131 is applied to the wiring SD. Further, a potential H is applied to the wiring SE. Then, the selector circuit 121 selects the wiring SD.

[0149] Next, a pulse signal is applied to the wiring PCK. Then, in synchronization with the rising edge of the pulse signal, data da applied to the wiring SD is stored in the scan flip-flop circuit 120 and output to the wiring Q. The data da is also applied to the wiring D2. After that, a potential L is applied to each of the wiring RV and the wiring SE.

[0150] In a period T14, the clock signal supplied to the line PCK is restarted.

[0151] Thereafter, data db is applied to the wiring D1. Then, in synchronization with the rising edge of the clock signal applied to the wiring PCK, the data db applied to the wiring D1 is stored in the scan flip-flop circuit 120 and output to the wiring Q. The data db is also applied to the wiring D2.

[0152] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0153] Embodiment 2 In this embodiment, a structural example of a transistor and a capacitor that can be used in the memory device described in the above embodiment will be described.

[0154] <Structure Example 1 of Transistor and Capacitor> In the memory device of one embodiment of the present invention, transistors with various structures can be used.

[0155] 4 is a cross-sectional view of a semiconductor device including a transistor 550, a transistor 500, and a capacitor 590. Note that FIG. 4 illustrates a cross-sectional view of the transistor 550 in the channel length direction (shown as the X direction).

[0156] 4, the transistor 500 is provided above the transistor 550. The capacitor 590 is provided above the transistor 500.

[0157] The conductor 328 over the transistor 550 may be connected to a conductor 591, a conductor 594, and the like over the transistor 550 via a conductor 330, a conductor 356_1, a conductor 356_2, a conductor 356_3, a conductor 356_4, a conductor 518, a conductor 546, and the like. Note that these conductors may be formed using conductors that function as plugs or wirings.

[0158] In this specification and the like, a conductor that functions as a plug or wiring may have multiple components collectively assigned the same reference symbol. The wiring and the plug may be integrated. That is, a portion of the conductor may function as a wiring and a portion of the conductor may function as a plug.

[0159] For each plug or wiring, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer.

[0160] In particular, it is preferable to use a high-melting-point material that has both heat resistance and conductivity for each plug or wiring. Examples of such materials include tungsten and molybdenum. It is also preferable to use a low-resistance conductive material that can reduce wiring resistance for each plug or wiring. Examples of such materials include aluminum and copper.

[0161] [Transistor 550] The transistor 550 will now be described.

[0162] As shown in FIG. 4, the transistor 550 is provided over a substrate 311 and includes a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulating film, a semiconductor region 313 functioning as a channel formation region, a low-resistance region 314a functioning as one of the source region and the drain region, and a low-resistance region 314b functioning as the other of the source region and the drain region.

[0163] The transistor 550 also has an element isolation layer 312 buried in the substrate 311. The element isolation layer 312 is provided between two adjacent transistors 550.

[0164] Note that the transistor 550 may be either a p-channel type or an n-channel type. For example, by connecting the gate of an n-channel transistor 550 and the gate of a p-channel transistor 550, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured.

[0165] Therefore, for example, when the transistor 550 is applied to a memory device, the transistor 550 may be used as a transistor that forms a peripheral circuit for operating the memory device. Furthermore, for example, in the memory device 100 described in the above-described Embodiment 1, the transistor 550 may be used as a transistor that forms the check bit generation unit 102, the error detection and correction unit 103, and the scan flip-flop circuit 120 included in the unit memory circuit 110.

[0166] 5, the transistor 550 can have a so-called Fin structure in which the top surface and the side surfaces in the channel width direction of a semiconductor region 313 made of a part of a substrate 311 are covered with a conductor 316 via an insulator 315. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 550. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 550.

[0167] The transistor 550 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby the region, the low-resistance region 314a that serves as one of the source and drain regions, and the low-resistance region 314b that serves as the other of the source and drain regions. Alternatively, the transistor 550 may be formed of a material containing, for example, germanium, silicon germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 550 may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice to change the lattice spacing. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide, gallium aluminum arsenide, or the like.

[0168] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0169] For example, a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, can be used as the conductor 316. Alternatively, for example, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0170] Note that the work function is determined by the material of a conductor; therefore, the threshold voltage of a transistor can be adjusted by selecting the material of the conductor.

[0171] It is preferable to use a material such as titanium nitride or tantalum nitride as the conductor 316. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum in a laminated state. In particular, in terms of heat resistance, it is preferable to use a tungsten in a laminated state.

[0172] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order to cover the transistor 550 .

[0173] It is preferable to use, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride as the insulators 320, 322, 324, and 326. In particular, it is preferable to use silicon oxide or silicon oxynitride because of their thermal stability.

[0174] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0175] The insulator 322 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0176] As the insulator 324, it is preferable to use an insulator having barrier properties that prevent impurities such as hydrogen from diffusing from the substrate 311 located below the insulator 324 or the transistor 550 to a region located above the insulator 324.

[0177] The insulator having a barrier property against hydrogen can be, for example, silicon nitride formed by chemical vapor deposition (CVD), or a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0178] Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor, such as the transistor 500 described later, the characteristics of the semiconductor element may deteriorate. Therefore, an insulator that suppresses hydrogen diffusion is preferably used between a region where the transistor 500 is provided and a region where the transistor 550 is provided. Specifically, the insulator that suppresses hydrogen diffusion is an insulator that releases a small amount of hydrogen.

[0179] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0180] A conductor 328 is embedded in the insulators 320 and 322. A conductor 330 is embedded in the insulators 324 and 326.

[0181] Each of the conductor 328 and the conductor 330 functions as a plug or a wiring.

[0182] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 4, an insulator 350_1, an insulator 352_1, and an insulator 354_1 are stacked in this order. Furthermore, a conductor 356_1 is embedded in the insulator 350_1, the insulator 352_1, and the insulator 354_1.

[0183] The conductor 356_1 functions as a plug or a wiring. For example, the same material as the conductors 328 and 330 can be used for the conductor 356_1. In particular, it is preferable to use a conductor having a barrier property against hydrogen.

[0184] The insulator 350_1, the insulator 352_1, and the insulator 354_1 can be made of a material similar to that of the insulators 324, 322, and 326. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0185] Here, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350_1 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by the conductor having a barrier property against hydrogen. Therefore, diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0186] For example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. Alternatively, a stack of tantalum nitride and highly conductive tungsten may be used. By using a stack of tantalum nitride and tungsten as the conductor, the conductor can suppress the diffusion of hydrogen while maintaining the conductivity of the wiring.

[0187] That is, by using a stack of tantalum nitride and tungsten for the conductor 356_1, the conductivity of the wiring can be maintained while preventing diffusion of hydrogen from the transistor 550. In this case, a tantalum nitride layer of the conductor 356_1 having a barrier property against hydrogen is preferably in contact with the insulator 350_1 having a barrier property against hydrogen.

[0188] 4, the insulator 350_2, the insulator 352_2, and the insulator 354_2 are stacked in this order. The conductor 356_2 is embedded in the insulator 350_2, the insulator 352_2, and the insulator 354_2.

[0189] The conductor 356_2 functions as a plug or a wiring. For example, the same material as the conductor 356_1 can be used for the conductor 356_2. In particular, it is preferable to include a conductor having a barrier property against hydrogen.

[0190] The insulators 350_2, 352_2, and 354_2 can be formed using materials similar to those of the insulators 350_1, 352_1, and 354_1, for example. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0191] 4, for example, an insulator 350_3, an insulator 352_3, and an insulator 354_3 are stacked in this order. Furthermore, a conductor 356_3 is embedded in the insulator 350_3, the insulator 352_3, and the insulator 354_3.

[0192] The conductor 356_3 functions as a plug or a wiring. For example, the same material as the conductor 356_1 can be used for the conductor 356_3. In particular, it is preferable to include a conductor having a barrier property against hydrogen.

[0193] The insulators 350_3, 352_3, and 354_3 can be formed using materials similar to those of the insulators 350_1, 352_1, and 354_1, for example. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0194] 4, for example, the insulator 350_4, the insulator 352_4, and the insulator 354_4 are stacked in this order. The conductor 356_4 is embedded in the insulator 350_4, the insulator 352_4, and the insulator 354_4.

[0195] The conductor 356_4 functions as a plug or a wiring. For example, the same material as the conductor 356_1 can be used for the conductor 356_4. In particular, it is preferable to include a conductor having a barrier property against hydrogen.

[0196] The insulators 350_4, 352_4, and 354_4 can be formed using materials similar to those of the insulators 350_1, 352_1, and 354_1, for example. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0197] Although an example in which four wiring layers similar to the wiring layer including the conductor 356_1 are provided has been described here, the present invention is not limited to this. A wiring layer including the conductor 356_1 may not be provided, the number of wiring layers similar to the wiring layer including the conductor 356_1 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356_1 may be five or more.

[0198] Note that the transistor 550 illustrated in FIG. 4 is just an example and is not limited to this configuration.

[0199] [Transistor 500] The transistor 500 will be described.

[0200] Fig. 6A is a top view of the transistor 500. Fig. 6B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 6A, and is also a cross-sectional view of the transistor 500 in the channel length direction (illustrated as the X direction). Fig. 6C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in Fig. 6A, and is also a cross-sectional view of the transistor 500 in the channel width direction (illustrated as the Y direction). Note that some elements are omitted from the top view of Fig. 6A for clarity.

[0201] The transistor 500 is a so-called planar transistor, and has a structure that makes it easier to increase the channel length compared to a vertical transistor such as the transistor 600 described later. Therefore, the structure makes it easy to reduce short channel effects such as drain induced barrier lowering (DIBL). In other words, the structure makes it easy to realize a transistor with high saturation (small change in drain current with respect to drain voltage in the saturation region of the transistor).

[0202] Therefore, for example, when the transistor 500 is applied to a memory device, the transistor 500 may be used as a transistor constituting a sense amplifier for reading data from memory cells included in the memory device. Furthermore, for example, the transistor 500 may be used as a transistor constituting the backup circuit 130 included in the unit memory circuit 110 in the memory device 100 described in the first embodiment.

[0203] As shown in FIGS. 6B and 6C, an insulator 514 and an insulator 516 are stacked in this order on top of the insulator 512.

[0204] Any of the insulators 512, 514, and 516 is preferably an insulator that has barrier properties against oxygen, hydrogen, and the like.

[0205] The insulator 514 is preferably an insulator having a barrier property that prevents impurities such as hydrogen from diffusing from outside the region where the transistor 500 is provided to the region where the transistor 500 is provided. The insulator 514 can be, for example, a material similar to the insulator 324 described above.

[0206] As an insulator having a barrier property against hydrogen, it is preferable to use a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0207] In particular, aluminum oxide has a high barrier property against both oxygen and impurities such as hydrogen and water. Therefore, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 500 during and after the manufacturing process of the transistor, and can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0208] Parasitic capacitance between wirings can be reduced by using a material with a relatively low dielectric constant for the insulators 512 and 516. For the insulators 512 and 516, for example, the same material as the insulator 326 described above can be used.

[0209] For example, a conductor 518 is embedded in the insulators 510, 512, 514, and 516.

[0210] The conductor 518 functions as a plug or a wiring. For the conductor 518, for example, the same materials as the conductors 328 and 330 described above can be used.

[0211] In particular, the conductor 518 preferably has a barrier property against both oxygen and impurities such as hydrogen and water in the regions in contact with the insulator 510 and the insulator 514. With such a structure, the transistor 550 and the transistor 500 can be separated by a conductor that has a barrier property against both oxygen and impurities such as hydrogen and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0212] As shown in Figures 6B and 6C, the transistor 500 includes a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 522 arranged on the insulator 516 and the conductor 503, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein so as to overlap between the conductors 542a and 542b, an insulator 545 arranged along the opening, and a conductor 560 arranged on the surface on which the insulator 545 is formed.

[0213] Note that the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0214] The oxide 530 functions as a semiconductor film including a channel formation region of the transistor 500 .

[0215] An oxide semiconductor can be used as the oxide 530. Note that the semiconductor that can be used as the oxide 530 is not limited to an oxide semiconductor. Therefore, in this specification and the like, the term "oxide" may be replaced with the term "semiconductor," "semiconductor layer," or "semiconductor film," as appropriate.

[0216] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560 .

[0217] Here, the conductor 503 preferably includes a conductor 503a provided in contact with the insulators 514 and 516 and a conductor 503b provided so as to be embedded inside the conductor 503a. Furthermore, an insulator 544 is preferably disposed between the insulator 580 and the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b. Furthermore, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Furthermore, an insulator 582 is preferably disposed over the insulator 580, the conductor 560, and the insulator 545.

[0218] 6B and 6C , the conductor 503 has a two-layer structure including the conductor 503a and the conductor 503b, but the conductor 503 is not limited to this structure. For example, the conductor 503 may have a single-layer structure or a three-layer structure.

[0219] Although the configuration in which the ends of the conductors 542a and 542b are aligned with the end of the oxide 530 is shown, the present invention is not limited to this. For example, the conductors 542a and 542b may extend beyond the end of the oxide 530.

[0220] Although the oxide 530 has a two-layer structure including the oxide 530a and the oxide 530b, the structure is not limited thereto. For example, the oxide 530 may have a single-layer structure or a three-layer structure or more.

[0221] Although the conductor 560 has a two-layer structure including the conductor 560a and the conductor 560b, the conductor 560 is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a three-layer structure.

[0222] Here, in the transistor 500, the conductor 560 functions as a gate electrode, the insulator 545 functions as a gate insulating film, and the conductor 542a and the conductor 542b function as one and the other of a source electrode or a drain electrode, respectively.

[0223] As described above, the conductor 560 is formed so as to be embedded in an opening (sometimes referred to as an opening of the insulator 580) formed in a region of the insulator 580 between the conductors 542a and 542b. Therefore, the conductor 560, the conductors 542a, and the conductors 542b are arranged in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. This structure allows the conductor 560 to be formed without providing a margin for alignment. Therefore, the area occupied by the transistor 500 can be reduced. This allows for miniaturization and high integration of semiconductor devices.

[0224] Furthermore, since the conductor 560 is disposed in a self-aligned manner in the region between the conductors 542a and 542b, the conductor 560 does not have a region overlapping with the conductors 542a and 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b. This improves the switching speed of the transistor 500. This improves the frequency characteristics of the semiconductor device.

[0225] Furthermore, miniaturization of semiconductor devices requires shortening the gate length of the transistor 500, but at the same time, it is necessary to ensure that the conductivity of the conductor 560 does not decrease. If the thickness of the conductor 560 is increased for this purpose, the conductor 560 may have a shape with a high aspect ratio. Therefore, by providing the conductor 560 so that it is embedded in the opening of the insulator 580, the conductor 560 with a shape with a high aspect ratio can be formed without collapsing during the process.

[0226] Here, the conductor 560 may function as a first gate (also simply referred to as a gate) electrode, and the conductor 503 may function as a second gate (also referred to as a back-gate) electrode. In this case, the insulator 545 functions as a first gate insulating film, and the insulators 522 and 524 function as second gate insulating films.

[0227] As described above, the conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.

[0228] In this case, in the transistor 500, for example, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 increases the threshold voltage of the transistor 500, thereby enabling a reduction in off-state current. Therefore, for example, applying a negative potential to the conductor 503 can reduce the drain current (sometimes referred to as cutoff current) when the potential applied to the conductor 560 is 0 V.

[0229] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification and the like can also be said to have a structure different from a Fin structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification and the like can also be regarded as a type of Fin structure or a type of planar structure. In this specification and the like, a Fin structure refers to a structure in which the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, a transistor can be obtained that has improved resistance to the short channel effect. In other words, a transistor can be obtained that is less susceptible to the short channel effect.

[0230] By forming a transistor in the S-channel structure, the channel formation region can be electrically surrounded by the electric field of the gate electrode. Since the S-channel structure electrically surrounds the channel formation region with the electric field of the gate electrode, it can be said that the S-channel structure is substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming a transistor in the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the semiconductor film and the gate insulating film can be the entire bulk of the semiconductor film. Therefore, it is possible to increase the density of current flowing through the transistor, thereby improving the on-state current of the transistor or the field-effect mobility of the transistor.

[0231] As described above, the conductor 503 has the conductor 503a formed in contact with the insulators 514 and 516, and the conductor 503b formed further inside.

[0232] The conductor 503a is preferably made of a conductive material that has barrier properties against impurities such as hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules), water, and copper (has the function of suppressing the diffusion of the impurities; i.e., the impurities are less likely to permeate). Furthermore, the conductor 503a is preferably made of a conductive material that has barrier properties against oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (has the function of suppressing the diffusion of oxygen; i.e., the impurities are less likely to permeate). In other words, the conductor 503a preferably has barrier properties against any one or all of the above impurities and oxygen.

[0233] In this way, the conductor 503a has a barrier property against oxygen, which can prevent the conductor 503b from being oxidized and reducing its conductivity, thereby allowing the conductor 503b to also function as a wiring.

[0234] In this case, it is preferable to use a conductive material with high conductivity as the conductor 503b, such as a conductive material containing tungsten, copper, or aluminum as its main component.

[0235] Note that the transistor 500 may not include the conductor 503 (that is, may not include a back gate).

[0236] Here, an oxide semiconductor that can be used for the oxide 530 will be described. The oxide semiconductor includes a metal oxide.

[0237] The metal oxide preferably contains at least one of indium and zinc. Furthermore, for example, it is preferable to have indium, M (wherein M is one or more elements selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. It is particularly preferable that M is one or more elements selected from gallium, aluminum, yttrium, and tin.

[0238] In particular, as the metal oxide, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO"). Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used. Alternatively, an oxide containing indium (In), tin (Sn), and zinc (Zn) (also referred to as "ITZO (registered trademark)") may be used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (also referred to as "IGZTO") may be used.

[0239] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in a metal oxide, a transistor using the metal oxide for a semiconductor film including a channel formation region can have excellent characteristics such as a large on-state current, high field-effect mobility, and high frequency characteristics.

[0240] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition in which In:M:Zn=1:1:1 or thereabouts, a composition in which In:M:Zn=1:1:1.2 or thereabouts, a composition in which In:M:Zn=2:1:3 or thereabouts, a composition in which In:M:Zn=3:1:2 or thereabouts, a composition in which In:M:Zn=4:2:3 or thereabouts, a composition in which In:M:Zn=4:2:4.1 or thereabouts, a composition in which In:M:Zn=5:1:3 or thereabouts, a composition in which In:M:Zn=5:1:6 or thereabouts, a composition in which In:M:Zn=5:1:7 or thereabouts, a composition in which In:M:Zn=5:1:8 or thereabouts, a composition in which In:M:Zn=6:1:6 or thereabouts, and a composition in which In:M:Zn=5:2:5 or thereabouts. Furthermore, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition of In:M:Zn=1:3:2 or a composition thereabout, or a composition of In:M:Zn=1:3:4 or a composition thereabout. Note that a composition thereabout includes a range of plus or minus 30% of the desired atomic ratio.

[0241] For example, when describing a composition having an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when In is taken as 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when In is taken as 5, Ga is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when In is taken as 1, Ga is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0242] Furthermore, when metal oxides are used in a stacked structure, for example, a three-layer stacked structure can be used in which a first layer is a metal oxide having an atomic ratio of metal elements of In:Ga:Zn = 1:1:1, a second layer is a metal oxide having an atomic ratio of metal elements of In:Zn = 4:1, and a third layer is a metal oxide having an atomic ratio of metal elements of In:Ga:Zn = 1:1:1. It is preferable that the band gaps of the metal oxides in the first and third layers are larger than the band gap of the metal oxide in the second layer. This configuration allows the metal oxide in the second layer to serve as the main current path, resulting in a so-called buried channel structure.

[0243] The composition of metal oxides can be analyzed by, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Spectrometry) or the like can be used. Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0244] The metal oxide can be formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

[0245] The oxide semiconductor preferably has crystallinity. Examples of the crystalline oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a nanocrystalline oxide semiconductor (nc-OS), a polycrystalline oxide semiconductor, and a single-crystalline oxide semiconductor. As the oxide semiconductor, it is preferable to use a CAAC-OS or an nc-OS, and it is particularly preferable to use a CAAC-OS.

[0246] The CAAC-OS preferably has multiple layered crystalline regions, each with its c-axis oriented in the normal direction to the surface where it is formed. For example, the oxide semiconductor preferably has layered crystals parallel to the surface where it is formed. With this structure, the layered crystals of the oxide semiconductor are formed parallel to the channel length direction of the transistor, which allows the on-state current of the transistor to be increased.

[0247] In one embodiment of the present invention, in a method for forming an oxide semiconductor, a CAAC-OS, which is an oxide semiconductor with high crystallinity, can be used as a nucleus or a seed to increase the crystallinity of oxide semiconductors formed above and below the CAAC-OS. This can increase the crystallinity of the entire oxide semiconductor. In other words, oxide semiconductors formed above and below the CAAC-OS can be grown by solid-phase growth using the CAAC-OS as a nucleus or a seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can be called an axial growth CAAC (AG CAAC).

[0248] By increasing the crystallinity of an oxide semiconductor, a transistor including the oxide semiconductor in a semiconductor film including a channel formation region can have excellent characteristics (for example, a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), and a highly reliable transistor).

[0249] Note that it is preferable to perform a treatment for increasing the crystallinity of the oxide semiconductor during or after the formation of the oxide semiconductor. Examples of the treatment for increasing the crystallinity of the oxide semiconductor include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0250] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0251] It is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor multiple times during the formation of the oxide semiconductor. For example, when the oxide semiconductor film is formed by an ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform the treatment for increasing the crystallinity every time an oxide semiconductor film having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the methods for forming the first oxide semiconductor film and the second oxide semiconductor film are not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor film by the ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor film and the second oxide semiconductor film. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Although a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single-layer oxide semiconductor film or a stacked structure of three or more layers.

[0252] Treatment for increasing the crystallinity of an oxide semiconductor may be performed after the oxide semiconductor is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor, or may be performed through another film, such as an insulating film, formed on the oxide semiconductor. For example, microwave plasma treatment may be performed after the oxide semiconductor is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor through the insulating film.

[0253] Note that the above-described treatment for increasing the crystallinity of an oxide semiconductor can also serve as treatment for removing impurities contained in the oxide semiconductor. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of an oxide semiconductor in an oxygen gas atmosphere, oxygen vacancies (V Ｏ This can reduce oxygen vacancy.

[0254] When the treatment for increasing the crystallinity of the oxide semiconductor is performed, the substrate temperature is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0255] By increasing the crystallinity of an oxide semiconductor, a highly reliable transistor can be provided.

[0256] The crystallinity of an oxide semiconductor can be analyzed by, for example, an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, a combination of these methods may be used for analysis.

[0257] Note that it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Hydrogen in the oxide semiconductor bonds with oxygen vacancies to form defects in which hydrogen enters the oxygen vacancies (V ＯBecause of this, the formation of a gate insulating film (also referred to as H) may deteriorate the transistor characteristics (e.g., the Id-Vg characteristics of the initial transistor or the Id-Vg characteristics in a long-term reliability test). Therefore, a material that releases little hydrogen is preferably used as a material surrounding the oxide semiconductor, for example, as a material used for an insulator in contact with the oxide semiconductor. Examples of such a material that releases little hydrogen include silicon nitride, silicon nitride oxide, aluminum oxide, and hafnium oxide. This can prevent hydrogen from entering the oxide semiconductor. In particular, using silicon nitride for at least one of the insulators in contact with the oxide semiconductor can improve the reliability of the transistor. Note that a material that releases little hydrogen may have a function of capturing or fixing (also referred to as gettering) hydrogen inside the insulator.

[0258] In the oxide semiconductor, V Ｏ H may function as a donor and generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress, such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, V in an oxide semiconductor Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic hydrogen.

[0259] In this way, V Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as hydrogen and water from the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also referred to as "oxygenation treatment"). Ｏ When an oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0260] Here, it is preferable to use an insulator containing more oxygen than the amount of oxygen required for the stoichiometric composition as the insulator in contact with the oxide 530. The oxygen is easily released from the insulator by heating. Note that in this specification and elsewhere, oxygen released by heating may be referred to as "excess oxygen."

[0261] The insulator 524 is in contact with the oxide 530. Therefore, the insulator 524 preferably has a region containing excess oxygen (also referred to as an "excess oxygen region").

[0262] In this manner, by providing an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced and the reliability of the transistor 500 can be improved.

[0263] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a barrier property against oxygen. The insulator 522 having a barrier property against oxygen can, for example, prevent oxygen contained in the oxide 530 from diffusing toward the insulator 516. Furthermore, for example, the conductor 503 can be prevented from reacting with oxygen contained in the insulator 524, the oxide 530, and the like.

[0264] Here, in a transistor using an oxide semiconductor for a semiconductor film, it is preferable that a channel formation region of the transistor has fewer oxygen vacancies or a lower impurity concentration (for example, the concentration of hydrogen, nitrogen, or a metal element) than a source region and a drain region. Ｏ H is formed and electrons that act as carriers may be generated, so V Ｏ It is also preferable that the amount of H is small. As described above, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0265] In addition, the source and drain regions of the transistor have more oxygen vacancies than the channel formation region. ＯIt is preferable that the source region and the drain region of the transistor have a high carrier concentration or a high impurity concentration. As described above, the source region and the drain region of the transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0266] The band gap of the metal oxide used as the oxide semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap as the oxide semiconductor, the off-state current of the transistor can be reduced.

[0267] The insulator 522 is preferably made of a material with a high relative dielectric constant (high-k).

[0268] As transistors become more miniaturized and highly integrated, the thinner gate insulating film can cause problems such as gate leakage current. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0269] Examples of insulators that function as gate insulating films include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), and strontium titanate (SrTiO ３ ), or an insulator including barium strontium titanate (BST), is preferably used in a single layer or a laminated layer.

[0270] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, in terms of an insulator having barrier properties against oxygen, impurities, etc. As the insulator, it is preferable to use, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0271] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. These insulators may be used after being nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on these insulators.

[0272] By forming the insulator 522 using such a material, the insulator 522 can function as an insulator that prevents oxygen from being released from the oxide 530 and prevents impurities such as hydrogen from being mixed into the oxide 530 from the periphery of the transistor 500.

[0273] 6B and 6C shows a structure in which two layers of the insulator 522 and the insulator 524 are stacked as the second gate insulating film, but the present invention is not limited to this. For example, the second gate insulating film may have a single-layer structure or a stacked structure of three or more layers. In this case, the second gate insulating film may have a structure in which the same material is stacked, or a structure in which different materials are stacked.

[0274] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used as a single layer or a stacked layer for the oxide 530 including the channel formation region. For example, a semiconductor that can be used for the oxide 650 described later may be used for the oxide 530. Note that the semiconductor that can be used for the oxide 530 is not limited to a metal oxide.

[0275] In the oxide 530, by providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0276] The oxide 530 preferably has a configuration of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, the atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to M in the metal oxide used for the oxide 530a.

[0277] The oxide 530a preferably has a conduction band minimum energy higher than that of the oxide 530b, or in other words, the oxide 530a preferably has a lower electron affinity than that of the oxide 530b.

[0278] Here, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes gradually. In other words, the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously, or the junction has a continuous junction. To achieve this, the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b may be reduced.

[0279] Specifically, when the oxide 530a and the oxide 530b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In—Ga—Zn oxide, the oxide 530a may be an In—Ga—Zn oxide, a Ga—Zn oxide, or gallium oxide.

[0280] In this case, the main carrier path is the oxide 530b. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of the transistor 500 can be increased.

[0281] A conductor 542a and a conductor 542b which function as a source electrode and a drain electrode are provided over the oxide 530b.

[0282] The conductors 542a and 542b can be made of, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, an alloy containing these metal elements, or an alloy combining these metal elements. In particular, conductive materials that are resistant to oxidation or that maintain conductivity even after absorbing oxygen are preferably used, such as tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel. Furthermore, metal nitride films such as tantalum nitride are preferably used because they have barrier properties against oxygen, hydrogen, and the like.

[0283] 6B and 6C show a structure in which the conductor 542a and the conductor 542b are single layers, but the present invention is not limited to this. For example, the conductor 542a and the conductor 542b may have a stacked structure of two or more layers.

[0284] The conductor 542a and the conductor 542b may be, for example, a structure in which a tantalum nitride film and a tungsten film are stacked, a structure in which a titanium film and an aluminum film are stacked, a structure in which an aluminum film is stacked on a tungsten film, a structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a structure in which a copper film is stacked on a titanium film, or a structure in which a copper film is stacked on a tungsten film.

[0285] Alternatively, for example, a three-layer structure may be used in which an aluminum film or copper film is stacked on top of a titanium film or titanium nitride film, and a titanium film or titanium nitride film is further stacked on top of that, or a three-layer structure in which an aluminum film or copper film is stacked on top of a molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further stacked on top of that.

[0286] Note that the conductor 542a and the conductor 542b may be formed using a transparent conductive material containing, for example, indium oxide, tin oxide, or zinc oxide.

[0287] 6B , in the oxide 530, a region 543a may be formed as a low-resistance region at the interface with the conductor 542a and in its vicinity. In addition, in the oxide 530, a region 543b may be formed as a low-resistance region at the interface with the conductor 542b and in its vicinity. In this case, the region 543a functions as one of a source region and a drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0288] In this way, by providing the conductors 542a and 542b so as to be in contact with the oxide 530, the oxygen concentrations in the regions 543a and 543b may be reduced. Furthermore, a metal compound layer containing the metal contained in the conductors 542a and 542b and components of the oxide 530 may be formed in the regions 543a and 543b. In such a case, the carrier concentrations in the regions 543a and 543b increase, and the regions 543a and 543b become low-resistance regions.

[0289] The insulator 544 is provided to cover the conductors 542 a and 542 b and suppresses oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided to cover the side surfaces of the oxide 530 and the insulator 524 and to be in contact with the insulator 522.

[0290] For example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used as the insulator 544. In addition, for example, silicon nitride oxide, silicon nitride, etc. can also be used.

[0291] Alternatively, an insulator containing an oxide of one or both of aluminum and hafnium may be used. For example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) may be used. In particular, it is preferable to use hafnium aluminate, for example, because it has high heat resistance and is less likely to crystallize during heat treatment in a later step.

[0292] Note that if the conductors 542a and 542b are made of a material that is resistant to oxidation or a material whose conductivity does not decrease significantly even when it absorbs oxygen, the insulator 544 does not necessarily have to be provided.

[0293] The insulator 544 can prevent impurities such as hydrogen and water contained in the insulator 580 from diffusing into the oxide 530b. The insulator 580 can also prevent excess oxygen from being contained in the conductor 542a and the conductor 542b from being oxidized.

[0294] It is preferable to use an insulator that contains excess oxygen and releases oxygen by heating, similar to the above-described insulator 524, as the insulator 545. In this way, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b.

[0295] Specifically, for example, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies can be used as the insulator 545. In particular, silicon oxide or silicon oxynitride is preferably used in terms of its thermal stability.

[0296] The insulator 545 is preferably an insulator with a reduced concentration of impurities such as hydrogen and water, similar to the insulator 524. The thickness of the insulator 545 is preferably 1 nm to 20 nm.

[0297] Here, a metal oxide may be provided between the insulator 545 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530. The metal oxide preferably has a barrier property against oxygen. This suppresses the diffusion of excess oxygen from the insulator 545 to the conductor 560. This suppresses a decrease in the amount of excess oxygen supplied to the oxide 530. Furthermore, it is possible to suppress oxidation of the conductor 560 due to excess oxygen. For example, a material that can be used for the insulator 544 may be used as the metal oxide.

[0298] 6B and 6C illustrate a structure in which the insulator 545 is a single layer, but the present invention is not limited to this. For example, the insulator 545 functioning as the first gate insulating film may have a stacked structure of two or more layers, similar to the insulators 522 and 524 functioning as the second gate insulating films. For example, the insulator 545 may have a stacked structure of a high-k material and a thermally stable material. This allows the gate voltage during operation of the transistor 500 to be reduced while maintaining the physical film thickness of the insulator 545.

[0299] The conductor 560a of the conductor 560 may be, for example, hydrogen, water, nitrogen, or nitrogen oxide (e.g., N ２ O, NO, or NO ２It is preferable to use a conductive material that has a barrier property against impurities such as copper and the like. It is also preferable to use a conductive material that has a barrier property against oxygen. When the conductor 560a has a barrier property against oxygen, it is possible to prevent the conductor 560b from being oxidized by oxygen contained in the insulator 545, which would reduce the electrical conductivity.

[0300] As the conductive material having a barrier property against oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0301] The conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, by forming the conductor 560b by a sputtering method, the electrical resistance of the conductor 560a can be reduced, making the conductor 560a a conductor. This can be called an oxide conductor (OC) electrode.

[0302] The conductor 560 can also function as a wiring. Therefore, it is preferable to use a conductive material with high conductivity as the conductor 560b, similar to the conductor 503b. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used.

[0303] The conductor 560b may be configured by laminating different materials, for example, titanium or titanium nitride and the above-mentioned conductive material.

[0304] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween.

[0305] The insulator 580 preferably has an excess oxygen region.

[0306] The insulator 580 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or resin. Silicon oxide or silicon oxynitride is particularly preferred because of its thermal stability. Furthermore, silicon oxide or silicon oxide having voids is preferred because it allows for easy formation of an excess oxygen region in a later step.

[0307] By providing the insulator 580 having an excess oxygen region, oxygen is released by heating, and the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the insulator 580 preferably has a reduced concentration of impurities such as hydrogen and water.

[0308] The insulator 582 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 582 by a sputtering method, excess oxygen regions can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions to the oxide 530.

[0309] The insulator 582 can be, for example, a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium.

[0310] In particular, aluminum oxide has a high barrier property against impurities such as hydrogen, and even a thin film with a thickness of 0.5 nm to 3.0 nm can suppress the diffusion of impurities such as hydrogen. Therefore, aluminum oxide formed by sputtering not only functions as an oxygen source but also as an insulator with barrier properties against impurities such as hydrogen.

[0311] An insulator 584 functioning as an interlayer film is preferably provided over the insulator 582. The insulator 584 preferably has a reduced concentration of impurities such as hydrogen and water, similar to the insulator 524, for example.

[0312] The conductor 540a and the conductor 540b are provided in openings formed in the insulator 584, the insulator 582, the insulator 580, and the insulator 544. In this case, the conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same structure as the conductor 546 described below.

[0313] An insulator 586 is provided on the insulator 584 .

[0314] An insulating material having a barrier property against oxygen, hydrogen, and the like is preferably used for the insulator 586. For example, the insulator 586 can be a material similar to that of the insulator 514.

[0315] An insulator 588 is provided on the insulator 586 .

[0316] Parasitic capacitance occurring between wirings can be reduced by using, for example, a material with a relatively low dielectric constant as the insulator 588. For example, a material similar to the insulator 512 or the insulator 516 can be used as the insulator 588.

[0317] For example, a conductor 546 is embedded in the insulators 580, 582, 584, 586, and 588.

[0318] The conductor 546 functions as a plug or wiring.

[0319] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen and water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, hydrogen and water can be prevented from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen and water. When forming an opening to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 may be formed, and the insulator with high barrier properties may be formed in contact with the insulator 522 or the insulator 514. This allows the manufacturing process of the transistor 500 to serve as part of the process. For example, a material similar to the insulator 522 or the insulator 514 may be used as the insulator with high barrier properties against hydrogen and water.

[0320] Note that the transistor 500 illustrated in FIGS. 6A to 6C is an example and is not limited to this configuration.

[0321] 4, a capacitor 590 is provided above the transistor 500. The capacitor 590 includes a conductor 591 over the conductor 546, an insulator 592 over the conductor 591, and a conductor 593 over the insulator 592. The conductor 591 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductor 593 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulator 592 functions as a dielectric. That is, the capacitor 590 forms a metal-insulator-metal (MIM) capacitor.

[0322] A conductor 594 may be provided over the conductor 546. The conductor 594 functions as a plug or a wiring. The conductor 591 functions as an electrode of the capacitor 590. Note that the conductor 594 and the conductor 591 can be formed in the same process.

[0323] For example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, or tungsten nitride film), can be used for the conductors 594 and 591. In addition, for example, indium tin oxide, a material containing tungsten oxide and indium oxide, indium zinc oxide containing tungsten oxide, a material containing titanium oxide and indium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide containing silicon oxide can also be used.

[0324] 4 shows a structure in which the conductor 594 and the conductor 591 are each a single layer, but the present invention is not limited to this. For example, each of the conductor 594 and the conductor 591 may have a stacked structure of two or more layers.

[0325] The conductor may have a structure in which, for example, a conductor having a barrier property against hydrogen and a conductor having high conductivity are provided between them, and a conductor having high adhesion to both of them is provided between them.

[0326] A high-k material having a high dielectric constant is preferably used for the insulator 592. By using a high-k material for the insulator 592, the insulator can be made thick enough to suppress gate leakage current and the capacitance of a capacitor element having the insulator can be sufficiently ensured.

[0327] The high-k insulator may be, for example, an oxide, an oxynitride, a nitride oxide, or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. These materials may also contain silicon. Insulators made of these materials may also be stacked.

[0328] Furthermore, examples of high-k insulators that can be used include aluminum oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, oxides having silicon and zirconium, oxynitrides having silicon and zirconium, oxides having hafnium and zirconium, and oxynitrides having hafnium and zirconium.

[0329] Insulators made of the above materials may be stacked. In this case, it is preferable to use a structure in which a high-k material and a material having a higher dielectric strength than the high-k material are stacked.

[0330] As such an insulator, for example, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used. Alternatively, for example, an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order can be used. Alternatively, for example, an insulator in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in this order can be used. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, as the insulator, the dielectric strength can be improved and electrostatic breakdown of a capacitor element having the insulator can be suppressed.

[0331] A conductor 593 is provided so as to overlap with the conductor 591 with the insulator 592 interposed therebetween.

[0332] The conductor 593 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0333] For example, a high-melting-point material that has both heat resistance and conductivity is preferably used as the conductor 593. Examples of such materials include tungsten and molybdenum, and tungsten is particularly preferred. Furthermore, when the conductor 593 is formed in the same process as other conductors, copper or aluminum may be used as the conductor 593 because they are low-resistance metal materials.

[0334] An insulator 595 is provided over the conductor 593 and the insulator 592. The insulator 595 can be formed using, for example, a material similar to that of the insulator 320. The insulator 595 may also function as a planarizing film that covers the uneven shape below it.

[0335] [Variation of Transistor 500] A transistor that can be used in one embodiment of the present invention is not limited to the transistor 500 illustrated in FIG. 6. For example, a transistor 500 having a structure illustrated in FIG. 7 may be used. The transistor 500 illustrated in FIG. 7 differs from the transistor illustrated in FIG. 6 in that an insulator 555 is used and that the conductors 542a and 542b have a stacked-layer structure.

[0336] 7, the conductor 542a has a layered structure of a conductor 542a1 and a conductor 542a2 on the conductor 542a1. The conductor 542b has a layered structure of a conductor 542b1 and a conductor 542b2 on the conductor 542b1.

[0337] The conductors 542a1 and 542b1 in contact with the oxide 530b are preferably conductors that are resistant to oxidation, such as metal nitrides, which can prevent the conductors 542a and 542b from being excessively oxidized by oxygen contained in the oxide 530b.

[0338] The conductors 542a2 and 542b2 preferably have higher conductivity than the conductors 542a1 and 542b1, which allows the conductors 542a and 542b to function as wirings or electrodes with high conductivity.

[0339] In this manner, conductors 542 a and 542 b that function as wirings or electrodes can be provided in contact with the top surface of the oxide 530 .

[0340] The conductors 542a1 and 542b1 are preferably made of a metal nitride. In particular, it is preferable to use a conductive material that is resistant to oxidation or a material that maintains its conductivity even when it absorbs oxygen.

[0341] For the conductor 542a1 and the conductor 542b1, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In particular, it is preferable to use a nitride containing tantalum. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used.

[0342] The conductors 542a2 and 542b2 preferably have higher conductivity than the conductors 542a1 and 542b1. For example, the film thickness of the conductors 542a2 and 542b2 is preferably greater than the film thickness of the conductors 542a1 and 542b1. The conductors 542a2 and 542b2 may be made of the same conductors that can be used for the conductor 560b described above. By using the above structure, the electrical resistance of the conductors 542a2 and 542b2 can be reduced.

[0343] For example, tantalum nitride or titanium nitride can be used as the conductors 542a1 and 542b1, and tungsten can be used as the conductors 542a2 and 542b2.

[0344] 7 , in the transistor 500, the insulator 555 is in contact with the side surfaces of the insulator 580 and the insulator 544 and is formed using a mask to separate the conductors 542a1 and 542b1. The opening overlaps with a region between the conductors 542a2 and 542b2. Parts of the conductors 542a1 and 542b1 protrude into the opening. Therefore, the insulator 555 is in contact with the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 within the opening. The insulator 545 is in contact with the top surface of the oxide 530 in the region between the conductors 542a1 and 542b1.

[0345] Therefore, in a cross-sectional view of the transistor 500 in the channel length direction, the distance between the conductor 542a1 and the conductor 542b1 is shorter than the distance between the conductor 542a2 and the conductor 542b2. This configuration makes it possible to further shorten the distance between the source and the drain, thereby shortening the channel length. This improves the frequency characteristics of the transistor 500. This makes it possible to provide a semiconductor device with improved operating speed.

[0346] The insulator 555 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 555 is formed in contact with the side surfaces of the conductor 542a2 and the conductor 542b2 and has the function of protecting the conductors 542a2 and 542b2. Since the insulator 555 is exposed to an oxidizing atmosphere, an inorganic insulator that is resistant to oxidation is preferable. Furthermore, since the insulator 555 is in contact with the conductors 542a2 and 542b2, an inorganic insulator that is resistant to oxidation of the conductors 542a2 and 542b2 is preferable. Therefore, it is preferable to use an insulator that has oxygen barrier properties for the insulator 555.

[0347] The insulator 555 can be, for example, silicon nitride.

[0348] The transistor 500 shown in FIG. 7 is formed by forming openings in the insulator 580 and the insulator 544, forming an insulator 555 in contact with the side surfaces of the openings, and then separating the conductors 542a1 and 542b1 using a mask. The openings overlap with the region between the conductors 542a2 and 542b2. Parts of the conductors 542a1 and 542b1 protrude into the openings. Therefore, the insulator 555 is in contact with the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 within the openings. The insulator 545 is in contact with the top surface of the oxide 530 in the region between the conductors 542a1 and 542b1.

[0349] After separating the conductor 542a1 and the conductor 542b1, heat treatment is preferably performed in an oxygen-containing atmosphere before forming the insulator 545. This allows oxygen to be supplied to the oxide 530a and the oxide 530b, thereby reducing oxygen vacancies. Furthermore, the insulator 555 is formed in contact with the side surfaces of the conductor 542a2 and the conductor 542b2, which prevents the conductors 542a2 and 542b2 from being excessively oxidized. As a result, the electrical characteristics and reliability of the transistor can be improved. Furthermore, variation in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed.

[0350] 4 and 6A to 6C and the transistor 500 illustrated in FIG. 7 are just examples and are not limited to these structures. In addition, the capacitor 590 illustrated in FIG. 4 is just an example and is not limited to this structure.

[0351] [Modification of Capacitor 590] A capacitor that can be used in one embodiment of the present invention is not limited to the capacitor 590 illustrated in FIG. 4. For example, a capacitor 590 having a structure illustrated in FIG. 8 may be used. Note that the transistor 550 and the transistor 500 illustrated in FIG. 8 are similar to those illustrated in FIG. 4; therefore, only the capacitor 590 illustrated in FIG. 8 will be described here.

[0352] FIG. 8 illustrates an insulator 596 on the insulator 588, a capacitor 590 on the insulator 596, an insulator 598 on the capacitor 590, and an insulator 595 on the insulator 598.

[0353] As shown in FIG. 8 , an insulator 596 in which a conductor 546 is embedded is provided over an insulator 588. An insulator 597, a conductor 591 embedded in the insulator 597, and a conductor 594 are provided over the insulator 596. An insulator 592 is provided over the conductor 591 to have a region overlapping with the insulator 597. A conductor 593 is provided over the insulator 592 so that an end of the conductor 593 coincides with that of the insulator 592. An insulator 598 is provided to cover the top surface of the insulator 596, the top surface of the conductor 594, the side surfaces of the insulator 592, the side surfaces of the conductor 593, and the top surface of the conductor 593. An insulator 595 is provided over the insulator 598.

[0354] The insulators 596 and 598 may be made of an insulating material that has barrier properties against oxygen, hydrogen, and the like. The insulators 596 and 598 may be made of, for example, a material similar to the insulator 586. The insulator 597 may be made of, for example, a material with a relatively low dielectric constant. This can reduce parasitic capacitance between wirings. The insulator 597 may be made of, for example, a material similar to the insulator 588. In the conductor 591, a region in contact with the insulators 596 and 597 may be made of a conductive material that has barrier properties against oxygen, hydrogen, and the like.

[0355] 8 , by embedding the conductor 591, which functions as one of the pair of electrodes of the capacitor 590, in the insulator 597, the top surfaces of the conductor 591 and the insulator 597 can be planarized and aligned. This allows the insulator 592, which functions as a dielectric of the capacitor 590, and the conductor 593, which functions as the other of the pair of electrodes of the capacitor 590, to be formed with good flatness on the top surfaces of the conductor 591 and the insulator 597, which have good flatness. Furthermore, the insulator 592 and the conductor 593 can be provided so as to encompass the conductor 591. This structure can suppress electric field concentration in the insulator 592. This can prevent leakage current between the pair of electrodes of the capacitor 590 (between the conductor 591 and the conductor 593). Therefore, a highly reliable semiconductor device can be realized.

[0356] <Structure Example 2 of Transistor and Capacitor> Another structure example of a transistor and a capacitor according to one embodiment of the present invention, which is different from the above description, will be described.

[0357] 9A to 9D are top views and cross-sectional views of a semiconductor device including a transistor 500A and a capacitor 590A. FIG. 9A is a top view of the semiconductor device. FIGS. 9B to 9D are cross-sectional views of the semiconductor device. FIG. 9B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 9A , which is also a cross-sectional view of the transistor 500A in the channel length direction (illustrated as the X direction). FIG. 9C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 9A , which is also a cross-sectional view of the transistor 500A in the channel width direction (illustrated as the Y direction). FIG. 9D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 9A , which is also a cross-sectional view of the capacitor 590A in the Y direction. Note that some elements are omitted from the top view of FIG. 9A for clarity.

[0358] 9A to 9D includes an insulator 514, a transistor 500A and a capacitor 590A on the insulator 514, an insulator 580 on the insulator 544 provided in the transistor 500A, an insulator 582 on the insulator 580, an insulator 584 on the capacitor 590A and on the insulator 582, and a conductor 546 (conductors 546a and 546b). The insulator 514, the insulator 580, the insulator 582, and the insulator 584 function as interlayer films. As shown in FIG. 9B, the transistor 500A and the capacitor 590A are at least partially embedded in the insulator 580.

[0359] Note that the insulator 582 and the insulator 522 may each have a function of capturing or fixing hydrogen, for example. This allows hydrogen contained in the insulator 580, the insulator 524, the insulator 545a, the insulator 545b, and the like to be captured or fixed in the insulator 582 or the insulator 522, for example.

[0360] Furthermore, the conductor 546 (the conductor 546a and the conductor 546b) functions as a plug (also referred to as a connection electrode) when connected to the transistor 500A.

[0361] The conductor 546 is disposed in an opening 568 formed in, for example, an insulator 580. The conductor 546 has an area that contacts part of the top surface and part of the side surface of the conductor 542a.

[0362] The transistor 500A includes an oxide 530 that functions as a semiconductor film including a channel formation region, a conductor 560 that functions as a first gate (also simply referred to as a gate) electrode, a conductor 503 that functions as a second gate (also referred to as a back gate) electrode, a conductor 542b that functions as one of a source electrode and a drain electrode, and a conductor 542a that functions as the other of the source electrode and the drain electrode. The transistor 500A also includes an insulator 545a and an insulator 545b that function as a first gate insulating film. The transistor 500A also includes an insulator 522 and an insulator 524 that function as a second gate insulating film.

[0363] The first gate electrode and the first gate insulating film are disposed in an opening 558 formed in the insulator 580 and the insulator 544. That is, the conductor 560, the insulator 545b, and the insulator 545a are disposed in the opening 558.

[0364] The capacitor 590A has a conductor 574 that functions as a lower electrode, an insulator 572 that functions as a dielectric, and a conductor 570 that functions as an upper electrode. That is, the capacitor 590A constitutes a metal-insulator-metal (MIM) capacitor.

[0365] The upper electrode, dielectric, and a portion of the lower electrode of capacitive element 590A are disposed within opening 578 formed in insulator 582, insulator 580, and insulator 544. That is, conductor 570, insulator 572, and conductor 574 are disposed within opening 578.

[0366] [Transistor 500A] As shown in FIGS. 9A to 9C , the transistor 500A includes an insulator 516 on an insulator 514, a conductor 503 (conductors 503a and 503b) disposed so as to be embedded in the insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, and a conductor 542a (conductors 542a1 and 542b1) on the oxide 530b. 42a2) and conductor 542b (conductor 542b1 and conductor 542b2), an insulator 545a on the oxide 530b, an insulator 545b on the insulator 545a, a conductor 560 (conductor 560a and conductor 560b) located on the insulator 545b and overlapping with part of the oxide 530b, and an insulator 544 arranged on the insulator 522, the insulator 524, the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b.

[0367] Note that the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530. The conductor 542a and the conductor 542b may be collectively referred to as the conductor 542.

[0368] The insulator 580 and the insulator 544 have openings 558 that reach the oxide 530b. That is, the openings 558 have a region that overlaps with the oxide 530b. The insulator 544 also has an opening that overlaps with the opening in the insulator 580. That is, the opening 558 includes an opening in the insulator 580 and an opening in the insulator 544.

[0369] The insulator 545a, the insulator 545b, and the conductor 560 are arranged in the opening 558. That is, the conductor 560 has a region overlapping with the oxide 530b with the insulators 545a and 545b interposed therebetween. The conductor 560, the insulator 545a, and the insulator 545b are provided between the conductor 542a and the conductor 542b in the channel length direction of the transistor 500A. The insulator 545b has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0370] As shown in FIG. 9C, the top surface of the insulator 522 is exposed in the region of the opening 558 that does not overlap with the oxide 530.

[0371] Note that the insulator 545a may be made of a material that has a high ability to capture or fix hydrogen, and the insulator 545b may be made of a material that has a high barrier property against hydrogen, thereby preventing impurities such as water and hydrogen from diffusing into the oxide 530. For example, aluminum oxide or the like may be used as the insulator 545a, and silicon nitride or the like may be used as the insulator 545b.

[0372] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b can be suppressed.

[0373] Note that although the transistor 500A has a structure in which the oxide 530 has two stacked layers of the oxide 530a and the oxide 530b, one embodiment of the present invention is not limited to this. For example, the oxide 530 may have a single layer of the oxide 530b. Alternatively, the oxide 530 may have a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b may have a stacked structure.

[0374] The conductor 560 functions as a first gate electrode, and the conductor 503 functions as a second gate electrode. The insulators 545a and 545b function as a first gate insulating film, and the insulators 522 and 524 function as a second gate insulating film. The conductor 542b functions as one of a source electrode and a drain electrode, and the conductor 542a functions as the other of the source electrode and the drain electrode. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0375] 9A , 9B, and 9D , the capacitor 590A includes a conductor 574, an insulator 572, and a conductor 570 (conductors 570a and 570b). The conductor 574 functions as one of a pair of electrodes (also referred to as a lower electrode) of the capacitor 590A, the conductor 570 functions as the other of the pair of electrodes (also referred to as an upper electrode) of the capacitor 590A, and the insulator 572 functions as a dielectric of the capacitor 590A.

[0376] At least a portion of the conductor 574, the insulator 572, the conductor 570a, and the conductor 570b are disposed in openings 578 formed in the insulators 544, 580, and 582. The conductor 574 is disposed over the conductor 542b, the insulator 572 is disposed over the conductor 574, the conductor 570a is disposed over the insulator 572, and the conductor 570b is disposed over the conductor 570a.

[0377] The conductor 574 is arranged along an opening 578 formed in the insulators 544, 580, and 582. It is preferable that the height of a portion of the upper surface of the conductor 574 is higher than the height of the upper surface of the insulator 582. In addition, the lower surface of the conductor 574 is in contact with the upper surface of the conductor 542b.

[0378] The conductor 574 is preferably formed by a film formation method with good coating properties, such as an ALD method or a CVD method.

[0379] The conductor 574 may be, for example, a material that can be used for the above-described conductor 503, conductor 560, or conductor 542. For example, by using the same conductive material as the conductor 542b for the conductor 574, the contact resistance between the conductor 574 and the conductor 542b can be reduced. For example, the conductor 574 can be made of titanium nitride or tantalum nitride formed by an ALD method.

[0380] The insulator 572 is arranged to cover the conductor 574 and a portion of the insulator 582 .

[0381] The insulator 572 is preferably formed by a film formation method with good coating properties, such as an ALD method or a CVD method.

[0382] A material with a high relative dielectric constant (high-k) is preferably used as the insulator 572. For example, the above-described material that can be used for the insulator 592 may be used as the insulator 572.

[0383] Conductor 570 is positioned to fill openings 578 formed in insulators 544 , 580 , and 582 .

[0384] The conductor 570 is preferably formed by, for example, ALD or CVD.

[0385] The conductor 570 may be, for example, a material that can be used for the conductor 503 or the conductor 560. For example, titanium nitride formed by ALD may be used as the conductor 570a, and tungsten formed by CVD may be used as the conductor 570b. Note that if the adhesion of tungsten to the insulator 572 is sufficiently high, a single layer of tungsten formed by CVD may be used as the conductor 570.

[0386] The opening 578 is provided to reach the conductor 542b. That is, the opening 578 has a region overlapping with the conductor 542b. The conductor 542b is one of the source electrode and the drain electrode of the transistor 500A, and can connect the transistor 500A and the capacitor 590A by being in contact with the bottom surface of the conductor 574 provided in the opening 578.

[0387] The distance between the opening 578 and the oxide 530 is preferably short in top view. With such a structure, the area occupied by the capacitor 590A and the transistor 500A can be reduced. Note that the shape of the opening 578 in top view may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse.

[0388] 9B and 9D , a conductor 574 is provided along the opening 578. Thus, the conductor 574 is in contact with the side surfaces of the insulators 544, 580, and 582, the side surface of the conductor 542b1, the side surface and top surface of the conductor 542b2, and the top surface of the insulator 522. Furthermore, the insulator 572 is provided in contact with the top surface of the conductor 574, the conductor 570a is provided in contact with the top surface of the insulator 572, and the conductor 570b is provided in contact with the top surface of the conductor 570a.

[0389] 9B and 9D , the capacitor 590A can be formed in such a manner that the conductor 574 and the conductor 570 are disposed opposite each other in the opening 578 with the insulator 572 interposed therebetween. Therefore, by increasing the depth of the opening 578 (which can also be referred to as the film thickness of the insulator 580), the capacitance of the capacitor 590A can be increased.

[0390] 9B , a portion of the conductor 574, a portion of the insulator 572, and a portion of the conductor 570 are exposed from the opening 578. In other words, a portion of the conductor 574, a portion of the insulator 572, and a portion of the conductor 570 are formed above the top surface of the conductor 560 or above the top surface of the insulator 582.

[0391] A portion of the conductor 574 and a portion of the insulator 572 contact the upper surface of the insulator 582. In other words, the side end of the conductor 574 is covered by the insulator 572. Furthermore, it is preferable that the conductor 570 has a region that overlaps with the insulator 582 via the insulator 572. Here, as shown in FIG. 9B , the side end of the conductor 570 and the side end of the insulator 572 coincide with each other. With this configuration, the conductors 570 and 574 can be separated by the insulator 572, thereby preventing short circuits between the conductors 570 and 574.

[0392] Furthermore, the portion of the conductor 570 above the insulator 582 may be routed to form a wiring. For example, as shown in FIG. 9C , the conductor 570 can be provided extending in the channel width direction of the transistor 500A. This allows the conductor 570 to function as a wiring when a plurality of transistors 500A and capacitors 590A are provided. In this case, the insulator 572 can also be provided extending along with the conductor 570.

[0393] 10 is a cross-sectional view illustrating another example of the structure of the transistor 500A and the capacitor 590A included in the semiconductor device illustrated in FIG. 9B. Here, differences between the semiconductor device illustrated in FIG. 10 and the semiconductor device illustrated in FIG. 9B will be mainly described.

[0394] The semiconductor device shown in FIG. 10 differs from the semiconductor device shown in FIG. 9B in that the side ends of the insulator 524, the oxide 530a, the oxide 530b, the conductor 542a1, and the conductor 542a2 are formed to coincide with each other.

[0395] In addition to the semiconductor device shown in FIG. 9B, the semiconductor device shown in FIG. 10 includes an insulator 552a, an insulator 552b, an insulator 554, an insulator 556, an insulator 521, an insulator 583a, and an insulator 583b.

[0396] 10 , the insulator 552a is provided between the conductor 542a2 and the insulator 544. The insulator 552b is provided between the conductor 542b2 and the insulator 544. Here, the insulators 552a and 552b may function as an etching stopper to protect the conductors 542a2 and 542b2 when the insulator 524, the oxide 530a, the oxide 530b, the conductor 542a1, the conductor 542a2, the insulator 552a, and the insulator 552b are processed collectively.

[0397] 10 , the insulator 554 is provided in the opening 558 between the insulator 545a and the conductor 542a2, the conductor 542b2, the insulator 552a, the insulator 552b, the insulator 544, and the insulator 580, and in contact with a portion of the top surface of the conductor 542a1 and a portion of the top surface of the conductor 542b1. In other words, the insulator 554 can be said to be formed in a sidewall shape in contact with the side surface of the opening 558. Here, the insulator 554 may function as a protective film that prevents the conductors 542a2 and 542b2 from being excessively oxidized when heat treatment is performed in an atmosphere containing oxygen after the conductors 542a1 and 542b1 are separated from each other.

[0398] 10 , the insulator 521 is provided in contact with the bottom surface of the insulator 522. The insulator 583a is provided in contact with the top surface of the insulator 582. The insulator 521 may have a function of suppressing diffusion of impurities such as water and hydrogen from an interlayer insulator disposed below the insulator 521 to the transistor 500A. The insulator 583a may have a function of suppressing diffusion of impurities such as water and hydrogen from an interlayer insulator disposed above the insulator 583a to the transistor 500A.

[0399] 10 , an insulator 583b is provided between the insulator 583a and the insulator 584. The insulator 583b has a function of changing the capacitance of the capacitor 590A depending on its thickness. That is, in the capacitor 590A, for example, the depth of the opening 578 can be increased (for example, by increasing the thickness of the insulator 583b), thereby increasing the capacitance of the capacitor 590A.

[0400] 10 , the insulator 556 is provided in contact with the side surface of the conductor 546. Specifically, the insulator 556 is formed in contact with the side surface of the opening (corresponding to the opening 568 shown in FIG. 9B ) of the insulators 516, 521, 522, 544, 580, 582, 583a, 583b, and 584. The insulator 556 is formed to protrude into the opening. The insulator 556 is also formed on the side surface of the insulator 524, the oxide 530, and the conductor 542a. Here, at least a portion of the conductor 542a is exposed from the insulator 556 and is in contact with the conductor 546. In other words, the conductor 546 is formed to fill the opening via the insulator 556.

[0401] The topmost portion of the insulator 556 formed below the conductor 542a is preferably located below the top surface of the conductor 542a. This structure allows the conductor 546 to be in contact with at least a portion of the side end portion of the conductor 542a. Note that the insulator 556 formed below the conductor 542a preferably has a region in contact with the side surface of the oxide 530. This structure can prevent impurities such as water or hydrogen contained in the insulator 580 from being mixed into the oxide 530 through the conductor 546. Note that the insulator 556 may have a stacked structure of two or more layers.

[0402] Note that the transistor 500A and the capacitor 590A illustrated in FIGS. 9A to 9D and the transistor 500A and the capacitor 590A illustrated in FIG. 10 are just examples and are not limited to these structures.

[0403] <Structure Example 3 of Transistor and Capacitor> Another structure example of a transistor and a capacitor according to one embodiment of the present invention, which is different from the above description, will be described.

[0404] 11A to 11D are a top view, a perspective schematic view, and a cross-sectional view of a semiconductor device including a transistor 600 and a capacitor 690. FIG. 11A is a top view of the semiconductor device. FIG. 11B is a perspective schematic view of the semiconductor device. FIGS. 11C and 11D are cross-sectional views of the semiconductor device. FIG. 11C is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 11A. FIG. 11D is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 11A. Note that some elements are omitted in the top view of FIG. 11A and the perspective schematic view of FIG. 11B for clarity.

[0405] 11A to 11D illustrate an insulator 612, a conductor 610 on the insulator 612, a transistor 600 and a capacitor 690 on the conductor 610, an insulator 620 on the conductor 610, an insulator 640 on the insulator 620, and an insulator 678 on the transistor 600 and the capacitor 690. The insulator 612, the insulator 620, the insulator 640, and the insulator 678 function as interlayer films. The conductor 610 functions as a wiring.

[0406] 11A to 11D , in the transistor 600, an oxide 650 functioning as a semiconductor including a channel formation region is provided along an opening 648 provided in the insulator 640. In the capacitor 690, an insulator 632 functioning as a dielectric is provided along an opening 628 provided in the insulator 620. The transistor 600 is provided so as to overlap with the capacitor 690. The opening 648 where part of the structure of the transistor 600 is provided overlaps with the opening 628 where part of the structure of the capacitor 690 is provided. In particular, the conductor 630 functions as one of the source and drain electrodes of the transistor 600 and one of the pair of electrodes of the capacitor 690. Therefore, the transistor 600 and the capacitor 690 share part of their structures. With this structure, the transistor 600 and the capacitor 690 can be provided without significantly increasing the area occupied by them in a top view.

[0407] Therefore, for example, when the transistor 600 and the capacitor 690 are applied to a memory device, they may be used as a memory cell included in the memory device. Furthermore, for example, in the memory device 100 described in Embodiment 1, the transistor and the capacitor may be used as a transistor and a capacitor included in the backup circuit 130 included in the unit memory circuit 110.

[0408] [Capacitor 690] The capacitor 690 has a conductor 634 on the conductor 610, an insulator 632 on the conductor 634, and a conductor 630 on the insulator 632. The conductor 630 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductor 634 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulator 632 functions as a dielectric. In other words, the capacitor 690 constitutes a metal-insulator-metal (MIM) capacitor.

[0409] 11C and 11D , an opening 628 is provided in the insulator 620, reaching the conductor 610. At least a portion of the conductor 634 is disposed in the opening 628. The conductor 634 has a region in contact with the upper surface of the conductor 610 in the opening 628, a region in contact with the side surface of the insulator 620 in the opening 628, and a region in contact with at least a portion of the upper surface of the insulator 620. The insulator 632 is disposed so that at least a portion of it is located in the opening 628. The conductor 630 is disposed so that at least a portion of it is located in the opening 628. As shown in FIGS. 11C and 11D , the conductor 630 is preferably disposed so as to fill the opening 628.

[0410] The capacitance element 690 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them not only at the bottom but also on the side surfaces of the opening 628, thereby increasing the capacitance per unit area. Therefore, the deeper the opening 628, the greater the capacitance of the capacitance element 690.

[0411] The side surface of the opening 628 (sometimes referred to as the side surface of the opening 628 of the insulator 620) is preferably perpendicular to the upper surface of the conductor 610. In other words, the insulator 620 can be said to have the opening 628 extending in a direction perpendicular to the upper surface of the conductor 610. In this case, the opening 628 has a cylindrical shape.

[0412] Although this embodiment describes an example in which the opening 628 has a circular shape when viewed from above, one embodiment of the present invention is not limited to this. For example, the opening 628 may have a substantially circular shape such as an ellipse, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above. In this case, the maximum width of the opening 628 can be calculated appropriately according to the shape of the topmost part of the opening 628 when viewed from above.

[0413] For example, if opening 628 is rectangular in top view, the maximum width of opening 628 may be the length of the diagonal of the rectangle. Alternatively, for example, if opening 628 is substantially circular such as an ellipse, polygonal, or polygonal with rounded corners in top view, the maximum width of opening 628 may be the maximum width of the shape of opening 628 in top view.

[0414] The portions of the conductor 634, the insulator 632, and the conductor 630 that are disposed in the opening 628 are provided to reflect the shape of the opening 628. Thus, the conductor 634 is provided along the opening 628, the insulator 632 is provided to cover the conductor 634, and the conductor 630 is provided to fill the recess in the insulator 632 that reflects the shape of the opening 628.

[0415] That is, a part of the dielectric (corresponding to the insulator 632) of the capacitor 690 is provided along the side surface of the opening 628. That is, it is provided in a direction perpendicular to the upper surface of the conductor 610. In other words, it can be said that the surface where the upper electrode of the capacitor 690 contacts the dielectric and the surface where the lower electrode contacts the dielectric each have a component perpendicular to the upper surface of the conductor 610.

[0416] 11C and 11D , the opening 628 is provided so that the side surface of the opening 628 is perpendicular to the top surface of the conductor 610; however, one embodiment of the present invention is not limited to this. For example, the side surface of the opening 628 may have a tapered shape.

[0417] In this specification and the like, a tapered shape refers to a shape in which at least a portion of a side surface of a structure is inclined with respect to the substrate surface. The angle between the inclined side surface and the substrate surface is referred to as a taper angle. In particular, in this specification and the like, a tapered shape having a taper angle greater than 0° and less than 90° is sometimes referred to as a forward taper shape, and a tapered shape having a taper angle greater than 90° and less than 180° is sometimes referred to as a reverse taper shape.

[0418] A conductor 634 and an insulator 632 are stacked along the side surface of the opening 628 and the top surface of the conductor 610. A conductor 630 is provided on the insulator 632 so as to fill the opening 628. In this specification and the like, a capacitor element 690 having such a configuration may be referred to as a trench capacitor, a trench capacitor, a deep-hole stacked capacitor, or the like.

[0419] The insulator 640 is arranged on the capacitor 690. That is, the insulator 640 is arranged above the conductor 634, the insulator 632, and the conductor 630. In other words, the conductor 630 is arranged below the insulator 640.

[0420] The conductor 610 is provided below the conductor 634. The conductor 634 has a region in contact with the conductor 610.

[0421] The conductor 610 is provided on the insulator 612. The conductor 610 can be provided, for example, in a planar shape.

[0422] The insulator 612 may be, for example, any of the materials that can be used for the insulator 514 described above.

[0423] It is preferable to use a conductive material with high conductivity as the conductor 610. Note that the conductor 610 may have a single-layer structure or a stacked structure of different materials. For example, the material that can be used for the conductor 503 or the conductor 560 described above may be used as the conductor 610. For example, tungsten or the like can be used.

[0424] The conductor 634 is preferably formed using a single layer or a stacked layer of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. When an oxide insulator is used for the insulator 632, the insulator 632 can suppress oxidation of the conductor 634. When an oxide insulator is used for the insulator 620, the insulator 620 can suppress oxidation of the conductor 634.

[0425] The conductor 634 may be, for example, a material that can be used for the conductor 503 or the conductor 560. For example, titanium nitride or indium tin oxide with added silicon may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used.

[0426] The insulator 632 is provided on the conductor 634. The insulator 632 is provided so as to contact the top surface and side surfaces of the conductor 634. In other words, the insulator 632 preferably has a structure that covers the side end portions of the conductor 634. This can prevent the conductor 634 and the conductor 630 from shorting out.

[0427] As shown in FIGS. 11C and 11D, the insulator 632 may be provided so as to extend in contact with the upper surface of the insulator 620 .

[0428] Alternatively, a structure may be used in which the side end of the insulator 632 coincides with the side end of the conductor 634. With such a structure, the insulator 632 and the conductor 634 can be formed using the same mask, thereby simplifying the manufacturing process.

[0429] A high-k material having a high dielectric constant is preferably used as the insulator 632. By using a high-k material as the insulator 632, the insulator 632 can be made thick enough to suppress gate leakage current and the capacitance of the capacitor 690 can be sufficiently ensured.

[0430] The insulator 632 may be, for example, any of the materials that can be used for the insulator 592 or the insulator 572 described above.

[0431] The conductor 630 is provided in contact with a portion of the upper surface of the insulator 632. The side end of the conductor 630 is preferably located more inward than the side end of the conductor 634 in both the X direction and the Y direction. In a structure in which the insulator 632 covers the side end of the conductor 634, the side end of the conductor 630 may be located more outward than the side end of the conductor 634.

[0432] A single layer or a stack of conductive materials can be used as the conductor 630. For example, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductor 630.

[0433] The conductor 630 may be made of, for example, the material that can be used for the above-described conductor 503, conductor 560, or conductor 542. For example, titanium nitride or tantalum nitride can be used.

[0434] Since the insulator 620 functions as an interlayer film, it preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulator 620, an insulator containing a material with a low dielectric constant can be used in a single layer or a stacked layer.

[0435] The insulator 620 may be, for example, any of the materials that can be used for the insulator 516. For example, silicon oxide or silicon oxynitride is preferably used because of its thermal stability.

[0436] The transistor 600 includes a conductor 630, a conductor 660 on an insulator 640, an oxide 650, an insulator 672 on the oxide 650, and a conductor 670 on the insulator 672. The oxide 650 functions as a semiconductor film including a channel formation region, the conductor 670 functions as a gate electrode, the insulator 672 functions as a gate insulating film, the conductor 630 functions as one of a source electrode and a drain electrode, and the conductor 660 functions as the other of the source electrode and drain electrode.

[0437] In the transistor 600, a metal oxide functioning as an oxide semiconductor is used for the oxide 650 including the channel formation region. For example, the metal oxide that can be used for the oxide 530 described above may be used for the oxide 650.

[0438] 11C and 11D , an opening 648 is provided in the insulator 640 and the conductor 660, reaching the conductor 630. At least a portion of the oxide 650 is disposed in the opening 648. The oxide 650 has a region in contact with the upper surface of the conductor 630 in the opening 648, a region in contact with the side surface of the conductor 660 in the opening 648, and a region in contact with at least a portion of the upper surface of the conductor 660. The insulator 672 is disposed so that at least a portion of it is located in the opening 648. The conductor 670 is disposed so that at least a portion of it is located in the opening 648. As shown in FIGS. 11C and 11D , the conductor 670 is preferably disposed so as to fill the opening 648.

[0439] The conductor 630 may have a structure in which tantalum nitride is stacked on titanium nitride, for example. In this case, the titanium nitride may be in contact with the insulator 632, and the tantalum nitride may be in contact with the oxide 650. With such a structure, excessive oxidation of the conductor 630 by the oxide 650 can be suppressed. Furthermore, when an oxide insulator is used for the insulator 632, excessive oxidation of the conductor 630 can be suppressed by the insulator 632. Note that the conductor 630 may have a structure in which tungsten is stacked on titanium nitride, for example.

[0440] Furthermore, since the conductor 630 has a region in contact with the oxide 650, it is preferable to use a conductive material containing oxygen. With such a structure, the conductor 630 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when a material containing oxygen is used for the insulator 632, the conductivity of the conductor 630 can be maintained.

[0441] Furthermore, as the conductor 630, for example, indium tin oxide (also referred to as ITO), indium tin oxide containing silicon oxide (also referred to as ITSO), or indium zinc oxide (also referred to as IZO (registered trademark)) can be used in a single layer or in a stacked layer.

[0442] The oxide 650 has a region in contact with the side surface of the conductor 660 in the opening 648 and a region in contact with part of the top surface of the conductor 660. In this way, the oxide 650 contacts not only the side surface but also the top surface of the conductor 660, thereby increasing the area in which the oxide 650 and the conductor 660 contact each other.

[0443] 11D shows a structure in which the side edge of the oxide 650 is located inside the side edge of the conductor 660. Note that one embodiment of the present invention is not limited to this. For example, a structure in which the side edge of the oxide 650 and the side edge of the conductor 660 coincide with each other in the Y direction may be used. Alternatively, a structure in which the side edge of the oxide 650 is located outside the side edge of the conductor 660 may be used.

[0444] 11A to 11D , it is preferable that the conductor 670 extends in the Y direction and the conductor 660 extends in the X direction. With this configuration, the conductor 670 and the conductor 660 intersect with each other. Although the conductor 610 is provided in a planar shape in FIG. 11A , one embodiment of the present invention is not limited to this. For example, the conductor 610 may be provided parallel to the conductor 670 or parallel to the conductor 660.

[0445] The side surface of the opening 648 (which may also be referred to as the side surface of the opening 648 of the insulator 640) is preferably perpendicular to the upper surface of the conductor 610. In other words, the insulator 640 can be said to have the opening 648 extending in a direction perpendicular to the upper surface of the conductor 610. In this case, the opening 648 has a cylindrical shape.

[0446] Although this embodiment describes an example in which the opening 648 has a circular shape when viewed from above, one embodiment of the present invention is not limited to this. For example, the opening 648 may have a substantially circular shape such as an ellipse, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above. In this case, the maximum width of the opening 648 can be calculated appropriately according to the shape of the topmost part of the opening 648 when viewed from above.

[0447] For example, if opening 648 is rectangular in top view, the maximum width of opening 648 may be the length of the diagonal of the rectangle. Alternatively, for example, if opening 648 is approximately circular such as an ellipse, polygonal, or polygonal with rounded corners in top view, the maximum width of opening 648 may be the maximum width of the shape of opening 648 in top view.

[0448] The portions of the oxide 650, the insulator 672, and the conductor 670 that are disposed in the opening 648 are provided to reflect the shape of the opening 648. Thus, the oxide 650 is provided along the opening 648, the insulator 672 is provided to cover the oxide 650, and the conductor 670 is provided to fill the recess in the insulator 672 that reflects the shape of the opening 648.

[0449] That is, a part of the semiconductor film (corresponding to the oxide 650) including the channel formation region of the transistor 600 is provided along the side surface of the opening 648. That is, the part is provided perpendicular to the top surface of the conductor 610. In other words, the channel length direction of the transistor 600 can be said to have a component perpendicular to the top surface of the conductor 610. That is, the channel length direction can be said to have a component in the vertical direction (the Z direction in FIGS. 11A to 11D , which is also referred to as the height direction or the direction perpendicular to the formation surface). That is, it can be said that the source electrode and the drain electrode are located at different heights and the drain current flows vertically. Therefore, the transistor of one embodiment of the present invention is a transistor whose channel length direction has a vertical component (that is, a transistor in which the drain current flows vertically), and can be called, for example, a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical-channel transistor, or a vertical-channel transistor.

[0450] Here, the conductor 660 may be, for example, a material that can be used for the conductor 630. The conductor 670 may be, for example, a material that can be used for the conductor 630. The insulator 672 may be, for example, a material that can be used for the above-described insulator 522, insulator 524, or insulator 545. The insulator 640 may be, for example, a material that can be used for the insulator 620. The insulator 678 may be, for example, a material that can be used for the above-described insulator 514 or insulator 612.

[0451] 11C and 11D , the opening 648 is provided so that the side surface of the opening 648 is perpendicular to the top surface of the conductor 610; however, one embodiment of the present invention is not limited to this. For example, the side surface of the opening 648 may have a tapered shape.

[0452] 11C and 11D , the oxide 650 is shown as a single layer, but one embodiment of the present invention is not limited to this. The oxide 650 may have a stacked structure of multiple oxide layers with different chemical compositions.

[0453] Here, an enlarged view of the oxide 650 and its vicinity in Fig. 11C is shown in Fig. 12A, and a cross-sectional view in the XY plane including the conductor 660 is shown in Fig. 12B.

[0454] As shown in FIG. 12A, the oxide 650 has a region 650i and regions 650na and 650nb that are provided to sandwich the region 650i.

[0455] The region 650na is a region of the oxide 650 that contacts the conductor 630. At least a portion of the region 650na functions as one of the source region and drain region of the transistor 600. The region 650nb is a region of the oxide 650 that contacts the conductor 660. At least a portion of the region 650nb functions as the other of the source region and drain region of the transistor 600. As shown in FIG. 12B , the conductor 660 contacts the entire periphery of the oxide 650. Therefore, the other of the source region and drain region of the transistor 600 can be formed along the entire periphery of the portion of the oxide 650 that is formed in the same layer as the conductor 660.

[0456] The region 650i is a region between the regions 650na and 650nb of the oxide 650. At least a part of the region 650i functions as a channel formation region of the transistor 600. That is, the channel formation region of the transistor 600 is located in a region of the oxide 650 between the conductor 630 and the conductor 660. It can also be said that the channel formation region of the transistor 600 is located in a region of the oxide 650 that is in contact with the insulator 640 or in a region in the vicinity of the insulator 640.

[0457] The channel length of the transistor 600 is the distance between the source region and the drain region. In other words, the channel length of the transistor 600 can be said to be determined by the thickness of the insulator 640 on the conductor 630. In Figure 12A, the channel length Lch of the transistor 600 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length Lch is the distance between the edge of the region where the oxide 650 and the conductor 630 meet and the edge of the region where the oxide 650 and the conductor 660 meet. In other words, the channel length Lch corresponds to the length of the side surface of the insulator 640 on the opening 648 side.

[0458] In a planar transistor, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in one embodiment of the present invention, the channel length can be set by the film thickness of the insulator 640. Therefore, the channel length of the transistor 600 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 600, thereby improving its frequency characteristics.

[0459] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 648. This allows the area occupied by the transistor 600 to be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane.

[0460] 12B , the oxide 650, the insulator 672, and the conductor 670 are arranged concentrically in the XY plane including the channel formation region of the oxide 650. Therefore, the side surface of the conductor 670 located at the center faces the side surface of the oxide 650 via the insulator 672. In other words, the entire periphery of the oxide 650 forms the channel formation region in a top view. In this case, the channel width of the transistor 600 is determined by, for example, the perimeter of the oxide 650. In other words, the channel width of the transistor 600 can be determined by the maximum width of the opening 648 (or the maximum diameter if the opening 648 is circular in a top view). In FIGS. 12A and 12B , the maximum width Dia of the opening 648 is indicated by a double-headed, dashed arrow. In FIG. 12B , the channel width Wch of the transistor 600 is indicated by a double-headed, dashed arrow. Increasing the maximum width Dia of the opening 648 increases the channel width per unit area, thereby increasing the on-state current.

[0461] When the opening 648 is formed using photolithography, the maximum width Dia of the opening 648 is limited by the exposure limit of photolithography, making further miniaturization difficult. The maximum width Dia of the opening 648 is set by the film thickness of each of the oxide 650, the insulator 672, and the conductor 670 provided in the opening 648. The maximum width Dia of the opening 648 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 648 is circular in top view, the maximum width Dia of the opening 648 corresponds to the diameter of the opening 648, and the channel width Wch can be calculated as "Dia x π".

[0462] The channel length Lch of the transistor 600 of one embodiment of the present invention is preferably smaller than the channel width Wch of the transistor 600. The channel length Lch of the transistor 600 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width Wch of the transistor 600. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0463] Furthermore, by forming the opening 648 so as to have a circular shape in top view, the oxide 650, the insulator 672, and the conductor 670 are arranged concentrically, which makes the distance between the conductor 670 and the oxide 650 uniform, allowing the gate electric field of the oxide 650 to be applied uniformly.

[0464] Note that the transistor 600 and the capacitor 690 illustrated in FIGS. 11A to 11D are just examples, and the present invention is not limited to these structures.

[0465] [Transistor 600B] In one embodiment of the present invention, the transistor 600 described above may have a back gate.

[0466] 13 is a cross-sectional view illustrating a structural example of a transistor having a back gate according to one embodiment of the present invention. A transistor 600B illustrated in FIG. 13 is a variation of the transistor 600. The transistor 600B has two gates (a gate and a back gate) corresponding to each other with a channel formation region therebetween.

[0467] The transistor 600B differs from the transistor 600 in that it includes a conductor 680 and an insulator 682. In the transistor 600B, the insulator 682 is provided between the insulator 640 and the oxide 650 on the side surface of the opening 648, and the conductor 680 is provided in part of the insulator 640 so as to surround the outer periphery of the oxide 650 with the insulator 682 interposed therebetween.

[0468] Here, the conductor 670 may function as a first gate (also simply referred to as a gate) electrode, and the conductor 680 may function as a second gate (also referred to as a back-gate) electrode. In this case, the insulator 672 functions as a first gate insulating film, and the insulator 682 functions as a second gate insulating film.

[0469] The transistor 600B also differs from the transistor 600 in that the conductor 630 has a recessed portion at a position overlapping with the opening 648. In the transistor 600B, part of the oxide 650 and part of the insulator 682 are provided in the recessed portion of the conductor 630. In this case, the bottom surface of the oxide 650 is located lower than the bottom surface of the insulator 682.

[0470] This structure can increase the area where the oxide 650 and the conductor 630 are in contact with each other, thereby reducing the contact resistance between the oxide 650 and the conductor 630.

[0471] Here, for example, a material that can be used for the conductor 670 may be used as the conductor 680. Furthermore, for example, a material that can be used for the insulator 672 may be used as the insulator 682.

[0472] In a transistor having a back gate, the threshold voltage is shifted by the back gate voltage. The back gate of the transistor may be connected to the gate, one of the source and the drain, or the other of the source and the drain.

[0473] 14A is a cross-sectional view showing an example of a configuration in which the back gate of the transistor 600B (corresponding to the conductor 680) is connected to the gate of the transistor 600B (corresponding to the conductor 670) via an insulator 672 and a conductor 684 embedded in the insulator 640. FIG. 14B is a cross-sectional view showing an example of a configuration in which the back gate of the transistor 600B (corresponding to the conductor 680) is connected to the other of the source or drain of the transistor 600B (corresponding to the conductor 660) via a conductor 684 embedded in the insulator 640. FIG. 14C is a cross-sectional view showing an example of a configuration in which the back gate of the transistor 600B (corresponding to the conductor 680) is connected to one of the source or drain of the transistor 600B (corresponding to the conductor 630) via a conductor 684 embedded in the insulator 640.

[0474] The conductor 684 functions as a plug or wiring.

[0475] 11A to 11D , the transistor 600 and the capacitor 690 may be different from those shown in FIG. 15A and FIG. 15B.

[0476] 15A and 15B illustrate a stacked-layer structure of a conductor 630_1 and a conductor 630_2 over the conductor 630_1 as the conductor 630. The conductor 630_1 functions as one of a pair of electrodes of the capacitor 690, and the conductor 630_2 functions as one of the source and drain electrodes of the transistor 600.

[0477] In addition, a stacked layer structure of a conductor 660_1 and a conductor 660_2 over the conductor 660_1 is illustrated as the conductor 660. For example, the conductor 660_1 can function as a wiring, and the conductor 660_2 can function as the other of the source electrode and drain electrode of the transistor 600.

[0478] 15A , the conductor 630_2 has a recess at a position overlapping with the opening 648, and part of the oxide 650, part of the insulator 672, and part of the conductor 670 are provided in the recess of the conductor 630_2. In this case, the bottom surface of the conductor 670 in the recess can be positioned lower than the top surface of the conductor 630_2 outside the recess.

[0479] By providing the oxide 650 in the recess of the conductor 630_2, the area where the oxide 650 and the conductor 630_2 are in contact with each other can be increased, thereby reducing the contact resistance between the oxide 650 and the conductor 630_2.

[0480] Furthermore, by lowering the height of the bottom surface of the conductor 670, a gate electric field can be easily applied to the channel formation region of the oxide 650. This can improve the electrical characteristics of the transistor 600. Furthermore, a gate electric field can be easily applied to a region of the oxide 650 in contact with the conductor 630_2. This can increase the on-state current of the transistor 600. Furthermore, regardless of whether the conductor 630 or the conductor 660 functions as a drain electrode, the electrical characteristics of the transistor 600 can be improved.

[0481] 15A , the oxide 650 may have a region 650p with rounded corners in the recess of the conductor 630_2. This can suppress electric field concentration in the insulator 672 near the region 650p, compared to when the region 650p has a right angle or an acute angle (a corner). In this way, suppressing the electric field concentration in the insulator 672 can suppress dielectric breakdown of the insulator 672, thereby providing a highly reliable semiconductor device.

[0482] 15B , the conductor 610 has a recess at a position overlapping with the opening 628, and part of the conductor 634, part of the insulator 632, and part of the conductor 630_1 are provided in the recess of the conductor 610. In this case, the bottom surface of the conductor 630_1 in the recess can be positioned lower than the top surface of the conductor 610 outside the recess.

[0483] By providing the conductor 634 in the recessed portion of the conductor 610, it is possible to increase the area where the conductor 634 and the conductor 610 are in contact with each other. Therefore, it is possible to reduce the contact resistance between the conductor 634 and the conductor 610.

[0484] 15B , the conductor 634 may have a region 634p with rounded corners in the recess of the conductor 610. This can suppress electric field concentration on the insulator 632 near the region 634p, compared to when the region 634p is a right angle or an acute angle (having a corner). Furthermore, the end 634q of the conductor 634 may be located below the top surface of the insulator 620. This can suppress electric field concentration on the insulator 632 near the end 634q, compared to when the end 634q is located on the insulator 620. In this way, suppressing the electric field concentration on the insulator 632 can suppress dielectric breakdown of the insulator 632, thereby providing a highly reliable semiconductor device.

[0485] <Transistor Structure Example 4> Another structure example of the transistor of one embodiment of the present invention, which is different from the above description, will be described.

[0486] 16A to 20E illustrate a structural example of a transistor 500F that is different from the above-described transistor 500. FIG.

[0487] [Transistor 500F] FIG. 16A is a top view of the transistor 500F. FIG. 16B is a schematic perspective view of the transistor 500F. FIGS. 16C to 16E are cross-sectional views of the transistor 500F. FIG. 16C is a cross-sectional view of a portion indicated by the dashed dotted line A1-A2 in FIG. 16A and is also a cross-sectional view of the transistor 500F in the channel width direction (Y direction here). FIG. 16D is a cross-sectional view of a portion indicated by the dashed dotted line A3-A4 in FIG. 16A and is also a cross-sectional view of the transistor 500F in the channel width direction. FIG. 16E is a cross-sectional view of a portion indicated by the dashed dotted line A5-A6 in FIG. 16A and is also a cross-sectional view of the transistor 500F in the channel length direction (X direction here). Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that some components are omitted from the top view of FIG. 16A and the schematic perspective view of FIG. 16B. Also, FIG. 17A shows an enlarged view of the vicinity of the conductor 560 in FIG. 16E. Also, FIG. 17B shows an enlarged view of the vicinity of the oxide 530 in FIG. 16C.

[0488] The transistor 500F has a structure that allows the channel width to be increased without significantly increasing the occupied area compared to the transistor 500. That is, the on-state current can be increased without significantly increasing the occupied area.

[0489] Therefore, for example, by applying the transistor 500F to a memory device, the operation speed of the memory device can be improved, such as by improving the speed of reading and writing data from and to memory cells included in the memory device. Furthermore, for example, in the memory device 100 described in Embodiment 1, the transistor 500F may be used as a transistor included in the backup circuit 130 included in the unit memory circuit 110.

[0490] The transistor 500F includes an insulator 514 on a substrate (not shown), an insulator 516 on the insulator 514, an insulator 521 on the insulator 516, an insulator 522 on the insulator 521, an oxide 530 on the insulator 522, conductors 542a and 542b on the oxide 530 and the insulator 522, an insulator 545 on the oxide 530, and a conductor 560 (conductors 560a and 560b) on the insulator 545. Note that in this specification and the like, the conductors 542a and 542b may be collectively referred to as conductors 542.

[0491] An insulator 544 is provided on the conductor 542, and an insulator 580 is provided on the insulator 544. The insulator 545 and the conductor 560 are provided inside a first opening that penetrates the insulator 580 and the insulator 544 and reaches the oxide 530. In a top view, the first opening has a region that overlaps with the oxide 530 and a region that extends beyond the edge of the oxide 530 along the channel width direction. Therefore, in a top view, the insulator 545 and the conductor 560 provided inside the first opening also have a region that overlaps with the oxide 530 and a region that extends beyond the edge of the oxide 530 along the channel width direction. The conductor 560 also functions as a wiring. The insulator 545 has a region that contacts the oxide 530 within the first opening. Furthermore, an insulator 582 is provided on the insulator 580 and the conductor 560. Furthermore, an insulator 584 is provided on the insulator 582.

[0492] Furthermore, insulator 541a is provided in contact with the side surface of the second opening, which penetrates insulators 584, 582, 580, and 544 to reach conductor 542a, and conductor 540a is provided in contact with insulator 541a. Conductor 540a has a region in contact with conductor 542a at the bottom of the first opening.

[0493] Furthermore, an insulator 541b is provided in contact with the side surface of a third opening that penetrates through insulators 584, 582, 580, and 544 to reach conductor 542b, and a conductor 540b is provided in contact with insulator 541b. Conductor 540b has a region that contacts conductor 542b at the bottom of the second opening.

[0494] In this specification and the like, the conductor 540a and the conductor 540b may be collectively referred to as the conductor 540. Furthermore, the insulator 541a and the insulator 541b may be collectively referred to as the insulator 541.

[0495] The oxide 530 includes a channel formation region of the transistor 500F. The conductor 560 has a region that functions as a gate electrode of the transistor 500F. The insulator 545 has a region that functions as a gate insulating film of the transistor 500F. In the transistor 500F, a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region. A region of the conductor 560 that overlaps with the oxide 530 functions as a gate electrode. A region of the insulator 545 where the insulator 545 and the oxide 530 overlap and where the insulator 545 and the conductor 560 overlap functions as a gate insulating film.

[0496] The conductor 542a has a region functioning as one of the source electrode or drain electrode of the transistor 500F. The conductor 540a functions as a plug connecting the conductor 542a and a conductor (not shown) on the insulator 584 to each other. The conductor 542b has a region functioning as the other of the source electrode or drain electrode of the transistor 500F. The conductor 540b functions as a plug connecting the conductor 542b and a conductor (not shown) on the insulator 584 to each other.

[0497] The oxide 530 is formed on the insulator 522. As shown in Fig. 17B, the oxide 530 has a shape with a high aspect ratio in a cross section in the channel width direction. Therefore, the oxide 530 can also be said to have a fin-like shape.

[0498] In this specification, the maximum length of the oxide 530 in the channel formation region in the channel width direction is defined as length Lx, and the maximum length of the oxide 530 in the channel formation region in the direction perpendicular to the formation surface (e.g., the top surface of the insulator 522) (here, this refers to the Z direction) is defined as length Lh. In this case, the ratio of length Lh to length Lx is referred to as the aspect ratio of the oxide 530. Furthermore, the term "fin-shaped" refers to a shape of the oxide 530 having a high aspect ratio (a shape in which length Lh is greater than length Lx) in a cross-sectional view in the channel width direction. Here, a transistor in which a semiconductor layer including a channel formation region is fin-shaped may be referred to as a fin transistor, a fin-type transistor, a fin transistor, a fin transistor, or the like.

[0499] The length Lx can also be considered as the maximum width of the oxide 530 in the channel formation region. Therefore, "length Lx" can be read as "width Lx." The length Lh can also be considered as the maximum height of the oxide 530 in the channel formation region. Therefore, "length Lh" can be read as "height Lh."

[0500] The aspect ratio of the oxide 530 is preferably as large as possible without causing the oxide 530 to collapse during the manufacturing process of the transistor 500F. The aspect ratio of the oxide 530 may be greater than 1 and less than 400, preferably greater than 2 and less than 100, more preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the oxide 530, the height Lh of the oxide 530 is preferably at least longer than the length Lx of the oxide 530. The height Lh of the oxide 530 may be greater than 1 and less than 400 times the length Lx of the oxide 530, preferably greater than 2 and less than 100 times, more preferably greater than 5 and less than 40 times, and even more preferably greater than 10 and less than 20 times. For example, the height Lh may be greater than 2 and less than 10 times the length Lx. For example, the length Lx may be greater than 5 nm and less than 100 nm, preferably greater than 5 nm and less than 50 nm, and even more preferably greater than 10 nm and less than 30 nm. For example, the height Lh may be 50 nm or more and 2000 nm or less, preferably 100 nm or more and 1000 nm or less.

[0501] Furthermore, as shown in FIG. 17B, in a cross-sectional view in the channel width direction, the angle θ formed between the formation surface of the oxide 530 on the insulator 522 and the side surface of the oxide 530 is preferably perpendicular.

[0502] The insulator 545, the conductor 560, and the conductor 542 are provided to cover the oxide 530 having such an aspect ratio. In the transistor 500F, as shown in FIG. 17B , the insulator 545 and a portion of the conductor 560 are provided so as to sandwich the oxide 530 in half. As a result, in a cross-sectional view in the channel width direction, the oxide 530 and the conductor 560 are provided facing each other with the insulator 545 sandwiched between them on the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the oxide 530. In other words, the upper portion, the side surface on the A1 side, and the side surface on the A2 side of the oxide 530 each function as a channel formation region. Therefore, the channel width of the transistor 500F is larger by the amount of the side surface on the A1 side and the side surface on the A2 side of the oxide 530 compared to when the oxide 530 is formed in a planar shape.

[0503] By increasing the channel width in this manner, the on-state current, transconductance, frequency characteristics, and the like of the transistor 500F can be improved. This allows a semiconductor device with high operating speed to be provided. Furthermore, in the structure of the transistor 500F, the channel width can be increased without increasing the occupied area due to the provision of the oxide 530. This allows for miniaturization or high integration of the semiconductor device.

[0504] 17B and other drawings, the upper portion of the oxide 530 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulator 545 and the conductor 542 near the upper portion of the oxide 530. Note that in FIG. 17B and other drawings, the upper portion of the oxide 530 has a symmetrical structure in which curved shapes are provided on both the A1 side and the A2 side; however, one embodiment of the present invention is not limited to this. For example, the upper portion of the oxide 530 may have an asymmetrical structure in which a curved shape is provided on either the A1 side or the A2 side.

[0505] Note that here, an example configuration is shown in which the oxide 530 includes an oxide 530a, an oxide 530b in contact with the oxide 530a, and an oxide 530c in contact with the oxide 530b.

[0506] In this case, for example, the films that become the oxides 530a and 530c may be formed by atomic layer deposition (ALD), and the film that becomes the oxide 530b may be formed by sputtering. Specifically, the film that becomes the oxide 530a may be formed to have a composition of In:Zn=2:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used for the film that becomes the oxide 530a. Alternatively, the film that becomes the oxide 530b may be formed using an oxide target with a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout. Alternatively, the film that becomes the oxide 530c may be formed to have a composition of In:Zn=2:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used for the film that becomes the oxide 530c.

[0507] Next, heat treatment is preferably performed in a temperature range in which the oxide 530 does not become polycrystallized.

[0508] For example, the heat treatment can be carried out at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0509] By forming the oxide 530 using the above method and then performing heat treatment, the oxide 530 can be converted into AG CAAC. As a result, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor 500F can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0510] 17A and 17B , when an oxide semiconductor is used for the oxide 530, the insulator 545 preferably has a stacked structure of an insulator 545a in contact with the oxide 530, an insulator 545b on the insulator 545a, an insulator 545c on the insulator 545b, and an insulator 545d on the insulator 545c. In this case, the insulator 545a and the insulator 545c preferably have a function of capturing hydrogen or fixing hydrogen.

[0511] Examples of insulators capable of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulators 545a and 545c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.

[0512] Furthermore, it is preferable to use a high-k material with a high relative dielectric constant for the insulators 545a and 545c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulators 545a and 545c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating film. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulating film.

[0513] For the insulators 545a and 545c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0514] The insulator 545a can be, for example, an aluminum oxide film. The aluminum oxide preferably has an amorphous structure. By providing the insulator 545a in contact with the oxide 530, hydrogen contained in the oxide 530 can be more effectively captured and fixed to the insulator 545a.

[0515] The insulator 545c can be, for example, hafnium oxide. By providing the insulator 545c between the insulators 545b and 545d, hydrogen contained in the insulators 545b and the like can be more effectively captured and fixed.

[0516] Next, the insulator 545b is preferably a thermally stable insulator such as silicon oxide or silicon oxynitride. A silicon oxide film used as the insulator 545b is preferably formed by a PEALD method.

[0517] In order to suppress oxidation of the conductor 542a, the conductor 542b, and the conductor 560, it is preferable to provide an oxygen barrier insulator near each of the conductor 542a, the conductor 542b, and the conductor 560. For example, an oxygen barrier insulator may be provided for the insulator 545a, the insulator 545d, the insulator 545c, and the insulator 544.

[0518] In this specification and the like, a barrier insulator refers to an insulator with barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. Furthermore, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0519] Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 545a, 545c, 545d, and 544 each preferably have a single-layer structure or a multilayer structure of oxygen barrier insulators.

[0520] The insulator 545a preferably has a barrier property against oxygen. The insulator 545a is preferably at least less permeable to oxygen than the insulator 580. The insulator 545a has a region in contact with the side surface of the conductor 542a and the side surface of the conductor 542b. The insulator 545a having a barrier property against oxygen can prevent the side surfaces of the conductors 542a and 542b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or field-effect mobility of the transistor 500F.

[0521] The insulator 545a is provided in contact with the top surface and side surface of the oxide 530 and the top surface of the insulator 522. The insulator 545a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide 530 during heat treatment or the like. Therefore, oxygen vacancies can be reduced in the oxide 530.

[0522] Furthermore, by providing the insulator 545a, an excessive amount of oxygen can be prevented from being supplied from the insulator 580 to the oxide 530, and an appropriate amount of oxygen can be supplied to the oxide 530. Therefore, excessive oxidation of the source and drain regions can be prevented, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 500F.

[0523] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and is therefore suitable as the insulator 545a.

[0524] The insulator 545d also preferably has a barrier property against oxygen. The insulator 545d is provided between the channel formation region of the oxide 530 and the conductor 560 and between the insulator 580 and the conductor 560. This structure can prevent oxygen contained in the channel formation region of the oxide 530 from diffusing to the conductor 560 and forming oxygen vacancies in the channel formation region of the oxide 530. Furthermore, oxygen contained in the oxide 530 and oxygen contained in the insulator 580 can be prevented from diffusing to the conductor 560 and oxidizing the conductor 560. The insulator 545d is preferably at least less permeable to oxygen than the insulator 580. For example, a silicon nitride film is preferably used as the insulator 545d. In this case, the insulator 545d is an insulator containing at least nitrogen and silicon.

[0525] The insulator 545d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the oxide 530.

[0526] The insulator 544 also preferably has a barrier property against oxygen. The insulator 544 is provided between the insulator 580 and the conductor 542a and between the insulator 580 and the conductor 542b. The insulator 544 is provided in contact with the side surface of the conductor 542, the side surface of the oxide 530, and the top surface of the insulator 522. This configuration can prevent oxygen contained in the insulator 580 from diffusing into the conductor 542. Therefore, it is possible to prevent the conductor 542 from being oxidized by the oxygen contained in the insulator 580 and its resistivity from increasing. The insulator 544 is preferably at least less permeable to oxygen than the insulator 580. For example, it is preferable to use silicon nitride as the insulator 544. In this case, the insulator 544 is an insulator containing at least nitrogen and silicon.

[0527] To prevent the hydrogen concentration in the source and drain regions from decreasing in the oxide 530, it is preferable to provide a hydrogen barrier insulator near each of the source and drain regions. For example, the insulator 544 may be provided with a hydrogen barrier insulator.

[0528] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 544 is preferably a single-layer structure or a stacked structure of a barrier insulator against hydrogen.

[0529] The provision of the insulator 544 can reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentrations in the source and drain regions, thereby making the source and drain regions n-type.

[0530] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 500F can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0531] The insulators 545a to 545d function as part of a gate insulating film. The insulators 545a to 545d, together with the conductor 560, are provided in an opening formed in the insulator 580. To miniaturize the transistor 500F, the insulators 545a to 545d preferably have a small thickness. The thickness of the insulators 545a to 545d is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that at least a portion of the insulators 545a to 545d may have a region having the above thickness.

[0532] The thickness of the silicon oxide film used as the insulator 545 is preferably greater than or equal to 0.7 nm and less than or equal to 3 nm.

[0533] In order to thin the film thicknesses of the insulators 545a to 545d as described above, it is preferable to deposit the insulators 545a to 545d by the ALD method. Furthermore, it is preferable to deposit the insulators 545a to 545d by the ALD method in order to provide the insulators 545a to 545d in openings such as the insulator 580. By depositing the insulator 545 by the ALD method, it is possible to deposit the insulator 545 with good coverage on the side surface of the first opening formed in the insulator 580, the side end of the conductor 542a, and the side end of the conductor 542b.

[0534] Although the insulator 545 has a four-layer structure including insulators 545a to 545d in the above description, one embodiment of the present invention is not limited to this structure. The insulator 545 can also have a structure including at least one of the insulators 545a to 545d. When the insulator 545 is formed using one, two, or three layers of the insulators 545a to 545d, the manufacturing process of the transistor 500F can be simplified and the productivity of a semiconductor device including the transistor 500F can be improved.

[0535] As shown in FIG. 16A , the oxide 530 preferably has a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) in a top view. That is, the oxide 530 preferably has a structure including a plurality of portions extending in the channel width direction and a plurality of portions extending in the channel length direction. This structure can prevent the oxide 530 from collapsing during the transistor manufacturing process when the aspect ratio of the oxide 530 is increased. Note that the oxide 530 shown in FIG. 16A can also be described as having an opening in the center. In FIG. 16A , the shape of the oxide 530 in a top view is line-symmetric about the center A1-A2; however, one embodiment of the present invention is not limited to this. For example, the shape of the oxide 530 in a top view may be asymmetric.

[0536] 16A is a structure in which two circumferential oxides 530 are formed in the channel width direction. As shown in Fig. 16A, the oxide 530 preferably overlaps with the conductor 560 at two or more locations when viewed from above. Therefore, the conductor 560 preferably has two or more regions that overlap with the oxide 530. In other words, it is preferable that the oxide 530 and the conductor 560 have two or more regions that overlap with each other.

[0537] With this structure, as shown in FIG. 16B , multiple fin-shaped oxides 530 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped oxides 530 includes a channel formation region. That is, the transistor 500F functions as a multi-channel transistor. Therefore, the channel width of the transistor 500F can be further increased, thereby increasing the on-state current. Therefore, the operating speed of a semiconductor device including the transistor 500F can be increased.

[0538] Although the structure in which two circumferential oxides 530 are provided has been described here, one embodiment of the present invention is not limited thereto. For example, a structure in which one or three or more circumferential oxides 530 are provided may be used. Furthermore, the circumferential oxides 530 may be joined to form an oxide 530 having a shape with a plurality of openings. Furthermore, a lattice-shaped oxide 530 may be used in top view.

[0539] The insulators 584, 582, 522, and 521 each preferably have an insulator that suppresses the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulators 584 and 521 are preferably made of silicon nitride, which has a high hydrogen barrier property. Furthermore, for example, the insulator 582 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulator 522 is preferably made of hafnium oxide, which is a high-k material and has a high ability to capture or fix hydrogen.

[0540] Note that at least one of the insulators 521 and 522 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulator 521 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 522 can have a stacked structure of hafnium oxide and silicon oxide.

[0541] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film disposed above the insulator 584 to the transistor 500F and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film disposed below the insulator 521 to the transistor 500F and the like. Furthermore, hydrogen contained in the insulator 580, the insulator 545, and the like can be captured and fixed to the insulator 582 or the insulator 522. Furthermore, the insulators 582 and 584 can prevent oxygen contained in the insulator 580 and the like from diffusing upward from the transistor 500F and the like. Furthermore, the insulators 522 and 521 can prevent oxygen contained in the oxide 530 and the like from diffusing downward from the transistor 500F and the like. Thus, by surrounding the transistor 500F from above and below with insulators that have a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen into the oxide semiconductor can be reduced. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0542] The insulators 516 and 580 preferably have a lower dielectric constant than the insulator 522. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0543] For example, it is preferable that the insulators 516 and 580 each include one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0544] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0545] The top surfaces of the insulators 516 and 580 may be planarized.

[0546] The concentration of impurities such as water and hydrogen is preferably reduced in the insulator 580. For example, the insulator 580 preferably includes an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0547] 18A to 18E , the transistor 500F may have a structure in which an insulator 524 is provided under the oxide 530. The planar shape of the insulator 524 (here, the shape when viewed from the Z direction) is similar to that of the oxide 530, and the insulator 524 overlaps with the oxide 530 in a top view. The lower surface of the insulator 524 is in contact with the insulator 522, the side surface of the insulator 524 is in contact with the insulator 545 and the conductor 542a, and the upper surface of the insulator 524 is in contact with the lower surface of the oxide 530. The insulator 524 may be made of an insulating material that can also be used for the insulator 545b. For example, silicon oxide can be used as the insulator 524. Here, FIGS. 18A to 18E correspond to FIGS. 16A to 16E . FIG. 19 corresponds to FIG. 17B . Regarding the configurations according to FIGS. 18A to 18E and 19 that are not explained below, the explanations according to FIGS. 16A to 16E and 17B can be referred to.

[0548] 19 , it is preferable that the thickness t2 of the insulator 545 at the bottom of the first opening be thinner than the thickness t1 (the length of the insulator 524 in the direction perpendicular to the surface on which it is formed) of the insulator 524. With this configuration, the lower surface of the conductor 560 (conductor 560 a) located in the first opening can be positioned lower than the lower surface of the oxide 530 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0549] By positioning the bottom surface of the conductor 560 below the bottom surface of the oxide 530, a sufficient gate electric field can be applied from the top to the bottom of the oxide 530. In other words, within an opening in the insulator 580 or the like, the entire oxide 530 is electrically surrounded by the electric field of the conductor 560, allowing it to function as a channel formation region. This structure prevents the bottom end of the oxide 530 from functioning as a parasitic channel, thereby reducing the off-state current between the source electrode and the drain electrode. Furthermore, it is possible to suppress the transistor from becoming normally on, which is caused by the parasitic channel. In other words, the electrical characteristics of the transistor 500F can be improved.

[0550] Furthermore, as described above, the oxide 530 functions as a channel formation region from the top to the bottom, thereby increasing the channel width, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 500F.

[0551] The transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is called an S-channel structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make the transistor less susceptible to the short channel effect.

[0552] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a GAA structure or an LGAA structure. By using the S-channel structure, the GAA structure, or the LGAA structure for the transistor 500F, the channel formation region formed at or near the interface between the oxide 530 and the insulator 545, which functions as a gate insulating film, can be the entire bulk of the oxide 530. Therefore, the current density flowing through the transistor can be increased, thereby improving the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the oxide 530 has a CAAC structure and a fin-like structure. With this structure, the current path flowing through the source and drain of the transistor can be parallel to the ab plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material. Furthermore, by using such an oxide semiconductor, a device having two-dimensional conduction can be manufactured.

[0553] 20A to 20E, the transistor 500F may have a structure in which a conductor 503 is provided under an insulator 521. Note that FIGS. 20A to 20E correspond to FIGS. 16A to 16E. Regarding the structures in FIGS. 20A to 20E that are not described below, the description of FIGS. 16A to 16E can be referred to.

[0554] The conductor 503 has a region that functions as a gate electrode, similar to the conductor 560. The conductor 560 may be referred to as a first gate electrode (upper gate electrode) of the transistor 500F, and the conductor 503 may be referred to as a second gate electrode (lower gate electrode) of the transistor 500F. Furthermore, when the conductor 560 is referred to as a gate electrode of the transistor 500F, the conductor 503 may be referred to as a backgate electrode of the transistor 500F.

[0555] When the transistor 500F includes the conductor 503 under the insulator 521, the insulators 522 and 521 each have a region that functions as a gate insulating film, similar to the insulator 545. Specifically, a region of the insulators 522 and 521 that overlaps with the conductor 503 functions as a gate insulating film. The insulator 545 may be referred to as a first gate insulating film (upper gate insulating film), and the insulators 522 and 521 may be referred to as a second gate insulating film (lower gate insulating film).

[0556] In the transistor 500F, the conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. In FIGS. 20C and 20E , the conductor 503 is provided inside a fourth opening that penetrates the insulator 516 and reaches the insulator 514. The fourth opening has, in a top view, a region that overlaps with the oxide 530 and a region that extends beyond the edge of the oxide 530 along the channel width direction. Therefore, the conductor 503 provided inside the fourth opening also has, in a top view, a region that overlaps with the oxide 530 and a region that extends beyond the edge of the oxide 530 along the channel width direction. The conductor 503 also functions as a wiring.

[0557] 20C and 20E, the conductor 503 preferably includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom and side surfaces of the fourth opening. The conductor 503b is provided so as to fill a recess in the conductor 503a formed along the bottom and side surfaces of the fourth opening. Here, the height of the upper surface of the conductor 503 coincides with the height of the upper surface of the insulator 516.

[0558] Here, the conductor 503a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0559] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, impurities such as hydrogen contained in the conductor 503b can be prevented from diffusing into the oxide 530 via the insulator 516 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, oxidation of the conductor 503b and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 503a can have a single-layer structure or a multilayer structure of the conductive materials described above. For example, the conductor 503a preferably contains titanium nitride.

[0560] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 503b preferably contains tungsten.

[0561] As described above, the conductor 503 can function as a second gate electrode. In this case, the threshold voltage of the transistor 500F can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500F and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential of the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0562] The electrical resistivity of the conductor 503 is designed taking into account the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 thin within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby suppressing the diffusion of the impurities into the oxide 530.

[0563] Note that although a stacked structure of the conductor 503a and the conductor 503b is shown here, one embodiment of the present invention is not limited thereto, and the conductor 503 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductor 503 has a three-layer stacked structure, in addition to the stacked structure of the conductor 503a and the conductor 503b, a conductor made of a material similar to that of the conductor 503a can be provided on the conductor 503b. In this case, the conductor described above may be formed so that the top surface of the conductor 503b is lower than the top of the conductor 503a and so as to fill the recess formed by the conductor 503a and the conductor 503b.

[0564] <Constituent Materials> Constituent materials that can be used for a semiconductor device including a transistor and a capacitor are not limited to the above-described structural examples. In one embodiment of the present invention, in addition to the above-described constituent materials, the following constituent materials can also be used as appropriate.

[0565] [Substrate] Examples of substrates that can be used for providing the semiconductor device of one embodiment of the present invention, the memory device including the semiconductor device, and the like include a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (e.g., a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, or a substrate including tungsten foil), a semiconductor substrate (e.g., a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate), or an SOI (Silicon on Insulator) substrate. A heat-resistant plastic substrate may also be used as the substrate. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Alternatively, for example, crystallized glass can be used as the glass substrate.

[0566] In addition, the substrate can be, for example, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of flexible substrates, laminated films, or base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic resins. Other examples include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Other examples include polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor deposition film, or paper. In particular, by manufacturing transistors using, for example, semiconductor substrates, single-crystal substrates, or SOI substrates, transistors with small variations in characteristics, size, or shape, high current capacity, and small size can be manufactured. Constructing a circuit using such transistors can reduce the power consumption of the circuit or increase the circuit integration.

[0567] Alternatively, a flexible substrate may be used as the substrate, and one or more of, for example, a transistor, a resistor, and a capacitor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and one or more of, for example, a transistor, a resistor, and a capacitor. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate and transfer the device to another substrate. In this case, for example, one or more of the transistor, resistor, and capacitor can be transferred to a substrate with poor heat resistance or a flexible substrate. Note that the release layer may be, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen.

[0568] That is, a semiconductor device may be formed on a certain substrate and then transferred to another substrate. Examples of substrates onto which a semiconductor device may be transferred include, in addition to the substrates on which the above-described transistors can be formed, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including, for example, natural fibers (silk, cotton, or hemp), synthetic fibers (nylon, polyurethane, or polyester), or recycled fibers (acetate, cupra, rayon, or recycled polyester)), leather substrates, and rubber substrates. By using these substrates, it is possible to manufacture a flexible semiconductor device or a semiconductor device that is not easily broken. It is also possible to impart heat resistance to the semiconductor device. It is also possible to reduce the weight or thickness of the semiconductor device.

[0569] By providing a semiconductor device over a flexible substrate, an increase in weight can be suppressed and a semiconductor device that is less likely to be damaged can be provided.

[0570] [Ferroelectric] A material that can have ferroelectricity may be used as an insulator (such as the insulator 632) that functions as a dielectric and can be used in the semiconductor device of one embodiment of the present invention. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is, for example, one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set as appropriate. For example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is, for example, one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of zirconium atoms to the number of element J2 atoms can be set as appropriate. For example, the ratio of the number of zirconium atoms to the number of element J2 atoms can be set to 1:1 or close to 1:1. Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0571] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is, for example, one or more elements selected from aluminum, gallium, and indium. Furthermore, element M2 is, for example, one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal nitrides containing element M1 and nitrogen may exhibit ferroelectricity even without element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Here, element M3 is, for example, one or more elements selected from magnesium, calcium, strontium, zinc, and cadmium. The ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0572] Furthermore, examples of materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as GaFeO or κ-alumina-type structure ３ Examples include:

[0573] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0574] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, an insulator using a material capable of exhibiting ferroelectricity can be formed as a layered structure made of multiple materials selected from the materials listed above. Incidentally, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also on various processes. Therefore, in this specification, not only a material that exhibits ferroelectricity is referred to as a ferroelectric, but also a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric.

[0575] Metal oxides containing one or both of hafnium and zirconium are preferred because they can exhibit ferroelectricity even in thin films of a few nanometers. The thickness of an insulator made of a ferroelectric material can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, the thickness of the insulator is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned as the insulator functioning as the dielectric of a capacitive element, for example, the capacitive element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In this specification, a layer of a ferroelectric material may be referred to as a ferroelectric layer, metal oxide film, or metal nitride film. Furthermore, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0576] Furthermore, a metal oxide containing either or both of hafnium and zirconium is preferable because it can have ferroelectricity even in a small area. ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２Even if the thickness is less than 100 nm, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element can be reduced.

[0577] Ferroelectrics are insulators that are polarized internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called, for example, an FeRAM (Ferroelectric Random Access Memory) or a ferroelectric memory. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor.

[0578] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in a ferroelectric layer due to an externally applied electric field. Furthermore, the manifestation of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulator made of a material capable of exhibiting ferroelectricity to exhibit ferroelectricity, the insulator must contain crystals. In particular, it is preferable for the insulator to contain crystals having an orthorhombic crystal structure, since ferroelectricity is manifested. The crystal structure of the crystals contained in the insulator may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystals. The insulator may also have an amorphous structure. In this case, the insulator may have a composite structure having an amorphous structure and a crystalline structure.

[0579] In one embodiment of the present invention, a transistor can be formed by appropriately combining the structures of the above-described transistor 500, the transistor 500A, the transistor 600, the transistor 600B, and the transistor 500F.Furthermore, a capacitor can be formed by appropriately combining the structures of the above-described capacitor 590, the capacitor 590A, and the capacitor 690.

[0580] In one embodiment of the present invention, the above-described transistor 500, the transistor 500A, the transistor 600, the transistor 600B, the transistor 500F, or a transistor obtained by appropriately combining any of these can be used in the memory device 100 described in Embodiment 1. For example, the transistors can be used as transistors included in a backup circuit included in the unit memory circuit 110. The above-described capacitors 590, 590A, and 690, or capacitors obtained by appropriately combining any of these, can be used in the memory device 100 described in Embodiment 1. For example, the transistors can be used as capacitors included in the backup circuit included in the unit memory circuit 110. The above-described transistor 550 can be used in the memory device 100 described in Embodiment 1. For example, the transistors can be used as transistors included in the check bit generation unit 102, the error detection and correction unit 103, and the scan flip-flop circuit 120 included in the unit memory circuit 110.

[0581] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0582] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) will be described. Note that the description of the OS transistor will be briefly compared with a transistor including silicon in a channel formation region (also referred to as a Si transistor).

[0583] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that when the carrier concentration in an oxide semiconductor is reduced, the density of defect states in the oxide semiconductor may be reduced by reducing the impurity concentration in the oxide semiconductor. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0584] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges trapped in the trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0585] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0586] Furthermore, when impurities or oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) in the channel formation region, generating electrons that serve as carriers. ＯWhen H is formed, the donor concentration in the channel formation region may increase. As a result, the threshold voltage of an OS transistor may vary as the donor concentration in the channel formation region increases. Therefore, if an OS transistor has oxygen vacancies in the channel formation region of an oxide semiconductor, the OS transistor is likely to have normally-on characteristics (a drain current flows when the gate voltage is 0 V). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0587] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0588] Furthermore, in Si transistors, a short channel effect (SCE) occurs as the transistors are miniaturized. This makes miniaturization of Si transistors difficult. One of the factors that causes the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0589] The short-channel effect is a deterioration in electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0590] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0591] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0592] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ It can also be regarded as an accumulation type non-junction transistor structure.

[0593] The above structure enables an OS transistor to have good electrical characteristics even when miniaturized or highly integrated. For example, an OS transistor can have good electrical characteristics even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor is preferably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in a direction in which carriers move inside a channel formation region during transistor operation and refers to the width of the bottom surface of the gate electrode in a top view of the transistor.

[0594] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0595] As described above, an OS transistor has excellent advantages over a Si transistor in that it has a smaller off-state current and can be manufactured as a transistor with a short channel length.

[0596] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0597] Embodiment 4 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described. The memory device according to one embodiment of the present invention is, for example, a memory device including an oxide semiconductor.

[0598] <Example of Hierarchical Structure of Storage Devices> Generally, computers and the like use various storage devices depending on the application. FIG. 21 shows various storage devices by hierarchy. The higher the storage device, the faster the operating speed is required, while the lower the storage device, the larger the storage capacity and recording density are required. FIG. 21 shows, from the top layer to the bottom, a register, a cache memory, a main memory, and storage. The cache memory may also include, from top to bottom, a primary cache (L1), a secondary cache (L2), and a tertiary cache (L3). While an example having up to a tertiary cache is shown here, a lower-level cache memory may also be included. The lowest-level cache memory may also be called an LLC (Last Level Cache) or an FLC (Final Level Cache). For example, a storage class memory may be included between the main memory and the storage.

[0599] Registers integrated into arithmetic processing units (also called processors) such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Processing Units), and TPUs (Tensor Processing Units) are used to temporarily store the results of calculations performed by cores. They also have the function of retaining setting information for the arithmetic processing units. For this reason, they are frequently accessed by the arithmetic processing units. Therefore, registers are required to have high operating speeds.

[0600] For example, a static random access memory (SRAM) is used as the cache memory. The cache memory has the function of duplicating and storing a portion of the data stored in the main memory. By storing a copy of frequently used data, the speed of accessing the data can be increased. The cache memory is required to have a faster operating speed than the main memory.

[0601] The main memory may be, for example, a dynamic random access memory (DRAM). The main memory has a function of storing programs and data read from storage. The main memory is required to have a larger storage capacity and a higher recording density than cache memory.

[0602] Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires large storage capacity and high recording density. For example, a hard disk drive (HDD) or a solid state drive (SSD) located on top of an HDD can be used as the storage. For example, a large-capacity, non-volatile storage device such as a NAND flash memory (e.g., 3D NAND) can be used as the SSD.

[0603] A memory device according to one embodiment of the present invention (for example, a memory device using an oxide semiconductor) is excellent in that it has high operation speed, is capable of retaining data for a long period of time, has high rewrite endurance, and can be driven at a low voltage.

[0604] A storage device according to one aspect of the present invention is suitable as a storage device located in an area target1 that includes a tier where a cache memory is located, a tier where a main memory is located, and a tier where a storage is located, because it is capable of retaining data for a long period of time. In other words, a storage device according to one aspect of the present invention is suitable for use in an area target1 that includes, in addition to the area where the main memory is located, the boundary area between the main memory and the storage, and the boundary area between the main memory and the cache memory.

[0605] Therefore, for example, it is preferable to replace a DRAM used in a main memory with a storage device according to one embodiment of the present invention. Here, since DRAM requires a refresh operation and is a destructive readout storage device, it consumes more power than other storage devices. Therefore, by not using DRAM, it is possible to reduce power consumption. It is also preferable to replace, for example, a portion of an SRAM used in a cache memory and a portion of a 3D NAND used in storage with a storage device according to one embodiment of the present invention.

[0606] Furthermore, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a layer where the cache memory is located and a layer where the register is located, because the storage device according to one embodiment of the present invention has a high operating speed and can achieve excellent write and read operations. In other words, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a part of the area where the cache memory is located and an area where the register is located.

[0607] Therefore, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a register included in a CPU, a GPU, an NPU, etc. Also, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a cache memory (such as L1, L2, L3, LLC, and FLC).

[0608] One embodiment of the present invention can be configured without using a DRAM, which has conventionally been used as a main memory or the like. In this case, a storage device according to one embodiment of the present invention can be used in place of the DRAM. With such a configuration, power consumption can be dramatically reduced (for example, by one hundredth or one thousandth or less). Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like to which such a configuration is applied throughout the world, global warming can be mitigated.

[0609] As one embodiment of the present invention, for example, at least a part of the memory device 100 described in Embodiment 1 can be used in a register integrated into an arithmetic processing device such as a CPU, a GPU, an NPU, or a TPU.

[0610] <Configuration Example of Memory Device> A memory device 700 of one embodiment of the present invention will be described. At least a part of the memory device 700 can be used as a memory device located in the area target1 including a layer where the cache memory is located, a layer where the main memory is located, and a layer where the storage is located in FIG. 21 described above. Furthermore, the transistor described in Embodiment 2 can be used for at least a part of the memory device 700.

[0611] 22 is a block diagram illustrating an example of the configuration of a memory device 700. The memory device 700 shown in FIG.

[0612] The memory array 721 has a plurality of memory cells 741. The plurality of memory cells 741 are arranged in a matrix of M rows and N columns, where M is an integer equal to or greater than 1, and N is an integer equal to or greater than 1.

[0613] In Figure 22, as representative examples, memory cell 741[1,1] arranged in the first row and first column, memory cell 741[1,N] arranged in the first row and Nth column, memory cell 741[M,1] arranged in the Mth row and first column, and memory cell 741[M,N] arranged in the Mth row and Nth column are shown.

[0614] In addition, Figure 22 shows, as representative examples, wiring WL[1] connected to N memory cells 741 arranged in the first row, wiring WL[M] connected to N memory cells 741 arranged in the Mth row, wiring BL[1] connected to M memory cells 741 arranged in the first column, and wiring BL[N] connected to M memory cells 741 arranged in the Nth column.

[0615] The drive circuit 722 includes a power switch 761, a power switch 762, and a peripheral circuit 771. The peripheral circuit 771 includes a peripheral circuit 781, a control circuit 772, and a voltage generation circuit 773.

[0616] In one embodiment of the present invention, for example, a Si transistor (a transistor including silicon in a channel formation region) can be used as a transistor included in the driver circuit 722. Therefore, for example, a CMOS circuit (e.g., a circuit operating complementarily, a CMOS logic gate, or a CMOS logic circuit) formed by connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor can be used as the driver circuit 722.

[0617] As the Si transistor, for example, at least a part of the transistor 550 described in Embodiment 2 can be applied.

[0618] Furthermore, for example, by using an OS transistor (a transistor including an oxide semiconductor in a channel formation region) as a transistor included in the memory cell 741, the memory array 721 can be stacked over a driver circuit 722 including a Si transistor. This allows the memory device 700 to be miniaturized. Furthermore, the wiring distance between the driver circuit 722 and the memory array 721 can be shortened. This allows the read speed and write speed of the memory device 700 to be improved.

[0619] As the OS transistor, for example, at least some of the transistors 500, 500A, 600, 600B, and 500F described in Embodiment 2 can be used.

[0620] Furthermore, although not shown, the memory device 700 may have a configuration in which the memory array 721 has a plurality of sense amplifiers arranged in a matrix, and a plurality of memory cells 741 are stacked on the sense amplifiers. With such a configuration, the data stored in the memory array 721 can be read out in a massively parallel manner by simultaneously accessing the plurality of sense amplifiers.

[0621] For example, a signal is supplied to each of the terminal BW, terminal CE, terminal GW, terminal MCK, terminal WAKE, terminal ADDR, terminal WDA, terminal PON1, and terminal PON2 from outside the storage device 700. In addition, for example, a signal is output from the terminal RDA to outside the storage device 700.

[0622] For example, a clock signal is applied to terminal MCK. Furthermore, a control signal is applied to each of terminal BW, terminal CE, and terminal GW. A chip enable signal is applied to terminal CE. A global write enable signal is applied to terminal GW. A byte write enable signal is applied to terminal BW. An address signal is applied to terminal ADDR. Write data is applied to terminal WDA. Read data is applied to terminal RDA. A power gating control signal is applied to terminals PON1 and PON2. The signals applied to terminals PON1 and PON2 may be generated by, for example, control circuit 772.

[0623] The control circuit 772 has a function of controlling the operation of the memory device 700. The control circuit 772 has a function of performing a logical operation on signals provided to the terminals CE, GW, and BW, respectively, to determine an operation mode (e.g., a write operation or a read operation) of the memory device 700. The control circuit 772 also has a function of generating a signal that controls the peripheral circuit 781 so that the operation mode is executed.

[0624] The voltage generation circuit 773 has a function of generating an arbitrary potential for operating the driver circuit 722. For example, the voltage generation circuit 773 has a function of generating an arbitrary potential by inputting a clock signal provided to a terminal MCK in accordance with a signal provided to a terminal WAKE. For example, a signal that controls whether or not the clock signal provided to the terminal MCK is input to the voltage generation circuit 773 is provided to the terminal WAKE.

[0625] The peripheral circuit 781 has a function of writing and reading data to and from the memory cells 741. The peripheral circuit 781 has a function of generating various signals for controlling the operation of the memory cells 741, etc. The peripheral circuit 781 has a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

[0626] The row decoder 782 and the column decoder 784 have the function of decoding an address signal applied to the terminal ADDR. The row decoder 782 has the function of specifying a row to be accessed. The column decoder 784 has the function of specifying a column to be accessed. The row driver 783 has the function of selecting the row specified by the row decoder 782 and applying a desired signal to, for example, the corresponding memory cell 741. The column driver 785 has the function of selecting the column specified by the column decoder 784 and applying a desired signal to, for example, the corresponding memory cell 741.

[0627] The data driver 786 has a function of writing and reading data to and from the memory cells 741 selected by the row driver and the column driver. The input circuit 787 has a function of holding data provided to a terminal WDA from outside the memory device 700. The data (data Din) held in the input circuit 787 is written to the memory cells 741 via the data driver 786. The data stored in the memory cells 741 is read out to the output circuit 788 via the data driver 786. The output circuit 788 has a function of holding the read data (data Dout). It also has a function of outputting the held data from a terminal RDA to outside the memory device 700.

[0628] In the memory device 700 shown in Figure 22, for example, the row driver 783 has the function of supplying desired signals to the wirings WL[1] to WL[M], and the column driver 785 and the data driver 786 have the function of exchanging data with the wirings BL[1] to BL[N].

[0629] The power switch 761 has a function of controlling whether or not the potential applied to the terminal VMD is supplied to the peripheral circuit 771. The power switch 762 has a function of controlling whether or not the potential applied to the terminal VMH is supplied to the row driver 783. Here, for example, a high power supply potential (e.g., potential VDD) for operating the drive circuit 722 is applied to the terminal VMD, and a low power supply potential (e.g., potential VSS) is applied to the terminal VMS. Also, for example, a high power supply potential (e.g., a potential higher than potential VDD) for operating the memory cell 741 and the like is applied to the terminal VMH. The power switch 761 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON1. The power switch 762 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON2.

[0630] Note that the circuits and terminals of the driver circuit 722 may be omitted as appropriate. Other circuits and terminals may be added as appropriate.

[0631] <Configuration Example of Memory Cell> A configuration example that can be applied to the memory cell 741 will be described. An OS transistor can be used as a transistor included in the memory cell described below. For example, at least some of the transistors 500, 500A, 600, 600B, and 500F described in Embodiment 2 can be used.

[0632] The memory cell 950a shown in FIG. 23A includes a transistor M911 and a capacitor C911. One of the source or drain of the transistor M911 is connected to one terminal of the capacitor C911. The other of the source or drain of the transistor M911 is connected to a wiring BL that functions as a bit line. The gate of the transistor M911 is connected to a wiring WL that functions as a word line. The other terminal of the capacitor C911 is connected to a wiring CL. Note that the wiring that connects the one of the source or drain of the transistor M911 and one terminal of the capacitor C911 may be referred to as a wiring MN in the following description.

[0633] The memory cell 950a can store binary data by associating the amount of charge stored in the capacitor C911, i.e., the amount of charge held in the wiring MN, with "1" or "0." Note that, for example, ternary or more levels of data may be stored. When writing data, the memory cell 950a controls the conduction state of the transistor M911 to apply a potential corresponding to the data from the wiring BL to the wiring MN, thereby holding a charge corresponding to the potential. When reading data, the memory cell 950a controls the conduction state of the transistor M911 to extract the charge held in the wiring MN to the wiring BL.

[0634] Note that when data is read from the memory cell 950a, the charge held in the wiring MN is extracted to the wiring BL, and the potential of the wiring MN changes. That is, when data is read from the memory cell 950a, the stored data is destroyed. That is, when data is read from the memory cell 950a, destructive reading occurs. Therefore, after data is read from the memory cell 950a, data needs to be written back (refreshed).

[0635] In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor M911.

[0636] Note that the memory cell 950a shown in FIG. 23A is a dynamic random access memory (DRAM) memory cell. In particular, a structure using an OS transistor as the transistor M911 may be referred to as a DOSRAM (registered trademark). Since the DOSRAM uses an OS transistor with extremely low off-state current, it can store data for a long period of time. Furthermore, it can store multi-valued data or analog data. Furthermore, since once-written data can be stored for a long period of time, the frequency of data refresh can be reduced. Furthermore, since the electrostatic capacitance of the cell capacitance (capacitor C911) can be reduced, the cell size can be reduced. Therefore, by using a DOSRAM, it is possible to reduce the power consumption and improve the recording density of a semiconductor device or a memory device.

[0637] The memory cell 950b shown in FIG. 23B is a modification of the memory cell 950a shown in FIG. 23A, and differs in that it does not have the capacitance element C911.

[0638] 23B, charge can be stored in the parasitic capacitance (the capacitance between the gate and either the source or the drain of the transistor M911) shown by the dashed line, etc. By using such a configuration, for example, the cell size can be reduced, and the recording density of the semiconductor device and the memory device can be improved.

[0639] The memory cell 950c shown in FIG. 23C includes a transistor M921, a transistor M922, and a capacitor C921. One of the source or drain of the transistor M921 is connected to the gate of the transistor M922 and one terminal of the capacitor C921. The other of the source or drain of the transistor M921 is connected to a wiring WBL functioning as a write bit line. The gate of the transistor M921 is connected to a wiring WWL functioning as a write word line. One of the source or drain of the transistor M922 is connected to a wiring RBL functioning as a read bit line. The other of the source or drain of the transistor M922 is connected to a wiring PL. The other terminal of the capacitor C921 is connected to a wiring RWL functioning as a read word line. Note that the wiring connecting the one of the source or drain of the transistor M921, the gate of the transistor M922, and one terminal of the capacitor C921 to each other may be referred to as a wiring MN.

[0640] The memory cell 950c can store binary data by associating the amount of charge stored in the capacitor C921, i.e., the amount of charge held in the wiring MN, with "1" or "0." Note that, for example, ternary or more levels of data may be stored. When writing data, the memory cell 950c applies a potential corresponding to the data from the wiring WBL to the wiring MN by controlling the conduction state of the transistor M921, and can hold a charge corresponding to the potential. When reading data, the memory cell 950c can output a potential corresponding to the data to the wiring RBL by turning the transistor M922 on or off depending on the potential of the wiring MN.

[0641] In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor M921, and for example, an n-channel transistor (such as an OS transistor or a Si transistor) can be used as the transistor M922.

[0642] The memory cell 950c shown in FIG. 23C is a gain cell type memory cell. In particular, a configuration using an OS transistor as the transistor M921 may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. Since NOSRAM uses an OS transistor with extremely low off-state current, it can store data for a long period of time. It can also store multilevel data or analog data. Furthermore, since the writing transistor (transistor M921) and the reading transistor (transistor M922) are different, data reading is nondestructive. Therefore, it can be used, for example, as a nonvolatile memory.

[0643] 23D is a modification of the memory cell 950c shown in FIG. 23C, and differs in that it does not include a capacitor C921 and in that the other of the source and the drain of the transistor M922 is connected to the wiring RWL.

[0644] 23D, charge can be stored in a parasitic capacitance added to the wiring MN. By adopting such a configuration, for example, the cell size can be reduced, and the recording density of the semiconductor device and the memory device can be improved.

[0645] The memory cell 950e shown in Figure 23E is a modified example of the memory cell 950c shown in Figure 23C, and differs in that the other of the source or the drain of the transistor M921 is connected to the wiring BL, and one of the source or the drain of the transistor M922 is connected to the wiring BL.

[0646] 23E, the wiring BL can function as both a write bit line and a read bit line. With this configuration, for example, the cell size can be reduced, and the storage density of the semiconductor device and the memory device can be improved.

[0647] 23F is a modification of the memory cell 950c shown in Fig. 23C, and differs in that it has a transistor M922p instead of the transistor M922. The transistor M922p can be, for example, a p-channel Si transistor.

[0648] 23F uses a p-channel transistor to read data, which may simplify the configuration and operation of the sense amplifier, etc. By using such a configuration, for example, the layout area of ​​the driver circuit can be reduced, thereby enabling miniaturization of the semiconductor device and memory device.

[0649] 23C , and further includes a transistor M923. One of the source and drain of the transistor M922 is connected to one of the source and drain of the transistor M923, the other of the source and drain of the transistor M922 is connected to a wiring PL, the other of the source and drain of the transistor M923 is connected to a wiring RBL, and the gate of the transistor M923 is connected to a wiring RWL. The other terminal of the capacitor C921 is connected to a wiring CL instead of the wiring RWL. The transistor M923 can be, for example, an n-channel transistor (e.g., an OS transistor or a Si transistor).

[0650] 23G, the parasitic capacitance between the wiring MN and the wiring RBL can be reduced. With this configuration, for example, it is possible to suppress the introduction of noise into the wiring MN via the gate capacitance of the transistor M922, thereby improving the reliability of the semiconductor device and the memory device.

[0651] The memory cell 950h shown in Figure 23H includes transistors M931, M932, M933, M934, capacitors C931, C932, inverters X931, and X932. One of the source or drain of the transistor M931 is connected to one of the source or drain of the transistor M933, the input terminal of the inverter X931, and the output terminal of the inverter X932. One of the source or drain of the transistor M932 is connected to one of the source or drain of the transistor M934, the output terminal of the inverter X931, and the input terminal of the inverter X932. The other of the source or drain of the transistor M933 is connected to one terminal of the capacitor C931. The other of the source or drain of the transistor M934 is connected to one terminal of the capacitor C932. The other of the source or drain of the transistor M931 is connected to a wiring BL that functions as one of a pair of bit lines. The other of the source and drain of the transistor M932 is connected to a wiring BLB that functions as the other of the pair of bit lines. The gates of the transistors M931 and M932 are connected to a wiring WL that functions as a word line. The gates of the transistors M933 and M934 are connected to a wiring BRL. The other terminal of the capacitor C931 and the other terminal of the capacitor C932 are connected to a wiring CL.

[0652] The memory cell 950h can store binary data of "1" or "0" in an inverter loop formed by an inverter X931 and an inverter X932. When writing data, the memory cell 950h can apply potentials corresponding to the data to the inverter loop from the wiring BL and the wiring BLB by controlling the conduction states of the transistors M931 and M932. When reading data, the memory cell 950h can extract potentials corresponding to the data stored in the inverter loop from the wiring BL and the wiring BLB by controlling the conduction states of the transistors M931 and M932.

[0653] Furthermore, by controlling the conduction states of the transistors M933 and M934, the memory cell 950h can apply a potential corresponding to the data stored in the inverter loop to one terminal of the capacitor C931 and one terminal of the capacitor C932, respectively, and can hold a charge corresponding to the potential. In other words, data can be backed up. Furthermore, by controlling the conduction states of the transistors M933 and M934, the memory cell 950h can extract the charge held in one terminal of the capacitor C931 and one terminal of the capacitor C932, respectively, to the inverter loop. In other words, data can be recovered.

[0654] In one embodiment of the present invention, for example, n-channel OS transistors can be used as the transistors M931, M932, M933, and M934. Furthermore, inverter circuits available in a standard circuit library can be used as the inverters X931 and X932. That is, for example, n-channel and p-channel Si transistors can be used as the transistors included in the inverters X931 and X932.

[0655] Note that the memory cell 950h shown in FIG. 23H is a memory cell of a back-up capable static random access memory (SRAM). In particular, a configuration in which OS transistors are used for the transistors M931, M932, M933, and M934 may be referred to as an OS-SRAM (Oxide Semiconductor-SRAM).

[0656] Note that one embodiment of the present invention is not limited to the memory cells 950a to 950h, and memory cells having structures each of which can be appropriately combined can be used.

[0657] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0658] Embodiment 5 In this embodiment, a structural example of a display module to which the memory device of one embodiment of the present invention can be applied will be described.

[0659] 24A shows a perspective view of a display module 880. The display module 880 includes a display device 800A and an FPC 890. Note that the display panel included in the display module 880 is not limited to the display device 800A and may be a display device 800B described later.

[0660] The display module 880 includes a substrate 891 and a substrate 892. The display module 880 includes a display area 881. The display area 881 is an area where an image is displayed.

[0661] 24B is a perspective view schematically illustrating the configuration on the substrate 891 side. A circuit portion 882, a display portion 883 on the circuit portion 882, and a pixel portion 884 on the display portion 883 are stacked on the substrate 891. A terminal portion 885 for connecting to an FPC 890 is provided in a portion of the substrate 891 that does not overlap with the pixel portion 884. The terminal portion 885 and the circuit portion 882 are connected by a wiring portion 886 composed of a plurality of wirings.

[0662] The pixel section 884 has a plurality of periodically arranged pixels 884a. An enlarged view of one pixel 884a is shown on the right side of Fig. 24B. The pixel 884a has a light-emitting element 810R that emits red light, a light-emitting element 810G that emits green light, and a light-emitting element 810B that emits blue light.

[0663] The display unit 883 has a plurality of pixel circuits 883a arranged periodically. Each pixel circuit 883a controls the light emission of three light-emitting elements included in one pixel 884a. One pixel circuit 883a may be configured to have three circuits for controlling the light emission of one light-emitting element. For example, the pixel circuit 883a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0664] The circuit portion 882 includes a circuit for driving each pixel circuit 883a in the display portion 883. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, it may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 882 may constitute part of the pixel circuit 883a. That is, the pixel circuit 883a may be configured using a transistor included in the display portion 883 and a transistor included in the circuit portion 882.

[0665] The circuit portion 882 can be provided with at least a part of the memory device 100 described in Embodiment 1, for example.

[0666] The FPC 890 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 882. An IC may be mounted on the FPC 890.

[0667] The display module 880 can have a structure in which a layer having a display portion 883 and a layer having a circuit portion 882 are stacked below the pixel portion 884, thereby enabling the aperture ratio (effective display area ratio) of the display region 881 to be extremely high. For example, the aperture ratio of the display region 881 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 884a can be arranged at an extremely high density, enabling the resolution of the display region 881 to be extremely high. For example, it is preferable that the pixels 884a be arranged in the display region 881 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0668] Because such a display module 880 has extremely high resolution, it can be suitably used in devices that implement spatial computing (also referred to as spatial computing devices or spatial computers), VR devices such as head-mounted displays, or glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 880 is viewed through lenses, the display module 880 has an extremely high-resolution display area 881, so that even if the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 880 is not limited to this, and can be suitably used in electronic devices that have relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0669] 25 is a cross-sectional view illustrating a configuration example of the display device 800 A. The display device 800 A has a stacked configuration of a transistor 550 having a channel formed in a substrate 311, a transistor 500 including a metal oxide in a semiconductor layer in which the channel is formed, a capacitor 590, and light-emitting elements 810 (light-emitting elements 810R, 810G, and 810B).

[0670] Substrate 311 corresponds to substrate 891 in FIGS. 24A and 24B.

[0671] 25 corresponds to a configuration in which the light-emitting element 810 is provided on the configuration shown in FIG. 4 of the above-described Embodiment 2. Therefore, the above description can be referred to as appropriate, and detailed description of the transistor 550, the transistor 500, and the capacitor 590 may be omitted.

[0672] An insulator 595 is provided to cover the capacitor 590 , an insulator 854 is provided over the insulator 595 , and an insulator 855 is provided over the insulator 854 .

[0673] An inorganic insulating film can be preferably used for each of the insulators 595, 854, and 855. For example, it is preferable to use a silicon oxide film for the insulators 595 and 855, and a silicon nitride film for the insulator 854. This allows the insulator 854 to function as an etching protective film. Note that although an example is shown here in which part of the insulator 855 is etched to form a recess, the insulator 855 does not necessarily have to have a recess.

[0674] On an insulator 855, a light emitting element 810R that emits red light, a light emitting element 810G that emits green light, and a light emitting element 810B that emits blue light are provided.

[0675] The light-emitting element 810R has a pixel electrode 811R on the insulator 855, an EL layer 812R provided to cover the pixel electrode 811R, a part of the common layer 814 on the EL layer 812R, and a part of the common electrode 813 on the common layer 814. The EL layer 812R has a light-emitting layer that emits red light. The light-emitting element 810G has a pixel electrode 811G on the insulator 855, an EL layer 812G provided to cover the pixel electrode 811G, a part of the common layer 814 on the EL layer 812G, and a part of the common electrode 813 on the common layer 814. The EL layer 812G has a light-emitting layer that emits green light. The light-emitting element 810B has a pixel electrode 811B on an insulator 855, an EL layer 812B provided to cover the pixel electrode 811B, a part of a common layer 814 on the EL layer 812B, and a part of a common electrode 813 on the common layer 814. The EL layer 812B has a light-emitting layer that emits blue light.

[0676] In the display device 800A, since a separate light-emitting element is fabricated for each emitted color, the change in chromaticity between light emitted at low luminance and light emitted at high luminance is small. Furthermore, since the EL layer 812R, the EL layer 812G, and the EL layer 812B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. Therefore, a high-resolution, high-quality display panel can be realized.

[0677] Insulators 825 and 826 are provided in regions between adjacent light-emitting elements.

[0678] An inorganic insulating film can be used for the insulator 825. The insulator 825 preferably functions as a barrier insulator against at least one of water and oxygen. The insulator 825 functions as a barrier insulator, which can suppress the entry of impurities (typically, at least one of water and oxygen) that can diffuse from the outside into each light-emitting element. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.

[0679] The insulator 826 can be an insulator containing an organic material. It is preferable to use a photosensitive organic resin as the organic material, and for example, it is preferable to use a photosensitive resin composition containing an acrylic resin. The insulator 826 may also be a material that absorbs visible light. The insulator 826 absorbs light emitted from a light-emitting element, thereby preventing light from leaking from the light-emitting element to an adjacent light-emitting element through the insulator 826 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0680] The pixel electrodes 811R, 811G, and 811B are connected to the conductor 591 by the insulators 592, 595, and 854, and the conductor 856 functioning as a plug embedded in the insulator 855, and are further connected to one of the source or drain of the transistor 500 by the conductor 540 functioning as a plug. The height of the top surface of the insulator 855 and the height of the conductor 856 are the same. Note that the pixel electrodes 811R, 811G, and 811B may be collectively referred to as pixel electrodes 811.

[0681] No insulator covering the upper end of the pixel electrode 811 is provided between two adjacent pixel electrodes 811. This allows the distance between adjacent light-emitting elements to be extremely narrow, thereby enabling a high-definition or high-resolution display device.

[0682] A protective layer 821 is provided on the light emitting elements 810R, 810G...

Claims

A check bit generating unit, a storage unit, and an error detection and correction unit, the storage unit includes a flip-flop circuit and a holding circuit; the check bit generation unit has a function of generating a check sequence from an information sequence, the storage unit has a function of storing a code word formed from the information sequence and the check sequence in the flip-flop circuit and outputting it as a received word; the error detection and correction unit has a function of outputting an error vector indicating a position of an error in the received word and a decoded word in which the error in the received word has been corrected; the storage unit has a function of storing the decoded word in the flip-flop circuit according to the error vector, a function of writing the decoded word to the holding circuit, and a function of writing the decoded word written in the holding circuit back to the flip-flop circuit; the flip-flop circuit has a first transistor; the holding circuit includes a second transistor; an off-current of the second transistor is smaller than an off-current of the first transistor; storage device. 　 In claim 1, the codeword is a Hamming code; storage device. 　 In claim 1 or claim 2, a change in electrical characteristics of the second transistor due to radiation exposure is smaller than a change in electrical characteristics of the first transistor due to radiation exposure; storage device. 　 In claim 1 or claim 2, the second transistor is stacked on a layer on which the first transistor is provided; storage device. 　 In claim 1 or claim 2, the first transistor includes silicon in a channel formation region; the second transistor includes an oxide semiconductor in a channel formation region; storage device.

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