Short-circuit current feedback limiting output stage control circuit and use thereof

Abstract

Disclosed in the present invention are a short-circuit current feedback limiting output stage control circuit and a use thereof. The output stage control circuit comprises a P-type control circuit for controlling a PMOS output transistor in a Class AB output stage and an N-type control circuit for controlling an NMOS output transistor in the Class AB output stage; the P-type control circuit comprises a first current mirror module used for mirroring output stage current of the PMOS output transistor, a first detection resistor used for collecting the output stage current of the PMOS output transistor, a first amplifier module used for generating a first feedback current on the basis of the output stage current of the PMOS output transistor mirrored by the first current mirror module, a first switch threshold module used for controlling the working state of the first amplifier module and a first bias circuit used for providing a first bias current; and the P-type control circuit outputs the first feedback current to the PMOS output transistor. According to the technical solution, the change trend of short-circuit current at different temperatures can be adjusted while the loop stability is ensured.

Description

An output stage control circuit with short-circuit current feedback limitation and its application Technical Field

[0001] The present invention belongs to the field of semiconductor and integrated circuit technology, and specifically relates to a push-pull output stage circuit structure in an integrated circuit, in particular to an output stage control circuit with short-circuit current feedback limitation and output current detection and current limiting functions, and its application. Background Art

[0002] When using a Class AB output structure in an operational amplifier, as shown in Figure 9, there are limits on the output current due to varying load capacity requirements and varying chip package temperature tolerances. Short-circuit current represents the maximum current a chip can output. For push-pull output structures with high output capacity, where short-circuit current requirements are low, a short-circuit current limiting circuit is necessary for improvement. Prior art methods typically limit short-circuit current by limiting the gate voltage of the PMOS and NMOS transistors in the output stage. However, due to the quadratic relationship of the MOS transistor in strong inversion and the influence of gate voltage on environmental, process, and junction temperature factors, short-circuit current can vary significantly. Consequently, in practical applications, this indicator may not meet ideal expectations with temperature and voltage variations. Furthermore, limiting the gate voltage also limits the maximum output voltage swing, impacting output stage performance to some extent.

[0003] Traditional control methods targeting gate voltage are open-loop control methods with no feedback structure. Both the output voltage and current depend on the gate voltage limit. This led to a feedback method for detecting output current. A small mirror transistor is added to one output stage to proportionally scale the output current. The current flows through a current-input amplifier, where it is converted to a voltage and differentially amplified with a reference voltage. The amplifier's output is then fed back to the output stage to control the Vgs voltage of the output transistor. This current-input amplifier, comprised of a BJT with a high response speed, receives the detected output current to obtain the input voltage, compares it with the reference voltage, and controls the gate of the output transistor based on the collector output voltage. A similar method is used for PMOS output transistors. However, the use of BJTs limits process options and occupies a large area. Furthermore, for high-voltage circuit applications, this structure has voltage withstand limitations. Furthermore, when mirroring the output transistor current, the sense resistor can lead to current inaccuracies. Instability in the loop can lead to instability in the entire output stage, impacting overall circuit operation.

[0004] Figure 2 shows a schematic diagram of a conventional short-circuit current limiting technique using gate voltage detection. The gate of output transistor M1 is connected to the input of amplifier A and compared with a reference voltage, Vref. When the output transistor current is excessive, the gate voltage rises above Vref, causing the output voltage of amplifier A to also rise. Its output is connected to the gate of switching transistor M2. When M2 is on, the loop limits the output transistor gate voltage to Vref. At this point, the output current is related to the gate voltage, Vg, and the aspect ratio of the output transistor. This control scheme, which uses the V / I relationship of the output transistor to control the output current, exhibits significant nonlinearity and is affected by process and device factors. Furthermore, when the output carries a large capacitive load but does not output high current, the gate voltage limitation also affects the output voltage range. To achieve a wider output voltage range, a trade-off often needs to be made with the short-circuit current capability, or the output current must be limited, sacrificing the output swing.

[0005] Figure 3 shows a schematic diagram of a conventional technology solution for detecting output current and limiting short-circuit current. The gate of output transistor M3 is connected to the output of amplifier A. M4, with a width-to-length ratio N times that of M3, is used to detect the output current, and its source is connected to a sense resistor R. The voltage drop across sense resistor R is fed into the input of amplifier A and compared with a reference voltage Vref. When Iout / N*R exceeds Vref, amplifier A forms a loop to limit the output transistor gate voltage, keeping 1 / N times the output current within the range of Vref / R. This control scheme achieves feedback control by acquiring a scaled-down output current and converting it into a voltage through a sense resistor, avoiding the potential swing limitations associated with direct control of the output transistor gate. However, this solution uses M4 as a current mirror to sense current. On the one hand, M4 is also connected to the output port and is therefore part of the output, potentially causing loop stability issues. On the other hand, the resistor R connected to the source of M4 significantly offsets the output current, making it only an approximation of the output current rather than a direct mirror image for calculation. If amplifier A adopts BJT design, then in order to adapt to the output tube of the PMOS part, the circuit process will also be required, and isolation devices will be required for high-voltage applications.

[0006] Summary of the Invention

[0007] The purpose of the present invention is to provide an output stage control circuit with short-circuit current feedback limitation and its application, which can adjust the variation trend of the short-circuit current under different temperatures while ensuring loop stability.

[0008] In order to achieve the above object, the solution of the present invention is:

[0009] An output stage control circuit for short-circuit current feedback limitation, comprising a P-type control circuit for controlling a PMOS output transistor in a Class AB output stage and an N-type control circuit for controlling an NMOS output transistor in a Class AB output stage;

[0010] The P-type control circuit includes a first mirror current module for mirroring the output stage current of the PMOS output tube, a first detection resistor for collecting the output stage current of the PMOS output tube, a first amplifier module for generating a first feedback current according to the output stage current of the PMOS output tube mirrored by the first mirror current module, a first switch threshold module for controlling the working state of the first amplifier module, and a first bias circuit for providing a first bias current. The P-type control circuit outputs the first feedback current to the PMOS output tube;

[0011] The N-type control circuit includes a second mirror current module for mirroring the output stage current of the NMOS output tube, a second detection resistor for collecting the output stage current of the NMOS output tube, a second amplifier module for generating a second feedback current based on the output stage current of the NMOS output tube mirrored by the second mirror current module, a second switch threshold module for controlling the working state of the second amplifier module, and a second bias circuit for providing a second bias current. The N-type control circuit outputs the second feedback current to the NMOS output tube.

[0012] The first current mirror module uses a tenth PMOS transistor, which is of the same type and size as the PMOS output transistor and has a predetermined number ratio; the gate of the tenth PMOS transistor is connected to the gate of the PMOS output transistor, the source of the tenth PMOS transistor is connected to the power supply voltage, and the drain of the tenth PMOS transistor is connected to the first detection resistor;

[0013] The second mirror current module uses a seventh NMOS transistor, which is the same type and size as the NMOS output tube and has a predetermined number ratio; the gate of the seventh NMOS tube is connected to the gate of the NMOS output tube, the source of the seventh NMOS tube is grounded, and the drain of the seventh NMOS tube is connected to the second detection resistor.

[0014] Wherein, the second end of the first detection resistor is grounded, and the first end of the first detection resistor is connected to the drain of the tenth PMOS transistor;

[0015] The second end of the second detection resistor is connected to the power supply voltage, and the first end of the second detection resistor is connected to the drain of the seventh NMOS transistor.

[0016] The first switch threshold module includes a tenth NMOS transistor, whose source is grounded, and whose gate and drain are connected in parallel and then connected to the first amplifier module, providing a switch threshold voltage for the first amplifier module;

[0017] The second switch threshold module includes a third PMOS transistor, a source of which is connected to a voltage power supply, and a gate and a drain of which are connected in parallel and then connected to the second amplifier module to provide a switch threshold voltage for the second amplifier module.

[0018] The first switch threshold module includes a first NPN transistor, the emitter of which is grounded, and the base and collector of which are connected in parallel and then connected to the first amplifier module to provide a switch threshold voltage for the first amplifier module;

[0019] The second switch threshold module includes a first PNP transistor, an emitter of which is connected to the power supply voltage, and a base and a collector of which are connected in parallel and then connected to the first amplifier module to provide a switch threshold voltage for the first amplifier module.

[0020] The first amplifier module includes an eighth NMOS transistor, a ninth NMOS transistor, and a fourth PMOS transistor, and the first bias current output by the first bias circuit includes a first-end bias current and a second-end bias current; wherein the source of the eighth NMOS transistor is connected to the first end of the first detection resistor, the gate of the eighth NMOS transistor, the drain of the eighth NMOS transistor, and the gate of the ninth NMOS transistor are connected, and are connected to the first-end bias current output by the first bias circuit; the source of the ninth NMOS transistor is connected to the first switch threshold module, and the drain of the ninth NMOS transistor is connected to the second-end bias current output by the first bias circuit; the drain of the ninth NMOS transistor is also connected to the gate of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the power supply voltage, and the drain of the fourth PMOS transistor is connected to the gate of the PMOS output transistor;

[0021] The second amplifier module includes a first PMOS transistor, a second PMOS transistor and a first NMOS transistor, and the second bias current output by the second bias circuit includes a third-end bias current and a fourth-end bias current; wherein, the source of the first PMOS transistor is connected to the first end of the second detection resistor, the drain of the first PMOS transistor, the gate of the first PMOS transistor, and the gate of the second PMOS transistor are connected, and are connected to the third-end bias current output by the second bias circuit; the source of the second PMOS transistor is connected to the second switch threshold module, and the drain of the second PMOS transistor is connected to the fourth-end bias current output by the second bias circuit; the drain of the second PMOS transistor is also connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to the gate of the NMOS output transistor.

[0022] Wherein, the first amplifier module further includes a first compensation capacitor, one end of the first compensation capacitor is connected to the drain of the ninth NMOS transistor, and the other end of the first compensation capacitor is connected to the drain of the fourth PMOS transistor;

[0023] The second amplifier module further includes a second compensation capacitor, one end of the second compensation capacitor is connected to the drain of the second PMOS transistor, and the other end of the second compensation capacitor is connected to the drain of the first NMOS transistor.

[0024] The first bias circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor, wherein the gate of the fifth PMOS transistor and the gate of the seventh PMOS transistor are both connected to the first control voltage, the source of the fifth PMOS transistor and the source of the seventh PMOS transistor are both connected to the power supply voltage, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor; the gate of the sixth PMOS transistor and the gate of the eighth PMOS transistor are both connected to the second control voltage, the drain of the sixth PMOS transistor is used to output a first-end bias current to the first amplifier module, and the drain of the eighth PMOS transistor is used to output a second-end bias current to the first amplifier module;

[0025] The second bias circuit includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are both connected to a third control voltage, the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are both grounded, the drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor; the gate of the second NMOS transistor and the gate of the third NMOS transistor are both connected to the fourth control voltage, the drain of the second NMOS transistor is used to output a third-end bias current to the second amplifier module, and the drain of the third NMOS transistor is used to output a fourth-end bias current to the second amplifier module.

[0026] The first detection resistor adopts a positive temperature drift or negative temperature drift type; the second detection resistor adopts a positive temperature drift or negative temperature drift type.

[0027] A chip circuit includes the output stage control circuit for short-circuit current feedback limitation as described above.

[0028] After adopting the above scheme, the beneficial effects of the present invention are as follows:

[0029] (1) The amplifier module of the present invention uses a dual current mirror for mirroring and simultaneously switches the position of the detection resistor, thus avoiding the problem that the mirrored current flows through the resistor after the traditional solution. However, the resistor is usually placed between the source of the output tube and the power rail, which destroys the mirror relationship of the current mirror and leads to inaccurate current mirroring. On this basis, the output swing and short-circuit current control of the Class-AB output stage are separated to a certain extent, reducing the influence between the two indicators.

[0030] (2) The present invention uses a combination of MOS / BJT and resistors to adjust the temperature drift characteristics of the short-circuit current. For example, when a steeper temperature drift curve is required, the design can be more convenient and more controllable;

[0031] (3) The present invention sets a MOS transistor to provide a switching threshold voltage, which can reduce the number of required detection resistors and save circuit area under low bias current conditions compared to traditional solutions. In addition, under the adjustment of the switching threshold voltage, the present invention does not turn on when the Class-AB output stage is operating normally, and the MOS transistor does not need to be large in size. Therefore, the impact of parasitic capacitance can be ignored compared to the gate capacitance of the output stage itself.

[0032] (4) The present invention compensates for loop stability by providing a compensation capacitor. Traditional solutions do not consider short-circuit stability, but the output tube gate potential will definitely rise during a short circuit, and the gate potential will also rise during normal operation. Therefore, under traditional solutions, the front-stage circuit may operate normally, but the step response generated by the gate potential rise is input to the back-stage circuit, causing the back-stage circuit to oscillate. The compensation capacitor ensures stability in the loop regardless of normal operation or short-circuit conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Fig. 1 is a schematic diagram of the present invention;

[0034] FIG2 is a circuit structure of a conventional scheme for limiting short-circuit current by detecting gate voltage;

[0035] FIG3 is a circuit structure of a conventional solution for limiting short-circuit current by detecting output current;

[0036] FIG4 is an implementation structure of an N-type control circuit in the present invention;

[0037] FIG5 is a schematic diagram of the working state of the circuit shown in FIG4 when it is turned off;

[0038] FIG6 is an implementation structure of a P-type control circuit in the present invention;

[0039] FIG7 is another implementation structure of the N-type control circuit of the present invention;

[0040] FIG8 is another implementation structure of the P-type control circuit in the present invention;

[0041] FIG9 is a block diagram of a general operational amplifier with a Class AB output structure. DETAILED DESCRIPTION

[0042] The technical solutions and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] The present invention provides an output-stage control circuit with short-circuit current feedback limitation, which is used to detect and control the output current of a Class AB output stage. FIG1 illustrates the principle of the circuit, which includes a P-type control circuit for controlling the PMOS output transistors in the Class AB output stage and an N-type control circuit for controlling the NMOS output transistors in the Class AB output stage.

[0044] As shown in FIG4 , the embodiment of the present invention takes the NMOS transistor MN6 in the Class AB output stage as an example to illustrate the control circuit for the NMOS output transistor. The control circuit for the PMOS output transistor is the same as the control circuit for the NMOS output transistor.

[0045] 4 , the N-type control circuit includes a second mirror current module for mirroring the output stage current of the NMOS output tube, a second detection resistor for collecting the output stage current, a second amplifier module for generating a second feedback current based on the output stage current, a second switch threshold module for controlling the working state of the second amplifier module, and a second bias circuit (BIAS) for providing a bias current, which are introduced below.

[0046] The second current mirror module is composed of devices of the same type as the output transistor, namely an NMOS transistor MN7, which is the same size and has a certain ratio with the NMOS transistor MN6. In this embodiment, the number of MN6 and MN7 is in a ratio of N:1. The source of MN7 is grounded, the gate is connected to the gate of MN6, and the drain of MN7 is connected to the sense resistor. Compared with traditional circuits, the source of the mirror transistor in this embodiment is no longer connected to the sense resistor. Instead, a dual circuit design is used to transmit current in a mirrored current manner, thereby avoiding inaccurate output stage current caused by the substrate bias effect of MN7 and output nonlinearity caused by the drain output.

[0047] The first end of the second detection resistor R2 is connected to the drain of MN7, and the second end of R2 is connected to the power supply voltage VDD; by connecting R2 to the drain of the NMOS tube, its influence on the output and the resulting bias effect that causes inaccurate current replication are avoided.

[0048] The second switch threshold module uses a PMOS tube MP3, whose source is connected to the power supply voltage VDD, and the gate and drain are connected in parallel and then connected to the second amplifier module. By providing the second amplifier module with a switch threshold voltage, the second amplifier module is controlled to work or shut down.

[0049] To avoid mutual influence between the Class-AB output stage structure's own loop and the control circuit's loop, the second amplifier module should be designed with a minimally simplistic structure and reliable loop stability. Furthermore, the feedback control function should be kept off in non-high-current output conditions. In this embodiment, for the NMOS transistor in the Class-AB output stage, the second amplifier module includes a first stage and a second stage. The first stage comprises two PMOS transistors, MP1 and MP2. The source of MP1 is connected to the first end of the detection resistor R2, and the drain and gate are connected in parallel to a third bias current output from the second bias circuit. The source of MP2 is connected to the drain of MP3, the gate of MP2 is connected to the gate of MP1, and the drain of MP2 is connected to a fourth bias current output from the second bias circuit. MP1 and MP2 share a common gate. The second stage comprises an NMOS transistor, MN1, with its gate connected to the drain of MP2. The source of MN1 is grounded, and the drain is connected to the gate of NMOS transistor MN6, for providing a second feedback current to the NMOS output transistor.

[0050] The second bias circuit includes NMOS transistors MN2-MN5, which are connected to control voltages VBIAS1 and VBIAS2 through their gates to generate third-end bias current I1 and fourth-end bias current I2. I1 and I2 can be very small to reduce power consumption, while making MP1 and MP2 work in the subthreshold region.

[0051] As a preferred embodiment of the present invention, in order to ensure loop stability, a compensation capacitor Cc is further provided in the second amplifier module, one end of Cc is connected to the drain of MP2, and the other end of Cc is connected to the gate of MN1.

[0052] FIG5 is a schematic diagram of the circuit shown in FIG4 in a non-operating state. The circuit of the present invention should be used without affecting the output of the main circuit, so it should be in the off state when the output current is normal. When Iout is very small, there is almost no voltage drop across R2, and the source of MP2 is connected to MP3 to provide a threshold voltage, so its source voltage is high and close to the gate voltage. MP2 is turned off, the drain voltage is very low (close to the ground voltage), and MN1 is turned off. The entire circuit can be regarded as the off state of the switch tube. When the output current increases, the voltage drop across R2 increases and the gate voltage of MP2 decreases, MP2 can be regarded as the on state of the switch tube, forming a current input-voltage output feedback loop. On the one hand, it eliminates the possible influence during normal operation, and on the other hand, it avoids the mutual limitation of the output swing and the output current, achieving accurate proportional replication and feedback control of the short-circuit current.

[0053] The control circuit structure for the NMOS output stage is provided above. The control circuit for the PMOS output stage is shown in Figure 6. The mirror current module uses the PMOS transistor MP10 of the same type as the output transistor MP9. The current mirror of the first stage in the amplifier module A uses the NMOS transistors MN8 and MN9 that are dual to the output transistor.

[0054] As shown in FIG6 , an embodiment of a P-type control circuit for controlling the PMOS transistor MP9 in a Class AB output stage according to the present invention is shown. The circuit includes a first current mirror module for mirroring the output stage current of the PMOS output transistor, a first detection resistor for collecting the output stage current of the PMOS output transistor, a first amplifier module for generating a first feedback current based on the output stage current of the PMOS output transistor, a first switching threshold module for controlling the operating state of the first amplifier module, and a first bias circuit for providing a first bias current. Each of these components is described below.

[0055] The first current mirror module is composed of devices of the same type as the PMOS output tube, including a PMOS tube MP10, which is the same size and has a certain ratio with the PMOS tube MP9. In this embodiment, the number of MP9 and MP10 is in a ratio of M:1. Here, M can be different from the ratio N in the N-type control circuit described above and is specifically set according to the short-circuit current required to be controlled. The source of MP10 is connected to the power supply voltage VDD, its gate is connected to the gate of MP9, and the drain of MP10 is connected to the first detection resistor. Compared with traditional circuits, the source of the mirror tube in this embodiment is no longer connected to the detection resistor. Instead, through a dual circuit design, current is transmitted in a mirrored current manner, avoiding inaccurate output stage current caused by the substrate bias effect of MP10 and output nonlinearity caused by the drain output.

[0056] The first end of the first detection resistor R1 is connected to the drain of MP10, and the second end of R1 is grounded. By connecting R1 to the drain of the PMOS tube, its influence on the output and the resulting bias effect that causes inaccurate current replication are avoided.

[0057] The first switch threshold module uses an NMOS transistor MP10, whose source is grounded, and whose gate and drain are connected in parallel and then connected to the first amplifier module. By providing a switch threshold voltage to the first amplifier module, the first amplifier module is controlled to work or shut down.

[0058] To avoid mutual influence between the Class-AB output stage structure's own loop and the control circuit's loop, the first amplifier module should be designed with a minimally simplistic structure and reliable loop stability. Furthermore, the feedback control function should be kept off in non-high-current output conditions. In this embodiment, for the PMOS transistor in the Class-AB output stage, the first amplifier module includes a first stage and a second stage. The first stage comprises two NMOS transistors MN8 and MN9, wherein the source of MN8 is connected to the first end of the first detection resistor R1, and the drain and gate are connected in parallel to the first bias current output by the first bias circuit. The source of MN9 is connected to the drain of MN10, the gate of MN9 is connected to the gate of MN8, and the drain of MN9 is connected to the second bias current output by the first bias circuit. MN8 and MN9 share a common gate arrangement. The second stage comprises a PMOS transistor MP4, wherein the gate of MP4 is connected to the drain of MN9, the source of MP4 is connected to the power supply voltage VDD, and the drain is connected to the gate of the PMOS transistor MP9, for providing a first feedback current to the PMOS output transistor.

[0059] The first bias circuit includes PMOS transistors MP5-MP8, which are connected to control voltages VBIAS3 and VBIAS4 through their gates to generate a first-end bias current I1 and a second-end bias current I2. I1 and I2 can be very small to reduce power consumption, while allowing MN8 and MN9 to operate in the subthreshold region.

[0060] As a preferred embodiment of the present invention, in order to ensure loop stability, a compensation capacitor Cc is further provided in the first amplifier module, one end of Cc is connected to the drain of MN9, and the other end of Cc is connected to the gate of MP4.

[0061] The structure and working principle of the P-type control circuit are similar to those of the aforementioned N-type control circuit and will not be described in detail.

[0062] It should be noted that both the switch threshold module MP3 in the N-type control circuit and the switch threshold module MN10 in the P-type control circuit described above can be BJTs as needed. For example, for the circuit shown in FIG4 , MP3 can be replaced with a PNP transistor, as shown in FIG7 . The emitter of the PNP transistor is connected to the power supply voltage VDD, and the base and collector of the PNP transistor are short-circuited and connected to the amplifier module. Similarly, for the P-type control circuit shown in FIG6 , MN10 can be replaced with an NPN transistor, as shown in FIG8 . The emitter of the NPN transistor is grounded, and the base and collector of the NPN transistor are short-circuited and connected to the amplifier module. BJTs can be selected based on their steeper temperature drift characteristics. Furthermore, the sense resistor can also be selected based on positive or negative temperature drift characteristics as needed.

[0063] The amplifier module A in the present invention can also use other structures, but further consideration must be given to potential stability issues caused by internal poles and the parasitic capacitance effects of the larger MOS area on the output stage. Since the bias current requirement is not high, it can be easily extracted from the overall circuit and used. The same applies to the PMOS output stage structure.

[0064] In summary, the amplifier module of the present invention utilizes a current mirror design that is dual to the output transistor, with the other branch of the current mirror connected to a sense resistor. The bias circuit employs a cascode structure to enhance stability, and its dimensions are designed based on the maximum current it can withstand. By designing the ratio of the sense current to the maximum output current, as well as the resistance and temperature coefficient of the sense resistor, the upper limit and temperature coefficient of the short-circuit current output after feedback can be effectively controlled.

[0065] An embodiment of the present invention further provides a chip circuit, which includes the output stage control circuit as described above.

[0066] It will be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention may be implemented in various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0067] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0068] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0070] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0071] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An output stage control circuit with short-circuit current feedback limitation, characterized in that: It includes a P-type control circuit for controlling the PMOS output tube in the Class AB output stage and an N-type control circuit for controlling the NMOS output tube in the Class AB output stage; The P-type control circuit includes a first mirror current module for mirroring the output stage current of the PMOS output tube, a first detection resistor for collecting the output stage current of the PMOS output tube, a first amplifier module for generating a first feedback current according to the output stage current of the PMOS output tube mirrored by the first mirror current module, a first switch threshold module for controlling the working state of the first amplifier module, and a first bias circuit for providing a first bias current. The P-type control circuit outputs the first feedback current to the PMOS output tube; The N-type control circuit includes a second mirror current module for mirroring the output stage current of the NMOS output tube, a second detection resistor for collecting the output stage current of the NMOS output tube, a second amplifier module for generating a second feedback current based on the output stage current of the NMOS output tube mirrored by the second mirror current module, a second switch threshold module for controlling the working state of the second amplifier module, and a second bias circuit for providing a second bias current. The N-type control circuit outputs the second feedback current to the NMOS output tube; The first current mirror module uses a tenth PMOS transistor, which is the same type and size as the PMOS output transistor and has a predetermined number ratio; the gate of the tenth PMOS transistor is connected to the gate of the PMOS output transistor, the source of the tenth PMOS transistor is connected to the power supply voltage, and the drain of the tenth PMOS transistor is connected to the first detection resistor; The second mirror current module uses a seventh NMOS transistor, which is the same type and size as the NMOS output tube and has a predetermined number ratio; the gate of the seventh NMOS tube is connected to the gate of the NMOS output tube, the source of the seventh NMOS tube is grounded, and the drain of the seventh NMOS tube is connected to the second detection resistor.

2. The output stage control circuit with short-circuit current feedback limitation according to claim 1, wherein: The second end of the first detection resistor is grounded, and the first end of the first detection resistor is connected to the drain of the tenth PMOS transistor; The second end of the second detection resistor is connected to the power supply voltage, and the first end of the second detection resistor is connected to the drain of the seventh NMOS transistor.

3. The output stage control circuit with short-circuit current feedback limitation according to claim 1, wherein: The first switch threshold module includes a tenth NMOS transistor, whose source is grounded, and whose gate and drain are connected in parallel and then connected to the first amplifier module, providing a switch threshold voltage for the first amplifier module; The second switch threshold module includes a third PMOS transistor, a source of which is connected to a voltage power supply, and a gate and a drain of which are connected in parallel and then connected to the second amplifier module to provide a switch threshold voltage for the second amplifier module.

4. The output stage control circuit with short-circuit current feedback limitation according to claim 1, wherein: The first switch threshold module includes a first NPN transistor, the emitter of which is grounded, and the base and collector of which are connected in parallel and then connected to the first amplifier module to provide a switch threshold voltage for the first amplifier module; The second switch threshold module includes a first PNP transistor, an emitter of which is connected to the power supply voltage, and a base and a collector of which are connected in parallel and then connected to the first amplifier module to provide a switch threshold voltage for the first amplifier module.

5. The output stage control circuit with short-circuit current feedback limitation according to claim 1, wherein: The first amplifier module includes an eighth NMOS transistor, a ninth NMOS transistor, and a fourth PMOS transistor. The first bias current output by the first bias circuit includes a first-end bias current and a second-end bias current. The source of the eighth NMOS transistor is connected to the first end of the first detection resistor, and the gate of the eighth NMOS transistor, the drain of the eighth NMOS transistor, and the gate of the ninth NMOS transistor are connected, and are connected to the first-end bias current output by the first bias circuit. The source of the ninth NMOS transistor is connected to the first switch threshold module, and the drain of the ninth NMOS transistor is connected to the second-end bias current output by the first bias circuit. The drain of the ninth NMOS transistor is also connected to the gate of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the power supply voltage, and the drain of the fourth PMOS transistor is connected to the gate of the PMOS output transistor. The second amplifier module includes a first PMOS transistor, a second PMOS transistor and a first NMOS transistor, and the second bias current output by the second bias circuit includes a third-end bias current and a fourth-end bias current; wherein, the source of the first PMOS transistor is connected to the first end of the second detection resistor, the drain of the first PMOS transistor, the gate of the first PMOS transistor, and the gate of the second PMOS transistor are connected, and are connected to the third-end bias current output by the second bias circuit; the source of the second PMOS transistor is connected to the second switch threshold module, and the drain of the second PMOS transistor is connected to the fourth-end bias current output by the second bias circuit; the drain of the second PMOS transistor is also connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to the gate of the NMOS output transistor.

6. The output stage control circuit with short-circuit current feedback limitation according to claim 5, wherein: The first amplifier module further includes a first compensation capacitor, one end of the first compensation capacitor is connected to the drain of the ninth NMOS transistor, and the other end of the first compensation capacitor is connected to the drain of the fourth PMOS transistor; The second amplifier module further includes a second compensation capacitor, one end of the second compensation capacitor is connected to the drain of the second PMOS transistor, and the other end of the second compensation capacitor is connected to the drain of the first NMOS transistor.

7. The output stage control circuit with short-circuit current feedback limitation according to claim 5, wherein: The first bias circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor, wherein the gate of the fifth PMOS transistor and the gate of the seventh PMOS transistor are both connected to a first control voltage, the source of the fifth PMOS transistor and the source of the seventh PMOS transistor are both connected to a power supply voltage, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, and the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor; the gate of the sixth PMOS transistor and the gate of the eighth PMOS transistor are both connected to a second control voltage, the drain of the sixth PMOS transistor is used to output a first-end bias current to the first amplifier module, and the drain of the eighth PMOS transistor is used to output a second-end bias current to the first amplifier module; The second bias circuit includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, wherein the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are both connected to a third control voltage, the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are both grounded, the drain of the fourth NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor; the gate of the second NMOS transistor and the gate of the third NMOS transistor are both connected to the fourth control voltage, the drain of the second NMOS transistor is used to output a third-end bias current to the second amplifier module, and the drain of the third NMOS transistor is used to output a fourth-end bias current to the second amplifier module.

8. The output stage control circuit with short-circuit current feedback limitation according to claim 1, wherein: The first detection resistor adopts a positive temperature drift or negative temperature drift type; the second detection resistor adopts a positive temperature drift or negative temperature drift type.

9. A chip circuit, characterized in that: The chip circuit includes an output stage control circuit for short-circuit current feedback limitation according to any one of claims 1 to 8.

Images