Array substrate, display panel and display apparatus

Abstract

An array substrate (10) comprising pixel circuits (30), first data lines (61), first connection lines (40) and second connection lines (50). The pixel circuits (30) each comprise a capacitor (C), a first reset transistor (T1) and a compensation transistor (T2), a second electrode plate (C2) of the capacitor (C) being connected to a first node (N1), a second electrode (313) of the first reset transistor (T1) being connected to a second node (N2), and a first electrode (312) and a second electrode (313) of the compensation transistor (T2) being respectively connected to the second node (N2) and the first node (N1). One end of each first connection line (40) is connected to a second electrode plate (C2) of a capacitor (C), while the other end thereof is connected to a second electrode (313) of a compensation transistor (T2). Each first connection line (40) is located between two adjacent first data lines (61), and is closer to one of the two first data lines (61). One end of each second connection line (50) is connected to a second electrode (313) of a first reset transistor (T1), while the other end thereof is connected to a first electrode (312) of a compensation transistor (T2). In a second direction, each second connection line (50) is located on the side of a first connection line (40) away from the closer first data line (61). The maximum distance between an adjacent first connection line (40) and second connection line (50) is less than or equal to 2.4 μm.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] With the rapid development of display technology, display devices have become increasingly ubiquitous in people's lives. Organic Light Emitting Diodes (OLEDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response, high contrast, and flexible display.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate includes a pixel circuit, a plurality of first data lines, a plurality of first connection lines, and a plurality of second connection lines. The pixel circuit includes a capacitor, a first reset transistor, and a compensation transistor. The first plate of the capacitor is connected to a first voltage signal terminal, and the second plate of the capacitor is connected to a first node. The first electrode of the first reset transistor is connected to a first initialization signal terminal, and the second electrode of the first reset transistor is connected to a second node. The first electrode of the compensation transistor is connected to the second node, and the second electrode of the compensation transistor is connected to the first node.

[0005] The first data line extends along a first direction, and the plurality of first data lines are spaced apart in a second direction; the first direction intersects the second direction. The first data line is connected to the pixel circuit. The first connecting line extends along the first direction, and one end of the first connecting line is connected to the second plate of the capacitor, and the other end is connected to the second electrode of the compensation transistor. The first connecting line is located between two adjacent first data lines and is relatively close to one of the two first data lines.

[0006] The second connecting line extends along the first direction, with one end of the second connecting line connected to the second electrode of the first reset transistor and the other end connected to the first electrode of the compensation transistor. The second connecting line is located between two adjacent first data lines and, in the second direction, is located on a side of the first connecting line away from the adjacent first data line. In the second direction, a maximum distance between adjacent first and second connecting lines is less than or equal to 2.4 μm.

[0007] In some embodiments, the first data line includes alternating straight segments and curved segments. The plurality of first data lines are divided into a plurality of data line groups, each data line group including two first data lines, and the curved segments of the two first data lines in the same data line group are arranged opposite each other and bend in directions away from each other. The first connecting line and the second connecting line are located between two adjacent first data lines belonging to different data line groups. Furthermore, in the second direction, the first connecting line and the curved segment are at least partially opposite each other, and the opposing portion is parallel to the opposing boundary of the adjacent second connecting line.

[0008] In some embodiments, the first connection line includes a first connection pad, a first routing segment, a second routing segment, and a second connection pad connected in sequence, the first connection pad being connected to the second plate of the capacitor, and the second connection pad being connected to the second electrode of the compensation transistor. The second connection line includes a third connection pad, a third routing segment, a fourth routing segment, and a fourth connection pad being connected in sequence, the third connection pad being connected to the first electrode of the compensation transistor, and the fourth connection pad being connected to the second electrode of the first reset transistor.

[0009] The first routing segment extends toward the adjacent second connection line and is located on a side of the third routing segment away from the fourth connection pad. In the second direction, the first routing segment is opposite the third connection pad, the second routing segment is opposite the third routing segment, and the fourth routing segment is opposite the second connection pad. Furthermore, the boundary between the second routing segment and the third routing segment is parallel, and the boundary between the second connection pad and the fourth routing segment is parallel.

[0010] In some embodiments, in the second direction, the fourth trace segment is opposite to a portion of the second connection pad, and the fourth connection pad is opposite to another portion of the second connection pad. The orthographic projections of the second and fourth connection pads on a reference plane are polygonal, and the boundaries between the second and fourth connection pads are parallel. The reference plane is a plane defined by the first and second directions.

[0011] In some embodiments, the second routing segment includes a first subsegment, a second subsegment, and a third subsegment connected in sequence, the first subsegment is connected to the first routing segment, the third subsegment is connected to the second connection pad, and the third subsegment is farther away from the adjacent first data line than the first subsegment. The third routing segment includes a fourth subsegment, a fifth subsegment, and a sixth subsegment connected in sequence, the fourth subsegment is connected to the third connection pad, the sixth subsegment is connected to the fourth routing segment, and the sixth subsegment is farther away from the adjacent first data line than the fourth subsegment. In the second direction, the first subsegment is opposite to the fourth subsegment, the second subsegment is opposite to the fifth subsegment, and the third subsegment is opposite to the sixth subsegment.

[0012] In some embodiments, the first routing segment is parallel to at least a portion of a boundary opposite to an adjacent second connecting line.

[0013] In some embodiments, the orthographic projection of the boundary of the first connecting line close to the adjacent first data line on the reference plane coincides with the orthographic projection of the boundary of the second electrode of the connected compensation transistor close to the corresponding first data line on the reference plane, and the reference plane is a plane determined by the first direction and the second direction.

[0014] In some embodiments, the pixel circuit further includes a driving transistor, a data writing transistor, a first enabling transistor, a second enabling transistor, a second reset transistor, and a third reset transistor.

[0015] The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the third node, and the second electrode of the driving transistor is connected to the second node. The control electrode of the data writing transistor is connected to the second scanning signal terminal, the first electrode of the data writing transistor is connected to the data signal terminal, and the second electrode of the data writing transistor is connected to the third node. The control electrode of the first enabling transistor is connected to the enabling signal terminal, the first electrode of the first enabling transistor is connected to the first voltage signal terminal, and the second electrode of the first enabling transistor is connected to the third node.

[0016] The control electrode of the second enable transistor is connected to the enable signal terminal, the first electrode of the second enable transistor is connected to the second node, and the second electrode of the second enable transistor is connected to the fourth node. The control electrode of the second reset transistor is connected to the second reset signal terminal, the first electrode of the second reset transistor is connected to the second initialization signal terminal, and the second electrode of the second reset transistor is connected to the fourth node. The control electrode of the third reset transistor is connected to the second reset signal terminal, the first electrode of the third reset transistor is connected to the third initialization signal terminal, and the second electrode of the third reset transistor is connected to the third node.

[0017] In some embodiments, the array substrate includes a first active layer including a plurality of first active patterns, a plurality of second active patterns, and a plurality of third active patterns.

[0018] The first active pattern includes the channel, first electrode, and second electrode of the drive transistor, the data write transistor, the first enable transistor, the second enable transistor, and the second reset transistor. The second active pattern includes the channel, first electrode, and second electrode of the first reset transistor. The plurality of first active patterns and the plurality of second active patterns are alternately arranged in the first direction, and the second active patterns are further away from the corresponding first data lines than the corresponding first active patterns. The third active pattern includes the channel, first electrode, and second electrode of the third reset transistor. Along the second direction, the third active pattern is located on the side of the channel of the second reset transistor that is closer to the channel of the first enable transistor.

[0019] In some embodiments, the array substrate further includes a first scan signal line extending along the second direction. An orthographic projection of the first scan signal line on a reference plane overlaps an orthographic projection of the channel of the compensation transistor on the reference plane. The reference plane is a plane defined by the first and second directions. The orthographic projections of the first scan signal line and the first connecting line on the reference plane overlap, and a boundary of the overlapping portion is parallel to the first or second direction.

[0020] In some embodiments, the first scan signal line includes a plurality of first scan routing segments connected in sequence, and the first scan routing segments include a first scan sub-segment and a second scan sub-segment connected in sequence. The first scan sub-segment overlaps with an orthographic projection of the first connection line on the reference plane, and the second scan sub-segment overlaps with an orthographic projection of the channel of the compensation transistor on the reference plane. Along the first direction, the width of the first scan sub-segment is smaller than the width of the second scan sub-segment, and the boundary connecting the second scan sub-segment to the first scan sub-segment is parallel to a boundary opposite the first connection line.

[0021] In some embodiments, the first scan signal line includes a plurality of first scan routing segments connected in sequence, and the first scan routing segments include a third scan sub-segment, a fourth scan sub-segment, and a fifth scan sub-segment connected in sequence. The fourth scan sub-segment overlaps with an orthographic projection of the first connection line on the reference plane, and the fifth scan sub-segment overlaps with an orthographic projection of the channel of the compensation transistor on the reference plane. Along the first direction, the width of the third scan sub-segment is smaller than the width of the fourth scan sub-segment, and the width of the fourth scan sub-segment is smaller than the width of the fifth scan sub-segment.

[0022] In some embodiments, a boundary connecting the fourth scanning subsegment and the third scanning subsegment is parallel to a boundary opposite to the first connecting line, and / or a boundary connecting the fifth scanning subsegment and the fourth scanning subsegment is parallel to a boundary opposite to the first connecting line.

[0023] In some embodiments, the array substrate includes a second active layer, a second gate conductive layer, and a third gate conductive layer. The second active layer includes a plurality of fourth active patterns, each of which includes a channel, a first electrode, and a second electrode of the compensation transistor. The second gate conductive layer and the third gate conductive layer are disposed on opposite sides of the second active layer, and the first scan signal line is located in the second gate conductive layer and / or the third gate conductive layer.

[0024] In some embodiments, the pixel circuit further includes a drive transistor and a data write transistor, wherein a first electrode of the drive transistor is connected to the third node, and a second electrode of the drive transistor is connected to the second node. A first electrode of the data write transistor is connected to the first data line, and a second electrode of the data write transistor is connected to the third node.

[0025] The array substrate further includes a second scan signal line extending along the second direction. An orthographic projection of the second scan signal line on a reference plane overlaps with an orthographic projection of a channel of the data write transistor on the reference plane, and overlaps with an orthographic projection of a second electrode of the compensation transistor on the reference plane. The reference plane is a plane defined by the first and second directions.

[0026] The second scanning signal line includes a second scanning routing segment and a widened portion. Along the first direction, the widened portion is located on one side of the second scanning routing segment, and the orthographic projection of the widened portion on the reference plane is located within the range of the orthographic projection of the second electrode of the compensation transistor on the reference plane.

[0027] In some embodiments, the array substrate further includes a plurality of first power signal lines, and the orthographic projection of the first connecting line on the reference plane is located within the range of the orthographic projection of the plurality of first power signal lines on the reference plane; the reference plane is a plane determined by the first direction and the second direction.

[0028] In some embodiments, the plurality of first power signal lines include a plurality of first power sub-lines, a plurality of second power sub-lines, and a plurality of third power sub-lines. The plurality of first power sub-lines extend along the first direction and are spaced apart in the second direction. The plurality of second power sub-lines extend along the first direction and are spaced apart in the second direction. The second power sub-lines are connected to the first voltage signal terminal of the pixel circuit. The plurality of third power sub-lines extend along the second direction and are spaced apart in the first direction. One first power sub-line is connected to one second power sub-line via one third power sub-line.

[0029] Part of the orthographic projection of the first connecting line on the reference plane is located within the range of the orthographic projection of the first power sub-line or the second power sub-line on the reference plane, and the other part is located within the range of the orthographic projection of the third power sub-line on the reference plane.

[0030] In some embodiments, the array substrate includes a first source-drain conductive layer, a second source-drain conductive layer, and a third source-drain conductive layer. The first connecting line and the second connecting line are located in the first source-drain conductive layer, the third power sub-line is located in the second source-drain conductive layer, and the first power sub-line and the second power sub-line are located in the third source-drain conductive layer.

[0031] In another aspect, a display panel is provided, comprising the array substrate according to any one of the above embodiments and a light-emitting device, wherein the light-emitting device is disposed on the array substrate.

[0032] In another aspect, a display device is provided, comprising the display panel according to the above embodiment and a circuit board, wherein the circuit board is connected to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0034] FIG1 is a structural diagram of a display device according to some embodiments;

[0035] FIG2 is a structural diagram of another display device according to some embodiments;

[0036] FIG3 is a cross-sectional view of the display device shown in FIG1 along section line AA;

[0037] FIG4 is a top view of a display panel according to some embodiments;

[0038] FIG5 is a cross-sectional view of a display panel according to some embodiments;

[0039] FIG6 is a circuit diagram of a pixel circuit according to some embodiments;

[0040] FIG7 is a partial enlarged view of a first connecting line and a second connecting line of an array substrate according to some embodiments;

[0041] FIG8 is a partial enlarged view of a first connecting line and a second connecting line of another array substrate according to some embodiments;

[0042] 9 is a top view of a stack of a first source-drain conductive layer, a second source-drain conductive layer, and a third source-drain conductive layer of an array substrate according to some embodiments;

[0043] FIG10 is a top view of a first source-drain conductive layer of an array substrate according to some embodiments;

[0044] FIG11 is a top view of a first active layer of an array substrate according to some embodiments;

[0045] FIG12 is a top view of a second source-drain conductive layer of an array substrate according to some embodiments;

[0046] FIG13 is a top view of a third source-drain conductive layer of an array substrate according to some embodiments;

[0047] FIG14 is a top view of a third source-drain conductive layer of another array substrate according to some embodiments;

[0048] FIG15 is a structural diagram of first and second connecting lines of an array substrate according to some embodiments;

[0049] FIG16 is a structural diagram of first connecting lines and second connecting lines of another array substrate according to some embodiments;

[0050] FIG17 is a top view of a first gate conductive layer of an array substrate according to some embodiments;

[0051] FIG18 is a top view of the second active layer of the array substrate according to some embodiments;

[0052] FIG19 is a top view of a second gate conductive layer of an array substrate according to some embodiments;

[0053] FIG. 20 is a top view of a third gate conductive layer of an array substrate according to some embodiments. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0057] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean mechanical or electrical connection; fixed or removable connection; or integral connection; direct connection or indirect connection through an intermediary; or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this document based on the specific circumstances.

[0058] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0059] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0060] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0061] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0062] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0063] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0064] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0065] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0066] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0067] The term "overlap" or "overlapping" means that a first object may be above or below or to the side of a second object, and vice versa. Additionally, the term "overlap" may include stacking, stacking, facing, facing, extending over, covering, or partially covering, or any other suitable term that would be appreciated and understood by one of ordinary skill in the art.

[0068] When an element is described as “not overlapping” or “will not overlap” another element, this may include the elements being spaced apart, offset, or separated from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0069] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0070] In the embodiments of the present disclosure, the transistors used may be thin film transistors (TFT), field effect transistors (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0071] Herein, the control electrode of each thin film transistor is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the thin film transistor is a P-type transistor, the first electrode of the thin film transistor is the source and the second electrode is the drain; exemplarly, in the case where the thin film transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0072] In the embodiments of the present disclosure, the capacitor can be a capacitive device independently manufactured through a process, for example, by manufacturing dedicated capacitive electrodes, each of which can be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or implemented by the transistor itself and other devices or circuits, or by utilizing the parasitic capacitance between the circuits within the circuit itself.

[0073] In the circuits provided in the embodiments of the present disclosure, nodes do not represent actual components, but rather represent junctions of related electrical connections in the circuit diagram. That is, these nodes are equivalent to junctions of related electrical connections in the circuit diagram.

[0074] As shown in FIG. 1 , some embodiments of the present disclosure provide a display device 1000 , which may be any device that displays an image, whether in motion (eg, video) or stationary (eg, still image), and whether textual or graphic.

[0075] Exemplarily, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a car display, a flight display, a wearable device, a virtual reality (VR) device, a projector, an electronic billboard or signboard, etc.

[0076] For example, as shown in FIG1 , the display device 1000 may be a portable display product; for example, the display device 1000 may be the mobile phone shown in FIG1 . For another example, referring to FIG2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be the watch shown in FIG2 .

[0077] It should be noted that, depending on different application scenarios, the display device 1000 can be a flat display device, a curved display device, a foldable display device, etc., and the shape of the display surface of the display device 1000 can be any one of a circular, elliptical, polygonal or irregular shape, which is not specifically limited in the embodiments of the present disclosure.

[0078] In some embodiments, referring to FIG3 , a display device 1000 includes a display panel 100 . The display panel 100 may include a display side and a non-display side that are opposite to each other. The display side refers to a side of the display panel 100 that displays a picture, and the non-display side refers to the other side opposite to the display side.

[0079] The display panel 100 may be of various types and may be selected based on actual needs. For example, the display panel 100 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (MicroLED) display panel, etc., and the present disclosure does not impose any specific limitations thereon.

[0080] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0081] 3 , the display device 1000 may further include a housing 200 , a cover plate 300 , a circuit board 400 , a photosensitive device 500 , and other electronic components. The display panel 100 , the circuit board 400 , and the photosensitive device 500 may be disposed within the housing 200 .

[0082] For example, as shown in Figure 3, the shell 200 can be a box-shaped structure with an opening, the display panel 100, the circuit board 400 and the photosensitive device 500 can be arranged in the shell 200, and the cover plate 300 is arranged on the side of the display panel 100 displaying the screen and is located at the opening of the shell 200.

[0083] The circuit board 400 can be bonded to the display panel 100 at its end and bent to the back of the display panel 100 to reduce the bezel of the display panel 100 and increase the screen-to-body ratio. The photosensitive device 500 can be integrated directly below the non-display side of the display panel 100 to reduce the bezel of the display panel 100 and increase the screen-to-body ratio.

[0084] It should be noted that the photosensitive device 500 can be a camera, an infrared sensor, a proximity sensor, an eye tracking module, a face recognition module, etc., and the embodiments of the present disclosure do not make specific limitations here.

[0085] 4 , the display panel 100 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA. FIG4 takes the peripheral area BB as an example, in which the peripheral area BB surrounds the display area AA.

[0086] The display area AA is an area for displaying images and is configured to house sub-pixels P. The peripheral area BB is an area for not displaying images and is configured to bind the circuit board 400 and house driving circuits. For example, the display panel 100 includes binding pins, a gate driving circuit, and a source driving circuit disposed in the peripheral area BB.

[0087] For example, as shown in FIG4 , a plurality of sub-pixels P may be arranged in a plurality of rows and columns in the display area A, wherein the plurality of columns include at least two sub-pixels P arranged along a first direction X, and the plurality of rows include at least two sub-pixels P arranged along a second direction Y. For example, each column includes at least two sub-pixels P arranged along the first direction X, and each row includes at least two sub-pixels P arranged along the second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0088] Some embodiments of the present disclosure are schematically described below by taking the perpendicularity between the first direction X and the second direction Y as an example, but the embodiments of the present disclosure are not limited thereto.

[0089] Furthermore, the plurality of sub-pixels P may include, for example, a plurality of sub-pixels P emitting different luminous colors, and the plurality of sub-pixels P emitting different luminous colors interact with each other to achieve full-color display. For example, the plurality of sub-pixels P may include a red sub-pixel R emitting red luminous color, a blue sub-pixel B emitting blue luminous color, and a green sub-pixel G emitting green luminous color.

[0090] It is understandable that when achieving full-color display, the arrangement of the red sub-pixels R, the blue sub-pixels B, and the green sub-pixels G is not unique.

[0091] For example, as shown in FIG4 , a plurality of red sub-pixels R and a plurality of blue sub-pixels B are arranged in an array of multiple rows and columns, with each column including a plurality of red sub-pixels R and a plurality of blue sub-pixels B staggered along a first direction X, and each row including a plurality of red sub-pixels R and a plurality of blue sub-pixels B staggered along a second direction Y. A plurality of green sub-pixels G are arranged in an array of multiple rows and columns, with one green sub-pixel G positioned between each of two adjacent rows and columns of red sub-pixels R and blue sub-pixels B. In this case, the red sub-pixels R, blue sub-pixels B, and green sub-pixels G are arranged in a first arrangement. Arranging the red sub-pixels R, blue sub-pixels B, and green sub-pixels G in the first arrangement results in a more detailed display and a better display quality.

[0092] It should be noted that the geometric centers of the sub-pixels P in the same column can be distributed on multiple parallel lines, and the first direction X is parallel to the lines. The geometric centers of the sub-pixels P in the same row can be distributed on multiple parallel lines, and the second direction Y is parallel to the lines.

[0093] Below, some embodiments of the present disclosure are schematically illustrated by taking multiple sub-pixels P including red sub-pixels R, blue sub-pixels B and green sub-pixels G, and arranged in the first arrangement as an example. However, the implementation methods of the present disclosure are not limited to this, and any other arrangements can also be considered as long as the same technical concept is applied.

[0094] In some embodiments, as shown in FIG5 , the display panel 100 includes a display substrate 110 and an encapsulation layer 120 disposed on one side of the display substrate 110. The encapsulation layer 120 covers the display substrate 110 to reduce the risk of water and oxygen corrosion. The encapsulation layer 120 can be an encapsulation film or an encapsulation substrate.

[0095] In some embodiments, as shown in FIG5 , the display panel 100 includes a display substrate 110 and an encapsulation layer 120 disposed on one side of the display substrate 110. The encapsulation layer 120 covers the display substrate 110 to reduce the risk of water and oxygen corrosion. The encapsulation layer 120 can be an encapsulation film or an encapsulation substrate.

[0096] 5 , the display panel 100 further includes an anti-reflection film 150 disposed on a side of the encapsulation layer 120 away from the display substrate 110 . The anti-reflection film 150 is configured to reduce the reflection intensity of ambient light on the display panel 100 .

[0097] In some examples, referring to FIG5 , the anti-reflection film 150 includes a black matrix 151 and a color filter 152. The black matrix 151 is used to separate the light emitted from different sub-pixels P (see FIG4 ) and has the function of reducing the reflected light generated by the external ambient light entering the interior of the display panel 100. The color filter 152 can filter out most of the wavelength bands of the external ambient light, thereby reducing the reflection intensity of the external ambient light on the display panel 100. In other examples, the anti-reflection film 150 includes a polarizer, which is not specifically limited in the embodiments of the present disclosure.

[0098] In some embodiments, as shown in FIG. 5 , the display substrate 110 includes an array substrate 10 , and a light emitting device 20 , a pixel defining layer 130 , and a spacer 140 disposed on one side of the array substrate 10 .

[0099] The pixel defining layer 130 defines a plurality of pixel openings 131, and a light-emitting device 20 is located within each pixel opening 131. Spacers 140 are disposed between the pixel defining layer 130 and the encapsulation layer 120, and are located in the region between the plurality of light-emitting devices 20. In this way, during the manufacturing process of the display panel 100, the spacers 140 can support the mask plate, reducing the risk of scratches caused by direct contact between the mask plate and the pixel defining layer 130 or the light-emitting device 20, thereby affecting the display effect.

[0100] In addition, the array substrate 10 includes a substrate 11 and a plurality of pixel circuits 30 disposed on the substrate 11. The light-emitting devices 20 are connected to the pixel circuits 30 to receive driving current signals and drive the light-emitting devices 20 to emit light. In this case, one sub-pixel P includes one light-emitting device 20 and a pixel circuit 30 that drives the light-emitting device 20.

[0101] The substrate 11 may be a rigid substrate, for example, a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0102] The substrate 11 may be a flexible substrate, for example, a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0103] As shown in Figures 5 and 6, the light-emitting device 20 includes a light-emitting functional layer 22, and a first electrode 21 and a second electrode 23 disposed on opposite sides of the light-emitting functional layer 22, with the first electrode 21 being closer to the array substrate 10. The first electrode 21 can be connected to the pixel circuit 30, for example, and the second electrode 22 can be connected to the second voltage signal terminal VSS, for example.

[0104] In some embodiments, the light-emitting functional layer 22 includes only a light-emitting layer. In other embodiments, the light-emitting functional layer 22 includes, in addition to the light-emitting layer, at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0105] It should be noted that, among the first electrode 21 and the second electrode 23 , one is an anode and the other is a cathode, which is not specifically limited in the embodiment of the present disclosure.

[0106] As shown in Figures 5 and 6, the pixel circuit 30 includes multiple transistors 310. The transistors 310 include a channel 311, a first electrode 312, a second electrode 313, and a control electrode 314. The first electrode 312 and the second electrode 313 are respectively connected to the channel 311. On this basis, the first electrode 21 is electrically connected to the first electrode 312 or the second electrode 313 of one of the multiple transistors 310. In Figure 5, the first electrode 21 is electrically connected to the first electrode 312 of the transistor 310.

[0107] In some embodiments, referring to FIG. 6 , the pixel circuit 30 includes a capacitor C, a first reset transistor T1 , and a compensation transistor T2 .

[0108] 5 and 6 , the first plate C1 of the capacitor C is connected to the first voltage signal terminal VDD. The second plate C2 of the capacitor C is connected to the first node N1. The control electrode 314 of the first reset transistor T1 is connected to the first reset signal terminal Reset1, the first electrode 312 of the first reset transistor T1 is connected to the first initialization signal terminal Vinit1, and the second electrode 313 of the first reset transistor T1 is connected to the second node N2. The control electrode 314 of the compensation transistor T2 is connected to the first scan signal terminal GATE1, the first electrode 312 of the compensation transistor T2 is connected to the second node N2, and the second electrode 313 of the compensation transistor T2 is connected to the first node N1.

[0109] For example, as shown in Figures 5, 6, 7, and 8, the array substrate 10 includes a plurality of first connection lines 40 and a plurality of second connection lines 50. The plurality of first connection lines 40 extend along a first direction X, and one end of the first connection line 40 is connected to the second electrode C2 of the capacitor C, and the other end is connected to the second electrode 313 of the compensation transistor T2. The plurality of second connection lines 50 extend along the first direction X, and one end of the second connection line 50 is connected to the second electrode 313 of the first reset transistor T1, and the other end is connected to the first electrode 312 of the compensation transistor T2.

[0110] It should be understood that the structure of the above-mentioned pixel circuit 30 includes various types and can be selected and set according to actual needs. This disclosure uses the internal compensation method and the pixel circuit 30 adopts the "8T1C" structure as an example to schematically illustrate the structure and operation process of the pixel circuit 30. Among them, "T" represents a transistor, and the number before "T" represents the number of transistors. "C" represents a capacitor, and the number before "C" represents the number of capacitors.

[0111] The pixel circuit 30 further includes a driving transistor T3 , a data writing transistor T4 , a first enabling transistor T5 , a second enabling transistor T6 , a second reset transistor T7 and a third reset transistor T8 .

[0112] In the pixel circuit 30 provided in the embodiment of the present disclosure, the transistor 310 may be a P-type transistor or an N-type transistor.

[0113] In the following, some embodiments of the present disclosure are schematically described by taking the first reset transistor T1, the drive transistor T3, the data writing transistor T4, the first enable transistor T5, the second enable transistor T6, the second reset transistor T7 and the third reset transistor T8 as P-type transistors and the compensation transistor T2 as an N-type transistor as an example, but the embodiments of the present disclosure are not limited thereto.

[0114] As shown in FIG5 and FIG6 , the control electrode 314 of the driving transistor T3 is connected to the first node N1 , the first electrode 312 of the driving transistor T3 is connected to the third node N3 , and the second electrode 313 of the driving transistor T3 is connected to the second node N2 .

[0115] As shown in FIG5 and FIG6, the control electrode 314 of the data writing transistor T4 is connected to the second scan signal terminal GATE2, the first electrode 312 of the data writing transistor T4 is connected to the data signal terminal Data, and the second electrode 313 of the data writing transistor T4 is connected to the third node N3.

[0116] As shown in FIG5 and FIG6 , the control electrode 314 of the first enabling transistor T5 is connected to the enable signal terminal EM, the first electrode 312 of the first enabling transistor T5 is connected to the first voltage signal terminal VDD, and the second electrode 313 of the first enabling transistor T5 is connected to the third node N3.

[0117] As shown in Figures 5 and 6, the control electrode 314 of the second enabling transistor T6 is connected to the enable signal terminal EM, the first electrode 312 of the second enabling transistor T6 is connected to the second node N2, and the second electrode 313 of the second enabling transistor T6 is connected to the fourth node N4. It should be noted that the first electrode 21 of the light emitting device 20 is connected to the fourth node N4.

[0118] As shown in FIG5 and FIG6, the control electrode 314 of the second reset transistor T7 is connected to the second reset signal terminal Reset2, the first electrode 312 of the second reset transistor T7 is connected to the second initialization signal terminal Vinit2, and the second electrode 313 of the second reset transistor T7 is connected to the fourth node N4.

[0119] As shown in FIG5 and FIG6, the control electrode 314 of the third reset transistor T8 is connected to the second reset signal terminal Reset2, the first electrode 312 of the third reset transistor T8 is connected to the third initialization signal terminal Vinit3, and the second electrode 313 of the third reset transistor T8 is connected to the third node N3.

[0120] On this basis, the first reset transistor T1 , the driving transistor T3 , the data writing transistor T4 , the first enabling transistor T5 , the second enabling transistor T6 , the second reset transistor T7 and the third reset transistor T8 may be, for example, low-temperature polysilicon transistors, and the compensation transistor T2 may be, for example, an oxide transistor.

[0121] It should be understood that the active layer of low-temperature polysilicon transistors uses low-temperature polysilicon (LTPS), which has advantages such as high mobility and fast charging. The active layer of oxide transistors uses oxide semiconductors (oxides), such as indium gallium zinc oxide and indium gallium tin oxide, and oxide transistors have advantages such as low leakage current.

[0122] Based on this, low-temperature polysilicon transistors and oxide transistors are integrated on an array substrate 10 to form a low-temperature polycrystalline oxide (LTPO) array substrate 10, which can take advantage of the advantages of both to reduce leakage current, lower power consumption, achieve low-frequency driving, and improve display quality.

[0123] In some embodiments, referring to FIG9 , the array substrate 10 further includes a plurality of first data lines 61 , which extend along a first direction X and are spaced apart in a second direction Y. Referring to FIG6 and FIG9 , a first data line 61 can be connected to a data signal terminal Data of a column of pixel circuits 30 to transmit a data signal.

[0124] At this time, the first connection line 40 and the second connection line 50 are located between two adjacent first data lines 61, and in the second direction Y, the distance between the first connection line 40 and one of the two first data lines 61 is closer, and the second connection line 50 is located on the side of the first connection line 40 away from the adjacent first data line 61.

[0125] In some related technologies, the spacing between the first data line and the first connecting line is small, and the parasitic capacitance between the first data line and the first connecting line increases, resulting in increased crosstalk between the first data line and the capacitor connected to the first connecting line, thereby causing the display effect of the display panel to decline.

[0126] Based on this, in the array substrate 10 provided in some embodiments of the present disclosure, referring to FIG. 9 , in the second direction Y, the maximum distance between adjacent first connection lines 40 and second connection lines 50 is less than or equal to 2.4 μm.

[0127] Exemplarily, in the second direction Y, the distance between adjacent first connecting lines 40 and second connecting lines 50 is 1μm to 2.4μm; for example, in the second direction Y, the distance between adjacent first connecting lines 40 and second connecting lines 50 is approximately any one of 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm, 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm and 2.4μm.

[0128] In this case, in the second direction Y, the distance between adjacent first connection lines 40 and second connection lines 50 can be reduced, that is, the first connection lines 40 can be offset in the direction close to the second connection lines 50 to increase the spacing between the first connection lines 40 and the adjacent first data lines 61 in the second direction Y. The increased spacing can, for example, reach 1.6μm to 3.1μm.

[0129] According to the capacitance calculation formula, in the second direction Y, as the distance between the first connecting line 40 and the adjacent first data line 61 increases, the parasitic capacitance between the first connecting line 40 and the adjacent first data line 61 decreases, thereby reducing crosstalk between the capacitor C connected to the first connecting line 40 and the adjacent first data line 61, thereby improving the display effect. Compared to the related art, in the array substrate 10 provided in some embodiments of the present disclosure, the parasitic capacitance between the first connecting line 40 and the adjacent first data line 61 can be reduced by approximately 0.13fF.

[0130] 5 and 10 , the array substrate 10 includes a first source-drain conductive layer SD1 disposed on a side of the substrate 11 close to the pixel circuit 30. The first connection line 40 and the second connection line 50 may be located in the first source-drain conductive layer SD1.

[0131] As shown in Figures 5, 6, 10, and 11, the first source-drain conductive layer SD1 may further include a third connection line 81 and a fourth connection line 82. The third connection line 81 extends along the first direction X, with one end of the third connection line 81 connected to the second electrode 313 of the first enable transistor T5 and the other end connected to the second electrode 313 of the third reset transistor T8. The fourth connection line 82 extends along the first direction X, with one end of the fourth connection line 82 connected to the first electrode 312 of the first enable transistor T5 and the other end connected to the second plate C2 of the capacitor C.

[0132] In addition, as shown in FIG. 10 , the first source-drain conductive layer SD1 may further include a fifth connection line 83 , a sixth connection line 84 and a seventh connection line 85 .

[0133] As shown in FIG. 5 , FIG. 6 , FIG. 10 and FIG. 11 , the fifth connection line 83 extends along the second direction Y, and both ends of the fifth connection line 83 are respectively connected to the first electrode 312 of the third reset transistor T8 , and the fifth connection line 83 is also connected to the third initialization signal line 75 .

[0134] As shown in FIG. 5 , FIG. 6 , FIG. 10 and FIG. 11 , the sixth connection line 84 extends along the first direction X. One end of the sixth connection line 84 is connected to the first electrode 312 of the second reset transistor T7 , and the other end is connected to the second initialization signal line 74 .

[0135] As shown in Figures 5, 6, 10 and 11, the seventh connection line 85 extends along the first direction X. One seventh connection line 85 is connected to any one of the plurality of first initialization signal lines 73, the plurality of second initialization signal lines 74 and the plurality of third initialization signal lines 75 to reduce resistance, reduce the voltage drop of the initialization signal transmitted by the first initialization signal line 73, the second initialization signal line 74 and the third initialization signal line 75, and improve brightness uniformity.

[0136] It should be noted that the first initialization signal line 73 , the second initialization signal line 74 and the third initialization signal line 75 may be specifically described below, and will not be elaborated herein in detail in the present disclosure.

[0137] In some embodiments, referring to Figure 9, the array substrate 10 also includes a plurality of first power signal lines 63, which are made of the same material and arranged in the same layer as the first data lines 61, and / or are located between the film layer where the first data lines 61 are located and the film layer where the first connection lines 40 are located.

[0138] The orthographic projection of the first connecting line 40 on the reference plane is within the range of the orthographic projections of the plurality of first power signal lines 63 on the reference plane. Thus, the first power signal lines 63 can function as electromagnetic shields, thereby reducing crosstalk between the capacitor C connected to the first connecting line 40 and the adjacent first data lines 61, thereby improving display quality. It should be noted that the reference plane is a plane defined by the first direction X and the second direction Y.

[0139] Exemplarily, referring to FIG. 9 , FIG. 12 and FIG. 13 , the plurality of first power signal lines 63 include a plurality of first power sub-lines 631 , a plurality of second power sub-lines 632 and a plurality of third power sub-lines 633 .

[0140] As shown in Figures 9 and 13 , the first power sub-lines 631 are configured to receive power signals provided by the circuit board 400. For example, multiple first power sub-lines 631 extend along a first direction X and are spaced apart in a second direction Y. One end of the first power sub-line 631 is directly connected to a binding pin, that is, directly connected to the circuit board 400 via the binding pin, to receive the power signal.

[0141] Here, among the multiple first power sub-lines 631, some first power sub-lines 631 can also be directly connected to the first voltage signal terminal VDD (see Figure 6) of a column of pixel circuits 30, and other first power sub-lines 631 are not directly connected to the first voltage signal terminal VDD (see Figure 6) of a column of pixel circuits 30, but are connected to the corresponding second power sub-lines 632 through the third power sub-line 633, and the second power sub-line 632 is directly connected to the first voltage signal terminal VDD (see Figure 6) of a column of pixel circuits 30.

[0142] As shown in Figures 9 and 13 , the second power sub-line 632 is configured to provide a power signal to the first voltage signal terminal VDD of the pixel circuit 30. For example, the second power sub-line 632 extends along the first direction X and is arranged at intervals in the second direction Y. Specifically, one second power sub-line 632 can be directly connected to the first voltage signal terminal VDD (see Figure 6 ) of a column of pixel circuits 30.

[0143] Here, the second power sub-line 632 is not directly connected to the binding pin, but is connected to the first power sub-line 631 through the third power sub-line 633 to receive the power signal. Here, the first power sub-line 631 connected to the third power sub-line 633 is not directly connected to the first voltage signal terminal VDD (see Figure 6) of the pixel circuit 30.

[0144] As shown in Figures 9, 12, and 13, a second power sub-line 632 is connected to a first power sub-line 631. For example, third power sub-lines 633 extend along the second direction Y and are spaced apart in the first direction X. A second power sub-line 632 is connected to a first power sub-line 631 via a third power sub-line 633.

[0145] On this basis, part of the orthographic projection of the above-mentioned first connecting line 40 on the reference plane is located within the range of the orthographic projection of the first power sub-line 631 or the second power sub-line 632 on the reference plane, and the other part is located within the range of the orthographic projection of the third power sub-line 633 on the reference plane.

[0146] 5 and 9 , the array substrate 10 may further include a second source-drain conductive layer SD2 and a third source-drain conductive layer SD3. The second source-drain conductive layer SD2 is disposed on a side of the first source-drain conductive layer SD1 away from the substrate 11, and the third source-drain conductive layer SD3 is disposed on a side of the second source-drain conductive layer SD2 away from the substrate 11. In this case, the third power sub-line 633 may be located in the second source-drain conductive layer SD2, and the first data line 61, the first power sub-line 631, and the second power sub-line 632 may be located in the third source-drain conductive layer SD3.

[0147] In some embodiments, referring to FIG. 9 , the array substrate 10 may further include a plurality of second data lines 62 , and the plurality of first data lines 61 may include first-type data lines 611 and second-type data lines 612 .

[0148] 6 and 9 , a first-type data line 611 is directly connected to the driving circuit and to the data signal terminal Data of a column of pixel circuits 30 to provide data signals to the pixel circuits 30. A second-type data line 612 is directly connected to the data signal terminal Data of a column of pixel circuits 30 and is connected to the driving circuit via a second data line 62.

[0149] For example, referring to Figures 9, 12, and 13, the second data lines 62 include first data sub-lines 621 and second data sub-lines 622. A plurality of first data sub-lines 621 extend along a first direction X and are spaced apart in a second direction Y. A plurality of second data sub-lines 622 extend along the second direction Y and are spaced apart in the second direction X. The first data sub-lines 621 are directly connected to the driving circuit; furthermore, each first data sub-line 621 is connected to a second-type data line 612 via a second data sub-line 622 to transmit a data signal to the second-type data line 612.

[0150] At this time, the second data sub-line 622 can be located in the second source-drain conductive layer SD2. The first data sub-line 621 can be located in the third source-drain conductive layer SD3. For example, as shown in FIG13, the first data sub-line 621 is directly connected to the driving circuit without switching or avoiding.

[0151] Alternatively, a portion of the first data sub-line 621 is located in the second source-drain conductive layer SD2, and the other portion is located in the third source-drain conductive layer SD3. For example, as shown in FIG14 , the first data sub-line 621 includes a main segment 6210 and a transition segment. The main segment 6210 is spaced apart in the first direction X to form an avoidance area. The avoidance area can be configured as a light-transmitting area to facilitate lighting of the photosensitive device 500 on the non-light-emitting side of the display panel 100.

[0152] It should be noted that the main segment 6210 may be located in the third source-drain conductive layer SD3 , and the transition segment may be located in the second source-drain conductive layer SD2 , which is not specifically limited in the embodiment of the present disclosure.

[0153] 9 , 13 , and 14 , the plurality of first data lines 61 are divided into a plurality of data line groups 610, each data line group 610 including two first data lines 61. In this case, the first data sub-line 621 may be located between two first data lines 61 in the same data line group 610.

[0154] The plurality of first data lines 61 include alternating straight segments 613 and curved segments 614. The plurality of first data lines 61 are divided into a plurality of data line groups 610, each of which includes two first data lines 61. The curved segments 614 of the two first data lines 61 in the same data line group 610 are arranged opposite each other and bend away from each other to form a clearance area. The clearance area can be configured as a light-transmitting area to facilitate light collection by the photosensitive device 500 on the non-light-emitting side of the display panel 100.

[0155] At this time, the first connection line 40 and the second connection line 50 are located between two adjacent first data lines 61 belonging to different data line groups 610. Furthermore, in the second direction Y, the first connection line 40 and the bent section 614 are at least partially opposite to each other, and the opposing portion is parallel to the opposing boundary of the adjacent second connection line 50.

[0156] It should be noted that “the boundary between the portion of the first connecting line 40 opposite to the bending section 614 and the adjacent second connecting line 50 ” does not include the portion where the ends of the first connecting line 40 and the second connecting line 50 are bent away from each other.

[0157] It should be understood that, in the second direction Y, the portion of the first connecting line 40 that is relatively close to the first data line 61 is the portion of the first connecting line 40 that is opposite the bent section 614. The portion of the first connecting line 40 that is opposite the bent section 614 is parallel to the boundary opposite the adjacent second connecting line 50. This allows the distance between the portion of the first connecting line 40 that is relatively close to the first data line 61 and the adjacent second connecting line 50 to be set to a process limit, thereby reducing the distance between the first connecting line 40 and the second connecting line 50, increasing the distance between the first connecting line 40 and the first data line 61, and reducing the parasitic capacitance between the first connecting line 40 and the adjacent first data line 61. This reduces crosstalk between the capacitor C connected to the first connecting line 40 and the adjacent first data line 61, thereby improving display quality.

[0158] Exemplarily, as shown in Figures 15 and 16, the first connecting line 40 includes a first connecting pad 41, a first routing segment 42, a second routing segment 43 and a second connecting pad 44 connected in sequence, and the second connecting line 50 includes a third connecting pad 51, a third routing segment 52, a fourth routing segment 53 and a fourth connecting pad 54 connected in sequence.

[0159] 5 , 6 , 11 , and 17 , the first connection pad 41 is connected to the second electrode C2 of the capacitor C, the second connection pad 44 is connected to the second electrode 313 of the compensation transistor T2, the third connection pad 51 is connected to the first electrode 312 of the compensation transistor T2, and the fourth connection pad 54 is connected to the second electrode 313 of the first reset transistor T1.

[0160] It should be noted that the shapes of the first connection pad 41 , the second connection pad 44 , the third connection pad 51 and the fourth connection pad 54 include at least one of polygonal, circular and elliptical shapes, which are not specifically limited in the embodiment of the present disclosure.

[0161] On this basis, as shown in Figures 15 and 16 , the first routing segment 42 extends toward the adjacent second connection line 50 and is located on the side of the third routing segment 52 away from the fourth connection pad 54. In the second direction Y, the first routing segment 42 is opposite to the third connection pad 51, the second routing segment 43 is opposite to the third routing segment 52, and the fourth routing segment 53 is opposite to the second connection pad 44.

[0162] Furthermore, the boundaries between the second routing segment 43 and the third routing segment 52 are parallel, and the boundaries between the second connection pad 44 and the fourth routing segment 53 are parallel. This allows the distances between the second routing segment 43 and the second connection pad 44 and the adjacent routing segment of the second connecting line 50 to be set to process limits. This reduces the distances between the second routing segment 43 and the second connection pad 44 and the routing segment of the second connecting line 50, increases the distances between the second routing segment 43 and the second connection pad 44 and the first data line 61, and reduces the parasitic capacitance between the second routing segment 43 and the second connection pad 44 and the adjacent first data line 61. This reduces crosstalk between the capacitor C connected to the first connecting line 40 and the adjacent first data line 61, thereby improving display quality. In this case, the portion of the first connecting line 40 opposite the bend 614 may include the second connection pad 44 and the second routing segment 43.

[0163] 15 and 16 , in the second direction Y, the fourth routing segment 53 may, for example, be opposite to a portion of the second connection pad 44, and the fourth connection pad 54 may, for example, be opposite to another portion of the second connection pad 44. Furthermore, the orthographic projections of the second connection pad 44 and the fourth connection pad 54 on the reference plane may, for example, be polygonal.

[0164] At this time, the second connection pad 44 can also be parallel to the boundary relative to the fourth connection pad 54, so that when the second connection pad 44 and the fourth connection pad 54 are partially relative, the distance between the second connection pad 44 and the fourth connection pad 54 can be set to the process limit value. This is conducive to increasing the distance between the second connection pad 44 and the first data line 61, reducing the parasitic capacitance between the second connection pad 44 and the adjacent first data line 61, thereby reducing the crosstalk between the capacitor C connected to the first connection line 40 and the adjacent first data line 61, and improving the display effect.

[0165] In some embodiments, referring to Figures 7, 8 and 11, in the same pixel circuit 30, along the first direction X, the channel 311 of the first reset transistor T1 is located on one side of the channel 311 of the driving transistor T3, and the second electrode 313 of the first reset transistor T1 is farther away from the adjacent first data line 61 than the second electrode 313 of the driving transistor T3.

[0166] 5 and 11 , the array substrate 10 further includes a first active layer ACT1 disposed between the substrate 11 and the first source / drain conductive layer SD1. The first active layer ACT1 includes a plurality of first active patterns 91, a plurality of second active patterns 92, and a plurality of third active patterns 93.

[0167] As shown in FIG5 and FIG11, the first active pattern 91 includes a channel 311, a first electrode 312 and a second electrode 313 of a driving transistor T3, a data writing transistor T4, a first enabling transistor T5, a second enabling transistor T6 and a second reset transistor T7;

[0168] As shown in Figures 5 and 11, the second active pattern 92 includes a channel 311 of the first reset transistor T1, a first electrode 312, and a second electrode 313. A plurality of first active patterns 91 and a plurality of second active patterns 92 are alternately arranged in the first direction X, and the second active patterns 92 are farther away from the corresponding first data lines 61 than the corresponding first active patterns 91.

[0169] 5 and 11 , the third active pattern 93 includes a channel 311 of the third reset transistor T8, a first electrode 312, and a second electrode 313. Along the second direction Y, the third active pattern 93 is located on a side of the channel 311 of the second reset transistor T7 close to the channel 311 of the first enabling transistor T5.

[0170] At this time, as shown in Figures 8, 9, 15 and 16, the third routing segment 52 may, for example, include a fourth sub-segment 521, a fifth sub-segment 522 and a sixth sub-segment 523 connected in sequence, the fourth sub-segment 521 is connected to the third connection pad 51, the sixth sub-segment 523 is connected to the fourth routing segment 53, and the sixth sub-segment 523 is farther away from the adjacent first data line 61 than the fourth sub-segment 521, so as to connect the second electrode 313 of the first reset transistor T1 with the second electrode 313 of the driving transistor T3.

[0171] Because the boundaries between the second routing segment 43 and the third routing segment 52 are parallel, the second routing segment 43 may include, for example, a first sub-segment 431, a second sub-segment 432, and a third sub-segment 433 connected in sequence. The first sub-segment 431 is connected to the first routing segment 42, and the third sub-segment 433 is connected to the second connection pad 44. In the second direction, the first sub-segment 431 is opposite to the fourth sub-segment 521, the second sub-segment 432 is opposite to the fifth sub-segment 522, and the third sub-segment 433 is opposite to the sixth sub-segment 523. The third sub-segment 433 is farther away from the adjacent first data line 61 than the first sub-segment 431.

[0172] In some embodiments, referring to Figures 9, 15, and 16, at least a portion of the boundary between the first routing segment 42 and the adjacent second connection line 50 is parallel in the second direction X. That is, at least a portion of the boundary between the first routing segment 42 and the adjacent third connection pad 51 is also parallel. This helps increase the distance between the first routing segment 42 and the first data line 61, reducing the parasitic capacitance between the first routing segment 42 and the adjacent first data line 61, thereby reducing crosstalk between the capacitor C connected to the first connection line 40 and the adjacent first data line 61, and improving the display effect.

[0173] For example, referring to Figures 15 and 16 , the first routing segment 42 includes a seventh subsegment 421 and an eighth subsegment 422. The seventh subsegment 421 is connected to the first connection pad 41 and extends toward the adjacent second connection line 50. The eighth subsegment 422 is connected to the second routing segment 43. For example, as shown in Figure 15 , the boundary between the eighth subsegment 422 and the third connection pad 51 extending along the first direction X is parallel. For another example, as shown in Figure 16 , the boundaries between the eighth subsegment 422 and the third connection pad 51 are both parallel.

[0174] In some embodiments, referring to Figures 7, 8, and 9, the orthographic projection of the boundary of the first connecting line 40 adjacent to the adjacent first data line 61 on a reference plane coincides with the orthographic projection of the boundary of the second electrode 313 of the connected compensation transistor T2 adjacent to the corresponding first data line 61 on the reference plane. The "corresponding first data line 61" refers to the first data line 61 adjacent to the first connecting line 40 connected to the second electrode 313 of the compensation transistor T2.

[0175] For example, referring to FIG. 18 , the array substrate 10 further includes a second active layer ACT2 disposed between the first active layer ACT1 and the first source / drain conductive layer SD1. The second active layer ACT2 includes a plurality of fourth active patterns 94 , each of which includes a channel 311 , a first electrode 312 , and a second electrode 313 of the compensation transistor T2 .

[0176] As shown in Figures 7, 9, 11, and 18, the fourth active pattern 94 is located between adjacent first active patterns 91 and second active patterns 92 along the first direction X. The fourth active pattern 94 is close to the boundary of the corresponding first data line 61 and coincides with the orthographic projection of the boundary of the connected first connection line 40 close to the adjacent first data line 61 on the reference plane.

[0177] At this time, when the second electrode 313 of the compensation transistor T2 forms a good electrical connection with the first connecting line 40, the distance between the second electrode 313 of the compensation transistor T2 and the adjacent first data line 61 is set relatively far, which is conducive to reducing the parasitic capacitance between the second electrode 313 of the compensation transistor T2 and the adjacent first data line 61, thereby further reducing the crosstalk between the capacitor C connected to the first connecting line 40 and the adjacent first data line 61, thereby improving the display effect.

[0178] In some embodiments, referring to Figures 6, 7, 18, and 19, the array substrate 10 further includes a plurality of first scan signal lines 71. The first scan signal lines 71 extend along the second direction Y and are connected to the first scan signal terminal GATE1 of a row of pixel circuits 30. Furthermore, the orthographic projection of the first scan signal lines 71 on the reference plane overlaps with the orthographic projection of the channel 311 of the compensation transistor T2 on the reference plane to form the control electrode 314 of the compensation transistor T2 (see Figure 5).

[0179] 7 , the orthographic projections of the first scanning signal line 71 and the first connecting line 40 on the reference plane overlap, and any boundary of the overlapping portion is parallel to the first direction X or the second direction Y. This can reduce the difference in the overlapping area between different first connecting lines 40 and the first scanning signal line 71 caused by process deviations, thereby improving the brightness uniformity of multiple sub-pixels P (see FIG. 4 ), thereby enhancing the display effect.

[0180] Exemplarily, referring to Figures 7 and 18, the first scan signal line 71 includes a plurality of first scan routing segments 710 connected in sequence, and the first scan routing segment 710 includes a first scan sub-segment 711 and a second scan sub-segment 712 connected in sequence. The first scan sub-segment 711 overlaps with the orthographic projection of the first connecting line 40 on the reference plane, and the second scan sub-segment 712 overlaps with the orthographic projection of the channel 311 of the compensation transistor T2 on the reference plane.

[0181] The width of the first scanning sub-segment 711 remains approximately constant, and the width of the second scanning sub-segment 712 remains approximately constant. Furthermore, along the first direction X, the width of the first scanning sub-segment 711 is smaller than the width of the second scanning sub-segment 712. The boundary connecting the second scanning sub-segment 712 and the first scanning sub-segment 711 is parallel to the boundary opposite the first connecting line 40. That is, the connection between the first scanning sub-segment 711 and the second scanning sub-segment 712 is a vertical abrupt change, rather than a gradual transition. This reduces differences in the overlapping areas of different first connecting lines 40 and the first scanning signal line 71 caused by process variations, improves the brightness uniformity of multiple sub-pixels P, and thus enhances the display effect.

[0182] Exemplarily, referring to Figures 8 and 18, the first scan signal line 71 includes a plurality of first scan routing segments 710 connected in sequence, the first scan routing segment 710 includes a third scan sub-segment 713, a fourth scan sub-segment 714 and a fifth scan sub-segment 715 connected in sequence, the fourth scan sub-segment 714 overlaps with the orthographic projection of the first connecting line 40 on the reference plane, and the fifth scan sub-segment 715 overlaps with the orthographic projection of the channel 311 of the compensation transistor T2 on the reference plane.

[0183] The width of the third scanning sub-segment 713 remains approximately constant, the width of the fourth scanning sub-segment 714 remains approximately constant, and the width of the fifth scanning sub-segment 715 remains approximately constant. Furthermore, along the first direction X, the width of the third scanning sub-segment 713 is smaller than the width of the fourth scanning sub-segment 714, and the width of the fourth scanning sub-segment 714 is smaller than the width of the fifth scanning sub-segment 715. This increases the overlapping area between the first scanning signal line 71 and the first connecting line 40, thereby reducing the impact of process fluctuations on the characteristic deviation of the driving transistor T3, reducing the impact of the characteristic deviation of the driving transistor T3 on image quality, and improving the display effect.

[0184] On this basis, the boundary connecting the fourth scanning subsegment 714 and the third scanning subsegment 713 is parallel to the boundary opposite the first connection line 40; and / or the boundary connecting the fifth scanning subsegment 715 and the fourth scanning subsegment 714 is parallel to the boundary opposite the first connection line 40. In other words, the connection between the third scanning subsegment 713, the fourth scanning subsegment 714, and the fifth scanning subsegment 715 is a vertical abrupt transition rather than a gradual transition. This can reduce the difference in the overlapping area between different first connection lines 40 and the first scanning signal line 71 caused by process variations, improve the brightness uniformity of multiple sub-pixels P, and thus enhance the display effect.

[0185] In some embodiments, referring to Figures 5, 19 and 20, the array substrate 10 also includes a second gate conductive layer GT2 and a third gate conductive layer GT3, the second gate conductive layer GT2 is arranged between the first active layer ACT1 and the second active layer ACT2, and the third gate conductive layer GT3 is arranged between the second active layer ACT2 and the first source and drain conductive layer SD1.

[0186] That is, the second gate conductive layer GT2 and the third gate conductive layer GT3 are disposed on opposite sides of the second active layer ACT2. The second gate conductive layer GT2 may include a first plate C1 of the capacitor C.

[0187] On this basis, referring to Figures 19 and 20, the first scanning signal lines 71 are located in the second gate conductive layer GT2 and / or the third gate conductive layer GT3. The orthographic projections of the two first scanning signal lines 71 located in the second gate conductive layer GT2 and the third gate conductive layer GT3, respectively, on the reference plane may completely or partially overlap, which is not specifically limited in the present embodiment.

[0188] Exemplarily, as shown in Figures 7, 18, 19 and 20, a fourth active pattern 94 overlaps with two first scan signal lines 71, and the two first scan signal lines 71 are respectively located in the second gate conductive layer GT2 and the third gate conductive layer GT3 to form the top gate and bottom gate of the compensation transistor T2, respectively, to reduce the risk of leakage current of the compensation transistor T2.

[0189] In addition, referring to FIG. 19 and FIG. 20 , the array substrate 10 may further include a plurality of first initialization signal lines 73 , a plurality of second initialization signal lines 74 , and a plurality of third initialization signal lines 75 .

[0190] As shown in Figures 6, 19, and 20, the first initialization signal line 73, the second initialization signal line 74, and the third initialization signal line 75 extend along the second direction Y and are respectively connected to the first initialization signal terminal Vinit1, the second initialization signal terminal Vinit2, and the third initialization signal terminal Vinit3 of a row of pixel circuits 30. Furthermore, the first initialization signal line 73 may be located in the second gate conductive layer GT2, and the second initialization signal line 74 and the third initialization signal line 75 may be located in the third gate conductive layer GT3.

[0191] In some embodiments, referring to FIG. 17 , the array substrate 10 further includes a plurality of second scan signal lines 72 . The second scan signal lines 72 extend along a second direction Y and are connected to the second scan signal terminal GATE2 of a row of pixel circuits 30 . Furthermore, the orthographic projections of the second scan signal lines 72 on the reference plane overlap with the orthographic projections of the channel 311 of the data writing transistor T4 on the reference plane, and also overlap with the orthographic projections of the second electrode 313 of the compensation transistor T2 on the reference plane.

[0192] On this basis, the second scan signal line 72 includes a second scan line segment 720 and multiple widened portions 721. Along the first direction X, the multiple widened portions 721 are located on one side of the second scan line segment 720, and the orthographic projections of the widened portions 721 on the reference plane are located within the orthographic projections of the second electrode 313 of the compensation transistor T2 on the reference plane. This arrangement increases the parasitic capacitance between the second scan signal line 72 and the second electrode 313 of the compensation transistor T2, i.e., the parasitic capacitance between the second scan signal line 72 and the first connection line 40 is increased. This helps reduce the black state voltage, thereby reducing power consumption.

[0193] In some embodiments, referring to Figures 5 and 17 , the array substrate 10 further includes a first gate conductive layer GT1 disposed between the first active layer ACT1 and the second gate conductive layer ACT2. On this basis, the second plate C2 of the capacitor C and the second scan signal line 72 can be located in the first gate conductive layer GT1.

[0194] In addition, referring to FIG. 17 , the array substrate 10 may further include a first reset signal line 76 , a second reset signal line 77 and an enable signal line 78 .

[0195] As shown in Figures 6 and 17, the first reset signal line 76, the second reset signal line 77, and the enable signal line 78 extend along the second direction Y and are respectively connected to the first reset signal terminal Reset1, the second reset signal terminal Reset2, and the enable signal terminal EM of a row of pixel circuits 30. In addition, the first reset signal line 76, the second reset signal line 77, and the enable signal line 78 can be located in the first gate conductive layer GT1.

[0196] It should be understood, referring to FIG5 , that an insulating film layer should be provided between adjacent conductive film layers in the array substrate 10. For example, as shown in the figure, along a direction perpendicular to and away from the substrate 11, the array substrate 10 includes, in sequence, a first active layer ACT1, a first gate conductive layer GT1, a second gate conductive layer GT2, a second active layer ACT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, a second source-drain conductive layer SD2, and a third source-drain conductive layer SD3.

[0197] It should be noted that at least one of the first gate conductive layer GT1, the second gate conductive layer GT2, the third gate conductive layer GT3, the first source and drain conductive layer SD1, the second source and drain conductive layer SD2 and the third source and drain conductive layer SD3 may also include a transfer block, which is not specifically limited in the embodiments of the present disclosure.

[0198] On this basis, as shown in Figure 5, along the direction perpendicular to the substrate 11 and away from the substrate 11, the array substrate 10 also includes a first gate insulation layer GI1, a first interlayer insulation layer ILD1, a second gate insulation layer GI2, a third gate insulation layer GI3, a second interlayer insulation layer ILD2, a first flat layer PLN1, a second flat layer PLN2 and a third flat layer PLN3.

[0199] Among them, the first gate insulation layer GI1 is located between the first active layer ACT1 and the first gate conductive layer GT1, the first interlayer insulation layer ILD1 is located between the first gate conductive layer GT1 and the second gate conductive layer GT2, the second gate insulation layer GI2 is located between the second gate conductive layer GT2 and the second active layer ACT2, the third gate insulation layer GI3 is located between the second active layer ACT2 and the third gate conductive layer GT3, the second interlayer insulation layer ILD2 is located between the third gate conductive layer GT3 and the first source-drain conductive layer SD1, the first flat layer PLN1 is located between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2, the second flat layer PLN2 is located between the second source-drain conductive layer SD2 and the third source-drain conductive layer SD3, and the third flat layer PLN3 is located between the third source-drain conductive layer SD3 and the light-emitting device 20.

[0200] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: A pixel circuit includes a capacitor, a first reset transistor, and a compensation transistor, wherein the first plate of the capacitor is connected to the first voltage signal terminal, and the second plate of the capacitor is connected to the first node; The first electrode of the first reset transistor is connected to the first initialization signal terminal, and the second electrode of the first reset transistor is connected to the second node; the first electrode of the compensation transistor is connected to the second node, and the second electrode of the compensation transistor is connected to the first node; a plurality of first data lines extending along a first direction and arranged at intervals in a second direction; the first direction intersects the second direction; and the first data lines are connected to the pixel circuit; a plurality of first connecting lines extending along the first direction, wherein one end of the first connecting line is connected to the second plate of the capacitor and the other end is connected to the second electrode of the compensation transistor; the first connecting line is located between two adjacent first data lines and is relatively close to one of the two first data lines; A plurality of second connection lines extend along the first direction, and one end of the second connection line is connected to the second electrode of the first reset transistor, and the other end is connected to the first electrode of the compensation transistor; the second connection line is located between two adjacent first data lines, and in the second direction, the second connection line is located on the side of the first connection line away from the adjacent first data line; in the second direction, the maximum distance between adjacent first connection lines and second connection lines is less than or equal to 2.4 μm.

2. The array substrate according to claim 1, wherein: The first data lines include alternating straight segments and bent segments; the plurality of first data lines are divided into a plurality of data line groups, each data line group includes two first data lines, and the bent segments of the two first data lines in the same data line group are arranged opposite to each other and bent in directions away from each other; The first connecting line and the second connecting line are located between two adjacent first data lines belonging to different data line groups; and, in the second direction, the first connecting line is at least partially opposite to the bending section, and the opposite portion is parallel to the opposite boundary of the adjacent second connecting line.

3. The array substrate according to claim 2, wherein: The first connection line includes a first connection pad, a first routing segment, a second routing segment, and a second connection pad connected in sequence, the first connection pad is connected to the second plate of the capacitor, and the second connection pad is connected to the second electrode of the compensation transistor; The second connection line includes a third connection pad, a third routing segment, a fourth routing segment, and a fourth connection pad connected in sequence, the third connection pad is connected to the first electrode of the compensation transistor, and the fourth connection pad is connected to the second electrode of the first reset transistor; The first routing segment extends in a direction approaching the adjacent second connection line and is located on a side of the third routing segment away from the fourth connection pad; in the second direction, the first routing segment is opposite to the third connection pad, the second routing segment is opposite to the third routing segment, and the fourth routing segment is opposite to the second connection pad; and the boundary between the second routing segment and the third routing segment is parallel, and the boundary between the second connection pad and the fourth routing segment is parallel.

4. The array substrate according to claim 3, wherein: In the second direction, the fourth routing segment is opposite to a portion of the second connection pad, and the fourth connection pad is opposite to another portion of the second connection pad; The orthographic projections of the second connection pad and the fourth connection pad on the reference plane are polygonal, and the boundaries between the second connection pad and the fourth connection pad are parallel. The reference plane is a plane determined by the first direction and the second direction.

5. The array substrate according to claim 3 or 4, wherein: The second routing segment includes a first sub-segment, a second sub-segment, and a third sub-segment connected in sequence, the first sub-segment is connected to the first routing segment, the third sub-segment is connected to the second connection pad, and the third sub-segment is farther away from the adjacent first data line than the first sub-segment; The third routing segment includes a fourth subsegment, a fifth subsegment, and a sixth subsegment connected in sequence, the fourth subsegment is connected to the third connection pad, the sixth subsegment is connected to the fourth routing segment, and the sixth subsegment is farther away from the adjacent first data line than the fourth subsegment; in the second direction, the first subsegment is opposite to the fourth subsegment, the second subsegment is opposite to the fifth subsegment, and the third subsegment is opposite to the sixth subsegment.

6. The array substrate according to any one of claims 3 to 5, wherein: At least a portion of a boundary between the first routing segment and the adjacent second connecting line is parallel.

7. The array substrate according to any one of claims 1 to 6, wherein: The orthographic projection of the boundary of the first connecting line close to the adjacent first data line on the reference plane coincides with the orthographic projection of the boundary of the second electrode of the connected compensation transistor close to the corresponding first data line on the reference plane, and the reference plane is a plane determined by the first direction and the second direction.

8. The array substrate according to any one of claims 1 to 7, wherein: The pixel circuit further includes: a driving transistor, wherein a control electrode of the driving transistor is connected to the first node, a first electrode of the driving transistor is connected to the third node, and a second electrode of the driving transistor is connected to the second node; a data writing transistor, wherein a control electrode of the data writing transistor is connected to the second scanning signal terminal, a first electrode of the data writing transistor is connected to the data signal terminal, and a second electrode of the data writing transistor is connected to the third node; a first enabling transistor, wherein a control electrode of the first enabling transistor is connected to the enabling signal terminal, a first electrode of the first enabling transistor is connected to the first voltage signal terminal, and a second electrode of the first enabling transistor is connected to the third node; a second enabling transistor, wherein a control electrode of the second enabling transistor is connected to the enabling signal terminal, a first electrode of the second enabling transistor is connected to the second node, and a second electrode of the second enabling transistor is connected to a fourth node; a second reset transistor, wherein a control electrode of the second reset transistor is connected to the second reset signal terminal, a first electrode of the second reset transistor is connected to the second initialization signal terminal, and a second electrode of the second reset transistor is connected to the fourth node; A third reset transistor, wherein the control electrode of the third reset transistor is connected to the second reset signal terminal, the first electrode of the third reset transistor is connected to the third initialization signal terminal, and the second electrode of the third reset transistor is connected to the first reset signal terminal. Three-node connection.

9. The array substrate according to claim 8, comprising a first active layer, wherein the first active layer comprises: a plurality of first active patterns, including channels, first electrodes, and second electrodes of the driving transistor, the data writing transistor, the first enabling transistor, the second enabling transistor, and the second reset transistor; a plurality of second active patterns, comprising a channel, a first electrode, and a second electrode of the first reset transistor; the plurality of first active patterns and the plurality of second active patterns are alternately arranged in the first direction, and the second active patterns are farther away from the corresponding first data lines than the corresponding first active patterns; A plurality of third active patterns include a channel, a first electrode, and a second electrode of the third reset transistor; along the second direction, the third active patterns are located on a side of the channel of the second reset transistor close to the channel of the first enable transistor.

10. The array substrate according to any one of claims 1 to 9, further comprising: a first scanning signal line extending along the second direction; and an orthographic projection of the first scanning signal line on a reference plane overlaps with an orthographic projection of the channel of the compensation transistor on the reference plane, wherein the reference plane is a plane defined by the first direction and the second direction; The orthographic projections of the first scanning signal line and the first connecting line on the reference plane overlap, and a boundary of the overlapping portion is parallel to the first direction or the second direction.

11. The array substrate according to claim 10, wherein: The first scan signal line includes a plurality of first scan routing segments connected in sequence, the first scan routing segment includes a first scan sub-segment and a second scan sub-segment connected in sequence, the first scan sub-segment overlaps with an orthographic projection of the first connection line on the reference plane, and the second scan sub-segment overlaps with an orthographic projection of a channel of the compensation transistor on the reference plane; Along the first direction, the width of the first scanning subsegment is smaller than the width of the second scanning subsegment, and a boundary connecting the second scanning subsegment and the first scanning subsegment is parallel to a boundary opposite to the first connection line.

12. The array substrate according to claim 10, wherein: The first scan signal line includes a plurality of first scan routing segments connected in sequence, the first scan routing segment includes a third scan sub-segment, a fourth scan sub-segment, and a fifth scan sub-segment connected in sequence, the fourth scan sub-segment overlaps with an orthographic projection of the first connection line on the reference plane, and the fifth scan sub-segment overlaps with an orthographic projection of a channel of the compensation transistor on the reference plane; Along the first direction, the width of the third scanning sub-segment is smaller than the width of the fourth scanning sub-segment, and the width of the fourth scanning sub-segment is smaller than the width of the fifth scanning sub-segment.

13. The array substrate according to claim 12, wherein: The boundary connecting the fourth scanning sub-segment and the third scanning sub-segment is parallel to the boundary opposite to the first connecting line; and / or the boundary connecting the fifth scanning sub-segment and the fourth scanning sub-segment is parallel to the boundary opposite to the first connecting line.

14. The array substrate according to any one of claims 10 to 13, comprising: The second active layer includes a plurality of fourth active patterns, wherein the fourth active patterns include the channel of the compensation transistor, first and second poles; The second gate conductive layer and the third gate conductive layer are arranged on opposite sides of the second active layer; the first scanning signal line is located in the second gate conductive layer and / or the third gate conductive layer.

15. The array substrate according to any one of claims 1 to 14, wherein: The pixel circuit further includes a driving transistor and a data writing transistor, wherein a first electrode of the driving transistor is connected to the third node, and a second electrode of the driving transistor is connected to the second node; a first electrode of the data writing transistor is connected to the first data line, and a second electrode of the data writing transistor is connected to the third node; The array substrate further includes: a second scanning signal line extending along the second direction; The orthographic projection of the second scanning signal line on the reference plane overlaps with the orthographic projection of the channel of the data writing transistor on the reference plane, and overlaps with the orthographic projection of the second electrode of the compensation transistor on the reference plane; the reference plane is a plane determined by the first direction and the second direction; The second scanning signal line includes a second scanning routing segment and a widened portion. Along the first direction, the widened portion is located on one side of the second scanning routing segment, and the orthographic projection of the widened portion on the reference plane is located within the range of the orthographic projection of the second electrode of the compensation transistor on the reference plane.

16. The array substrate according to any one of claims 1 to 15, further comprising: a plurality of first power signal lines, wherein an orthographic projection of the first connecting line on the reference plane is located within a range of the orthographic projections of the plurality of first power signal lines on the reference plane; The reference plane is a plane determined by the first direction and the second direction.

17. The array substrate according to claim 16, wherein: The plurality of first power signal lines include: a plurality of first power sub-lines extending along the first direction and arranged at intervals in the second direction; a plurality of second power sub-lines extending along the first direction and arranged at intervals in the second direction; the second power sub-lines are connected to the first voltage signal terminal of the pixel circuit; A plurality of third power sub-lines extend along the second direction and are arranged at intervals in the first direction; a first power sub-line is connected to a second power sub-line through a third power sub-line; a portion of the orthographic projection of the first connecting line on the reference plane is located within the range of the orthographic projection of the first power sub-line or the second power sub-line on the reference plane, and another portion is located within the range of the orthographic projection of the third power sub-line on the reference plane.

18. The array substrate according to claim 17, comprising: a first source-drain conductive layer, wherein the first connecting line and the second connecting line are located in the first source-drain conductive layer; a second source-drain conductive layer, wherein the third power sub-line is located in the second source-drain conductive layer; A third source-drain conductive layer, wherein the first power sub-line and the second power sub-line are located in the third source-drain conductive layer.

19. A display panel comprising The array substrate according to any one of claims 1 to 18; The light emitting device is arranged on the array substrate.

20. A display device comprising: The display panel according to claim 19; A circuit board is connected to the display panel.

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