ESD protection device and manufacturing method therefor

Abstract

The present invention relates to an ESD protection device and a manufacturing method therefor. The ESD protection device comprises: a P-type substrate; an N-type region, located above at least part of the P-type substrate; a P-type well region, located on the N-type region; an insulation structure, located on the side of the N-type region and the side of the P-type well region, wherein the bottom depth of the insulation structure is deeper than that of the N-type region; and a conductive structure, wherein at least part of the insulation structure is located between the conductive structure and a transistor body structure, the transistor body structure comprises the P-type well region, the N-type region, and the portion of the P-type substrate below the N-type region, and the bottom of the conductive structure is connected to the P-type substrate. The top of the conductive structure is used for grounding, and the top of the P-type well region is used for connection to an ESD port. In the present invention, the occupied chip area is small.

Description

ESD protection device and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to application number 202410202696.X, filing date February 23, 2024, invention name “ESD protection device and manufacturing method thereof,” and incorporates the contents of that invention herein in its entirety by reference for all purposes. Technical Field

[0003] The present invention relates to the field of semiconductor manufacturing, in particular to an ESD protection device and a method for manufacturing the ESD protection device. Background Art

[0004] ESD (Electro-Static Discharge) protection is an important part of IC (Integrated Circuit) design. ESD protection devices play a role in protecting internal circuits from damage by static electricity.

[0005] ESD protection is limited by the current discharge capacity of the ESD protection device per unit area. It's generally believed that the greater the current a device can discharge per unit area, the stronger its ESD protection capability. Lateral PNP transistors, a common ESD device in IC circuits, have relatively weak current discharge capacity per unit area. Furthermore, if a lateral PNP transistor used as an ESD device needs to meet higher withstand voltage requirements, the device's area must be larger. Summary of the Invention

[0006] Based on this, it is necessary to provide an ESD protection device that occupies a smaller chip area and a manufacturing method thereof.

[0007] An ESD protection device comprises: a P-type substrate; an N-type region located above at least a portion of the P-type substrate; a P-type well region located on the N-type region; an insulating structure located on the sides of the N-type region and the P-type well region, with the bottom depth of the insulating structure being deeper than the bottom depth of the N-type region; a conductive structure, at least a portion of the insulating structure being located between the conductive structure and a transistor main structure, the transistor main structure comprising the P-type well region, the N-type region, and a portion of the P-type substrate below the N-type region, the bottom of the conductive structure being connected to the P-type substrate; wherein the top of the conductive structure is used for grounding, and the top of the P-type well region is used for connecting to an ESD port.

[0008] This ESD protection device optimizes the current discharge path from a horizontal to a vertical path, reducing the device area. Furthermore, to increase the withstand voltage, simply increase the depth of the N-type region and the insulation structure, eliminating the need to increase the device area as the operating voltage increases. Consequently, this ESD protection device occupies a relatively small chip area.

[0009] In one embodiment, the insulating structure is formed on the sidewall of the trench, the conductive structure is formed in the trench, and the insulating structure is located on both sides of the conductive structure.

[0010] In one embodiment, the trench is a closed surrounding structure in the laterally direction, and the N-type region and the P-type well region are laterally surrounded by the inner circle of the insulating structure.

[0011] In one embodiment, the ESD protection device further includes a P-type buffer zone, which is located below the conductive structure and between the P-type substrate and the conductive structure. The doping concentration of the P-type buffer zone is greater than the doping concentration of the P-type substrate.

[0012] In one embodiment, the ESD protection device further includes a first P-type doped region, which is located in the P-type buffer region and directly contacts the bottom of the conductive structure, and the doping concentration of the first P-type doped region is greater than the doping concentration of the P-type buffer region.

[0013] In one embodiment, the ESD protection device further includes a second P-type doped region located on top of the P-type well region, the doping concentration of the second P-type doped region is greater than the doping concentration of the P-type well region, and the P-type well region is connected to the ESD port through the second P-type doped region.

[0014] A method for manufacturing an ESD protection device comprises: obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate; the P-type well region being located on the N-type region, with at least a portion of the P-type substrate being located below the N-type region; forming trenches on the side surfaces of the N-type region and the P-type well region; the bottom of the trench being deeper than the bottom of the N-type region; forming an insulating structure on the inner wall of the trench; forming a conductive structure in the trench, with at least a portion of the insulating structure being located between the conductive structure and a transistor main structure, the transistor main structure comprising the P-type well region, the N-type region, and a portion of the P-type substrate below the N-type region, the bottom of the conductive structure being connected to the P-type substrate; wherein the top of the conductive structure is used for grounding, and the top of the P-type well region is used for connecting to an ESD port.

[0015] The above-described method for manufacturing an ESD protection device provides a vertical current discharge path for the resulting ESD protection device, reducing the device area. Furthermore, to increase the withstand voltage, simply increase the depth of the N-type region and the depth of the insulation structure, eliminating the need to increase the device area as the operating voltage increases. Consequently, the ESD protection device occupies a relatively small chip area.

[0016] In one embodiment, the step of obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate includes: forming the N-type region in the P-type substrate; forming an epitaxial layer on the P-type substrate; and forming the P-type well region in the epitaxial layer.

[0017] In one embodiment, the step of forming trenches on the side of the N-type region and the side of the P-type well region includes: forming a shallow trench isolation structure, the bottom of the shallow trench isolation structure extends into the P-type well region, and at least a portion of the top of the P-type well region directly above the N-type region is not formed with the shallow trench isolation structure and is thus exposed; forming a patterned hard mask layer on the shallow trench isolation structure and the P-type well region; using the hard mask layer as an etching barrier layer, etching the shallow trench isolation structure, and continuing to etch the P-type well region and the N-type region downward to form the trench.

[0018] In one embodiment, before the step of forming a conductive structure in the trench, the step further includes: forming a P-type buffer zone in the P-type substrate below the trench by ion implantation, wherein the doping concentration of the P-type buffer zone is greater than the doping concentration of the P-type substrate.

[0019] In one embodiment, before the step of forming a conductive structure in the groove, the step further includes: forming a first P-type doping region in direct contact with the bottom of the conductive structure in the P-type buffer region by ion implantation, the doping concentration of the first P-type doping region being greater than the doping concentration of the P-type buffer region.

[0020] In one embodiment, after the step of forming the conductive structure, the method further includes: removing the hard mask layer; forming a second P-type doping region on top of the P-type well region, wherein the doping concentration of the second P-type doping region is greater than the doping concentration of the P-type well region, and the P-type well region is connected to the ESD port through the second P-type doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0022] FIG1 is a schematic structural diagram of an ESD protection device according to an embodiment of the present application;

[0023] FIG2a is a top view of the groove in an embodiment in which the groove 131 is in a square shape in the transverse direction, and FIG2b is a top view of the groove in an embodiment in which the groove 131 is in a circular shape in the transverse direction;

[0024] FIG3 a is a top view of the insulating structure 140 and the conductive structure 150 in an embodiment in which the trench 131 is in a box shape in the transverse direction; FIG3 b is a top view of the insulating structure 140 and the conductive structure 150 in an embodiment in which the trench 131 is in a ring shape in the transverse direction;

[0025] FIG4 is a circuit diagram of an ESD protection device in an embodiment of the present application;

[0026] 5 is a flow chart of a method for manufacturing an ESD protection device according to an embodiment of the present application;

[0027] FIG6 is a flowchart of sub-steps of step S510 in one embodiment of the present application;

[0028] 7a to 7h are schematic cross-sectional views of the device during the process of manufacturing the ESD protection device using the method shown in FIG5 ;

[0029] FIG8 is a flowchart of sub-steps of step S520 in an embodiment of the present application. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings of the present invention.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0036] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0037] This application proposes a new ESD protection device, which optimizes the current discharge path of the ESD protection device from horizontal to vertical through a trench process, reducing the device area. The device area will not increase with the increase of the operating voltage. Only the depth of the N-type region and the depth of the insulation structure need to be adjusted to meet the voltage resistance requirements, thereby improving the ESD device's current discharge capacity and electrostatic protection capability.

[0038] FIG1 is a schematic diagram of the structure of an ESD protection device in one embodiment of the present application. The ESD protection device shown in FIG1 is bilaterally symmetrical, so some structures are only numbered on one side. In the embodiment shown in FIG1 , the ESD protection device includes a P-type substrate 110, an N-type region 122, a P-type well region 132, an insulating structure 140, and a conductive structure 150. A portion of the structure of the P-type substrate 110 is located below the N-type region 122. The P-type well region 132 is located on the N-type region 122. The insulating structure 140 is located on the side of the N-type region 122 and the side of the P-type well region 132, and the bottom depth of the insulating structure 140 is deeper than the bottom depth of the N-type region 122, that is, the depth of the insulating structure 140 extending into the P-type substrate 110 is deeper than the depth of the N-type region 122 extending into the P-type substrate 110. The P-type well region 132, the N-type region 122, and a portion of the P-type substrate 110 below the N-type region 122 form the transistor main structure. At least a portion of the insulating structure 140 is located between the conductive structure 150 and the transistor main structure, blocking the lateral current flow of the transistor main structure. This allows the current in the transistor main structure to flow vertically along the P-type well region 132, the N-type region 122, and the P-type substrate 110, then bypass the insulating structure 140 and flow from the P-type substrate 110 into the conductive structure 150, as indicated by the arrows in FIG1 . The bottom of the conductive structure 150 is connected to the P-type substrate 110. The top of the conductive structure 150 is used for grounding (GND), that is, for connecting to the cathode electrode; the top of the P-type well region 132 is used for connecting to the ESD port, that is, for connecting to the anode electrode.

[0039] When an electrostatic surge arrives at the ESD port, the PNP transistor composed of the P-type well region 132, the N-type region 122, and the P-type substrate 110 is turned on under a sufficiently large electrostatic voltage. The electrostatic surge at the ESD port passes through the P-type well region 132, the N-type region 122, and the P-type substrate 110, then flows into the conductive structure 150, and finally reaches GND to complete the electrostatic discharge.

[0040] The aforementioned ESD protection device optimizes the current discharge path from a horizontal to a vertical orientation, reducing the device area. Furthermore, to increase the withstand voltage, simply increase the depth of the N-type region 122 and the depth of the insulation structure 140, eliminating the need to increase the device area as the operating voltage increases. Consequently, the ESD protection device occupies a relatively small chip area.

[0041] In one embodiment of the present application, the insulating structure 140 is formed on the sidewall of the trench, the conductive structure 150 is formed in the trench, and the insulating structure 140 is located on both sides of the conductive structure 150 .

[0042] In one embodiment of the present application, the trench is a closed, enclosing structure in the transverse direction, with the N-type region 122 and the P-type well region 132 laterally surrounded by the inner ring of the insulating structure 140. Figure 2a is a top view of the trench in an embodiment in which the trench 131 is a square in the transverse direction, and Figure 2b is a top view of the trench in an embodiment in which the trench 131 is a circular in the transverse direction. In other embodiments of the present application, the trench 131 may also be a closed, enclosing structure in other shapes, such as an elliptical ring or a racetrack shape. Figure 3a is a top view of the insulating structure 140 and the conductive structure 150 in an embodiment in which the trench 131 is a square in the transverse direction, and Figure 3b is a top view of the insulating structure 140 and the conductive structure 150 in an embodiment in which the trench 131 is a circular in the transverse direction.

[0043] In one embodiment of the present application, the ESD protection device further includes a P-type buffer region 136. The P-type buffer region 136 is located below the conductive structure 150 and between the P-type substrate 110 and the conductive structure 150. The doping concentration of the P-type buffer region 136 is greater than that of the P-type substrate 110, thereby reducing on-resistance and improving current discharge capability. In the embodiment shown in FIG1 , the P-type buffer region 136 extends laterally below the insulating structure 140.

[0044] In one embodiment of the present application, the ESD protection device further includes a first P-type doped region 138. The first P-type doped region 138 is located in the P-type buffer region 136 and is in direct contact with the bottom of the conductive structure 150. The doping concentration of the first P-type doped region 138 is greater than the doping concentration of the P-type buffer region 136, thereby reducing contact resistance.

[0045] In one embodiment of the present application, the ESD protection device further includes a second P-type doped region 134 located on top of the P-type well region 132. The doping concentration of the second P-type doped region 134 is greater than that of the P-type well region 132, thereby reducing contact resistance. The P-type well region 132 is connected to the ESD port via the second P-type doped region 134.

[0046] FIG4 is a schematic circuit diagram of an ESD protection device according to one embodiment of the present application. The P-type well region 132 serves as the emitter of the PNP transistor, the N-type region 122 serves as the floating base of the PNP transistor, and the P-type substrate 110 and the P-type buffer 136 serve as the collector of the PNP transistor. When an electrostatic surge is applied to the ESD port, the PNP transistor conducts under a sufficiently high electrostatic voltage. The electrostatic surge at the ESD port flows into the conductive structure 150 as shown by the arrow in FIG1 , and then reaches GND, completing the electrostatic discharge.

[0047] In some embodiments of the present application, the conductive structure 150 may be made of polysilicon, or metal or alloy. In one embodiment of the present application, the insulating structure 140 is made of silicon oxide, such as silicon dioxide.

[0048] The present application accordingly provides a method for manufacturing an ESD protection device, which is used to manufacture the ESD protection device described in any of the above embodiments. FIG5 is a flow chart of the method for manufacturing an ESD protection device in an embodiment of the present application, comprising the following steps:

[0049] S510 , obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate.

[0050] The P-type well region 132 is located on the N-type region 122 , and at least a portion of the P-type substrate 110 is located below the N-type region 122 .

[0051] Referring to FIG. 6 , in one embodiment of the present application, step S510 includes:

[0052] S512, forming an N-type region in the P-type substrate.

[0053] Referring to FIG. 7 a , in one embodiment of the present application, a pad oxide layer (PAD Oxide) 142 can be first formed on the surface of the P-type substrate 110 of the wafer by thermal oxidation, and then an N-type buried layer (N-bury) is formed in the P-type substrate 110 by patterning (e.g., photolithography) and ion implantation (implanting N-type ions), and a well is formed to obtain an N-type region 122.

[0054] S514, forming an epitaxial layer on the P-type substrate.

[0055] In one embodiment of the present application, after the pad oxide layer 142 is removed, an epitaxial layer is grown on the P-type substrate 110 and the N-type region 122 .

[0056] S516 , forming a P-type well region in the epitaxial layer.

[0057] 7 b , a P-type well region (P-Well) 132 is formed in the epitaxial layer on the N-type region 122 by patterning (eg, photolithography) and ion implantation (implanting P-type ions) on the epitaxial layer.

[0058] At this point, step S510 is completed and the process proceeds to step S520.

[0059] S520 , forming trenches on side surfaces of the N-type region and the P-type well region.

[0060] The bottom of the trench is deeper than the bottom of the N-type region.

[0061] Referring to FIG. 8 , in one embodiment of the present application, step S520 includes:

[0062] S522 , forming a shallow trench isolation structure.

[0063] The front side of the wafer is patterned (e.g., by photolithography and etching) to form shallow trenches, and then an oxide layer is deposited to form shallow trench isolation structures 144 (see FIG7 c ). The bottom of shallow trench isolation structures 144 extends into P-type well region 132, while at least a portion of the top of P-type well region 132 directly above N-type region 122 is not covered by shallow trench isolation structures 144, thereby exposing P-type well region 132 on the front side of the wafer.

[0064] S524 , forming a patterned hard mask layer on the P-type well region.

[0065] In one embodiment of the present application, silicon nitride is deposited on the front side of the wafer (i.e., on the P-type well region 132 and shallow trench isolation structure 144), and then a hard mask layer 152 is formed through patterning (photolithography and etching), as shown in FIG7d. The window exposed by the hard mask layer 152 is located on the shallow trench isolation structure 144. In one embodiment of the present application, before depositing silicon nitride, a step of forming a PAD oxide on the front side of the wafer is also included, and the silicon nitride is deposited on the PAD oxide.

[0066] S526 , using the hard mask layer as an etching barrier layer, etching to form a trench.

[0067] After etching through the shallow trench isolation structure 144 , the P-type well region 132 and the N-type region 122 are further etched downward to form a trench 131 , as shown in FIG. 7 e .

[0068] At this point, step S520 is completed and the process proceeds to step S530.

[0069] S530 , forming an insulating structure on the inner wall of the trench.

[0070] In one embodiment of the present application, an oxide layer is deposited on the front side of the wafer, and an insulating structure 140 is formed on the inner wall of the trench 131. In one embodiment of the present application, after the oxide layer is deposited (see FIG. 7f ), the oxide layer at the bottom of the trench 131 is removed by etching, exposing the P-type substrate 110 at the bottom of the trench 131 (see FIG. 7g ).

[0071] S540 , forming a conductive structure in the trench.

[0072] At least a portion of the insulating structure 140 is located between the conductive structure 150 and the transistor main structure. The transistor main structure includes the P-type well region 132, the N-type region 122, and a portion of the P-type substrate 110 below the N-type region 122. The bottom of the conductive structure 150 is connected to the P-type substrate 110. The top of the conductive structure 150 is used for grounding, and the top of the P-type well region 132 is used for connecting to the ESD port.

[0073] In one embodiment of the present application, the conductive structure 150 can be made of polysilicon, or alternatively, a metal or alloy. After the conductive structure 150 is filled into the trench 131, excess conductive structure 150 on the wafer surface can be removed by chemical mechanical polishing (CMP). In one embodiment of the present application, CMP is performed so that the upper surface of the conductive structure 150 is slightly lower than the upper surface of the hard mask layer 152.

[0074] The above-described method for manufacturing an ESD protection device provides a vertical current discharge path, reducing the device area. Furthermore, to increase the withstand voltage, simply increase the depth of the N-type region 122 and the depth of the insulating structure 140, eliminating the need to increase the device area as the operating voltage increases. Consequently, the ESD protection device occupies a relatively small chip area.

[0075] In one embodiment of the present application, after step S530 and before step S540, a step is further included to form a P-type buffer region 136 in the P-type substrate 110 below the trench 131 by ion implantation (implanting P-type ions). The doping concentration of the P-type buffer region 136 is greater than the doping concentration of the P-type substrate 110.

[0076] In one embodiment of the present application, after ion implantation of the P-type buffer region 136, a further step is included to form a first P-type doping region 138 in the P-type buffer region 136, directly contacting the bottom of the conductive structure 150, by ion implantation (see FIG. 7h ). The doping concentration of the first P-type doping region 138 is greater than that of the P-type buffer region 136.

[0077] In one embodiment of the present application, after step S540, the step of removing the hard mask layer 152 is also included. Specifically, it can be removed by etching. After removing the hard mask layer 152, the step of forming a second P-type doping region 134 on the top of the P-type well region 132 is also included. Specifically, the second P-type doping region 134 can be formed by photolithography and ion implantation (injecting P-type ions). The doping concentration of the second P-type doping region 134 is greater than the doping concentration of the P-type well region 132, which plays a role in reducing the contact resistance. The P-type well region 132 is connected to the ESD port through the second P-type doping region 134. The structure of the ESD protection device after the second P-type doping region 134 is formed can be referred to Figure 1.

[0078] The manufacturing method of the ESD protection device of the present application and the ESD protection device are based on the same inventive concept. For matters not specifically described in the manufacturing method of the ESD protection device, please refer to the above introduction to the ESD protection device.

[0079] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0080] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An ESD protection device, characterized in that: include: P-type substrate; an N-type region located above at least a portion of the P-type substrate; A P-type well region, located on the N-type region; an insulating structure, located on a side surface of the N-type region and a side surface of the P-type well region, wherein a bottom depth of the insulating structure is deeper than a bottom depth of the N-type region; a conductive structure, wherein at least a portion of the insulating structure is located between the conductive structure and a transistor main structure, the transistor main structure including the P-type well region, the N-type region, and a portion of the P-type substrate below the N-type region, and a bottom of the conductive structure is connected to the P-type substrate; The top of the conductive structure is used for grounding, and the top of the P-type well region is used for connecting to an ESD port.

2. The ESD protection device according to claim 1, wherein: The insulating structure is formed on the sidewall of the trench, the conductive structure is formed in the trench, and the insulating structure is located on both sides of the conductive structure.

3. The ESD protection device according to claim 2, characterized in that: The trench is a closed surrounding structure in the lateral direction, and the N-type region and the P-type well region are surrounded by the inner circle of the insulating structure in the lateral direction.

4. The ESD protection device according to claim 1, wherein: It also includes a P-type buffer zone, which is located below the conductive structure and between the P-type substrate and the conductive structure. The doping concentration of the P-type buffer zone is greater than the doping concentration of the P-type substrate.

5. The ESD protection device according to claim 4, characterized in that: It also includes a first P-type doping region, which is located in the P-type buffer region and directly contacts the bottom of the conductive structure. The doping concentration of the first P-type doping region is greater than the doping concentration of the P-type buffer region.

6. The ESD protection device according to claim 1, wherein: It also includes a second P-type doping region located on the top of the P-type well region, the doping concentration of the second P-type doping region is greater than the doping concentration of the P-type well region, and the P-type well region is connected to the ESD port through the second P-type doping region.

7. A method for manufacturing an ESD protection device, characterized in that: include: Obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate; The P-type well region is located on the N-type region, and at least a portion of the P-type substrate is located below the N-type region; forming trenches on the side surfaces of the N-type region and the side surfaces of the P-type well region; wherein the bottom of the trenches is deeper than the bottom of the N-type region; forming an insulating structure on an inner wall of the trench; forming a conductive structure in the trench, wherein at least a portion of the insulating structure is located between the conductive structure and a transistor main structure, the transistor main structure comprising the P-type well region, the N-type region, and a portion of a P-type substrate below the N-type region, and a bottom portion of the conductive structure is connected to the P-type substrate; The top of the conductive structure is used for grounding, and the top of the P-type well region is used for connecting to an ESD port.

8. The method for manufacturing an ESD protection device according to claim 7, wherein: The step of obtaining a wafer having an N-type region and a P-type well region formed on a P-type substrate comprises: forming the N-type region in the P-type substrate; forming an epitaxial layer on the P-type substrate; The P-type well region is formed in the epitaxial layer.

9. The method for manufacturing an ESD protection device according to claim 7, wherein: The step of forming trenches on the side surfaces of the N-type region and the side surfaces of the P-type well region comprises: forming a shallow trench isolation structure, wherein the bottom of the shallow trench isolation structure extends into the P-type well region, and the shallow trench isolation structure is not formed on the top of at least a portion of the P-type well region directly above the N-type region; forming a patterned hard mask layer on the P-type well region; The shallow trench isolation structure is etched using the hard mask layer as an etching barrier, and the P-type well region and the N-type region are further etched downward to form the trench.

10. The method for manufacturing an ESD protection device according to claim 8, wherein: Before the step of forming a conductive structure in the trench, the method further includes: A P-type buffer zone is formed in the P-type substrate below the trench by ion implantation, wherein the doping concentration of the P-type buffer zone is greater than the doping concentration of the P-type substrate.

11. The method for manufacturing an ESD protection device according to claim 10, wherein: Before the step of forming a conductive structure in the trench, the method further includes: A first P-type doping region directly contacting the bottom of the conductive structure is formed in the P-type buffer region by ion implantation, wherein the doping concentration of the first P-type doping region is greater than the doping concentration of the P-type buffer region.

12. The method for manufacturing an ESD protection device according to claim 8, wherein: After the step of forming the conductive structure, the method further includes: removing the hard mask layer; A second P-type doping region is formed on the top of the P-type well region. The doping concentration of the second P-type doping region is greater than the doping concentration of the P-type well region. The P-type well region is connected to the ESD port through the second P-type doping region.

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