Use of variable capacitor diodes for impedance matching

Abstract

Disclosed herein are methods, systems, and apparatuses that involve variable capacitor diodes for impedance matching. In some embodiments, an RF match circuit for impedance matching in a semiconductor fabrication chamber may comprise a variable reactance comprising a variable capacitor diode. A voltage associated with the variable capacitor diode is modified to cause a change in a width of a depletion region of the variable capacitor diode based at least in part on an impedance of a plasma load associated with plasma within at least one station of the semiconductor fabrication chamber to perform impedance matching between an RF source and the plasma load.

Description

USE OF VARIABLE CAPACITOR DIODES FOR IMPEDANCE MATCHINGINCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claim benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0002] Many fabrication processes, such as plasma-based deposition or etch processes, utilize an RF signal to provide plasma in a process station. However, due to impedance associated with the plasma in the process station, there may be a mismatch between the impedance at the process station and the impedance at the RF generator. This impedance mismatch may cause reflected power, which can reduce the effectiveness of the fabrication process.

[0003] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] Disclosed herein are techniques, systems, and apparatuses that involve use of variable capacitor diodes for impedance matching. In some embodiments, an RF match circuit for impedance matching in a semiconductor fabrication chamber may comprise a variable reactance comprising a variable capacitor diode, wherein a voltage associated with the variable capacitor diode is modified to cause a change in a width of a depletion region of the variable capacitor diode based at least in part on an impedance of a plasma load associated with plasma within at least one station of the semiconductor fabrication chamber to perform impedance matching between an RF source and the plasma load.

[0005] In some examples, the variable capacitor diode is configured to have a variable capacitance within at least a 100:1 ratio range.

[0006] In some examples, the variable capacitor diode has a breakdown voltage of at least 1000 V.

[0007] In some examples, the variable capacitor diode comprises a semiconductor that is at least one of: gallium oxide, diamond or gallium nitride.

[0008] In some examples, the variable reactance does not include any mechanical reactances.

[0009] In some examples, the impedance matching is performed in less than 10 milliseconds.

[0010] In some examples, the variable reactance operates in conjunction with circuitry configured to modify a frequency of the RF source to perform the impedance matching.

[0011] In some examples, the variable reactance further comprises a second variable capacitor diode. In some examples, the variable capacitor diode and the second variable capacitor diode each rectify half of an alternating current (AC) signal.

[0012] In some embodiments, a semiconductor fabrication chamber comprises: at least one station configured to receive a substrate undergoing a plasma-based fabrication process; an RF source; and an RF match circuit configured to match an impedance at the RF source and an impedance of a plasma load associated with plasma in the at least one station, wherein the RF match circuit comprises: a variable reactance comprising a variable capacitor diode, wherein a voltage associated with the variable capacitor diode is modified to cause a change in a width of a depletion region of the variable capacitor diode based at least in part on the impedance of the plasma load.

[0013] In some examples, the semiconductor fabrication chamber further comprises a controller configured to determine a modified voltage associated with the variable capacitor diode. In some examples, the controller is configured to utilize a model-predictive control (MPC) algorithm to determine the modified voltage. In some examples, the MPC algorithm operates in conjunction with a proportional-integral-derivative (PID) control algorithm to determine the modified voltage. In some examples, the MPC algorithm generates predicted voltages over a prediction horizon based on a target impedance.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a schematic diagram of a portion of a system for performing impedance matching for a process chamber in accordance with some embodiments.

[0015] FIG. 2 is a plot that illustrates example tuning times for a system that utilizes a variable capacitor diode for impedance matching in accordance with some embodiments.

[0016] FIGS. 3A and 3B are schematic diagrams of portions of example systems for performing impedance matching using a variable capacitor diode in accordance with some embodiments.

[0017] FIG. 4 is a plot of example predictions of a model-based control algorithm in accordance with some embodiments.

[0018] FIG. 5 is a flowchart of an example process for performing impedance matching using a variable capacitor diode in accordance with some embodiments.

[0019] FIG. 6 presents an example computer system that may be employed to implement certain embodiments described herein.DETAILED DESCRIPTION

[0020] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

[0021] Many fabrication processes, such as plasma-based deposition or etch processes, utilize a radio frequency (RF) signal to provide plasma in a process station. However, due to impedance associated with the plasma in the process station, there may be a mismatch between the load impedance at the process station and the source impedance at the RF generator. This impedance mismatch may cause reflected power, which can reduce the effectiveness of the fabrication process.

[0022] Impedance matching is typically performed by changing the reactance associated with the RF input network, which may be done by changing inductance, capacitance, or a frequency of the input signal. Reactance is the imaginary component of impedance. Note that, as used herein, the input network generally refers to the RF signal generator and match circuitry, where the match circuitry is configured to modify the reactance associated with the input network (generally referred to herein as “input impedance” or “source impedance”). Conventional techniques may perform impedance matching by actuating a variable capacitor of the matchcircuitry such that the capacitance changes such that the load impedance at the process station and the impedance of the RF input network are matched. Because changing the capacitance in turn changes the reactance (i.e., the imaginary part of impedance) of the input network, the impedances between the load at the process station(s) and the source impedance at the RF input network are matched. The variable capacitor is sometimes referred to as “a variable reactance” element, because modifying the capacitance of the variable capacitor in turn changes the reactance. For example, the capacitance may be changed such that the complex conjugate of the source impedance is substantially similar to, close to, or matches the load impedance.

[0023] The variable capacitor of the match circuitry is typically mechanically actuated such that the capacitance is changed by manual rotation. The actuation process with conventionally used variable capacitors may take tens of milliseconds, or even hundreds (e.g., 500, 600, etc.) of milliseconds. During the time the variable capacitor is being actuated (e.g., during the rotation time period), the delivered power to the station may be substantially reduced due to the reflected power, which may cause deposition processes to occur more slowly. By way of example, for an Atomic Layer Deposition (ALD) process, a given plasma on cycle may be 500 milliseconds. If mechanical actuation of a variable capacitor takes, e.g., 100 milliseconds, the actual plasma on time during a 500 millisecond cycle is only 80%. If mechanical actuation takes, e.g., 250 milliseconds, the actual plasma on time for a 500 millisecond cycle is only 50%. In other words, mechanical actuation of the variable capacitor for impedance matching may substantially reduce plasma on time, which affects wafer throughput.

[0024] Disclosed herein are techniques for performing impedance matching using a variable capacitor diode (sometimes also referred to as “a varactor diode”) that is part of a match circuit. The capacitance of a variable capacitor diode may be modified by changing a voltage applied to the variable capacitor diode. In some embodiments, impedance matching may be performed by applying voltage to the variable capacitor diode to thereby change the capacitance of the variable capacitor diode, e.g., based on the impedance of the plasma load in a plasma station operatively coupled to the match circuit. Due to the abruptness in capacitance change of the variable capacitor diode, impedance matching may be performed in less than 10 milliseconds (e.g., in 8 milliseconds, in 5 milliseconds, in 2 milliseconds, etc.). It should be understood that the variable capacitor diode may be considered a variable reactance component or a part of a variable reactance element, because the capacitance associated with the variable capacitor diode is modified by modifying the voltage applied. As described above, modification of the capacitance causes a change in reactance (i.e., the imaginary component of impedance).

[0025] A variable capacitor diode used for impedance matching as disclosed herein may comprise a semiconductor with a relatively high breakdown voltage (e.g., about 800 V, above 1000 V, above 1500 V, etc.) to enable use with the high RF powers provided by an RF generator. For example, the semiconductor may be gallium oxide, diamond, and / or gallium nitride.

[0026] Note that, in some embodiments, changing the frequency of the input RF signal may additionally be used in conjunction with a variable capacitor diode to perform impedance matching. In other words, the impedance may be changed both by changing frequency of the RF input signal as well as by changing capacitive reactance via the variable capacitor diode(s). For example, a variable capacitor diode that is part of a match circuit may be used to adjust the source impedance of the RF input network. Continuing with this example, frequency adjustments may be made to a frequency of a signal provided by an RF generator. Because the source impedance (and in particular, the source reactance) is dependent on frequency, changing the frequency of the input signal may be used to additionally perform impedance matching.

[0027] It should be understood that the techniques described herein for performing impedance matching using a variable capacitor diode may be performed using a process chamber with one process station, or a process chamber with multiple (e.g., two, four, eight, etc.) process stations. In instances in which a process chamber includes multiple process stations, there may be one match circuit for the multiple process stations. In some embodiments, each station may have its own match circuit, and, optionally there may be a system match circuit for the entire system, which may allow for variation from station to station and differing load impedances at each station. Note that each match circuit may have one or more variable capacitor diodes.

[0028] Additionally, it should be noted that, in some embodiments, a match circuit may include two variable capacitor diodes. In such embodiments, each variable capacitor diode may rectify half of an alternating circuit (AC) signal. Because each variable capacitor diode may rectify half of the AC signal, such a match circuit may be configured to handle high AC voltage swings.

[0029] FIG. 1 illustrates an example system for performing impedance matching using conventional techniques. As illustrated, an RF input 102 is provided via one or more RF generators. The RF input 102 may be at any suitable frequency or combination of frequencies. For example, a high frequency may be provided at, e.g., 13.56 MHz. As another example, alow frequency may be provided at, e.g., 400 kHz. RF input 102 may be conveyed to a process station or a set of process stations of a multi-station process chamber via RF output 104. A process station may be configured to perform plasma-based operations (e.g., plasma-enhanced chemical vapor deposition (PECVD), ALD, plasma-based etching operations, etc.). Due to plasma impedance in a process station, and / or changes in the plasma impedance, there may be a difference in impedance between RF input 102 (e.g., the source impedance) and RF output 104 (e.g., the load impedance). This difference in impedance may lead to reflected power. To minimize reflected power, a match circuit 106 may be used to change a reactance (e.g., the imaginary part of the impedance). In particular, match circuit 106 may utilize variable capacitor 108 to change the reactance of the input network (which includes RF input 102 and match network 106) to minimize reflected power by matching a load impedance at RF output 104 to the source impedance of the input network. The desired reactance of variable capacitor 108 to minimize the reflected power may be determined using phase / magnitude sensors 110. Phase / magnitude sensors 110 are configured to measure the phase and / or magnitude of the RF signal at RF input 102. Because the measured phase and / or magnitude may include both forward power and reflected power, the phase and / or magnitude may be indicative of the degree of reflected power, and in turn, the degree of impedance mismatch. The phase and / or magnitude may be sampled at any suitable sampling frequency. In conventional systems, variable capacitor 108 is a mechanical capacitor that must be moved (e.g., rotated) to affect a different capacitance to change the reactance. Physical rotation of variable capacitor 108 may take hundreds of milliseconds, or even up to 1 second. Because of the duration of time required to actuate variable capacitor 108, there are correspondingly long durations of time in which the delivered power to the one or more process stations are substantially less than what is provided at RF input 102, due to the reflected power. This reduces throughput of process wafers. Moreover, variations in delivered power may cause non-uniformity differences in thickness of film of substrates being processed.

[0030] Disclosed herein are RF match circuits and / or circuitry that utilize a variable reactance comprising a variable capacitor diode. Note that, the term “varactor diode” may be used interchangeably with “variable capacitor diode.” A voltage (sometimes referred to as “a reverse bias”, where the voltage is applied in a reverse direction) applied to the variable capacitor diode causes a change in a width of a depletion region of the variable capacitor diode, which in turn changes the capacitance associated with the variable capacitor diode. For example, applying a smaller reverse bias may cause a width of a depletion region (e.g. , betweenp-type and n-type regions) to narrow, which in turn causes capacitance to increase. Conversely, increasing the reverse bias applied may cause an increase in the width of the depletion region, which in turn causes capacitance to decrease. The voltage to be applied may be determined based at least in part on an impedance associated with a plasma load of plasma within at least one station of a fabrication chamber. For example, the voltage may be determined as one that minimizes an impedance mismatch between the load impedance and the source impedance associated with the RF input network. By determining the voltage applied to the variable capacitor diode, and in turn the capacitance associated with the variable capacitor diode based on the plasma load impedance, the RF match circuit may provide impedance matching with reactance changes actuated in less than 10 milliseconds, in less than 8 milliseconds, in less than 5 milliseconds, etc., or the like.

[0031] As disclosed herein, an RF match circuit, when used to provide impedance matching between an RF input network and one or more stations of a fabrication chamber, generally includes one or more variable capacitor diodes which have a breakdown voltage of greater than at least 1000 Volts, and can carry at least 50 Amps of current. Additionally, to provide impedance matching between the RF input network and a station of the fabrication chamber, a variable capacitor diode may ideally be able to provide a variable capacitance within at least a 100: 1 ratio range (e.g., where the largest possible capacitance is at least 100 times the smallest possible capacitance). The current requirements, breakdown voltage specification, and capacitance range specification may be met by utilizing one or more variable capacitor diodes that utilize a semiconductor having properties that allow these specifications to be met. For example, the breakdown voltage specification may be met based on a given semiconductor material having particular bandgap energies, which allow for higher breakdown voltages. Examples of semiconductors that may be utilized in a variable capacitor diode include diamond, gallium oxide, and / or gallium nitride.

[0032] FIG. 2 illustrates a histogram representing example RF tuning or impedance matching times for an example RF match circuit utilizing a variable capacitor diode. As illustrated, in some embodiments, impedance matching may be performed on the order of about 5 milliseconds. Tn some embodiments, impedance matching may be performed in less than about 10 milliseconds. In contrast, as described above, impedance matching utilizing a variable capacitor that is mechanically rotated may take hundreds of milliseconds.

[0033] In some embodiments, the voltage applied across a variable capacitor diode that causes a reactance / capacitance change of the variable capacitor diode may be controlled using a controller. The controller may receive information indicative of a phase angle and / or a magnitude of the RF signal, which may be indicative of delivered power and / or reflected power, and therefore, a degree of impedance mismatch. Based on the phase and / or magnitude measured, the controller may determine a modification to a reactance of the input network to be implemented by modifying a voltage applied to the variable capacitor diode. Based on the phase / magnitude information and a current state of the variable capacitor diode (e.g., a current voltage being applied, a current reactance / capacitance associated with the variable capacitor diode, etc.), the controller may determine the voltage to be applied to the variable capacitor diode to perform impedance matching to match the load impedance associated with the plasma in one or more process stations and the source impedance of the RF input network.

[0034] FIG. 3A illustrates an example system which includes a variable capacitor diode in a match circuit in accordance with some embodiments. Similar to what is shown in and described above in connection with FIG. 1, phase / magnitude measurement block 110 obtains phase angle and magnitude information associated with an RF signal input, which may be indicative of the delivered power and / or the reflected power. The phase angle and magnitude information, along with a current voltage across variable capacitor diode 308 of match circuit 306 are provided to a controller 310. Based on the phase angle and magnitude information, as well as the current voltage across variable capacitor diode 308, controller 310 may determine an updated voltage to be applied across variable capacitor diode 308. The updated voltage may be one which causes variable capacitor diode 308 to have a capacitance that yields an impedance match between the plasma load and the source impedance at the RF input network (which includes the RF generator and match circuit 306). Note that the phase angle and magnitude information may be used to determine how changes in the capacitance of variable capacitor diode 308 affect power delivery. For example, the phase angle and magnitude information may be indicative of a degree of reflected power, and therefore the degree of impedance mismatch, and the controller may determine changes in the capacitance of the variable capacitor diode 308 that will minimize the impedance mismatch, and in turn, reduce the phase angle difference between the transmitted signal and the reflected signal. Because the impedance of the plasma load may change, e.g., during performance of a fabrication process, controller 310 may dynamically determine updated voltages to be applied to variable capacitor diode 308 to responsively perform impedance matching.

[0035] Note that, in some embodiments, an RF match circuit may include two variable capacitor diodes, which each rectify half of an AC signal. This may allow protection against high AC voltage swings.

[0036] An example of a match circuit that includes two variable capacitor diodes is shown in FIG. 3B, which includes two variable capacitor diodes 352 and 354. Capacitors 356 and 358 block DC leakage current. Note that the example shown in FIG. 3B is an LC tank circuit, which includes both an inductive component and a capacitive component. It should be noted that, in some embodiments, a match circuit may include inductances only, capacitances only, or any combination thereof.

[0037] In some implementations, a controller (e.g., controller 310 of FIG. 3A) which determines a voltage to be applied to a variable capacitor diode to perform impedance matching may utilize a proportional-integral-derivative (PID) control algorithm. Additionally or alternatively, in some embodiments, a controller may utilize model predictive control (MPC). For example, in some embodiments, an MPC algorithm may work in conjunction with a PID algorithm. In some embodiments, utilizing an MPC algorithm in conjunction with a PID algorithm may minimize oscillatory state changes (e.g., voltage changes) that may occur using only a PID algorithm.

[0038] In instances in which an MPC algorithm is used, the MPC algorithm may utilize a model to predict how impedance (e.g., the source impedance associated with the RF input network) changes as a function of voltage across the variable capacitor diode. Impedance changes may be determined based on predicted changes in phase angle. The model may be a physics-based model. The model may be developed using previously collected experimental data. Based on predictions of the model of future phase information and impedance information, future voltages across the variable capacitor diode may be predicted. The model may work in conjunction with an optimizer algorithm that selects future voltages of the variable capacitor diode based on predictions of the model, e.g., to achieve a target impedance of the RF input network that matches the load impedance.

[0039] FIG. 4 is a graph that illustrates use of model predictions to control a variable capacitor diode for impedance matching. In the graph shown in FIG. 4, “t” on the X-axis represents time samples at which measurements (e.g., impedance / phase measurements) are made. Time samples may be made with a period on the order of milliseconds or hundreds of microseconds. In the graph shown in FIG. 4, “p” represents a number of time samples ahead of a present timefor which the MPC algorithm predicts voltages to be applied to the variable capacitor diode.

[0040] Curve 402 illustrates a reference, or target, impedance and phase. The target impedance and phase represent a goal impedance and phase such that the MPC algorithm predicts voltages that will drive the measured impedance and phase (represented by curve 404a, prior to time t) toward the target impedance and phase represented by curve 402. Note that, the impedance is dependent on resistance, inductive reactance, and capacitive reactance. When there is a difference in capacitive reactance relative to inductive reactance, there will be a phase difference between the AC voltage and the AC current, where impedance increases as the phase difference increases. Accordingly, the MPC algorithm may utilize the current voltage applied to the variable capacitor diode and the current magnitude and phase information to make predictions for next values of variable capacitor diode voltage. Curve 406 illustrates previous voltages applied to the variable capacitor diode of the match circuitry. Curve 408 illustrates the voltages predicted by the MPC algorithm for future times (e.g., within the prediction horizon of the MPC algorithm, as shown in FIG. 4). Note that the predicted impedance and phase (represented by curve 404b, after time t) approaches the target impedance and phase (represented by curve 402).

[0041] FIG. 5 is a flowchart of an example process 500 for actuating a variable capacitor diode in accordance with some embodiments. In some implementations, blocks of process 500 may be executed by a controller associated with RF match circuitry. An example is controller 310 of FIG. 3A. In some embodiments, blocks of process 500 may be executed in an order other than what is shown in FIG. 5. In some embodiments, two or more blocks of process 500 may be executed substantially in parallel. In some embodiments, one or more blocks of process 500 may be omitted.

[0042] Process 500 can begin at 502 by receiving data indicating a current variable capacitor diode voltage and characteristics of an RF system under control. The current variable capacitor diode voltage represents the voltage applied to the variable capacitor diode at a present time. The characteristics of the RF system may include impedance, phase, and / or magnitude information associated with the RF signal. The characteristics of the RF system may indicate a degree of reflected power, which in turn may indicate a degree of impedance mismatch between the source impedance at the RF input network and the load impedance at the one or more process stations. The characteristics of the RF system may be measured using one or more VI sensors (voltage-current sensors). An example of circuitry that may provide thecharacteristics of the RF system is phase-magnitude measurement block 110 of FIGS. 1 and 3A.

[0043] At 504, process 500 can predict at least a change in impedance and / or phase associated with the RF system based on the received data. Process 500 may predict the change in impedance and / or phase using a control algorithm. For example, the control algorithm may be part of an MPC algorithm which uses a model (e.g., a physics-based model) to predict changes in the impedance and / or phase. The change in impedance may be predicted for any suitable prediction time horizon, which may be on the order of hundreds or thousands of milliseconds.

[0044] At 506, process 500 can determine a next voltage for the variable capacitor diode based at least in part on the predicted change in impedance and / or phase. The next voltage may be determined by an optimizer algorithm of an MPC controller that generates an optimal voltage based on the predicted change in impedance and a target impedance and / or phase. The voltage applied to the variable capacitor diode may be considered the actuator of the system, which may be used to change the trajectory of the system, e.g., the magnitude and phase of the RF signal.

[0045] At 508, process 500 can cause the next voltage to be applied to the variable capacitor diode. Process 500 can then loop back to block 502 and can receive updated data regarding the current variable capacitor diode and characteristics of the RF system under control. Blocks 502-508 may be looped until a fabrication process (e.g., a plasma-based fabrication process) has been completed.CONTEXT FOR DISCLOSED COMPUTATIONAL EMBODIMENTS

[0046] Systems including fabrication tools as described herein may include logic for actuating variable reactance diodes, e.g., to control impedance matching.

[0047] The analysis logic may be designed and implemented in any of various ways. For example, the logic can be implemented in hardware and / or software. Examples are presented in the controller section herein. Hardware-implemented control logic may be provided in any of a variety of forms, including hard coded logic in digital signal processors, applicationspecific integrated circuits, and other devices that have algorithms implemented as hardware. Analysis logic may also be implemented as software or firmware instructions configured to be executed on a general-purpose processor. System control software may be provided by “programming” in a computer readable programming language.

[0048] The computer program code for controlling processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may be hard coded.

[0049] Integrated circuits used in logic may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated in the form of various individual settings (or program files), defining operational parameters for carrying out a particular analysis or image analysis application.

[0050] FIG. 6 is a block diagram of an example of the computing device 600 suitable for use in implementing some embodiments of the present disclosure. For example, device 600 may be suitable for implementing some or all functions associated with model-based control algorithms or other control algorithms, actuating a variable reactance diode in accordance with a control algorithm, or the like.

[0051] Computing device 600 may include a bus 602 that directly or indirectly couples the following devices: memory 604, one or more central processing units (CPUs) 606, one or more graphics processing units (GPUs) 608, a communication interface 610, input / output (I / O) ports 612, input / output components 614, a power supply 616, and one or more presentation components 618 (e.g., display(s)). In addition to CPU 606 and GPU 608, computing device 600 may include additional logic devices that are not shown in FIG. 6, such as but not limited to an image signal processor (ISP), a digital signal processor (DSP), an ASIC, an FPGA, or the like.

[0052] Although the various blocks of FIG. 6 are shown as connected via the bus 602 with lines, this is not intended to be limiting and is for clarity only. For example, in some embodiments, a presentation component 618, such as a display device, may be considered an VO component 614 (e.g., if the display is a touch screen). As another example, CPUs 606 and / or GPUs 608 may include memory (e.g., the memory 604 may be representative of a storage device in addition to the memory of the GPUs 608, the CPUs 606, and / or other components). In other words, the computing device of FIG. 6 is merely illustrative. Distinction is not made between such categories as “workstation,” “server,” “laptop,” “desktop,” “tablet,” “client device,”“mobile device,” “hand-held device,” “electronic control unit (ECU),” “virtual reality system,” and / or other device or system types, as all are contemplated within the scope of the computing device of FIG. 6.

[0053] Bus 602 may represent one or more busses, such as an address bus, a data bus, a control bus, or a combination thereof. The bus 602 may include one or more bus types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standards association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, and / or another type of bus.

[0054] Memory 604 may include any of a variety of computer-readable media. The computer- readable media may be any available media that can be accessed by the computing device 600. The computer-readable media may include both volatile and nonvolatile media, and removable and non-removable media. By way of example, and not limitation, the computer-readable media may comprise computer-storage media and / or communication media.

[0055] The computer-storage media may include both volatile and nonvolatile media and / or removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 604 may store computer-readable instructions (e.g., that represent a program(s) and / or a program element / s), such as an operating system. Computer-storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device 600. As used herein, computer storage media does not comprise signals per se.

[0056] The communication media may embody computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” may refer to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, the communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.Combinations of any of the above should also be included within the scope of computer- readable media.

[0057] CPU(s) 606 may be configured to execute the computer-readable instructions to control one or more components of the computing device 600 to perform one or more of the methods and / or processes described herein. CPU(s) 606 may each include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) that are capable of handling a multitude of software threads simultaneously. CPU(s) 606 may include any type of processor and may include different types of processors depending on the type of computing device 600 implemented (e.g., processors with fewer cores for mobile devices and processors with more cores for servers). For example, depending on the type of computing device 600, the processor may be an ARM processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). Computing device 600 may include one or more CPUs 606 in addition to one or more microprocessors or supplementary co-processors, such as math co-processors.

[0058] GPU(s) 608 may be used by computing device 600 to render graphics (e.g., 3D graphics). GPU(s) 608 may include many (e.g., tens, hundreds, or thousands) of cores that are capable of handling many software threads simultaneously. GPU(s) 608 may generate pixel data for output images in response to rendering commands (e.g., rendering commands from CPU(s) 606 received via a host interface). GPU(s) 608 may include graphics memory, such as display memory, for storing pixel data. The display memory may be included as part of memory 604. GPU(s) 608 may include two or more GPUs operating in parallel (e.g., via a link). When combined, each GPU 608 can generate pixel data for different portions of an output image or for different output images (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU can include its own memory or can share memory with other GPUs.

[0059] In examples where the computing device 600 does not include the GPU(s) 608, the CPU(s) 606 may be used to render graphics.

[0060] Communication interface 610 may include one or more receivers, transmitters, and / or transceivers that enable computing device 600 to communicate with other computing devices via an electronic communication network, included wired and / or wireless communications. Communication interface 610 may include components and functionality to enable communication over any of a number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communicatingover Ethernet), low-power wide-area networks (e.g., LoRaWAN, SigFox, etc.), and / or the internet.

[0061] RO ports 612 may enable the computing device 1300 to be logically coupled to other devices including RO components 614, presentation component(s) 618, and / or other components, some of which may be built in to (e.g., integrated in) computing device 600. Illustrative RO components 614 include a microphone, mouse, keyboard, joystick, track pad, satellite dish, scanner, printer, wireless device, etc. RO components 614 may provide a natural user interface (NUI) that processes air gestures, voice, or other physiological inputs generated by a user. In some instances, inputs may be transmitted to an appropriate network element for further processing. An NUI may implement any combination of speech recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition both on screen and adjacent to the screen, air gestures, head and eye tracking, and touch recognition (as described in more detail below) associated with a display of computing device 600. Computing device 600 may be include depth cameras, such as stereoscopic camera systems, infrared camera systems, RGB camera systems, touchscreen technology, and combinations of these, for gesture detection and recognition. Additionally, computing device 600 may include accelerometers or gyroscopes (e.g., as part of an inertia measurement unit (IMU)) that enable detection of motion. In some examples, the output of the accelerometers or gyroscopes may be used by computing device 600 to render immersive augmented reality or virtual reality.

[0062] Power supply 616 may include a hard-wired power supply, a battery power supply, or a combination thereof. Power supply 616 may provide power to computing device 600 to enable the components of computing device 600 to operate.

[0063] Presentation component(s) 618 may include a display (e.g., a monitor, a touch screen, a television screen, a heads-up-display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. Presentation component(s) 618 may receive data from other components (e.g., GPU(s) 608, CPU(s) 606, etc.), and output the data (e.g., as an image, video, sound, etc.).

[0064] The disclosure may be described in the general context of computer code or machine- useable instructions, including computer-executable instructions such as program modules, being executed by a computer or other machine, such as a personal data assistant or other handheld device. Generally, program modules including routines, programs, objects, components, data structures, etc., refer to code that perform particular tasks or implementparticular abstract data types. The disclosure may be practiced in a variety of system configurations, including hand-held devices, consumer electronics, general-purpose computers, more specialty computing devices, etc. The disclosure may also be practiced in distributed computing environments where tasks are performed by remote-processing devices that are linked through a communications network.Additional Considerations

[0065] Without limitation, example systems may include a plasma etch chamber or module, a plasma-assisted deposition chamber or module such as a plasma-assisted chemical vapor deposition (PECVD) chamber or module or a plasma-assisted atomic layer deposition (PEALD) chamber or module, an atomic layer etch (ALE) chamber or module, a clean chamber or module, a physical vapor deposition (PVD) chamber or module, an ion implantation chamber or module, and any other plasma-assisted semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0066] Unless otherwise specified, the plasma power levels and associated parameters provided herein are appropriate for processing a 300 mm wafer substrate. One of ordinary skill in the art would appreciate that these parameters may be adjusted as necessary for substrates of other sizes.

[0067] The apparatus / process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of electronic devices including semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools / processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following operations, each operation enabled with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0068] As used in this specification and appended claims, the singular forms “a”, “an”, and “the”include plural referents unless the content and context dictates otherwise. For example, reference to “a cell” includes a combination of two or more such cells. Unless indicated otherwise, an “or” conjunction is used in its correct sense as a Boolean logical operator, encompassing both the selection of features in the alternative (A or B, where the selection of A is mutually exclusive from B) and the selection of features in conjunction (A or B, where both A and B are selected).

[0069] It is to be understood that the phrases “for each <item> of the one or more <items>,” “each <item> of the one or more <items>,” or the like, if used herein, are inclusive of both a single-item group and multiple-item groups, i.e., the phrase “for ... each” is used in the sense that it is used in programming languages to refer to each item of whatever population of items is referenced. For example, if the population of items referenced is a single item, then “each” would refer to only that single item (despite the fact that dictionary definitions of “each” frequently define the term to refer to “every one of two or more things”) and would not imply that there must be at least two of those items. Similarly, the term “set” or “subset” should not be viewed, in itself, as necessarily encompassing a plurality of items — it will be understood that a set or a subset can encompass only one member or multiple members (unless the context indicates otherwise).

[0070] The use, if any, of ordinal indicators, e.g., (a), (b), (c). .. or the like, in this disclosure and claims is to be understood as not conveying any particular order or sequence, except to the extent that such an order or sequence is explicitly indicated. For example, if there are three steps labeled (i), (ii), and (iii), it is to be understood that these steps may be performed in any order (or even concurrently, if not otherwise contraindicated) unless indicated otherwise. For example, if step (ii) involves the handling of an element that is created in step (i), then step (ii) may be viewed as happening at some point after step (i). Similarly, if step (i) involves the handling of an element that is created in step (ii), the reverse is to be understood. It is also to be understood that use of the ordinal indicator “first” herein, e.g., “a first item,” should not be read as suggesting, implicitly or inherently, that there is necessarily a “second” instance, e.g., “a second item.”

[0071] Various computational elements including processors, memory, instructions, routines, models, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, the phrase “configured to” is used to connote structure by indicating that the component includes structure (e.g., stored instructions, circuitry, etc.) that performsthe task or tasks during operation. As such, the unit / circuit / component can be said to be configured to perform the task even when the specified component is not necessarily currently operational (e.g., is not on).

[0072] The components used with the “configured to” language may refer to hardware — for example, circuits, memory storing program instructions executable to implement the operation, etc. Additionally, “configured to” can refer to generic structure (e.g., generic circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the recited task(s). Additionally, “configured to” can refer to one or more memories or memory elements storing computer executable instructions for performing the recited task(s). Such memory elements may include memory on a computer chip having processing logic. In some contexts, “configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.

[0073] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

CLAIMSWhat is claimed is:

1. An RF match circuit for impedance matching in a semiconductor fabrication chamber, the RF match circuit comprising: a variable reactance comprising a variable capacitor diode, wherein a voltage associated with the variable capacitor diode is modified to cause a change in a width of a depletion region of the variable capacitor diode based at least in part on an impedance of a plasma load associated with plasma within at least one station of the semiconductor fabrication chamber to perform impedance matching between an RF source and the plasma load.

2. The RF match circuit of claim 1 , wherein the variable capacitor diode is configured to have a variable capacitance within at least a 100:1 ratio range.

3. The RF match circuit of claim 1, wherein the variable capacitor diode has a breakdown voltage of at least 1000 V.

4. The RF match circuit of claim 1 , wherein the variable capacitor diode comprises a semiconductor that is at least one of: gallium oxide, diamond or gallium nitride.

5. The RF match circuit of any one of claims 1-4, wherein the variable reactance does not include any mechanical reactances.

6. The RF match circuit of any one of claims 1-4, wherein the impedance matching is performed in less than 10 milliseconds.

7. The RF match circuit of any one of claims 1-4, wherein the variable reactance operates in conjunction with circuitry configured to modify a frequency of the RF source to perform the impedance matching.

8. The RF match circuit of any one of claims 1-4, wherein the variable reactance further comprises a second variable capacitor diode.

9. The RF match circuit of claim 8, wherein the variable capacitor diode and the second variable capacitor diode each rectify half of an alternating current (AC) signal.

10. A semiconductor fabrication chamber, comprising: at least one station configured to receive a substrate undergoing a plasma-based fabrication process; an RF source; and an RF match circuit configured to match an impedance at the RF source and an impedance of a plasma load associated with plasma in the at least one station, wherein the RF match circuit comprises: a variable reactance comprising a variable capacitor diode, wherein a voltage associated with the variable capacitor diode is modified to cause a change in a width of a depletion region of the variable capacitor diode based at least in part on the impedance of the plasma load.

11. The semiconductor fabrication chamber of claim 10, wherein the variable capacitor diode has a breakdown voltage of at least 1000 V.

12. The semiconductor fabrication chamber of claim 10, wherein the variable capacitor diode comprises a semiconductor that is at least one of: gallium oxide, diamond or gallium nitride.

13. The semiconductor fabrication chamber of any one of claims 10-12, wherein the variable reactance does not include any mechanical reactances.

14. The semiconductor fabrication chamber of any one of claims 10-12, wherein the impedance matching is performed in less than 10 milliseconds.

15. The semiconductor fabrication chamber of any one of claims 10-12, further comprising a controller configured to determine a modified voltage associated with the variable capacitor diode.

16. The semiconductor fabrication chamber of claim 15, wherein the controller is configured to utilize a model-predictive control (MFC) algorithm to determine the modified voltage.

17. The semiconductor fabrication chamber of claim 16, wherein the MPC algorithm operates in conjunction with a proportional-integral-derivative (PID) control algorithm to determine the modified voltage.

18. The semiconductor fabrication chamber of claim 16, wherein the MPC algorithm generates predicted voltages over a prediction horizon based on a target impedance.

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