Chip electrode structure and manufacturing method therefor, and biosensing chip

Abstract

A manufacturing method for a chip electrode structure, comprising the following steps: providing a layered structure, comprising a first conductive layer, a first transition layer, and a second conductive layer that are successively stacked, wherein an annealing temperature of the second conductive layer is higher than that of the first conductive layer; and performing annealing treatment on the layered structure at the annealing temperature of the first conductive layer to increase the surface roughness of the first conductive layer, thereby increasing the specific surface area of the second conductive layer. The present application further provides a chip electrode structure and a biosensing chip. In the present application, the first conductive layer having undergone annealing treatment is conducive to increasing the specific surface area of the chip electrode structure and reducing the electrochemical impedance.

Description

Chip electrode structure and preparation method thereof, and biosensor chip Technical Field

[0001] The present application relates to the field of biotechnology, and in particular to a chip electrode structure and a preparation method thereof, as well as a biosensing chip having the chip electrode structure. Background Art

[0002] In biosensor chips, the area of ​​their electrode regions is usually fixed. Due to the miniaturization and high integration of biosensor chips, how to simply and effectively utilize the small area of ​​the electrode region to improve the stability of electrode sensing is currently a problem that needs to be solved.

[0003] Summary of the Invention

[0004] One object of the present application is to provide a method for preparing a chip electrode structure that is conducive to increasing the specific surface area of ​​the electrode. The present application also provides a chip electrode structure and a biosensor chip using the chip electrode structure.

[0005] In a first aspect, the present application provides a method for preparing a chip electrode structure, comprising the following steps:

[0006] Providing a layered structure comprising a first conductive layer, a first transition layer, and a second conductive layer stacked in sequence, wherein the annealing temperature of the second conductive layer is higher than the annealing temperature of the first conductive layer;

[0007] The layered structure is annealed at the annealing temperature of the first conductive layer, so that the surface roughness of the first conductive layer is increased, thereby increasing the specific surface area of ​​the second conductive layer.

[0008] In some embodiments, the annealing temperature of the first conductive layer is lower than 500°C.

[0009] In some embodiments, the annealing temperature of the first conductive layer is lower than the annealing temperature of the first transition layer.

[0010] In some embodiments, the material of the first conductive layer is selected from magnesium, zinc, magnesium alloy or aluminum.

[0011] In some embodiments, the material of the second conductive layer is selected from noble metals or graphene.

[0012] In some embodiments, when the material of the second conductive layer is selected from noble metals, the material of the second conductive layer is selected from platinum, gold, or silver.

[0013] In some embodiments, the first transition layer is a titanium layer.

[0014] In some embodiments, the thickness of the first conductive layer is 0.5 μm to 2 μm.

[0015] In some embodiments, the second conductive layer has a thickness of 200 nm to 500 nm.

[0016] In some embodiments, the thickness of the first transition layer is 20 nm to 100 nm.

[0017] In some embodiments, the annealing treatment specifically includes:

[0018] The temperature is raised from room temperature to the annealing temperature of the first conductive layer at a first rate lower than 20°C / s, maintained at the annealing temperature of the first conductive layer for no more than 3 minutes, and then lowered to room temperature at a second rate lower than 20°C / s.

[0019] In some embodiments, the first rate does not exceed 15°C / s.

[0020] In some embodiments, the second rate does not exceed 15°C / s.

[0021] In some embodiments, at least one of the first conductive layer, the first transition layer, and the second conductive layer is formed by evaporation, sputtering, or ion plating.

[0022] In some embodiments, the layered structure further includes a substrate, wherein the substrate is bonded to a side of the first conductive layer facing away from the first transition layer.

[0023] In some embodiments, the layered structure further includes a second transition layer coupled between the substrate and the first conductive layer.

[0024] In some embodiments, the second transition layer is a titanium layer.

[0025] In some embodiments, the second transition layer has a thickness of 20 nm to 100 nm.

[0026] In some embodiments, the second transition layer is formed by evaporation, sputtering or ion plating.

[0027] In some embodiments, the base includes a substrate and a passivation layer disposed on one side of the substrate, and the passivation layer is at least partially located between the substrate and the first conductive layer.

[0028] In some embodiments, the passivation layer includes a plurality of passivation films, and the first conductive layer is embedded in at least one of the passivation films.

[0029] The second aspect of the present application provides a chip electrode structure, comprising a first electrode layer, a first transition layer, and a second electrode layer stacked in sequence. The first electrode layer is made by annealing a conductive layer, and the annealing temperature of the second electrode layer is higher than the annealing temperature of the conductive layer.

[0030] In some embodiments, the annealing temperature of the conductive layer is lower than 500°C.

[0031] In some embodiments, the annealing temperature of the conductive layer is lower than the annealing temperature of the first transition layer.

[0032] In some embodiments, the material of the first electrode layer is selected from magnesium, zinc, magnesium alloy or aluminum.

[0033] In some embodiments, the material of the second electrode layer is selected from noble metals or graphene.

[0034] In some embodiments, when the material of the second electrode layer is selected from noble metals, it is selected from platinum, gold, or silver.

[0035] In some embodiments, the first transition layer is a titanium layer.

[0036] In some embodiments, the thickness of the first electrode layer is 0.5 μm to 2 μm.

[0037] In some embodiments, the thickness of the second electrode layer is 200 nm to 500 nm.

[0038] In some embodiments, the thickness of the first transition layer is 20 nm to 100 nm.

[0039] In some embodiments, the chip electrode structure further includes a substrate, and the substrate is bonded to a side of the first electrode layer facing away from the first transition layer.

[0040] In some embodiments, the chip electrode structure further includes a second transition layer, wherein the second transition layer is bonded between the substrate and the first electrode layer.

[0041] In some embodiments, the second transition layer is a titanium layer.

[0042] In some embodiments, the second transition layer has a thickness of 20 nm to 100 nm.

[0043] In some embodiments, the base includes a substrate and a passivation layer disposed on one side of the substrate, and the passivation layer is at least partially located between the substrate and the first electrode layer.

[0044] In some embodiments, the passivation layer includes a plurality of passivation films, and the first electrode layer is embedded in at least one of the passivation films.

[0045] A third aspect of the present application provides a biosensor chip, comprising electrodes, wherein the electrodes are the chip electrode structure as described above.

[0046] In some embodiments, the biosensing chip further includes a main body structure having a concave hole, and the electrode is embedded in the concave hole.

[0047] The chip electrode structure and its preparation method, as well as the biosensor chip having the chip electrode structure, provided in embodiments of the present application, increase the surface roughness of the first electrode layer / first conductive layer through annealing, thereby increasing the specific surface area of ​​the second electrode layer / second conductive layer, thereby facilitating an increase in the electrode's reaction area during use. The annealing treatment also helps reduce electrochemical impedance, thereby improving the stability of electrode sensing and achieving better performance for the biosensor chip. Furthermore, the preparation method of the present application is simple and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0049] FIG1 is a flow chart of a method for preparing a chip electrode structure according to an embodiment of the present application.

[0050] FIG2 is a cross-sectional view of a layered structure according to an embodiment of the present application.

[0051] FIG3 is a cross-sectional view of a chip electrode structure according to an embodiment of the present application.

[0052] FIG4 is a cross-sectional view of a biosensor chip according to an embodiment of the present application.

[0053] FIG5 is a temperature curve of the annealing treatment in Example 1 of the present application.

[0054] FIG6 is an electron microscope image of the surface of the platinum layer of the comparative example and Example 1 of the present application.

[0055] Description of Main Component Symbols Layered structure 10 First conductive layer 11 First transition layer 12 Second conductive layer 13 Base 14 Substrate 141 Passivation layer 143 Second transition layer 15 Chip electrode structure 100 First electrode layer 11a Second electrode layer 13a DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application are described clearly and in detail below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present application. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0057] In addition, for the sake of brevity and clarity, the size or thickness of various components or layers may be exaggerated in the accompanying drawings. Throughout the text, the same numerical value refers to the same element. As used herein, the terms "and / or" and "and / or" include any and all combinations of one or more related enumerated items. In addition, it should be understood that when element A is referred to as "connecting" element B, element A can be directly connected to element B, or there may be an intermediate element C and element A and element B can be indirectly connected to each other.

[0058] Further, when describing embodiments of the present application, the use of “may” refers to “one or more embodiments of the present application.”

[0059] The technical terms used herein are for the purpose of describing specific embodiments and are not intended to limit this application. As used herein, the singular is intended to include the plural, unless the context clearly indicates otherwise. It should be further understood that the term "comprising", when used in this specification, refers to the presence of the described features, values, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, values, steps, operations, elements, components and / or combinations thereof.

[0060] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part without departing from the teachings of the exemplary embodiments.

[0061] Referring to FIG. 1 and FIG. 2 , an embodiment of the present application provides a method for preparing a chip electrode structure, comprising the following steps:

[0062] In step S1 , a layered structure 10 is provided, comprising a first conductive layer 11 , a first transition layer 12 , and a second conductive layer 13 stacked in sequence.

[0063] The annealing temperature of the second conductive layer 13 is higher than the annealing temperature of the first conductive layer 11 .

[0064] In some embodiments, the annealing temperature of the first conductive layer 11 may be lower than 500° C. In some embodiments, the annealing temperature of the first conductive layer 11 may be lower than the annealing temperature of the first transition layer 12 .

[0065] The first conductive layer 11 is a metal layer. For example, but not limited to, the material of the first conductive layer 11 can be selected from magnesium, zinc, a magnesium alloy, or aluminum. In some embodiments, the first conductive layer 11 can be an aluminum layer. This allows for a lower annealing temperature during subsequent annealing, which is beneficial for energy conservation and cost reduction. It also helps expand the range of materials that can be selected for the second conductive layer 13 that are compatible with the first conductive layer 11 and helps increase the difference in annealing temperatures between the first conductive layer 11 and the second conductive layer 13, thereby preventing any impact on the second conductive layer 13 during subsequent annealing.

[0066] In some embodiments, the thickness of the first conductive layer 11 may be 0.5 μm to 2 μm, specifically, but not limited to, 0.7 μm, 0.9 μm, 1.1 μm, 1.3 μm, or 1.5 μm.

[0067] The first transition layer 12 can be a titanium layer, which helps to improve the bonding strength between the first conductive layer 11 and the second conductive layer 13, thereby reducing the risk of the second conductive layer 13 peeling off, thereby improving the overall stability and service life of the chip electrode structure.

[0068] In some embodiments, the thickness of the first transition layer 12 may be 20 nm to 100 nm, specifically, but not limited to, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, and 90 nm.

[0069] The second conductive layer 13 can be a metal layer, a non-metallic semiconductor layer, or the like, such as, but not limited to, a noble metal or graphene. The noble metal can be selected from gold, silver, ruthenium, rhodium, palladium, osmium, iridium, or platinum. Preferably, the noble metal can be selected from platinum, gold, or silver. In some embodiments, the second conductive layer 13 can be a platinum metal layer.

[0070] In some embodiments, the thickness of the second conductive layer 13 may be 200 nm to 500 nm, specifically, but not limited to, 250 nm, 300 nm, 350 nm, 400 nm, or 450 nm.

[0071] In some embodiments, the layered structure 10 may further include a substrate 14 , which is bonded to a side of the first conductive layer 11 facing away from the first transition layer 12 .

[0072] In some embodiments, the base 14 may include a substrate 141 and a passivation layer 143 disposed on one side of the substrate 41 , wherein the passivation layer 143 is at least partially located between the substrate 141 and the first conductive layer 11 .

[0073] The substrate 141 may be, but is not limited to, a silicon-based substrate, a glass substrate, a carbon-based substrate, an integrated circuit wafer, a printed circuit board, a flexible circuit board, and the like.

[0074] In some embodiments, the passivation layer 143 may have a single-layer structure or a multi-layer structure.

[0075] When the passivation layer 143 is a single-layer structure, the material of the passivation layer 143 can be, but is not limited to, conventional silicon-based passivation materials such as silicon dioxide and silicon nitride. It can also be a thin layer of photoresist (such as, but not limited to, epoxy photoresist or polyimide film) or an insulating varnish commonly used for printed circuit board passivation (such as, but not limited to, acrylic resin). In some embodiments, the passivation layer 143 can be entirely located between the substrate 141 and the first conductive layer 11.

[0076] When the passivation layer 143 is a multi-layer structure, the passivation layer 143 includes a plurality of stacked passivation films, and the material of each passivation film may be, but is not limited to, conventional silicon-based passivation materials such as silicon dioxide and silicon nitride, or may be a thin layer of photoresist (such as, but not limited to, epoxy resin photoresist or polyimide film, etc.) or an insulating varnish commonly used for passivation of printed circuit boards (such as, but not limited to, acrylic resin, etc.). The materials selected between any two layers of passivation films may be the same or different. The number of layers of the passivation film can be selected as needed, for example, it may be, but is not limited to, two layers, three layers, etc. In some embodiments, at least one layer of the multiple passivation films may be entirely located between the substrate 141 and the first conductive layer 11, while the remaining passivation films are located on both sides of the first conductive layer 11, that is, the first conductive layer 11 is embedded in the remaining passivation films.

[0077] In some embodiments, the layered structure 10 may further include a second transition layer 15 disposed on the substrate 14. The second transition layer 15 is bonded between the substrate 14 and the first conductive layer 11. In some embodiments, the second transition layer 15 may be a titanium layer to enhance the bonding strength between the substrate 14 and the first conductive layer 11, thereby reducing the risk of the first conductive layer 11 peeling off from the substrate 14.

[0078] In some embodiments, the thickness of the second transition layer 15 may be 20 nm to 100 nm, specifically, but not limited to, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, or 90 nm.

[0079] Any of the first conductive layer 11, the first transition layer 12, the second conductive layer 13, and the second transition layer 15 can be deposited by, but not limited to, evaporation, sputtering, or ion plating. In some embodiments, the first conductive layer 11, the first transition layer 12, the second conductive layer 13, and the second transition layer 15 can also be formed by other methods.

[0080] In step S2 , the layered structure 10 is annealed at the annealing temperature of the first conductive layer 11 to increase the surface roughness of the first conductive layer 11 , thereby increasing the specific surface area of ​​the second conductive layer 13 formed on the first conductive layer 11 .

[0081] The annealing treatment in the above-mentioned preparation method is beneficial for increasing the surface roughness of the first conductive layer 11, thereby increasing the specific surface area of ​​the second conductive layer 13 formed on the first conductive layer 11, and further increasing the reaction area of ​​the electrode when using the above-mentioned chip electrode structure. Furthermore, the annealing treatment is also beneficial for reducing the electrochemical impedance. In addition, the preparation method of the present application is simple and efficient, and is beneficial for reducing costs and improving the consistency of the electrode structure.

[0082] In some embodiments, the annealing process may include but is not limited to:

[0083] The temperature is raised from room temperature to the annealing temperature of the first conductive layer 11 at a first rate lower than 20°C / s, maintained at the annealing temperature of the first conductive layer 11 for no more than 3 minutes, and then lowered to room temperature at a second rate lower than 20°C / s.

[0084] In some embodiments, the first rate is less than 20°C / s, and particularly not more than 15°C / s, to avoid delamination or even peeling caused by excessive stress due to the heating rate, thereby ensuring the overall stability, yield, and service life of the chip electrode structure. Furthermore, the first rate may be no less than 1°C / s, thereby improving overall manufacturing efficiency. In this embodiment, the first rate may be 15°C / s.

[0085] The second rate is lower than 20°C / s, and particularly not more than 15°C / s, to avoid delamination or even peeling caused by excessive stress due to the cooling rate, thereby ensuring the overall stability, yield, and service life of the chip electrode structure. Furthermore, the second rate can be no less than 1°C / s, thereby improving overall manufacturing efficiency. In this embodiment, the second rate can be 5°C / s.

[0086] Furthermore, the constant temperature time may be no less than 1 minute, which is beneficial to ensuring the roughening effect of the first conductive layer 11 .

[0087] As shown in FIG3 , the present application further provides a chip electrode structure 100 according to an embodiment, which can be prepared by the above-mentioned preparation method. Specifically, the chip electrode structure 100 includes a first electrode layer 11a, a first transition layer 12, and a second electrode layer 13a stacked in sequence. The first electrode layer 11a is prepared by annealing a conductive layer, namely the aforementioned first conductive layer 11. The annealing temperature of the first conductive layer 11 is lower than the annealing temperature of the second electrode layer 13a. The first electrode layer 11a has a higher roughness and lower chemical impedance than the first conductive layer 11 before annealing, which is beneficial to improving the stability of the chip electrode structure 100 during sensing.

[0088] In some embodiments, the annealing temperature of the first conductive layer 11 may be lower than 500° C. In some embodiments, the annealing temperature of the first conductive layer 11 may be lower than the annealing temperature of the first transition layer 12 .

[0089] The first conductive layer 11 is a metal layer. For example, but not limited to, the material of the first conductive layer 11 can be selected from magnesium, zinc, a magnesium alloy, or aluminum. In some embodiments, the first conductive layer 11 can be an aluminum layer, which corresponds to a lower annealing temperature during the subsequent annealing process, which is beneficial for energy conservation and cost reduction. It also helps to expand the range of materials that can be selected for the second electrode layer 13a that are compatible with the first conductive layer 11, and helps to increase the difference in annealing temperatures between the first conductive layer 11 and the second electrode layer 13a, thereby preventing the subsequent annealing process from affecting the second electrode layer 13a.

[0090] In some embodiments, the thickness of the first electrode layer may be 0.5 μm to 2 μm, specifically, but not limited to, 0.7 μm, 0.9 μm, 1.1 μm, 1.3 μm, or 1.5 μm.

[0091] In some embodiments, the second electrode layer 13 a is the aforementioned second conductive layer 13 .

[0092] Likewise, in some embodiments, the chip electrode structure 100 may further include the aforementioned substrate 14 and may further include the aforementioned second transition layer 15, which will not be described in detail here.

[0093] As shown in Figure 4 , the chip electrode structure 100 can be used as an electrode in, but is not limited to, a biosensor chip 200. The biosensor chip 200 also includes a main structure 201 having a recess 203, into which the chip electrode structure 100 can be embedded. Using a chip electrode structure with low electrochemical impedance and a larger electrode reaction area facilitates improved performance of the biosensor chip.

[0094] Specifically, the first electrode layer 11a, the first transition layer 12, and the second electrode layer 13a in the chip electrode structure 100 are embedded into the recessed hole 203 from one side of the recessed hole 203. When the chip electrode structure 100 further includes a substrate 14, the substrate 14 can be disposed on one side of the main structure 201 and seal one side of the recessed hole 203. When the chip electrode structure 100 further includes a second transition layer 15, the second transition layer 15 is also embedded into the recessed hole 203.

[0095] In some embodiments, the material of the main structure 201 can be a non-conductive photoresist or other non-conductive material. The main structure 201 can also include a semiconductor material or a conductive material. In this case, it is sufficient to ensure that the main structure 201 is electrically insulated from the substrate 14 of the chip electrode structure 100. This insulation can be achieved, for example, but not limited to, by providing a non-conductive passivation layer. Specifically, the material of the main structure 201 can include, but is not limited to, silicon-based materials, photosensitive epoxy resin photoresists, etc.

[0096] The main structure 201 may be a single-layer structure or a multi-layer structure, which is not specifically limited in this application.

[0097] The shape of the recessed hole 203 is not limited in this application and can be selected according to specific needs.

[0098] The biosensing chip 200 can be applied to, but is not limited to, gene sequencing, protein sequencing, biomolecule detection, and the like.

[0099] The present application will be better described below through examples and comparative examples.

[0100] Comparative Example

[0101] A chip electrode structure is provided, comprising a substrate, a passivation layer, a titanium layer and a platinum layer stacked in sequence.

[0102] Example 1

[0103] The difference between Example 1 and the comparative example is that an aluminum layer and another titanium layer are sequentially stacked between the above-mentioned titanium layer and the above-mentioned platinum layer to obtain a layered structure, wherein the aluminum layer is located between the two titanium layers, and the above-mentioned layered structure is further annealed to obtain the chip electrode structure of this embodiment. The annealing treatment is specifically to raise the temperature from room temperature to 450°C at a rate of 15°C / s in air, and keep the temperature at 450°C for 1 minute, and then cool to room temperature at a rate of 5°C / s. Among them, Figure 5 is the temperature curve of the annealing treatment of Example 1. The left side of Figure 6 is an electron microscope image of the platinum layer surface of the chip electrode structure of the comparative example, and the right side is an electron microscope image of the platinum layer surface of the chip electrode structure of Example 1. It can be seen from Figure 6 that compared with the comparative example, the chip electrode structure of Example 1 has a larger specific area and more obvious roughness.

[0104] The above disclosure is only a preferred embodiment of the present application and certainly cannot be used to limit the present application. Therefore, equivalent changes made based on the present application are still within the scope covered by the present application.

Claims

1. A method for preparing a chip electrode structure, characterized in that: The following steps are involved: Providing a layered structure comprising a first conductive layer, a first transition layer, and a second conductive layer stacked in sequence, wherein the annealing temperature of the second conductive layer is higher than the annealing temperature of the first conductive layer; The layered structure is annealed at the annealing temperature of the first conductive layer, so that the surface roughness of the first conductive layer is increased, thereby increasing the specific surface area of ​​the second conductive layer.

2. The method for preparing a chip electrode structure according to claim 1, wherein: The annealing temperature of the first conductive layer is lower than 500°C.

3. The method for preparing a chip electrode structure according to any one of claims 1 to 2, characterized in that: The annealing temperature of the first conductive layer is lower than the annealing temperature of the first transition layer.

4. The method for preparing a chip electrode structure according to claim 2, wherein: The material of the first conductive layer is selected from magnesium, zinc, magnesium alloy or aluminum.

5. The method for preparing a chip electrode structure according to any one of claims 1 to 4, characterized in that: The material of the second conductive layer is selected from noble metal or graphene.

6. The method for preparing a chip electrode structure according to claim 5, wherein: When the material of the second conductive layer is selected from noble metals, the material of the second conductive layer is selected from platinum, gold or silver.

7. The method for preparing a chip electrode structure according to any one of claims 1 to 6, wherein: The first transition layer is a titanium layer.

8. The method for preparing a chip electrode structure according to any one of claims 1 to 7, wherein: The thickness of the first conductive layer is 0.5 μm to 2 μm.

9. The method for preparing a chip electrode structure according to any one of claims 1 to 8, wherein: The thickness of the second conductive layer is 200 nm to 500 nm.

10. The method for preparing a chip electrode structure according to any one of claims 1 to 9, wherein: The thickness of the first transition layer is 20 nm to 100 nm.

11. The method for preparing a chip electrode structure according to any one of claims 1 to 10, characterized in that: The annealing treatment specifically includes: The temperature is raised from room temperature to the annealing temperature of the first conductive layer at a first rate lower than 20°C / s, maintained at the annealing temperature of the first conductive layer for no more than 3 minutes, and then lowered to room temperature at a second rate lower than 20°C / s.

12. The method for preparing a chip electrode structure according to claim 11, wherein: The first rate does not exceed 15°C / s.

13. The method for preparing a chip electrode structure according to any one of claims 11 to 12, characterized in that: The second rate does not exceed 15°C / s.

14. The method for preparing a chip electrode structure according to any one of claims 1 to 13, wherein: At least one of the first conductive layer, the first transition layer, and the second conductive layer is formed by evaporation, sputtering, or ion plating.

15. The method for preparing a chip electrode structure according to any one of claims 1 to 14, wherein: The layered structure further includes a substrate bonded to a side of the first conductive layer facing away from the first transition layer.

16. The method for preparing a chip electrode structure according to claim 15, wherein: The layered structure further includes a second transition layer bonded between the substrate and the first conductive layer.

17. The method for preparing a chip electrode structure according to claim 16, wherein: The second transition layer is a titanium layer.

18. The method for preparing a chip electrode structure according to any one of claims 16 to 17, wherein: The thickness of the second transition layer is 20 nm to 100 nm.

19. The method for preparing a chip electrode structure according to any one of claims 16 to 18, wherein: The second transition layer is formed by evaporation, sputtering or ion plating.

20. The method for preparing a chip electrode structure according to any one of claims 15 to 19, wherein: The base includes a substrate and a passivation layer provided on one side of the substrate, wherein the passivation layer is at least partially located between the substrate and the first conductive layer.

21. The method for preparing a chip electrode structure according to claim 20, wherein: The passivation layer includes a plurality of passivation films, and the first conductive layer is embedded in at least one of the passivation films.

22. A chip electrode structure, comprising a first electrode layer, a first transition layer, and a second electrode layer stacked in sequence, characterized in that: The first electrode layer is made by annealing a conductive layer, and the annealing temperature of the second electrode layer is higher than the annealing temperature of the conductive layer.

23. The chip electrode structure according to claim 22, wherein: The annealing temperature of the conductive layer is lower than 500°C.

24. The chip electrode structure according to any one of claims 22 to 23, characterized in that: The annealing temperature of the conductive layer is lower than the annealing temperature of the first transition layer.

25. The chip electrode structure according to any one of claims 22 to 24, characterized in that: The material of the first electrode layer is selected from magnesium, zinc, magnesium alloy or aluminum.

26. The chip electrode structure according to any one of claims 22 to 25, characterized in that: The material of the second electrode layer is selected from noble metals or graphene.

27. The chip electrode structure according to claim 26, wherein: When the material of the second electrode layer is selected from noble metals, it is selected from platinum, gold or silver.

28. The chip electrode structure according to any one of claims 22 to 27, wherein: The first transition layer is a titanium layer.

29. The chip electrode structure according to any one of claims 22 to 28, wherein: The thickness of the first electrode layer is 0.5 μm to 2 μm.

30. The chip electrode structure according to any one of claims 22 to 29, wherein: The thickness of the second electrode layer is 200 nm to 500 nm.

31. The chip electrode structure according to any one of claims 22 to 30, characterized in that: The thickness of the first transition layer is 20 nm to 100 nm.

32. The chip electrode structure according to any one of claims 22 to 31, characterized in that: The chip electrode structure further includes a substrate, which is combined with a side of the first electrode layer facing away from the first transition layer.

33. The chip electrode structure according to claim 32, wherein: The chip electrode structure further includes a second transition layer, which is bonded between the substrate and the first electrode layer.

34. The chip electrode structure according to claim 33, wherein: The second transition layer is a titanium layer.

35. The chip electrode structure according to any one of claims 33 to 34, characterized in that: The thickness of the second transition layer is 20 nm to 100 nm.

36. The chip electrode structure according to any one of claims 32 to 35, characterized in that: The base includes a substrate and a passivation layer provided on one side of the substrate, wherein the passivation layer is at least partially located between the substrate and the first electrode layer.

37. The chip electrode structure according to claim 36, wherein: The passivation layer includes a plurality of passivation films, and the first electrode layer is embedded in at least one of the passivation films.

38. A biosensor chip, characterized in that: It comprises an electrode, wherein the electrode is a chip electrode structure as described in any one of claims 22 to 37.

39. The biosensor chip according to claim 38, wherein: It also includes a main body structure, wherein the main body structure has a concave hole, and the electrode is embedded in the concave hole.

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