Package

Abstract

The present invention improves heat dissipation on the back surface side of a chip while alleviating wiring constraints on the back surface side of the chip.　This package is provided with: a chip, on a front surface of which an external terminal used for signal transmission is formed; a substrate on which the chip is mounted via the back surface thereof; a plurality of thermally conductive layers that are disposed in mutually different layers of the substrate and have a higher thermal conductivity than the substrate; and a via that interconnects the plurality of thermally conductive layers. The external terminal includes first bonding pads, and the substrate includes second bonding pads disposed around the chip. The first bonding pads and the second bonding pads may be connected to each other via bonding wires.

Description

package

[0001] The present technology relates to a package, and more particularly to a package capable of dissipating heat from the back side of a substrate on which a chip is mounted.

[0002] To improve heat dissipation from the backside of the chip, there is a technique for providing a heat dissipation member on the backside of the chip, such as forming a bonding member dedicated to heat dissipation that does not exchange electrical signals in an area overlapping the MOSFET region (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2007-53148

[0004] However, in the above-mentioned conventional technology, a bonding member that does not form an electrical signal path is provided separately from the bonding member that connects the electrical signal path from the active region to the wiring substrate via the signal wiring, which raises the risk that the bonding member that connects the electrical signal path may restrict the heat dissipation path from the back side of the chip.

[0005] This technology was developed in light of these circumstances, and aims to improve the heat dissipation performance on the back side of the chip while easing the constraints on wiring on the back side of the chip.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a package including a chip having external terminals used for signal transmission formed on its surface, a substrate on which the chip is mounted via the back surface of the chip, multiple thermally conductive layers arranged on different layers of the substrate and having a higher thermal conductivity than the substrate, and vias connecting the multiple thermally conductive layers to each other. This provides the effect of arranging the thermally conductive layer on the back surface of the chip while easing restrictions on the arrangement of the external terminals on the chip.

[0007] In the first aspect, the via may be disposed at a position overlapping the chip, thereby enabling wiring to be formed on the substrate and improving heat dissipation from the chip mounting surface to the back surface of the substrate.

[0008] In addition, in the first aspect, the vias may be arranged at equal intervals across the entire back surface of the chip, thereby enabling wiring to be formed on the substrate and improving heat dissipation across the entire back surface of the chip.

[0009] In the first aspect, the vias may be arranged in accordance with a heat distribution of the chip, thereby enabling wiring to be formed on the substrate and improving heat dissipation from high-temperature portions.

[0010] In addition, in the first aspect, the external terminals may include first bonding pads, and the substrate may include second bonding pads arranged around the chip, the first bonding pads and the second bonding pads being connected to each other via bonding wires, thereby enabling heat dissipation from the entire back surface of the chip and electrically connecting the chip to the outside via the substrate.

[0011] In the first aspect, the plurality of thermally conductive layers may include an upper thermally conductive layer and a lower thermally conductive layer, and the upper thermally conductive layer and the bonding pads may be disposed on the same layer of the substrate, thereby reducing thermal resistance between the upper thermally conductive layer and the chip while allowing bonding wires to be connected to the bonding pads.

[0012] In the first aspect, the substrate may further include a land electrode formed on the rear surface thereof, and the lower thermal conduction layer may be disposed above the layer on which the land electrode is formed, thereby reducing the thermal resistance on the rear surface of the substrate.

[0013] In the first aspect, the plurality of thermally conductive layers may be formed at positions overlapping the entire back surface of the chip, thereby reducing the thermal resistance between the upper thermally conductive layer and the chip over the entire back surface of the chip.

[0014] In the first aspect, the upper thermal conduction layer may extend to the outside of the back surface of the chip so as to surround the periphery of the second bonding pad, thereby providing an effect of expanding the heat dissipation path from the back surface side of the chip to the outside of the chip.

[0015] In addition, in the first aspect, a terminal may be provided on a side surface of the substrate and have a thermal conductivity higher than that of the substrate, and the thermal conduction layer may be connected to the terminal, thereby achieving the effect of dissipating heat from the chip not only from the back surface side of the substrate but also from the side surface of the substrate.

[0016] In addition, the first aspect may further include a housing joined to the terminals via a joining member, thereby providing the effect that heat generated from the chip is dissipated from the housing via the side surface of the substrate.

[0017] In addition, in the first aspect, the chip may include a light receiving unit that receives light, and may further include a lens supported on the light receiving unit via the housing, thereby providing the effect of supporting the lens on the light receiving unit via the housing and dissipating heat generated from the chip from the housing via the side surface of the substrate.

[0018] In addition, in the first aspect, a sealing material may be further provided for sealing the chip and the bonding wires on the substrate, thereby improving heat dissipation from the back surface side of the substrate and protecting the chip and the bonding wires.

[0019] In addition, in the first aspect, the semiconductor device may further include a transparent substrate disposed on the chip and a rib supporting the transparent substrate on the chip, thereby providing the effect of protecting the chip and bonding wires while allowing the chip to operate optically.

[0020] In addition, the first aspect may further include a heat sink joined to the rear surface of the substrate, thereby improving heat dissipation from the rear surface side of the substrate.

[0021] FIG. 1 is a diagram illustrating a configuration example of a package according to a first embodiment. FIG. 2 is a plan view illustrating another configuration example of the package according to the first embodiment. FIG. 3 is a plan view illustrating yet another configuration example of the package according to the first embodiment. FIG. 4 is a cross-sectional view illustrating a configuration example of a package according to a second embodiment. FIG. 5 is a cross-sectional view illustrating a configuration example of a package according to a third embodiment. FIG. 6 is a cross-sectional view illustrating a configuration example of a package according to a fourth embodiment. FIG. 7 is a cross-sectional view illustrating a configuration example of a package according to a fifth embodiment. FIG. 8 is a cross-sectional view illustrating a configuration example of a package according to a sixth embodiment. FIG. 9 is a block diagram illustrating a schematic configuration example of a vehicle control system. FIG. 10 is an explanatory diagram illustrating an example of an installation position of an imaging unit.

[0022] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below. The descriptions will be made in the following order: 1. First embodiment (an example in which a ball grid array (BGA) on which a sensor chip is mounted is provided with a plurality of thermally conductive layers having a higher thermal conductivity than the substrate, the plurality of thermally conductive layers being inter-layer connected by vias, and bonding wires being arranged inside ribs that support a transparent substrate on a light-receiving element) 2. Second embodiment (an example in which a ball grid array (BGA) on which a sensor chip is mounted is provided with a plurality of thermally conductive layers having a higher thermal conductivity than the substrate, the plurality of thermally conductive layers being inter-layer connected by vias, and the bonding wires being covered by ribs that support a transparent substrate on a light-receiving element) 3. Third embodiment (an example in which a ceramic substrate on which a sensor chip is mounted is provided with a plurality of thermally conductive layers having a higher thermal conductivity than the substrate, and the plurality of thermally conductive layers being inter-layer connected by vias) 4. 4. Fourth embodiment (an example in which a BGA on which a semiconductor chip is mounted is provided with a plurality of thermally conductive layers having a higher thermal conductivity than the substrate, the plurality of thermally conductive layers being connected to each other by vias, and the semiconductor chip and bonding wires being covered with a sealing material) 5. Fifth embodiment (an example in which a BGA on which a sensor chip is mounted is provided with a plurality of thermally conductive layers having a higher thermal conductivity than the substrate, the plurality of thermally conductive layers being connected to each other by vias, and a heat sink being bonded to the back surface of the package substrate) 6. Sixth embodiment (an example in which a BGA on which a sensor chip is mounted is provided with a plurality of thermally conductive layers having a higher thermal conductivity than the substrate, the plurality of thermally conductive layers being connected to each other by vias, and a thermally conductive terminal provided on the side of the substrate being bonded to a housing that supports a lens) 7. Application to a moving body

[0023] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of a package according to a first embodiment. In the figure, "a" is a cross-sectional view showing an example of the configuration of a package 100A cut vertically, and "b" in the figure is a plan view showing an example of the configuration of the package 100A. "a" in the figure is cut along line A1-A2 in "b" in the figure. "b" in the figure shows an example of the planar pattern of an upper thermally conductive layer 106A. In the drawings used in the following description, the scale and shape may differ from the actual structure to make each configuration easier to understand.

[0024] In the figure, the package 100A includes a package substrate 101A, a chip 111, and a transparent substrate 122. In this case, the package 100A can form a hollow package in which the chip 111 is mounted.

[0025] The package substrate 101A may be a multilayer substrate. The package substrate 101A may be a BGA. For example, a PGA (Pin Grid Array) or an LGA (Land Grid Array) may also be used. A chip 111 is mounted on the package substrate 101A. The package substrate 101A can dissipate heat generated by the chip 111. The package substrate 101A includes multiple thermally conductive layers with higher thermal conductivity than the base material to improve heat dissipation of the heat generated by the chip 111. These thermally conductive layers are arranged on different layers and connected through vias. The base material of the package substrate 101A may be, for example, ceramic or resin. The package substrate 101A has wiring 102A, bonding pads 105A, and land electrodes 109 formed thereon. The wiring 102A may be used as a signal line, a power line, or a ground line. The bonding pads 105A are arranged on the surface of the package substrate 101A. In this case, the bonding pads 105A can be arranged along the four sides of the chip 111. The land electrodes 109 are arranged on the back surface of the package substrate 101A. Also, vias 103A that perform interlayer connection of the package substrate 101A are formed in the package substrate 101A. In this case, the vias 103A can perform interlayer connection among the wiring 102A, the bonding pads 105A, and the land electrodes 109.

[0026] The package substrate 101A also includes an upper thermally conductive layer 106A and a lower thermally conductive layer 107 as thermally conductive layers. The upper thermally conductive layer 106A and the bonding pads 105A are disposed on the same layer of the package substrate 101A. In this case, the upper thermally conductive layer 106A and the bonding pads 105A may be disposed on the top layer of the package substrate 101A. A protective film may be formed on the surface of the package substrate 101A. In this case, the protective film on the upper thermally conductive layer 106A and the bonding pads 105A can be removed to expose the upper thermally conductive layer 106A and the bonding pads 105A to the surface. The lower thermally conductive layer 107 can be disposed on the layer above the land electrodes 109. The lower thermally conductive layer 107 and the land electrodes 109 may be disposed on the same layer of the package substrate 101A. In this case, the lower thermally conductive layer 107 and the land electrodes 109 may be disposed on the bottom layer of the package substrate 101A.

[0027] The upper thermally conductive layer 106A and the lower thermally conductive layer 107 can be formed at positions overlapping the entire back surface of the chip 111. The upper thermally conductive layer 106A extends to the outside of the back surface of the chip 111 so as to surround the periphery of the bonding pad 105A. The lower thermally conductive layer 107 extends to the outside of the back surface of the chip 111. In this case, the upper thermally conductive layer 106A and the lower thermally conductive layer 107 may reach the four outer edges of the package substrate 101A. Here, the upper thermally conductive layer 106A and the lower thermally conductive layer 107 can be dedicated to heat dissipation without being assigned to signal lines or power lines. Therefore, the upper thermally conductive layer 106A and the lower thermally conductive layer 107 can be formed continuously over the entire surface of the package substrate 101A. Here, an opening KA1 can be formed around the bonding pad 105A in the upper thermally conductive layer 106A to separate the bonding pad 105A from the upper thermally conductive layer 106A within the same layer. An opening KA2 can be formed around the via 103A in the lower thermally conductive layer 107 to separate the via 103A from the lower thermally conductive layer 107. The upper thermally conductive layer 106A and the lower thermally conductive layer 107 are connected to each other via heat dissipation vias 108A. The heat dissipation vias 108A can penetrate the package substrate 101A between the upper thermally conductive layer 106A and the lower thermally conductive layer 107. The heat dissipation vias 108A can be arranged at equal intervals across the entire back surface of the chip 111.

[0028] Thermally conductive terminals 104 are formed on the side surfaces of the package substrate 101A. The thermally conductive terminals 104 may be arranged at equal intervals along the four sides of the outer periphery of the package substrate 101A. The thermally conductive terminals 104 may be connected to the upper thermally conductive layer 106A and the lower thermally conductive layer 107.

[0029] The wiring 102A, the via 103A, the bonding pad 105A, the land electrode 109, the upper thermally conductive layer 106A, the lower thermally conductive layer 107, the heat dissipation via 108A, and the heat conduction terminal 104 may be made of the same material. The wiring 102A, the via 103A, the bonding pad 105A, the land electrode 109, the upper thermally conductive layer 106A, the lower thermally conductive layer 107, the heat dissipation via 108A, and the heat conduction terminal 104 may be made of a metal such as Cu. A plating layer of Ni, Au, or the like may be formed on the bonding pad 105A and the land electrode 109.

[0030] The chip 111 is mounted face up on the package substrate 101A. The chip 111 may be bonded to the upper thermally conductive layer 106A via a solder material or a paste material such as Ag paste. The chip 111 and the upper thermally conductive layer 106A may be bonded directly. In this case, a Cu film may be formed on the entire back surface of the chip 111, the upper thermally conductive layer 106A may be made of Cu, and the chip 111 and the upper thermally conductive layer 106A may be bonded directly based on Cu-Cu bonding.

[0031] The chip 111 is connected to the package substrate 101A via bonding wires 116. At this time, bonding pads 113 to which the bonding wires 116 are connected can be formed on the chip 111. Here, by connecting the chip 111 to the package substrate 101A via the bonding wires 116, it is possible to eliminate the need to form bump electrodes on the chip 111. The bonding wires 116 can be made of a metal such as Au or Al.

[0032] A semiconductor element, an optical element, or a MEMS (Micro Electro Mechanical Systems) may be formed on the chip 111. The substrate used for the chip 111 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0033] The light receiving element may be an image sensor such as a CCD (Charged Coupled Device) sensor, a CMOS (Complementary Metal-Oxide Semiconductor) sensor, or a SPAD (Single Photon Avalanche Diode) sensor. The light received by the image sensor may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, or X-rays. The optical element may be a light receiving element such as a PD (Photo Diode), or a light emitting element such as an LD (Laser Diode), an LED (Light Emitting Diode), or a VCSEL (Vertical Cavity Surface Emitting Laser). The optical element may be an optical switch or a DMD (Digital Micromirror Device). The optical element may be a display element such as a liquid crystal element or an organic EL (Electroluminescence) element. The material used for the optical element may be a semiconductor such as Si, GaAs, or InGaAs, or LiNbO ３ , or may be a dielectric material such as glass or transparent resin.

[0034] The semiconductor element may include an IC (Integrated Circuit), a transistor, a resistor, a capacitor, etc. The semiconductor element may include a memory, a processor, a signal processing circuit, a data processing circuit, or an interface circuit. The semiconductor element may include a hardware circuit such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). Materials used for the semiconductor element may include Si, GaAs, SiC, GaN, InGaAs, InP, InGaAsP, etc.

[0035] For example, a CMOS image sensor can be formed on the chip 111. At this time, a light receiving section 112 is provided on the chip 111. In the light receiving section 112, pixels and pixel transistors are arranged in a matrix along the row and column directions. A photodiode can be formed in the pixel. A color filter 114 is formed on the light receiving section 112 for each pixel. An on-chip lens 115 is formed on the color filter 114 for each pixel. The material of the color filter 114 and the on-chip lens 115 is, for example, SiO ２ An insulating film such as SiN or SiCN, or a transparent resin such as acrylic or polycarbonate can be used. The color filter 114 may contain a pigment. The color filter 114 may have, for example, a Bayer array or a Quad Bayer array. The color filter 114 may include an RGB filter, a complementary color filter, or a white filter. A lens, a color splitter, or a deflector made of a metasurface may be formed on the light receiving unit 112.

[0036] The transparent substrate 122 is disposed on the chip 111. At this time, the transparent substrate 122 is supported on the package substrate 101A via the ribs 121 and bonded to the package substrate 101A. The transparent substrate 122 may be a glass substrate, a quartz substrate, or a transparent resin substrate such as acrylic or polycarbonate. The transparent substrate 122 is formed of Al or AlN, depending on the wavelength of light received by the chip 111. ２ O ３ , CaF ２ , MgF ２ Alternatively, LiF or the like may be used.

[0037] The ribs 121 are positioned between the chip 111 and the transparent substrate 122. In this case, the ribs 121 can support the transparent substrate 122 on the chip 111. The ribs 121 can be continuously arranged along the outer periphery of the package substrate 101A. In this case, the ribs 121 can be arranged outside the bonding pads 105A. The material of the ribs 121 may be a thermosetting resin or a UV-curable resin. For example, the material of the ribs 121 may be a resin such as a siloxane-based resin, an acrylic-based resin, or an epoxy-based resin. The ribs 121 may contain an inorganic or organic filler to improve reliability. The filler material may be glass. The ribs 121 may be blackened or comprise an opaque layer to reduce flare on the light receiving unit 112. For example, the ribs 121 may contain a black pigment such as carbon black or a filler such as carbon fiber.

[0038] Here, heat generated in the chip 111 is conducted from the back surface side of the chip 111 to the upper thermally conductive layer 106A. The heat conducted to the upper thermally conductive layer 106A is conducted to the lower thermally conductive layer 107 through the heat dissipation vias 108A and is dissipated from the back surface side of the package substrate 101A. In addition, the heat conducted to the upper thermally conductive layer 106A and the lower thermally conductive layer 107 is conducted to the heat conduction terminal 104 and is dissipated from the side surface side of the package substrate 101A. At this time, the heat generated in the chip 111 can be conducted to the upper thermally conductive layer 106A via the entire back surface of the chip 111, thereby improving the heat dissipation performance of the heat generated in the chip 111.

[0039] 2 is a plan view showing another example of the configuration of the package according to the first embodiment, which shows an example of the planar pattern of the upper thermally conductive layer 106B.

[0040] In the figure, the package 100B includes a package substrate 101B instead of the above-described package substrate 101A. The other configuration of this package 100B is the same as the configuration of the above-described package 100A.

[0041] The package substrate 101B includes wiring 102B, vias 103B, bonding pads 105B, and an upper thermally conductive layer 106B instead of the wiring 102A, vias 103A, bonding pads 105A, and upper thermally conductive layer 106A described above. The rest of the configuration of the package substrate 101B is the same as that of the package substrate 101A described above.

[0042] The bonding pads 105B are arranged along two opposing sides of the periphery of the package substrate 101B. At this time, the bonding pads 113 of the chip 111 can also be arranged along two opposing sides of the periphery of the chip 111. The bonding pads 105B are connected to the vias 103B through the wiring 102B.

[0043] The upper thermal conduction layer 106B can be formed at a position overlapping the entire back surface of the chip 111. The upper thermal conduction layer 106B also extends to the outside of the back surface of the chip 111 so as to surround the periphery of the bonding pad 105B. In this case, an opening KB1 can be formed in the upper thermal conduction layer 106B around the bonding pad 105B to separate the bonding pad 105B from the upper thermal conduction layer 106A within the same layer.

[0044] 3 is a plan view showing yet another example of the configuration of the package according to the first embodiment, which shows an example of the planar pattern of the upper thermally conductive layer 106C.

[0045] In the figure, the package 100C includes a package substrate 101C instead of the above-described package substrate 101A. The other configuration of this package 100C is the same as the configuration of the above-described package 100A.

[0046] The package substrate 101C includes heat dissipation vias 108C instead of the heat dissipation vias 108A. The other configuration of this package substrate 101C is the same as that of the package substrate 101A.

[0047] The heat dissipation vias 108C provide interlayer connection between the upper thermal conduction layer 106A and the lower thermal conduction layer 107. The heat dissipation vias 108C can be arranged in accordance with the heat generation distribution of the chip 111. In this case, the arrangement density of the heat dissipation vias 108C can be increased in areas where the chip 111 generates a large amount of heat, compared to areas where the chip 111 generates a small amount of heat. The diameter of the heat dissipation vias 108C can be changed in accordance with the heat generation distribution of the chip 111. In this case, the diameter of the heat dissipation vias 108C can be increased in areas where the chip 111 generates a large amount of heat, compared to areas where the chip 111 generates a small amount of heat.

[0048] As described above, in the first embodiment, upper thermally conductive layer 106A and lower thermally conductive layer 107, which have higher thermal conductivity than package substrate 101A, are provided and connected to each other through heat dissipation vias 108C. This allows heat generated in chip 111 to be dissipated to package substrate 101A through the entire back surface of chip 111, thereby improving the dissipation of heat generated in chip 111.

[0049] 2. Second Embodiment In the first embodiment described above, upper thermally conductive layer 106A and lower thermally conductive layer 107 having higher thermal conductivity than package substrate 101A are provided, and interlayer connection is made via heat dissipation vias 108A, with ribs 121 arranged outside bonding pads 105A. In this second embodiment, upper thermally conductive layer and lower thermally conductive layer having higher thermal conductivity than the package substrate are provided, and interlayer connection is made via heat dissipation vias, with ribs arranged in positions covering the bonding pads.

[0050] FIG. 4 is a cross-sectional view showing an example of the configuration of a package according to the second embodiment.

[0051] In the figure, the package 200 includes a package substrate 201, a chip 211, a transparent substrate 222, and a sealing material 224. In this case, the package 200 can form a hollow package in which the chip 211 is mounted.

[0052] The package substrate 201 can be a multilayer substrate. A chip 211 is mounted on the package substrate 201. Wiring 202, bonding pads 205, and land electrodes 209 are formed on the package substrate 201. The wiring 202 can be used as a signal line, a power line, or a ground line. The bonding pads 205 are arranged on the front surface of the package substrate 201. The land electrodes 209 are arranged on the back surface of the package substrate 201. In addition, vias 203 are formed in the package substrate 201 to perform interlayer connection of the package substrate 201. In this case, the vias 203 can perform interlayer connection of the wiring 202, the bonding pads 205, and the land electrodes 209.

[0053] The package substrate 201 also includes an upper thermally conductive layer 206 and a lower thermally conductive layer 207 as thermally conductive layers. The upper thermally conductive layer 206 and the bonding pads 205 are disposed on the same layer of the package substrate 201. In this case, the upper thermally conductive layer 206 and the bonding pads 205 may be disposed on the uppermost layer of the package substrate 201. The lower thermally conductive layer 207 can be disposed on a layer above the land electrodes 209. The lower thermally conductive layer 207 and the land electrodes 209 may be disposed on the same layer of the package substrate 201. In this case, the lower thermally conductive layer 207 and the land electrodes 209 may be disposed on the lowermost layer of the package substrate 201.

[0054] The upper thermally conductive layer 206 and the lower thermally conductive layer 207 can be formed at positions overlapping the entire back surface of the chip 211. The upper thermally conductive layer 206 extends to the outside of the back surface of the chip 211 so as to surround the periphery of the bonding pad 205. The lower thermally conductive layer 207 extends to the outside of the back surface of the chip 211. Here, an opening KD1 can be formed in the upper thermally conductive layer 206 around the bonding pad 205 to separate the bonding pad 205 from the upper thermally conductive layer 206 within the same layer. An opening KD2 can be formed in the lower thermally conductive layer 207 around the via 203 to separate the via 203 from the lower thermally conductive layer 207. The upper thermally conductive layer 206 and the lower thermally conductive layer 207 are connected to each other via a heat dissipation via 208.

[0055] Thermally conductive terminals 204 are formed on the side surfaces of the package substrate 201. The thermally conductive terminals 204 may be arranged at equal intervals along the four sides of the periphery of the package substrate 201. The thermally conductive terminals 204 may be connected to the upper thermally conductive layer 206 and the lower thermally conductive layer 207.

[0056] The chip 211 is mounted face up on the package substrate 201. The chip 211 may be bonded onto the upper thermally conductive layer 206 via a solder material, a paste material such as Ag paste, or a direct bond between the chip 211 and the upper thermally conductive layer 206.

[0057] The chip 211 is connected to the package substrate 201 via bonding wires 216. At this time, bonding pads 213 to which the bonding wires 216 are connected may be formed on the chip 211.

[0058] For example, a CMOS image sensor can be formed on the chip 211. In this case, a light receiving section 212 is provided on the chip 211. Pixels and pixel transistors are arranged in a matrix along the row and column directions in the light receiving section 212. A color filter 214 is formed for each pixel on the light receiving section 212. An on-chip lens 215 is formed for each pixel on the color filter 214.

[0059] The transparent substrate 222 is disposed on the chip 211. At this time, the transparent substrate 222 is supported on the package substrate 201 via the ribs 221 and is bonded to the package substrate 201.

[0060] The ribs 221 are located between the chip 211 and the transparent substrate 222. In this case, the ribs 221 can support the transparent substrate 222 on the chip 211. The ribs 221 can be arranged continuously along the outer periphery of the package substrate 201.

[0061] The encapsulant 224 encapsulates the chip 211 and the bonding wires 216 on the package substrate 201. The encapsulant 224 is formed on the package substrate 201 outside the chip 211 and the ribs 221. In this case, the encapsulant 224 can be continuously disposed in a position surrounding the outer periphery of the chip 211 and the ribs 221. The encapsulant 224 may be disposed in a position where the rear ends of the bonding wires 216 are embedded. The encapsulant 224 may contact the side surfaces of the transparent substrate 222. The material of the encapsulant 224 may be a thermosetting resin or an ultraviolet-curing resin. For example, the material of the encapsulant 224 may be a resin such as a siloxane-based resin, an acrylic-based resin, or an epoxy-based resin. The encapsulant 224 may contain an inorganic or organic filler to improve reliability. The filler material may be glass. The encapsulant 224 may be blackened or may be composed of an opaque layer to reduce flare on the light receiving unit 212. For example, the encapsulant 224 may contain a black pigment such as carbon black, or a filler such as carbon fiber. The material of the encapsulant 224 may be the same as or different from the material of the rib 221. In this case, the material of the encapsulant 224 may be selected so as to mitigate warpage of the package substrate 201, or so as to mitigate stress applied to the transparent substrate 222.

[0062] As described above, in the second embodiment, upper thermally conductive layer 206 and lower thermally conductive layer 207 having higher thermal conductivity than package substrate 201 are provided, and are connected to each other via heat dissipation vias 208, and ribs 224 are disposed in positions that cover bonding pads 213. This eliminates the need to form spaces between bonding pads 213 and ribs 224 on chip 211, making it possible to reduce the chip size without reducing the light-receiving area, and improving the heat dissipation performance of heat generated in chip 211.

[0063] 3. Third Embodiment In the first embodiment described above, upper thermally conductive layer 106A and lower thermally conductive layer 107 having higher thermal conductivity than BGA package substrate 101A are provided, and the layers are connected to each other via heat dissipation vias 108A. In this third embodiment, upper thermally conductive layer and lower thermally conductive layer having higher thermal conductivity than the package substrate of a ceramic package provided with a cavity are provided, and the layers are connected to each other via heat dissipation vias.

[0064] FIG. 5 is a cross-sectional view showing an example of the configuration of a package according to the third embodiment.

[0065] In the figure, the package 300 includes a package substrate 301 and a transparent substrate 322 instead of the package substrate 101A and the transparent substrate 122 of the first embodiment described above. The other configuration of the package 300 of the third embodiment is similar to the configuration of the package 100A of the first embodiment described above.

[0066] In the figure, a ceramic substrate can be used as the package substrate 301. The package substrate 301 is provided with a cavity CAV capable of accommodating the chip 111. The cavity CAV can be provided with a step. In this case, the chip 111 is mounted on the bottom level of the cavity CAV. The package substrate 301 is formed with wiring 302, bonding pads 305, and land electrodes 309. The wiring 302 can be used as a signal line, a power line, or a ground line. The bonding pads 305 can be arranged on the second level of the cavity CAV. The land electrodes 309 are arranged on the back surface of the package substrate 301. In addition, the package substrate 301 is formed with vias 303 for interlayer connection of the package substrate 301. In this case, the vias 303 can provide interlayer connection between the wiring 302, the bonding pads 305, and the land electrodes 309.

[0067] The package substrate 301 also includes an upper thermally conductive layer 306 and a lower thermally conductive layer 307 as thermally conductive layers. The upper thermally conductive layer 306 is disposed at the bottom of the cavity CAV. The lower thermally conductive layer 307 can be disposed above the land electrodes 309. The lower thermally conductive layer 307 and the land electrodes 309 may be disposed on the same layer of the package substrate 301. In this case, the lower thermally conductive layer 307 and the land electrodes 309 may be disposed on the bottom layer of the package substrate 301.

[0068] The upper thermally conductive layer 306 and the lower thermally conductive layer 307 can be formed at positions overlapping the entire back surface of the chip 111. The upper thermally conductive layer 306 and the lower thermally conductive layer 307 extend outside the back surface of the chip 311. An opening KE1 can be formed in the upper thermally conductive layer 306 around the via 303 to separate the via 303 from the upper thermally conductive layer 306. An opening KE2 can be formed in the lower thermally conductive layer 307 around the via 303 to separate the via 303 from the lower thermally conductive layer 307. The upper thermally conductive layer 306 and the lower thermally conductive layer 307 are connected to each other via a heat dissipation via 308.

[0069] Thermally conductive terminals 304 are formed on the side surfaces of the package substrate 301. The thermally conductive terminals 304 may be arranged at equal intervals along the four sides of the periphery of the package substrate 301. The thermally conductive terminals 304 may be connected to the upper thermally conductive layer 306 and the lower thermally conductive layer 307.

[0070] The transparent substrate 322 is disposed on the chip 111. At this time, the transparent substrate 322 can be bonded to the uppermost layer of the package substrate 301 via an adhesive layer 321. The adhesive layer 321 may be, for example, an epoxy resin.

[0071] As described above, in the third embodiment, upper thermally conductive layer 306 and lower thermally conductive layer 307, which have higher thermal conductivity than package substrate 301 of the ceramic package provided with cavity CAV, are provided, and are connected to each other through heat dissipation via 308. This improves the airtightness of package 300 and also improves the dissipation of heat generated by chip 311.

[0072] 4. Fourth Embodiment In the first embodiment described above, upper thermally conductive layer 106A and lower thermally conductive layer 107 having higher thermal conductivity than package substrate 101A are provided, and an interlayer connection is made via heat dissipation vias 108A, and transparent substrate 122 is disposed on chip 111. In this fourth embodiment, upper thermally conductive layer 106A and lower thermally conductive layer 107 having higher thermal conductivity than package substrate 101A are provided, and an interlayer connection is made via heat dissipation vias 108A, and the chip is sealed with a sealing material.

[0073] FIG. 6 is a cross-sectional view showing an example of the configuration of a package according to the fourth embodiment.

[0074] In the figure, package 400 includes a chip 411 and a sealing material 421 instead of chip 111, rib 121, and transparent substrate 122 of the first embodiment described above. The rest of the configuration of package 400 of the fourth embodiment is similar to the configuration of package 100A of the first embodiment described above.

[0075] The chip 411 is mounted face up on the package substrate 101A. The chip 411 may be bonded to the upper thermally conductive layer 106A via a solder material or a paste material such as Ag paste. The chip 411 and the upper thermally conductive layer 106A may also be bonded directly to each other.

[0076] The chip 411 is connected to the package substrate 101A via bonding wires 116. At this time, bonding pads 413 to which the bonding wires 116 are connected may be formed on the chip 411.

[0077] A circuit section 412 is formed on the chip 411. A semiconductor element can be formed on the circuit section 412. The semiconductor element may include an IC (Integrated Circuit), a transistor, a resistor, a capacitor, etc. The semiconductor element may include a memory, a processor, a signal processing circuit, a data processing circuit, an interface circuit, or a power semiconductor element such as an inverter. The semiconductor substrate used for the chip 411 may be Si, GaAs, SiC, GaN, InGaAs, InP, InGaAsP, or the like.

[0078] The encapsulant 421 encapsulates the chip 411 and the bonding wires 116 on the package substrate 101A. At this time, the encapsulant 421 can cover the chip 411 and the bonding wires 116 on the package substrate 101A. The surface of the encapsulant 421 may be flattened. The material of the encapsulant 421 may be a thermosetting resin or an ultraviolet curing resin. For example, the material of the encapsulant 421 may be a resin such as a siloxane resin, an acrylic resin, or an epoxy resin. The encapsulant 421 may be formed based on molding or potting.

[0079] Protruding electrodes 110 are formed on the land electrodes 109. The protruding electrodes 110 can be used as external connection terminals for connecting the package 400 to a motherboard or the like. The protruding electrodes 110 may be, for example, solder balls or pillar electrodes made of a conductor. In this case, the package 400 can be mounted on the motherboard via the protruding electrodes 110, for example, by solder reflow.

[0080] As described above, in the fourth embodiment, the upper thermally conductive layer 106A and the lower thermally conductive layer 107, which have higher thermal conductivity than the package substrate 101A, are provided, and are connected to each other via the heat dissipation vias 108A, and the chip 411 is sealed with the sealing material 421. This makes it possible to seal the chip 411 with the sealing material 421 while eliminating the need for a gap above the chip 411, thereby simplifying the manufacturing process and improving the dissipation of heat generated in the chip 411. 5. Fifth Embodiment In the first embodiment, the upper thermally conductive layer 106A and the lower thermally conductive layer 107, which have higher thermal conductivity than the package substrate 101A, are provided, and are connected to each other via the heat dissipation vias 108A. In the fifth embodiment, an upper thermally conductive layer 106A and a lower thermally conductive layer 107 having higher thermal conductivity than the package substrate 101A are provided, and are connected to each other via a heat dissipation via 108A, and a heat sink is bonded to the back surface of the package substrate 101A.

[0081] FIG. 7 is a cross-sectional view showing an example of the configuration of a package according to the fifth embodiment.

[0082] In the figure, a package 500 is obtained by adding a heat sink 503 to the package 100 of the first embodiment described above. The other configuration of the package 500 of the fifth embodiment is the same as the configuration of the package 100A of the first embodiment described above.

[0083] The package 500 is mounted on a motherboard 501. At this time, protruding electrodes 110 are formed on the land electrodes 109. Land electrodes 502 are formed on the motherboard 501. Then, by joining the protruding electrodes 110 to the land electrodes 502, the package 500 can be mounted on the motherboard 501.

[0084] A heat sink 503 is bonded to the back surface of the package substrate 101A. The heat sink 503 may be bonded to the back surface of the package substrate 101A so that the tip of the heat sink 503 penetrates the motherboard 501. In this case, the land electrodes 109, 502 may be arranged around the heat sink 503. The heat sink 503 may be provided with fins. The heat sink 503 may be made of a metal such as Cu or Al. The heat sink 503 may be bonded directly to the lower thermally conductive layer 107. In this case, a protective film such as a solder resist may be removed from on the lower thermally conductive layer 107.

[0085] Furthermore, a housing 505 is mounted on the motherboard 501. The housing 505 is joined to the thermal conduction terminals 104 of the package substrate 101A via joining members 504. The housing 505 may be in the shape of a rectangular tube. In this case, the housing 505 can be joined to the thermal conduction terminals 104 arranged along the four sides of the outer periphery of the package substrate 101A. In order to improve heat dissipation from the housing 505, it is desirable that the material of the housing 505 be a metal such as Cu, Al, or stainless steel.

[0086] As described above, in the fifth embodiment, the upper thermally conductive layer 106A and the lower thermally conductive layer 107, which have higher thermal conductivity than the package substrate 101A, are provided, and are connected to each other through the heat dissipation vias 108A, and the heat sink 503 is joined to the back surface of the package substrate 101A. This makes it possible to improve the dissipation of heat generated by the chip 111 without requiring any changes to the configuration of the package substrate 101A.

[0087] In the fifth embodiment described above, the thermally conductive terminals 104 of the package substrate 101A are joined to the housing 505, but the housing 505 may be a case for an electronic device such as a smartphone or a camera. This makes it possible to prevent the electronic device from becoming too large and dissipate heat generated by the chip 111 to the outside of the electronic device. The housing 505 may also be a lens barrel that supports optical components such as lenses and filters on the package 500.

[0088] 6. Sixth Embodiment In the above-described fifth embodiment, the housing 505 is joined to the thermal conduction terminals 104 of the package substrate 101A via the joining member 504. In this sixth embodiment, the thermal conduction terminals 104 of the package substrate 101A are joined to a housing that supports a lens.

[0089] FIG. 8 is a cross-sectional view showing an example of the configuration of a package according to the sixth embodiment.

[0090] In the figure, the package 100A is mounted on a motherboard 601. At this time, protruding electrodes 110 are formed on the land electrodes 109. Land electrodes 602 are formed on the motherboard 601. Then, by joining the protruding electrodes 110 to the land electrodes 602, the package 100A can be mounted on the motherboard 601.

[0091] A housing 605 is mounted on the motherboard 601. The housing 605 supports a lens 603 on the light receiving unit 112. The lens 603 focuses light incident on the light receiving unit 112. The housing 605 is joined to the heat conduction terminals 104 of the package substrate 101A via a joining member 604. The housing 605 may be in the shape of a rectangular tube. In this case, the housing 605 can be joined to the heat conduction terminals 104 on four surfaces on the periphery of the package substrate 101A. The material of the housing 605 may be, for example, stainless steel or aluminum die-cast.

[0092] As described above, in the sixth embodiment, the thermally conductive terminals 104 of the package substrate 101A are joined to the housing 605 that supports the lens 603. This allows the lens 603 to be supported on the light receiving unit 112 via the housing 605, while heat generated by the chip 111 can be dissipated from the housing 605 via the side surface of the package substrate 101A.

[0093] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0094] FIG. 9 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0095] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 9, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0096] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0097] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0098] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0099] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0100] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0101] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0102] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0103] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0104] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 9, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0105] FIG. 10 is a diagram showing an example of the installation position of the imaging unit 12031.

[0106] In FIG. 10, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0107] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0108] 10 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0109] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0110] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0111] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0112] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0113] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the drivetrain control unit 12010, body system control unit 12020, vehicle exterior information detection unit 12030, vehicle interior information detection unit 12040, integrated control unit 12050, and image capture unit 12031 among the above-described configurations. Specifically, for example, the package of the fourth embodiment described above can be applied to the drivetrain control unit 12010, body system control unit 12020, vehicle exterior information detection unit 12030, vehicle interior information detection unit 12040, and integrated control unit 12050. The package of any of the first to third, fifth, and sixth embodiments described above can be applied to the image capture unit 12031. Applying the technology disclosed herein to the vehicle control system 12000 can improve the heat dissipation performance of the package while suppressing an increase in package size, thereby improving package reliability.

[0114] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0115] The present technology can also be configured as follows. (1) A package comprising: a chip having external terminals used for signal transmission formed on its surface; a substrate on which the chip is mounted via the back surface of the chip; a plurality of thermally conductive layers arranged on different layers of the substrate and having a thermal conductivity higher than that of the substrate; and vias connecting the plurality of thermally conductive layers to each other. (2) The package according to (1), in which the vias are arranged at positions overlapping the chip. (3) The package according to (1) or (2), in which the vias are arranged at equal intervals across the entire back surface of the chip. (4) The package according to (1) or (2), in which the vias are arranged in accordance with the heat generation distribution of the chip. (5) The package according to any of (1) to (4), in which the external terminals include first bonding pads; the substrate has second bonding pads arranged around the chip; and the first bonding pads and the second bonding pads are connected to each other via bonding wires. (6) The package according to (5), wherein the plurality of thermally conductive layers include an upper thermally conductive layer and a lower thermally conductive layer, and the upper thermally conductive layer and the bonding pads are arranged on the same layer of the substrate. (7) The package according to (6), wherein the package includes land electrodes formed on the rear surface of the substrate, and the lower thermally conductive layer is arranged on a layer above the layer on which the land electrodes are formed. (8) The package according to any of (5) to (7), wherein the plurality of thermally conductive layers are formed in a position overlapping the entire rear surface of the chip. (9) The package according to (8), wherein the upper thermally conductive layer extends to the outside of the rear surface of the chip so as to surround the periphery of the second bonding pad. (10) The package according to (9), wherein the package includes terminals provided on side surfaces of the substrate and having a higher thermal conductivity than the substrate, and the thermally conductive layers are connected to the terminals. (11) The package according to (10), further including a housing joined to the terminals via a joining member. (12) The package according to (11), wherein the chip includes a light receiving portion that receives light, and further includes a lens supported on the light receiving portion via the housing.(13) The package according to any one of (5) to (12), further comprising: an encapsulant that encapsulates the chip and the bonding wires on the substrate. (14) The package according to any one of (1) to (12), further comprising: a transparent substrate disposed on the chip; and ribs that support the transparent substrate on the chip. (15) The package according to any one of (1) to (14), further comprising: a heat sink bonded to the back surface of the substrate.

[0116] 100A Package 101A Package substrate 102 Wiring 103 Via 104 Thermal conduction terminal 105, 113 Bonding pad 106A Upper thermal conduction layer 107 Lower thermal conduction layer 108A Heat dissipation via 109 Land electrode 111 Sensor chip 112 Light receiving section 114 Color filter 115 On-chip lens 116 Bonding wire 121 Sealant 122 Transparent substrate

Claims

1. A package comprising: a chip having external terminals used for signal transmission formed on its surface; a substrate on which the chip is mounted via the back surface of the chip; a plurality of thermally conductive layers arranged on different layers of the substrate and having a higher thermal conductivity than the substrate; and vias connecting the plurality of thermally conductive layers to each other.

2. The package according to claim 1, wherein the via is positioned so as to overlap the chip.

3. The package of claim 1, wherein the vias are evenly spaced across the entire backside of the chip.

4. The package according to claim 1, wherein the vias are arranged in accordance with the heat distribution of the chip.

5. The package according to claim 1, wherein the external terminals include first bonding pads, the substrate has second bonding pads arranged around the chip, and the first bonding pads and the second bonding pads are connected to each other via bonding wires.

6. The package according to claim 5, wherein the plurality of thermally conductive layers comprises an upper thermally conductive layer and a lower thermally conductive layer, and the upper thermally conductive layer and the bonding pad are disposed on the same layer of the substrate.

7. The package according to claim 6, further comprising land electrodes formed on the rear surface of the substrate, and the lower thermal conductive layer is disposed above the layer on which the land electrodes are formed.

8. The package according to claim 5, wherein the plurality of thermally conductive layers are formed in positions that overlap the entire back surface of the chip.

9. The package according to claim 8, wherein the upper thermally conductive layer extends to the outside of the back surface of the chip so as to surround the periphery of the second bonding pad.

10. The package according to claim 9, further comprising a terminal provided on a side surface of the substrate and having a thermal conductivity higher than that of the substrate, the thermally conductive layer being connected to the terminal.

11. The package according to claim 10, further comprising a housing joined to the terminals via a joining member.

12. The package according to claim 11, wherein the chip comprises a light receiving portion for receiving light, and further comprises a lens supported on the light receiving portion via the housing.

13. The package of claim 5, further comprising an encapsulant that encapsulates the chip and the bonding wires on the substrate.

14. The package of claim 1, further comprising: a transparent substrate disposed over the chip; and ribs supporting the transparent substrate over the chip.

15. The package of claim 1 further comprising a heat sink bonded to the backside of the substrate.

Images