Semiconductor manufacturing device-use member and method for manufacturing same

Abstract

Provided is a method for manufacturing a second semiconductor manufacturing device-use member using a first semiconductor manufacturing device-use member as a raw material. The method is for manufacturing a second semiconductor manufacturing device-use member by using a first semiconductor manufacturing device-use member provided with a first ceramic substrate that has an upper surface with a plurality of protrusions on which a wafer can be placed and that has a built-in electrode, said second semiconductor manufacturing device-use member being provided with a second ceramic substrate that has an upper surface with a plurality of protrusions on which a wafer can be placed and that has a built-in electrode. Said method comprises: a step A in which the upper surface of the first ceramic substrate is processed to form a flat surface from which the plurality of protrusions are removed; a step B1 in which the flat surface of the first ceramic substrate and a lower surface of a ceramic plate are bonded at room temperature to form a second ceramic substrate in which the first ceramic substrate and the ceramic plate are bonded; and a step C in which, before or after the execution of the step B1, a plurality of protrusions on which a wafer can be placed are formed on the upper surface of the ceramic plate.

Description

Semiconductor manufacturing equipment components and manufacturing method thereof

[0001] The present invention relates to a semiconductor manufacturing equipment member and a method for manufacturing the semiconductor manufacturing equipment member.

[0002] Conventionally, semiconductor manufacturing equipment components have been known that are used for wafer holding, temperature control, transport, etc. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract a wafer by electrostatic force.

[0003] A known example of a semiconductor manufacturing equipment component is a ceramic substrate having an upper surface on which a wafer can be placed and a lower surface, and incorporating electrodes, and a base plate located on the lower surface of the ceramic substrate and incorporating a coolant flow path. The upper surface on which the wafer can be placed is provided with multiple protrusions for supporting the wafer.

[0004] Such protrusions are generally very small, and when dry cleaning is performed using plasma, the ceramic particles that make up the protrusions may fall off, i.e., shedding may occur. The fallen ceramic particles may cause contamination of wafers, etc. Therefore, Patent Document 1 describes that the size and surface roughness of the ceramic particles that make up the protrusions are controlled to prevent the ceramic particles from falling off.

[0005] Japanese Patent Application Laid-Open No. 2023-31112

[0006] The ceramic particles that make up the protrusions can fall off not only during dry cleaning processes, but also when a wafer is electrostatically attracted to an electrostatic chuck, or when the wafer slides due to thermal expansion while in contact with the protrusions. While particle shedding can occur due to a combination of factors, such as wear and corrosion, it is inevitable that semiconductor manufacturing equipment components will fall off over long periods of use. Furthermore, factors other than particle shedding can also cause the protrusions to deteriorate, resulting in a decline in the performance of the semiconductor manufacturing equipment components.

[0007] When the quality of semiconductor manufacturing equipment components deteriorates, the deteriorated semiconductor manufacturing equipment components can be discarded. However, from the perspective of reducing waste, making effective use of resources, and promoting a circular economy, it is desirable to be able to repair and reuse semiconductor manufacturing equipment components.

[0008] In view of the above circumstances, an object of the present invention is to provide, in one embodiment, a method for manufacturing a second semiconductor manufacturing equipment member using the first semiconductor manufacturing equipment member as a raw material. Also, an object of the present invention is to provide, in another embodiment, a semiconductor manufacturing equipment member that can be manufactured by the manufacturing method according to one embodiment of the present invention.

[0009] The present inventors conducted extensive research to solve the above-mentioned problems and have created the present invention, as exemplified below. [Aspect 1] A method for manufacturing a second semiconductor manufacturing equipment member having a second ceramic substrate having an upper surface with a plurality of protrusions on which a wafer can be mounted and a built-in electrode, using a first semiconductor manufacturing equipment member including a first ceramic substrate having an upper surface with a plurality of protrusions on which a wafer can be mounted and a built-in electrode, the method comprising: Step A: processing the upper surface of the first ceramic substrate to form a flat surface from which the plurality of protrusions have been removed; Step B1: room-temperature bonding the flat surface of the first ceramic substrate to the lower surface of a ceramic plate to form a second ceramic substrate in which the first ceramic substrate and the ceramic plate are bonded; and Step C: forming, before or after Step B1, a plurality of protrusions on which a wafer can be mounted, on the upper surface of the ceramic plate. [Aspect 2] The manufacturing method according to [Aspect 1], wherein the ceramic plate contains the same ceramic material as the ceramic constituting the first ceramic substrate. [Aspect 3] The manufacturing method according to [Aspect 1] or [Aspect 2], wherein the ceramic plate and the first ceramic substrate both contain one or two types selected from aluminum oxide and aluminum nitride. [Aspect 4] The manufacturing method according to any one of [Aspects 1] to [Aspect 3], wherein the lower surface of the ceramic plate and the flat surface of the first ceramic substrate are joined via an amorphous layer. [Aspect 5] The manufacturing method according to any one of [Aspects 1] to [Aspect 4], wherein the arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate.[Aspect 6] A method for manufacturing a second semiconductor manufacturing equipment member having a second ceramic substrate having an upper surface with a plurality of protrusions on which a wafer can be mounted and an electrode built-in, using a first semiconductor manufacturing equipment member having a first ceramic substrate having an upper surface with a plurality of protrusions on which a wafer can be mounted and an electrode built-in, the method comprising: Step A: processing the upper surface of the first ceramic substrate to form a flat surface from which the plurality of protrusions have been removed; and Step B2: room-temperature bonding the flat surface of the first ceramic substrate to lower end surfaces of a plurality of protrusion-forming components to form a second ceramic substrate in which the first ceramic substrate and the plurality of protrusion-forming components are bonded. [Aspect 7] The manufacturing method according to [Aspect 6], wherein the plurality of protrusion-forming components contain the same ceramic material as the ceramic constituting the first ceramic substrate. [Aspect 8] The manufacturing method according to [Aspect 6] or [Aspect 7], wherein the plurality of protrusion-forming components and the first ceramic substrate both contain one or two types selected from aluminum oxide and aluminum nitride. [Aspect 9] The manufacturing method according to any one of [Aspects 6] to [Aspect 8], wherein the lower end surface of the component for forming the plurality of protrusions and the flat surface of the first ceramic substrate are joined via an amorphous layer. [Aspect 10] The manufacturing method according to any one of [Aspects 6] to [Aspect 9], wherein the arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate. [Aspect 11] A component for semiconductor manufacturing equipment, comprising: a ceramic substrate having an electrode built in; and a ceramic plate having a lower surface joined to the upper surface of the ceramic substrate via an amorphous layer, and an upper surface having a plurality of protrusions on which a wafer can be placed. [Aspect 12] A component for semiconductor manufacturing equipment, comprising: a ceramic substrate having an electrode built in; and a plurality of protrusions having a lower surface joined to the upper surface of the ceramic substrate via an amorphous layer, and an upper surface for placing a wafer. [Embodiment 13] The semiconductor manufacturing equipment member according to [Embodiment 11], wherein the ceramic plate contains the same material as the ceramic that constitutes the ceramic substrate.[Aspect 14] The semiconductor manufacturing equipment member according to [Aspect 12], wherein the plurality of protrusions contain the same material as the ceramic that constitutes the ceramic substrate. [Aspect 15] The semiconductor manufacturing equipment member according to [Aspect 11] or [Aspect 13], wherein the ceramic plate and the ceramic substrate both contain one or two types selected from aluminum oxide and aluminum nitride. [Aspect 16] The semiconductor manufacturing equipment member according to [Aspect 12] or [Aspect 14], wherein the plurality of protrusions and the ceramic substrate both contain one or two types selected from aluminum oxide and aluminum nitride.

[0010] According to a method for manufacturing a semiconductor manufacturing equipment member according to one embodiment of the present invention, a second semiconductor manufacturing equipment member can be manufactured using a first semiconductor manufacturing equipment member as a raw material. Therefore, even if the quality of the first semiconductor manufacturing equipment member deteriorates due to, for example, shedding of ceramic particles that form the protrusions on the wafer mounting surface, it is not necessary to manufacture a new semiconductor manufacturing equipment member from scratch. Therefore, this manufacturing method significantly contributes to reducing waste, making effective use of resources, and promoting a circular economy.

[0011] 1B is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to embodiment A of the present invention (a partial sectional view when cut along a plane including the central axis of the semiconductor manufacturing equipment member). FIG. 1C is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to embodiment B of the present invention (a partial sectional view when cut along a plane including the central axis of the semiconductor manufacturing equipment member). FIG. 1A is a schematic partial enlarged view of the vicinity of the area surrounded by the thick frame shown in FIG. 1B. FIG. 1B is a schematic partial enlarged view of the vicinity of the area surrounded by the thick frame shown in FIG. 1C. FIG. 1C is a schematic plan view of a wafer mounting surface of a ceramic substrate according to embodiment A of the present invention. FIG. 1D is a schematic plan view of a wafer mounting surface of a ceramic substrate according to embodiment B of the present invention. FIG. 1E is a manufacturing process diagram of a semiconductor manufacturing equipment member according to embodiment A of the present invention. FIG. 1F is a manufacturing process diagram of a semiconductor manufacturing equipment member according to embodiment B of the present invention. FIG. 1G is a schematic perspective view of a polishing apparatus for performing lapping.

[0012] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when the semiconductor manufacturing equipment component's ceramic substrate is placed on a horizontal surface with the upper surface facing up, and do not represent absolute positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0013] 1. Configuration of a Semiconductor Manufacturing Equipment Member (1-1. Embodiment A) Referring to the partial vertical cross-sectional view shown in FIG. 1A, a semiconductor manufacturing equipment member 10A according to embodiment A of the present invention can be used when performing processes such as CVD and etching on a wafer W using plasma. The semiconductor manufacturing equipment member 10A includes a ceramic substrate 20 incorporating an electrode 26a, and a ceramic plate 70 having a lower surface 73 bonded to an upper surface 21 of the ceramic substrate 20 via an amorphous layer 80, and an upper surface 71 with a plurality of protrusions 72 on which a wafer W can be placed. The semiconductor manufacturing equipment member 10A also includes a base plate 30 located on the lower surface 23 side of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded to each other via a bonding layer 40.

[0014] The ceramic substrate 20 includes a central portion 20a having a circular upper surface 21 in a planar view, and an outer peripheral portion 20b having an annular upper surface 27 in a planar view, surrounding the central portion 20a. The central portion 20a of the ceramic substrate 20 may have a diameter of 130 to 450 mm and a thickness of 1 to 5 mm, for example. A wafer W can be placed on the upper surface 71 of a ceramic plate 70 bonded to the upper surface 21 of the central portion 20a. A focus ring (not shown) can be placed on the upper surface 27 of the outer peripheral portion 20b of the ceramic substrate 20. The upper surface 27 of the outer peripheral portion 20b is one step lower than the upper surface 21 of the central portion 20a. The central portion 20a and the lower surface 23 of the outer peripheral portion 20b may be flush with each other. The illustrated ceramic substrate 20 may have the central portion 20a but not the outer peripheral portion 20b, i.e., it may not have the one-step lower upper surface 27.

[0015] The upper surface 71 of the ceramic plate 70 is provided with a plurality of protrusions 72 for placing the wafer W thereon. The upper surface 71 may also have a seal band 75 formed along its outer edge. In this case, the wafer W may be supported by an upper end surface 71c of the seal band 75 and upper end surfaces 71a of the plurality of protrusions 72. It is preferable that the seal band 75 and the plurality of protrusions 72 have the same height. As shown in FIG. 3A , in one embodiment, the upper surface 71 of the ceramic plate 70 is formed with an annular seal band 75 along its outer edge, and a plurality of protrusions 72 are formed over the entire inner surface of the seal band 75.

[0016] 2A is a schematic enlarged partial view of the vicinity of the area surrounded by the thick frame shown in FIG. 1A, and shows a schematic structure of protrusions 72 provided on the upper surface 71 of the ceramic plate 70. The number density per unit area of ​​the protrusions 72 in a plan view is, for example, 1 to 150 pieces / mm 2 and the number of particles per mm can be set to 10 to 150. 2The shape of the protrusions 72 is not limited, but may be, for example, a columnar shape such as a cylinder or a rectangular pillar. The height h of the protrusions 72 is, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 72 is, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm. Here, the diameter d of the protrusions 72 refers to the circle-equivalent diameter when the protrusions 72 are viewed in plan. The portion of the upper surface 71 of the ceramic plate 70 on which the seal band 75 and the protrusions 72 are not provided is referred to as the reference surface 71b.

[0017] At least the upper end surfaces 71 a of the plurality of protrusions 72 may be coated with a coating film. Similarly, at least the upper end surface 71 c of the seal band 75 may be coated with a coating film. Examples of the coating film include a coating film containing at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0018] From the viewpoint of improving thermal shock resistance by bringing the thermal expansion coefficients closer together, it is desirable that the ceramic plate 70 contain the same material as the ceramic constituting the ceramic substrate 20. Specifically, in one embodiment, the ceramic plate 70 and the ceramic substrate 20 both contain one or two types selected from aluminum oxide (alumina) and aluminum nitride. In a preferred embodiment, the ceramic plate 70 and the ceramic substrate 20 both contain 80 mass % or more of one or two types selected from aluminum oxide and aluminum nitride. In an even more preferred embodiment, the ceramic plate 70 and the ceramic substrate 20 both contain 95 mass % or more of one or two types selected from aluminum oxide and aluminum nitride.

[0019] The upper surface 21 of the ceramic substrate 20 and the lower surface 73 of the ceramic plate 70 can be bonded via an amorphous layer 80. In this case, the amorphous layer 80 preferably contains at least one element constituting the ceramic substrate 20 and at least one element constituting the ceramic plate 70.

[0020] When a longitudinal cross section of the semiconductor manufacturing equipment member 10A near the interface between the ceramic substrate 20 and the ceramic plate 70 is observed with a transmission electron microscope (TEM) at 4,000,000 magnification, the amorphous layer 80 is observed as a thin band-like portion. The amorphous layer 80 may be formed as a single layer or as multiple layers (e.g., three layers). The average thickness of the amorphous layer 80 is preferably 0.1 nm or more, more preferably 1 nm or more, to enhance the bonding strength between the ceramic substrate 20 and the ceramic plate 70. Furthermore, the average thickness of the amorphous layer 80 is preferably 30 nm or less, more preferably 20 nm or less, to prevent the incorporation of different materials. Therefore, the average thickness of the amorphous layer 80 is preferably, for example, 0.1 nm or more to 30 nm or less, more preferably 1 nm or more to 20 nm or less. When the amorphous layer 80 is composed of multiple layers, the thickness of the amorphous layer 80 refers to the total thickness of the multiple layers.

[0021] The average thickness of the amorphous layer 80 at the bonding interface between the ceramic plate 70 and the ceramic substrate 20 is measured by TEM observation using the following procedure. On a TEM photograph (magnification: 4,000,000 times) of one field of view in a vertical cross section including the bonding interface, the thickness of the amorphous layer 80 is measured at five locations at 10 nm intervals along the bonding interface, and the average thickness of the amorphous layer in one field of view is calculated. This thickness measurement by TEM observation is performed on three fields of view: near the center, near the outer periphery, and near the center of the radius when the ceramic plate 70 is viewed in plan. The average thickness of the amorphous layer 80 in the three fields of view is then taken as the measured value.

[0022] The fact that the thin band-shaped portion observed by TEM is an amorphous layer 80 can be confirmed by the fact that, when an X-ray diffraction pattern is obtained by XRD, a broader peak is observed inside the thin band-shaped portion than in the portion of the ceramic substrate 20 and the ceramic plate 70 that is sufficiently distant from the bonding interface.

[0023] The fact that the amorphous layer 80 contains at least one element constituting the ceramic substrate 20 and at least one element constituting the ceramic plate 70 can be confirmed by methods such as EDS (Energy Dispersive X-ray Spectroscopy) and EPMA (Electron Probe Micro Analyzer). In a preferred embodiment, the amorphous layer 80 contains at least one amorphous material (e.g., amorphous aluminum nitride, amorphous alumina, etc.) constituting the ceramic substrate 20 and the ceramic plate 70.

[0024] In this way, the semiconductor manufacturing equipment member 10A according to one embodiment of the present invention can make the bonding layer (amorphous layer 80) between the ceramic substrate 20 and the ceramic plate 70 extremely thin, thereby reducing the thermal resistance between the ceramic substrate 20 and the ceramic plate 70.

[0025] The electrode 26a is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26a is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed midway along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26a, the wafer W is attracted and fixed to the wafer mounting surface, specifically, the upper end surface 71c of the seal band 75 and the upper end surface 71a of the protrusion 72, by electrostatic attraction. When the application of the DC voltage is stopped, the wafer W is released from the wafer mounting surface.

[0026] Instead of or in addition to the electrode for electrostatic attraction, a heater electrode (resistance heating element) 26b or an RF electrode for plasma generation may be built in. In this case, a heater power supply is connected to the heater electrode 26b, and an RF power supply is connected to the RF electrode. The ceramic substrate 20 may have one layer of electrodes built in, or two or more layers of electrodes spaced apart.

[0027] The base plate 30 may be, for example, disk-shaped. The base plate 30 may have an annular flange portion on its lower surface that is used to clamp the semiconductor manufacturing equipment member 10A to a jig inside the chamber. The thickness of the base plate 30 may be 20 to 40 mm, typically 25 to 35 mm. The base plate 30 is connected to a radio frequency (RF) power source and can also be used as an RF electrode.

[0028] The base plate 30 may be a circular plate (having the same diameter as or larger than the ceramic substrate 20) with good electrical and thermal conductivity. A refrigerant flow path 32 through which a refrigerant circulates may be formed within the base plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include a fluorine-based inert liquid. The refrigerant flow path 32 may be formed, for example, in a single stroke across the entire base plate 30 in a plan view from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port of an external refrigerant device (not shown), respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0029] The base plate 30 can be made of, for example, a metal material or a composite material of metal and ceramic. Examples of metal materials include Al, Ti, Mo, and alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also known as SiSiCTi), a material in which porous SiC is impregnated with Al and / or Si, and a composite material of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient similar to that of the material for the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, the base plate 30 is preferably made of SiSiCTi or AlSiC, which have a thermal expansion coefficient similar to that of alumina.

[0030] As shown in FIG. 1A , the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be formed, for example, by a metal layer made of solder or a metal brazing material. The bonding layer 40 may be formed, for example, by thermal compression bonding (TCB). TCB refers to a known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of the metal layer. The resin bonding layer may be formed, for example, by a cured product of a silicone resin adhesive, an epoxy resin adhesive, an acrylic resin adhesive, or a urethane resin adhesive.

[0031] At least one of the side surface of the ceramic substrate 20, the outer periphery of the bonding layer 40, and the side surface of the base plate 30 can be covered with an insulating film 35. The insulating film 35 may be, for example, a thermally sprayed film of alumina, yttria, or the like.

[0032] In the above-described embodiment, the semiconductor manufacturing equipment member 10A may have a plurality of holes penetrating the ceramic plate 70 and the ceramic substrate 20 in the vertical direction. Examples of such holes include a plurality of gas holes 50 opening in the upper surface 71 and lift pin holes for inserting lift pins that move the wafer W up and down relative to the upper surface 21. A plurality of gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see FIG. 3A ). The gas holes 50 communicate with a gas flow path provided inside the base plate 30 and can supply a thermally conductive gas, such as He gas, that has passed through the gas flow path. Typically, the gas holes 50 can be provided so as to open to a portion of the upper surface 71 where the seal band 75 and the plurality of protrusions 72 are not provided (reference surface 71b). Furthermore, the gas holes 50 are formed at a position that does not overlap with the electrode 26. When a thermally conductive gas is supplied to the gas holes 50, the thermally conductive gas fills the space on the backside of the wafer W placed on the upper surface 71. A plug 55 having a gas flow path may be embedded in the gas hole 50. A plurality of lift pin holes may be provided at equal intervals along concentric circles on the upper surface 71 when the upper surface 71 is viewed in plan view.

[0033] (1-2. Embodiment B) Referring to the partial vertical cross-sectional view shown in FIG. 1B, a semiconductor manufacturing equipment member 10B according to embodiment B of the present invention can also be used when performing processes such as CVD and etching on a wafer W using plasma. The semiconductor manufacturing equipment member 10B includes a ceramic substrate 20 incorporating an electrode 26a, a lower end surface 92b bonded to the upper surface 21 of the ceramic substrate 20 via an amorphous layer 80, and a plurality of protrusions 92 each having an upper end surface 92a on which the wafer W is placed. The semiconductor manufacturing equipment member 10B also includes a base plate 30 located on the lower surface 23 of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded to each other via a bonding layer 40.

[0034] The ceramic substrate 20 includes a central portion 20a having a circular upper surface 21 in a planar view, and an outer peripheral portion 20b having an annular upper surface 27 in a planar view, surrounding the central portion 20a. The central portion 20a of the ceramic substrate 20 may have a diameter of 190 to 450 mm and a thickness of 1 to 5 mm, for example. A wafer W can be placed on the upper end surfaces 92a of multiple protrusions 92 bonded to the upper surface 21 of the central portion 20a. A focus ring (not shown) can be placed on the upper surface 27 of the outer peripheral portion 20b of the ceramic substrate 20. The upper surface 27 of the outer peripheral portion 20b is one step lower than the upper surface 21 of the central portion 20a. The central portion 20a and the lower surface 23 of the outer peripheral portion 20b may be flush with each other. The illustrated ceramic substrate 20 may have a central portion 20a but no outer peripheral portion 20b, i.e., it may not have the one-step lower upper surface 27.

[0035] A plurality of protrusions 92 for placing a wafer W are bonded to the upper surface 21 of the ceramic substrate 20 via an amorphous layer 80. A seal band 95 formed along the outer edge of the upper surface 21 may also be bonded to the upper surface 21 via the amorphous layer 80. In this case, the wafer W may be supported by an upper end surface 95a of the seal band 95 and upper end surfaces 92a of the plurality of protrusions 92. It is preferable that the seal band 95 and the plurality of protrusions 92 have the same height. As shown in FIG. 3B , in one embodiment, an annular seal band 95 is bonded to the upper surface 21 of the ceramic substrate 20 along the outer edge, and a plurality of protrusions 92 are bonded to the entire inner surface of the seal band 95.

[0036] 2B is a schematic enlarged partial view of the vicinity of the area surrounded by the thick frame shown in FIG. 1B, and shows a schematic structure of the protrusions 92 bonded to the upper surface 21 of the ceramic substrate 20. The number density per unit area of ​​the protrusions 92 in a plan view is, for example, 1 to 150 pieces / mm 2 and the number of particles per mm can be set to 10 to 150. 2The shape of the protrusions 92 is not limited, but may be, for example, a columnar shape such as a cylinder or a rectangular pillar. The height h of the protrusions 92 may be, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 92 may be, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm. Here, the diameter d of the protrusions 92 refers to the circle-equivalent diameter when the protrusions 92 are viewed in plan.

[0037] At least the upper end surfaces 92a of the plurality of protrusions 92 may be coated with a coating film. Similarly, at least the upper end surface 95a of the seal band 95 may be coated with a coating film. Examples of the coating film include a coating film containing at least one selected from silicon carbide, diamond-like carbon, amorphous silicon, molybdenum, chromium, and tantalum.

[0038] From the viewpoint of improving thermal shock resistance by bringing the thermal expansion coefficients closer together, it is desirable that the multiple protrusions 92 contain the same material as the ceramic constituting the ceramic substrate 20. Similarly, it is desirable that the seal band 95 also contain the same material as the ceramic constituting the ceramic substrate 20. Specifically, in one embodiment, the protrusions 92 and the ceramic substrate 20 all contain one or two types selected from aluminum oxide (alumina) and aluminum nitride. In another embodiment, the protrusions 92, the seal band 95, and the ceramic substrate 20 all contain one or two types selected from aluminum oxide (alumina) and aluminum nitride. In a preferred embodiment, the protrusions 92 and the ceramic substrate 20 all contain 80 mass% or more of one or two types selected from aluminum oxide and aluminum nitride. In another preferred embodiment, the protrusions 92, the seal band 95, and the ceramic substrate 20 all contain 80 mass% or more of one or two types selected from aluminum oxide and aluminum nitride. In an even more preferred embodiment, the protrusions 92 and the ceramic substrate 20 contain 95 mass % or more of one or two selected from aluminum oxide and aluminum nitride. In another even more preferred embodiment, the protrusions 92, the seal bands 95, and the ceramic substrate 20 contain 95 mass % or more of one or two selected from aluminum oxide and aluminum nitride.

[0039] The upper surface 21 of the ceramic substrate 20 and the lower end surfaces 92b of the plurality of protrusions 92 can be bonded via an amorphous layer 80. In this case, it is preferable that the amorphous layer 80 contains at least one element constituting the ceramic substrate 20 and at least one element constituting the plurality of protrusions 92. Similarly, the upper surface 21 of the ceramic substrate 20 and the lower end surface 95b of the seal band 95 can be bonded via an amorphous layer 80. In this case, it is preferable that the amorphous layer 80 contains at least one element constituting the ceramic substrate 20 and at least one element constituting the seal band 95.

[0040] When a longitudinal cross section of the semiconductor manufacturing equipment member 10A near the interface between the ceramic substrate 20 and the plurality of protrusions 92 or seal bands 95 is observed with a transmission electron microscope (TEM) at 4,000,000 magnification, the amorphous layer 80 is observed as a thin band-like portion. The amorphous layer 80 may be formed as a single layer or as multiple layers (e.g., three layers). The average thickness of the amorphous layer 80 is preferably 0.1 nm or more, more preferably 1 nm or more, to enhance the bonding strength between the ceramic substrate 20 and the plurality of protrusions 92 or seal bands 95. Furthermore, the average thickness of the amorphous layer 80 is preferably 30 nm or less, more preferably 20 nm or less, to prevent the inclusion of different materials. Therefore, the average thickness of the amorphous layer 80 is preferably, for example, 0.1 nm or more to 30 nm or less, more preferably 1 nm or more to 20 nm or less. When the amorphous layer 80 is made up of a plurality of layers, the thickness of the amorphous layer 80 refers to the total thickness of the plurality of layers.

[0041] The average thickness of the amorphous layer 80 at the bonding interface between each protrusion 92 and the ceramic substrate 20 is measured by TEM observation using the following procedure. A TEM photograph is obtained of a vertical cross section including the bonding interface near the center of the protrusion 92 in a plan view of the protrusion 92 being measured. Next, the thickness of the amorphous layer 80 is measured at three locations at 10 nm intervals along the bonding interface on a TEM photograph (magnification: 4,000,000 times) of one field of view, and the average value of the amorphous layer thickness in one field of view is calculated and used as the measured value.

[0042] The average thickness of the amorphous layer 80 at the bonding interface between the seal band 95 and the ceramic substrate 20 is measured by TEM observation using the following procedure. On a TEM photograph (magnification: 4,000,000 times) of one field of view in a vertical cross section including the bonding interface, the thickness of the amorphous layer 80 is measured at five locations at 10 nm intervals along the bonding interface, and the average thickness of the amorphous layer in one field of view is calculated. This thickness measurement by TEM observation is performed on three fields of view at equal intervals (every 120°) around the circumferential direction of the seal band 95. The average thickness of the amorphous layer 80 in the three fields of view is then taken as the measured value.

[0043] The fact that the thin band-shaped portion observed by TEM is an amorphous layer 80 can be confirmed by the fact that, when an X-ray diffraction pattern is obtained by XRD, a broader peak is observed inside the thin band-shaped portion than in the portion of the ceramic substrate 20 and the protrusion 92 (seal band 95) that is sufficiently distant from the bonding interface.

[0044] The fact that the amorphous layer 80 contains at least one element constituting the ceramic substrate 20 and at least one element constituting the plurality of protrusions 92 (or seal bands 95) can be confirmed by methods such as EDS (Energy Dispersive X-ray Spectroscopy) and EPMA (Electron Probe Micro Analyzer). In a preferred embodiment, the amorphous layer 80 contains at least one amorphous material (e.g., amorphous aluminum nitride, amorphous alumina, etc.) constituting the ceramic substrate 20 and the plurality of protrusions 92 (or seal bands 95).

[0045] In this way, the semiconductor manufacturing equipment member 10B according to one embodiment of the present invention can make the bonding layer (amorphous layer 80) between the ceramic substrate 20 and the plurality of protrusions 92 (or seal bands 95) extremely thin, thereby reducing the thermal resistance between the ceramic substrate 20 and the plurality of protrusions 92 (or seal bands 95).

[0046] The other components, such as the electrodes 26a and 26b, the base plate 30, and the bonding layer 40, are the same as those described in embodiment A, and therefore, redundant description will be omitted.

[0047] 2. Manufacturing Method of Semiconductor Manufacturing Equipment Members According to one embodiment of the present invention, there is provided a method for manufacturing a second semiconductor manufacturing equipment member having a second ceramic substrate with an upper surface having a plurality of protrusions (second plurality of protrusions) on which a wafer can be mounted and with a built-in electrode, using a first semiconductor manufacturing equipment member having a first ceramic substrate with an upper surface having a plurality of protrusions (first plurality of protrusions) on which a wafer can be mounted and with a built-in electrode. In one embodiment, the second semiconductor manufacturing equipment member corresponds to semiconductor manufacturing equipment member 10A according to embodiment A. In another embodiment, the second semiconductor manufacturing equipment member corresponds to semiconductor manufacturing equipment member 10B according to embodiment B.

[0048] (2-1. Manufacturing Method of a Semiconductor Manufacturing Equipment Member According to Embodiment A) A manufacturing method of a semiconductor manufacturing equipment member according to embodiment A will be described by way of example with reference to FIG. 4A.

[0049] First, a first semiconductor manufacturing equipment member 100 is prepared. Any known semiconductor manufacturing equipment member can be used as the first semiconductor manufacturing equipment member 100. The first semiconductor manufacturing equipment member 100 has an upper surface 22 with a plurality of protrusions 22a (first plurality of protrusions) on which a wafer W can be placed, and includes a first ceramic substrate 120 with built-in electrodes 26a. The first semiconductor manufacturing equipment member 100 may be either an unused product or a used product (one that has been used in a semiconductor manufacturing process). The first semiconductor manufacturing equipment member 100 is typically a used product, for example, one in which the quality of the protrusions 22a is lower than that of an unused product, or an unused, defective product that does not exhibit the desired characteristics.

[0050] The first ceramic substrate 120 can be manufactured by a manufacturing method including, for example, the steps of: preparing a ceramic powder compact having an electrode built in; preparing a ceramic sintered body by hot-press sintering the compact; and providing a plurality of protrusions on the upper surface of the ceramic sintered body by laser processing or blasting. The above-mentioned compact may be manufactured by stacking a plurality of tape compacts, by mold casting, or by compressing ceramic powder.

[0051] The first semiconductor manufacturing equipment member 100 can also have a base plate 30 bonded to the underside of the first ceramic substrate 120 via a bonding layer 40. Methods for bonding the first ceramic substrate 120 and the base plate 30 include, but are not limited to, thermal compression bonding (TCB). Metal bonding materials such as Al-Mg bonding materials and Al-Si-Mg bonding materials can be used as the bonding material for forming the bonding layer 40. When TCB is performed using an Al-Si-Mg bonding material, the stack is pressurized while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of approximately 100 μm.

[0052] The base plate 30 may also include a coolant flow path 32. The base plate 30 including the coolant flow path 32 can be manufactured, for example, by joining a plurality of MMC plate members, in which grooves and holes corresponding to the coolant flow paths 32 have been formed by machining, using a method such as TCB (thermal compression bonding). A gas flow path may be formed that penetrates the base plate 30 from the top surface to the bottom surface and has an opening on the bottom surface. The gas flow path can be formed by machining the base plate 30 after the coolant flow paths 32 have been formed.

[0053] As the first semiconductor manufacturing equipment member, the semiconductor manufacturing equipment member according to the above-described embodiment A or the semiconductor manufacturing equipment member according to embodiment B may be used.

[0054] In one embodiment, the manufacturing method includes the following steps: Step A: processing the upper surface 22 of the first ceramic substrate 120 to form a flat surface 24 from which the plurality of protrusions 22a (first plurality of protrusions) have been removed; Step B1: bonding the flat surface 24 of the first ceramic substrate 120 to the lower surface 73 of the ceramic plate 70 at room temperature to form a second ceramic substrate 220 in which the first ceramic substrate 120 and the ceramic plate 70 are bonded; and Step C: forming, before or after Step B1, a plurality of protrusions 72 (second plurality of protrusions) on the upper surface 71 of the ceramic plate 70, on which a wafer W can be placed.

[0055] In step A, the upper surface 22 of the first ceramic substrate 120 is processed to form a flat surface 24 from which the plurality of protrusions 22a (first plurality of protrusions) have been removed. While there are no particular limitations on the processing method, for example, lapping is preferred. It is also preferable to process the flat surface 24 up to a position above the position of the built-in electrodes. The flat surface 24 of the first ceramic substrate 120 is preferably processed so that the surface roughness (arithmetic mean roughness) Ra measured with a non-contact surface roughness meter in accordance with the ISO 25178 standard is 1 nm or less (e.g., 0.2 nm to 1 nm).

[0056] Lapping is a method of lapping the upper surface 22 of the first ceramic substrate 120 using, for example, a polishing apparatus 60 shown in FIG. 5 . The polishing apparatus 60 includes a large-diameter disc-shaped polishing platen 62 equipped with a polishing pad 64, a small-diameter disc-shaped carrier 66, and a pipe 68 for supplying a slurry containing abrasive grains to the polishing pad 64. The polishing platen 62 includes a shaft 67 at the center of its lower surface, which is rotated by a drive motor (not shown) to rotate around its axis (spin). The carrier 66 includes a shaft 69 at the center of its upper surface, which is rotated by a drive motor (not shown) to rotate around its axis (spin). The carrier 66 is positioned off-center from the center of the polishing platen 62.

[0057] To polish the upper surface 22 of the first ceramic substrate 120 using this polishing apparatus 60, the first semiconductor manufacturing equipment member 100 is attached to the lower surface of the carrier 66, and the first semiconductor manufacturing equipment member 100 is sandwiched between the polishing pad 64 of the polishing table 62 and the carrier 66 so that the upper surface 22 of the first ceramic substrate 120 contacts the polishing pad 64. Then, a slurry containing abrasive grains is supplied from a pipe 68 to the polishing pad 64. This supplies the slurry between the first ceramic substrate 120 and the polishing pad 64 of the polishing table 62. In this state, the polishing table 62 and the carrier 66 are rotated on their axes while the carrier 66 presses the first semiconductor manufacturing equipment member 100 against the polishing pad 64, thereby performing polishing.

[0058] Next, in step B1, the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70 are bonded at room temperature to form a second ceramic substrate 220 in which the first ceramic substrate 120 and the ceramic plate 70 are bonded. Room temperature bonding is a method in which the bonding surfaces are activated by irradiating them with a fast atom beam (FAB) without heating, and bonding is performed in a state in which an amorphous layer is formed on the surface. Therefore, the lower surface 73 of the ceramic plate 70 and the flat surface 24 of the first ceramic substrate 120 are typically bonded via an amorphous layer.

[0059] From the viewpoint of improving thermal shock resistance by bringing the thermal expansion coefficients closer together, it is preferable that the ceramic plate 70 contains the same material as the ceramic constituting the first ceramic substrate 120. Specifically, in one embodiment, the ceramic plate 70 and the first ceramic substrate 120 both contain one or two types selected from aluminum oxide (alumina) and aluminum nitride. In a preferred embodiment, the ceramic plate 70 and the first ceramic substrate 120 both contain 80 mass% or more of one or two types selected from aluminum oxide and aluminum nitride. In an even more preferred embodiment, the ceramic plate 70 and the first ceramic substrate 120 both contain 95 mass% or more of one or two types selected from aluminum oxide and aluminum nitride.

[0060] The thickness of the ceramic plate 70 can be set to, for example, 0.1 mm to 1 mm.

[0061] The lower surface 73 of the ceramic plate 70 preferably has a surface roughness (arithmetic mean roughness) Ra of 1 nm or less, for example, 0.2 nm to 1 nm, as measured with a non-contact surface roughness meter in accordance with ISO 25178. In order to make the lower surface 73 of the ceramic plate 70 such a flat surface, it is preferable to perform lapping, similar to the first ceramic substrate 120.

[0062] Next, the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70 are subjected to surface activation treatment (fast atom beam (FAB) or plasma activation treatment) under high vacuum. The FAB conditions are, for example, set to a voltage of 0.5 to 2 kV, a current of 50 to 200 mA, and an irradiation time of 30 to 300 seconds. This removes oxides and adsorbed molecules from the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70, while forming an amorphous layer on these surfaces, activating them. Next, while maintaining the high vacuum condition, the flat surface 24 of the first ceramic substrate 120 and the lower surface 73 of the ceramic plate 70 are overlapped so that they face each other, and then they are bonded at room temperature while being pressed. The load during pressing can be set to, for example, 0.1 to 50 kN. After room temperature bonding, the second ceramic substrate 220 may be heated at approximately 100°C for one hour or more to increase the bonding strength.

[0063] In step C, a plurality of protrusions 72 (second plurality of protrusions) on which a wafer W can be placed are formed on the upper surface 71 of the ceramic plate 70. The plurality of protrusions 72 formed here may be arranged in the same manner as or different from the arrangement of the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120. The height and diameter of each of the second plurality of protrusions may also be the same as or different from the height and diameter of the first plurality of protrusions. Step C may be performed before or after step B1. The plurality of protrusions 72 can be formed on the upper surface 71 of the ceramic plate 70 by laser processing or blasting. Furthermore, since the upper end surfaces of the multiple protrusions 22a (first multiple protrusions) on the upper surface 22 of the first ceramic substrate 120 deteriorate due to use, the upper end surfaces of the multiple protrusions 72 (second multiple protrusions) on the upper surface 71 of the ceramic plate 70 in the second ceramic substrate 220 typically have a surface roughness Ra different from that of the upper end surfaces of the multiple protrusions 22a (first multiple protrusions) on the upper surface 22 of the first ceramic substrate 120.

[0064] (2-2. Manufacturing Method of a Semiconductor Manufacturing Equipment Member According to Embodiment B) Next, a manufacturing method of a semiconductor manufacturing equipment member according to embodiment B will be exemplarily described with reference to FIG. 4B.

[0065] First, prepare the first semiconductor manufacturing equipment member 100. The first semiconductor manufacturing equipment member 100 is the same as that described in the method for manufacturing a semiconductor manufacturing equipment member according to embodiment A, and therefore a duplicated description will be omitted.

[0066] In one embodiment, the manufacturing method includes: a step A of processing the upper surface 22 of the first ceramic substrate 120 to form a flat surface 24 from which the plurality of protrusions 22a (first plurality of protrusions) have been removed; and a step B2 of room temperature bonding the flat surface 24 of the first ceramic substrate 120 to the lower end surfaces 192a of the plurality of protrusion forming parts 192 to form a second ceramic substrate 220 in which the first ceramic substrate 120 and the plurality of protrusion forming parts 192 are bonded.

[0067] Step A is the same as that described in the method for manufacturing a semiconductor manufacturing equipment member according to embodiment A, and therefore a duplicated description will be omitted.

[0068] Next, in step B2, the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 192a of the plurality of protrusion-forming components 192 are bonded at room temperature to form a second ceramic substrate 220 in which the first ceramic substrate 120 and the plurality of protrusion-forming components 192 are bonded. In this case, the lower end surfaces 192a of the plurality of protrusion-forming components 192 and the flat surface 24 of the first ceramic substrate 120 are typically bonded via an amorphous layer. Furthermore, because the upper end surfaces of the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120 deteriorate with use, the upper end surfaces of the plurality of protrusion-forming components 192 typically have a surface roughness Ra different from that of the upper end surfaces of the plurality of protrusions 22a (first plurality of protrusions) on the upper surface 22 of the first ceramic substrate 120.

[0069] Each of the multiple protrusion-forming components 192 is a component that will eventually become the protrusions 72 (second multiple protrusions), and can have a columnar shape such as a cylindrical column or a rectangular column that corresponds to the protrusions 72. The height h of the protrusion-forming components 192 can be, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusion-forming components 192 can be, for example, 0.3 to 3.0 mm, and typically 0.8 to 2.2 mm.

[0070] Furthermore, the flat surface 24 of the first ceramic substrate 120 and the lower end surface 195a of the seal band forming component 195 may be bonded at room temperature to form a second ceramic substrate 220 in which the first ceramic substrate 120 and the seal band forming component 195 are bonded. In this case, the lower end surface 195a of the seal band forming component 195 and the flat surface 24 of the first ceramic substrate 120 are typically bonded via an amorphous layer. The seal band forming component 195 is a component that will ultimately become the seal band 95 and can have an annular (typically circular) shape corresponding to the seal band 95. Its thickness is preferably the same as that of the protrusion forming component 192.

[0071] From the viewpoint of improving thermal shock resistance by making the thermal expansion coefficients similar, it is preferable that the protrusion-forming component 192 contains the same material as the ceramic constituting the first ceramic substrate 120. Similarly, it is desirable that the seal band-forming component 195 also contains the same material as the ceramic constituting the first ceramic substrate 120. Specifically, in one embodiment, the protrusion-forming component 192 and the first ceramic substrate 120 all contain one or two types selected from aluminum oxide (alumina) and aluminum nitride. In another embodiment, the protrusion-forming component 192, the seal band-forming component 195, and the first ceramic substrate 120 all contain one or two types selected from aluminum oxide (alumina) and aluminum nitride. In a preferred embodiment, the protrusion-forming component 192 and the first ceramic substrate 120 all contain 80 mass% or more of one or two types selected from aluminum oxide and aluminum nitride. In another preferred embodiment, the protrusion-forming component 192, the seal band-forming component 195, and the first ceramic substrate 120 all contain 80 mass% or more of one or two selected from aluminum oxide and aluminum nitride. In an even more preferred embodiment, the protrusion-forming component 192 and the first ceramic substrate 120 contain 95 mass% or more of one or two selected from aluminum oxide and aluminum nitride. In another even more preferred embodiment, the protrusion-forming component 192, the seal band-forming component 195, and the first ceramic substrate 120 contain 95 mass% or more of one or two selected from aluminum oxide and aluminum nitride.

[0072] The lower end surfaces 192a of the multiple protrusion-forming components 192 preferably have a surface roughness (arithmetic mean roughness) Ra of 1 nm or less, for example, 0.2 nm to 1 nm, as measured with a non-contact surface roughness meter in accordance with ISO 25178. In order to make the lower end surfaces 192a of the multiple protrusion-forming components 192 such flat surfaces, it is preferable to perform lapping, as with the first ceramic substrate 120. One method for producing multiple protrusion-forming components 192 having such flat lower end surfaces 192a is to perform lapping on the lower surface of a ceramic plate and then cut out the multiple protrusion-forming components 192 individually by laser processing.

[0073] Similarly, the surface roughness (arithmetic mean roughness) Ra of the lower end surface 195a of the seal band forming component 195 is preferably 1 nm or less, for example, 0.2 nm to 1 nm, as measured with a non-contact surface roughness meter in accordance with ISO 25178. In order to make the lower end surface 195a of the seal band forming component 195 such a flat surface, it is preferable to perform lapping polishing on the lower end surface 195a in the same manner as the first ceramic substrate 120.

[0074] Next, the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 195a of the multiple protrusion-forming components 192 are subjected to surface activation treatment (fast atomic beam (FAB) or plasma activation treatment) under high vacuum. The FAB conditions are, for example, set to a voltage of 0.5 to 2 kV, a current of 50 to 200 mA, and an irradiation time of 30 to 300 seconds. This removes oxides and adsorbed molecules from the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 192a of the multiple protrusion-forming components 192, and activates these surfaces by forming amorphous layers. Next, while maintaining the high vacuum condition, the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 192a of the multiple protrusion-forming components 192 are overlapped with each other so that they face each other, and are then bonded at room temperature while being pressurized. The load applied during pressing can be set to, for example, 0.1 to 50 kN. One example of a method for room-temperature bonding is to prepare a die having a plurality of holes corresponding to the positions where the plurality of protrusion-forming components 192 are to be placed, when the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 192a of the plurality of protrusion-forming components 192 face each other, and then remove the die after the plurality of protrusion-forming components 192 are placed in the plurality of holes, thereby performing room-temperature bonding. After room-temperature bonding, the second ceramic substrate 220 may be heated at about 100°C for one hour or more in order to increase the bonding strength.

[0075] The same procedure can be used to perform room-temperature bonding between the flat surface 24 of the first ceramic substrate 120 and the lower end surface 195a of the seal band forming component 195. That is, surface activation treatment (fast atom beam (FAB) or plasma activation treatment) is performed on the flat surface 24 of the first ceramic substrate 120 and the lower end surface 195a of the seal band forming component 195 under high vacuum. Next, while maintaining the high vacuum condition, the flat surface 24 of the first ceramic substrate 120 and the seal band forming component 195 are overlapped so that they face each other, and room-temperature bonding is performed while applying pressure. The FAB conditions and room-temperature bonding conditions are the same as those used to perform room-temperature bonding between the flat surface 24 of the first ceramic substrate 120 and the lower end surfaces 195a of the multiple protrusion forming components 192.

[0076] In this embodiment, even if gas holes or lift pin holes exist on the upper surface 22 of the first ceramic substrate 120, there is no need to perform a process of closing them, which has the advantage that there is no need to form these holes again.

[0077] 3. Method of Using the Semiconductor Manufacturing Equipment Component Next, an exemplary method of using the semiconductor manufacturing equipment component 10A (10B) will be described. First, the semiconductor manufacturing equipment component 10A (10B) is placed in a chamber (not shown). A focus ring is placed on the upper surface 27 of the semiconductor manufacturing equipment component 10A (10B), and a disk-shaped wafer W is placed on the wafer mounting surface, i.e., the upper end surface 71 a of the protrusion 72 (the upper end surface 92 a of the protrusion 92) and the upper end surface 71 c of the seal band 75 (the upper end surface 95 a of the seal band 95). The chamber is then depressurized using a vacuum pump to adjust the chamber to a predetermined vacuum level, and a voltage is applied to the electrode 26 a of the ceramic substrate 20 to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface.

[0078] Next, a process gas is supplied from a showerhead (not shown) to create a reaction gas atmosphere at a predetermined pressure (several tens to several hundreds of Pa) inside the chamber. In this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) provided on the ceiling of the chamber and the base plate 30 of the semiconductor manufacturing equipment member 10A (10B). This generates plasma between the wafer W and the showerhead. The plasma is then used to process the wafer W (by CVD film formation or etching).

[0079] A refrigerant circulates through the refrigerant flow path 32 of the base plate 30. A supply port and a recovery port of an external refrigerant device (not shown) are connected to one end and the other end of the refrigerant flow path 32 via refrigerant piping, respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0080] A gas flow path (not shown) is formed inside the base plate 30, and a backside gas can be introduced from a gas cylinder (not shown). A thermally conductive gas (e.g., He gas) can be used as the backside gas. After passing through the gas flow path inside the base plate 30, the backside gas flows out through the gas holes 50 and fills the space on the backside of the wafer W.

[0081] The focus ring 78 also wears out as the wafers W are plasma processed. However, since the focus ring 78 is thicker than the wafers W, the focus ring 78 is replaced after processing a plurality of wafers W.

[0082] Below, experimental data is presented to demonstrate the superiority of the bonding strength of the amorphous layer.

[0083] (Experimental Example 1: Formation of AD film) A plate (20 mm × 20 mm × 5 mm) made of SiSiCTi, a type of MMC, was prepared. An aerosol deposition film (AD film) was formed on the entire upper surface of the plate by aerosol deposition using an alumina powder raw material (purity 99.9%). Next, the plate was cut in the thickness direction along a cutting line passing near the center of the upper surface of the plate to expose the longitudinal cross section. The thickness of the AD film was measured at 3000x magnification using a scanning electron microscope (SEM), and was found to be approximately 3 μm.

[0084] (Experimental Example 2: Formation of a Thermal Sprayed Film) A plate made of the same SiSiCTi material as in Experimental Example 1 was prepared. A thermal sprayed film was formed on the entire upper surface of the plate by thermal spraying using an alumina powder raw material (purity 99.9%). Next, the plate was cut in the thickness direction along a cutting line passing through the vicinity of the center of the upper surface of the plate to expose a longitudinal cross section, which was observed at 500x magnification using a scanning electron microscope (SEM). The thickness of the thermal sprayed film was measured to be approximately 50 μm.

[0085] (Experimental Example 3: Formation of Amorphous Layer) Two dense alumina plates with a diameter of 10 mm, a thickness of 1 mm, and a purity of 99.9% or higher were prepared. Next, both dense alumina plates were polished using a polishing device to a surface roughness Ra of 0.7 μm or less. Next, each polished surface was irradiated with an Ar beam (FAB) under high vacuum. The two plates were then overlapped with their polished surfaces facing each other and bonded under pressure to obtain a bonded structure. The plates were cut in the thickness direction along a cutting line passing near the center of the top surface of the bonded structure to expose the longitudinal cross section. The cross section was observed under a transmission electron microscope (TEM) at 4,000,000 magnification, and the thickness of the amorphous layer was measured to be approximately 5 nm.

[0086] (Tensile Test) The tip of a stud pin (φ2.7 mm, length 15 mm) was fixed with adhesive to the top surface of each of the AD film-coated plate, thermal spray film-coated plate, and pair of plates bonded by an amorphous layer produced in Experimental Examples 1, 2, and 3. The stud pin was then pulled perpendicular to the top surface of the plate (vertically upward) using a tensile testing device (manufactured by Shimadzu Corporation) to remove it from the plate. As a result, the stud pin came off in the plates of Experimental Examples 1 and 2 at a tensile stress of about 60 MPa. After the tensile test, visual inspection of the fracture site revealed that in both Experimental Examples 1 and 2, fracture did not occur at the interface between the stud pin and the adhesive, but rather occurred within the film.

[0087] On the other hand, the stud pin came off the plate in Experimental Example 3 when a tensile stress of around 70 MPa was applied. After the tensile test, the fracture location was visually inspected and it was found to have occurred at the interface between the stud pin and the adhesive. Since the amorphous layer did not fracture even when a tensile stress higher than the film strength of the AD film and the thermal spray film was applied, it was confirmed that the bonding strength via the amorphous layer is higher than that of the AD film and the thermal spray film.

[0088] DESCRIPTION OF SYMBOLS 10A: Member for semiconductor manufacturing equipment 10B: Member for semiconductor manufacturing equipment 20: Ceramic substrate 20a: Central portion 20b: Peripheral portion 21: Upper surface 22: Upper surface 22a: Protrusion 23: Lower surface 24: Flat surface 26a: Electrode 26b: Electrode 27: Upper surface 30: Base plate 31: Upper surface 32: Coolant flow path 35: Insulating film 40: Bonding layer 50: Gas hole 55: Plug 60: Polishing device 62: Polishing surface plate 64: Polishing pad 66: Carrier 67: Shaft 68: Pipe 69: Shaft 70: Ceramic plate 71: Upper surface 71a: Upper end surface 71b: Reference surface 71c: Upper end surface 72: Protrusion 73 : Lower surface 75 : Seal band 78 : Focus ring 80 : Amorphous layer 92 : Protrusion 92a : Upper end surface 92b : Lower end surface 95 : Seal band 95a : Upper end surface 95b : Lower end surface 100 : First member for semiconductor manufacturing equipment 120 : First ceramic substrate 192 : Protrusion forming component 192a : Lower end surface 195 : Seal band forming component 195a : Lower end surface 220 : Second ceramic substrate

Claims

1. A method for manufacturing a second semiconductor manufacturing equipment component using a first semiconductor manufacturing equipment component comprising a first ceramic substrate having an upper surface with a plurality of protrusions on which a wafer can be placed and a second ceramic substrate having an electrode built in, the method comprising: Step A: processing the upper surface of the first ceramic substrate to form a flat surface from which the plurality of protrusions have been removed; Step B1: room temperature bonding the flat surface of the first ceramic substrate to the underside of a ceramic plate to form a second ceramic substrate in which the first ceramic substrate and the ceramic plate are bonded; and Step C: before or after performing Step B1, forming a plurality of protrusions on the upper surface of the ceramic plate, the plurality of protrusions on which a wafer can be placed.

2. The manufacturing method according to claim 1, wherein the ceramic plate contains the same material as the ceramic that constitutes the first ceramic substrate.

3. The manufacturing method according to claim 2, wherein the ceramic plate and the first ceramic substrate both contain one or two materials selected from aluminum oxide and aluminum nitride.

4. The manufacturing method according to claim 1, wherein the lower surface of the ceramic plate and the flat surface of the first ceramic substrate are bonded via an amorphous layer.

5. The manufacturing method according to claim 1, wherein the arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate.

6. A method for manufacturing a second semiconductor manufacturing equipment member having a second ceramic substrate having an upper surface with a plurality of protrusions on which a wafer can be placed and an electrode built in, using a first semiconductor manufacturing equipment member having a first ceramic substrate having an upper surface with a plurality of protrusions on which a wafer can be placed and an electrode built in, the method comprising: a step A of processing the upper surface of the first ceramic substrate to form a flat surface from which the plurality of protrusions have been removed; and a step B2 of room temperature bonding the flat surface of the first ceramic substrate to the lower end surfaces of a plurality of protrusion-forming parts to form a second ceramic substrate in which the first ceramic substrate and the plurality of protrusion-forming parts are bonded.

7. The manufacturing method according to claim 6, wherein the plurality of protrusion forming parts contain the same material as the ceramic that constitutes the first ceramic substrate.

8. The manufacturing method according to claim 6, wherein the plurality of protrusion-forming components and the first ceramic substrate both contain one or two types selected from aluminum oxide and aluminum nitride.

9. The manufacturing method according to claim 6, wherein the lower end surfaces of the plurality of projection-forming components and the flat surface of the first ceramic substrate are joined via an amorphous layer.

10. The manufacturing method according to claim 6, wherein the arrangement of the plurality of protrusions on the upper surface of the first ceramic substrate is the same as the arrangement of the plurality of protrusions on the upper surface of the second ceramic substrate.

11. A component for semiconductor manufacturing equipment comprising: a ceramic substrate having an electrode built in; and a ceramic plate having a lower surface joined to the upper surface of the ceramic substrate via an amorphous layer, and an upper surface having a plurality of protrusions on which a wafer can be placed.

12. A member for semiconductor manufacturing equipment comprising: a ceramic substrate having an electrode built in; and a plurality of protrusions having a lower end surface joined to the upper surface of the ceramic substrate via an amorphous layer, and an upper end surface for placing a wafer thereon.

13. A semiconductor manufacturing equipment member according to claim 11, wherein the ceramic plate contains the same material as the ceramic that constitutes the ceramic substrate.

14. A semiconductor manufacturing equipment member according to claim 12, wherein the plurality of protrusions contain the same material as the ceramic that constitutes the ceramic substrate.

15. A semiconductor manufacturing equipment member according to claim 11, wherein the ceramic plate and the ceramic substrate both contain one or two materials selected from aluminum oxide and aluminum nitride.

16. A semiconductor manufacturing equipment member according to claim 12, wherein the plurality of protrusions and the ceramic substrate both contain one or two types selected from aluminum oxide and aluminum nitride.

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