Method of forming a stitched photonic structure

Abstract

A method of forming a solid state device includes exposing to radiation a first area and an overlapping boundary region of the solid state device through a first mask having a first taper design overlying the overlapping boundary region, and exposing to radiation a second area and the overlapping boundary region of the solid state device through a second mask having a second taper design or a V-shape design overlying the overlapping boundary region.

Description

PATENT APPLICATIONFORMETHOD OF FORMING A STITCHED PHOTONIC STRUCTUREInventors:Erik R. HosierNicholas V. LiCausiMETHOD OF FORMING A STITCHED PHOTONIC STRUCTUREFIELD

[0001] The present disclosure relates generally to solid state devices, and more particularly to a method of forming a stitched photonic structure.BACKGROUND

[0002] In a lithographic process, radiation exposure typically results in a Gaussian intensity profile on a wafer. A shape of the Gaussian intensity profile may be partially controlled through assist features (e.g., printing and / or sub-resolution) and a choice of neighboring structures (e.g., dense vs. isolated lines). It may be very difficult or impossible to deliver a square wave profile on the wafer, which would therefore yield an ideal square resist exposure profile.SUMMARY

[0003] According to an aspect of the present disclosure, a method of forming a solid state device includes exposing to radiation a first area and an overlapping boundary region of the solid state device through a first mask having a first taper design overlying the overlapping boundary region, and exposing to radiation a second area and the overlapping boundary region of the solid state device through a second mask having a second taper design or a V- shape design overlying the overlapping boundary region.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the Figures.

[0005] FIG. 1 is a plan view (e.g., top-down view in the z-direction) of a solid-state device 100, according to one or more embodiments.

[0006] FIG. 2 is a schematic view of a lithographic scanner 200 according to one or more embodiments.

[0007] FIG. 3 is a flow chart illustrating a method of forming the solid state device 100 according to one or more embodiments.

[0008] FIG. 4A is a plan view (e.g., top-down view) of a mask overlay design (e.g., mask design) for forming the solid state device 100, according to one or more embodiments.

[0009] FIG. 4B is a plan view (e.g., top-down view) of the stitched photonic structure 10 (e.g., on wafer print illustration) that may be formed by the mask overlay design in FIG. 4A, according to one or more embodiments.

[0010] FIG. 5 illustrates a first mask 610 and a second mask 620 that may be overlapped in order to produce the mask overlay design (e.g., mask design) of FIG. 4 A, according to one or more embodiments.

[0011] FIG. 6A is a plan view (e.g., top-down view) of an alternative mask overlay design (e.g., mask design) for forming the solid state device 100, according to one or more embodiments.

[0012] FIG. 6B is a plan view (e.g., top-down view) of alternative stitched photonic structure 10 (e.g., on wafer print illustration) that may be formed by the mask overlay design in FIG. 6A, according to one or more embodiments.

[0013] FIG. 7 illustrates a third mask 720 that may be overlapped with the first mask 610 in order to produce an alternative mask overlay design (e.g., alternative mask design) in FIG. 6A, according to one or more embodiments.DETAILED DESCRIPTION

[0014] As discussed above, the embodiments of the present disclosure are directed to a method of forming a stitched photonic structure, the various aspects of which are discussed herein in detail. The drawings are not necessarily drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or onthe interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a “layer” refers to a continuous portion of at least one material including a region having a thickness. A layer may consist of a single material portion having a homogeneous composition, or may include multiple material portions having different compositions.

[0015] As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0 x 105S / cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0 x 10'5S / cm. As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0 x 10'5S / cm to 1.0 x 105S / cm. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.

[0016] In a typical lithographic process, when exposing a mask pattern, a resulting shape on a wafer (i.e., a shape of the exposed and developed (i.e., patterned) photoresist and / or an underlying device component that is etched using the patterned photoresist as an etch mask) may be quite different than that of an intended design. In particular, in a top-down view (e.g., plan view), edges may be curved. In a vertical cross-sectional view, a sidewall angle may be sloped to a varying degree depending on size and assist features.

[0017] Reticle stitching (e.g., mask stitching) may be used to stitch together two separate structures (e.g., two patterned photoresist structures or two device structures etched using the two patterned photoresist structures as etch masks) in solid state device, such as a photonic integrated circuit (“photonic IC”). Stitched structures (e.g., features) may be typically formed in the back end of line (BEOL) or middle of line (MOL) process. Stitched structures may include features having a critical dimension (CD) in a range from 50nm to 150nm. For photonic waveguides, a size of stitched CD may be greater, for which a specific design and / or an optical proximity correction (OPC) tuning are desired to minimize structural defects at a stitching boundary (e.g., overlapping boundary).

[0018] One or more embodiments of the present disclosure may include a solid state device including a stitched photonic structure, and method of forming the solid state device.

[0019] FIG. 1 is a plan view (e.g., top-down view in the z-direction) of a solid-state device 100, according to one or more embodiments. As illustrated in FIG. 1, the solid statedevice 100 may include a substrate 105 (e.g., photonic substrate), such as a silicon wafer or a silicon-on-insulator substrate. The solid state device 100 may also include a first mask area 110 on the substrate 105. The first mask area 110 may include an area (region) that is exposed in a photolithography process by using a first mask. The first mask area 110 may include a first photonic structure 110c formed on a surface of the substrate 105. The first photonic structure 110c is etched using a first patterned photoresist structure as an etch mask. The first patterned photoresist structure is formed by exposure through the radiation transparent portions in the first mask and subsequent development, and is then removed (e.g., by ashing) after the etching of the first photonic structure 110c.

[0020] The solid state device 100 may also include a second mask area 120 on the substrate 105. The second mask area 120 may include an area (region) that is exposed in a photolithography process by using a second mask. The second mask may comprise a different mask than the first mask, or the second mask may comprise the first mask which is laterally translated in the y-direction relative to the substrate 105 in FIG. 1. The second mask area 120 may include a second photonic structure 120c. The second photonic structure 120c is etched using a second patterned photoresist structure as an etch mask. The second patterned photoresist structure is formed by exposure through the radiation transparent portions in the second mask and subsequent development, and is then removed (e.g., by ashing) after the etching of the second photonic structure 120c. o

[0021] The solid state device 100 may also include an overlapping boundary region 130 between the first mask area 110 and the second mask area 120. The overlapping boundary region 130 may include an area (i.e., region) that is exposed in a photolithography process by overlapping the first mask and the second mask (e.g., the first mask may overlap the second mask in the overlapping boundary region 130). The overlapping boundary region 130 may include a smooth dislocation stitching portion 130c stitching the first photonic structure 110c to the second photonic structure 120c. The smooth dislocation stitching portion 130c together with the first photonic structure 110c and the second photonic structure 120c may constitute a stitched photonic structure 10. In one embodiment, the first photonic structure 110c and the second photonic structure 120c comprise respective first and second portions of the stitched photonic structure 10 which are connected to each other by the dislocation stitching portion 130c. The dislocation stitching portion 130c is etched using both the first and the second patterned photoresist structures as etch masks.

[0022] In one embodiment, a first photoresist layer is deposited over one or more underlying device layers, is exposed through the radiation transparent portions in the first mask in the first mask area 110 and in the overlapping boundary region 130, and subsequently developed to form the first patterned photoresist structure. The first patterned photoresist structure is used as an etch mask to etch one or more underlying device layers to form a part of the dislocation stitching portion 130c and the first photonic structure 110c. The first patterned photoresist structure is then removed (e.g., by ashing). After removing the first patterned photoresist structure, a second photoresist layer is deposited over the one or more underlying device layers, is exposed through the radiation transparent portions in the second mask in the second mask area 120 and in the overlapping boundary region 130, and subsequently developed to form the second patterned photoresist structure. The second patterned photoresist structure is used as an etch mask to etch the one or more underlying device layers to form the remaining part of the dislocation stitching portion 130c and the second photonic structure 120c. The first patterned photoresist structure is then removed (e.g., by ashing).

[0023] In an alternative embodiment, a first photoresist layer is deposited over one or more underlying device layers, is exposed through the radiation transparent portions in the first mask in the first mask area 110 and in the overlapping boundary region 130. The first photoresist layer is then exposed through the radiation transparent portions in the second mask in the second mask area 120 and in the overlapping boundary region 130, and subsequently developed to form the first patterned photoresist structure in the first mask area 110, the second patterned photoresist structure in the second mask area 120 and a third patterned photoresist structure in the overlapping boundary region 130. The first, second and third patterned photoresist structures are then used as an etch mask to etch the one or more underlying device layers to form the first photonic structure 110c, the second photonic structure 120c and the dislocation stitching portion 130c during the same etching step. The first, second and third patterned photoresist structures are then removed (e.g., by ashing) during the same removal step.

[0024] A prior art dislocation stitching portion formed by a prior art method may have a highly angular (i.e., highly curved) shape creating a large dislocation (e.g., acutely angular dislocation) in case of an overlay error (e.g., misalignment in the x-direction in FIG. 1) between the first and the second masks. This may produce, for example, photon losses in awaveguide (i.e., if the the solid state device 100 is waveguide). The smooth dislocation stitching portion 130c may provide a smooth dislocation in case of the overlay error (e.g., misalignment in the x-direction in FIG. 1) and thereby have a reduced amount of photon losses in the waveguide compared to the prior art stitching portion.

[0025] As illustrated in FIG. 1, the smooth dislocation stitching portion 130c may include a first sidewall having an angle 9 (e.g., an angle between a line tangent to the first sidewall and a line corresponding to an extension of the corresponding sidewall of the first photonic structure 110c in the y-direction) of less than 45°. In one embodiment, the smooth dislocation stitching portion 130c may include a first sidewall having an angle 9 of less than 30°, such as 0° to 20°.

[0026] The smooth dislocation stitching portion 130c may further include a second sidewall opposite the first sidewall. The second sidewall may also have an angle 9 (e.g., an angle between a line tangent to the second sidewall and a line corresponding to an extension of the corresponding sidewall of the second photonic structure 120c in the y-direction) of less than 45°. In one embodiment, the smooth dislocation stitching portion 130c may include a second sidewall having an angle 9 of less than 30°, such as 0° to 20°. A width (e.g., in the x- direction) of the smooth dislocation stitching portion 130c between the first sidewall and the second sidewall may be substantially uniform over an entirety of the second sidewall.

[0027] The first photonic structure 110c may include a first portion of a photonic (i.e., optical) waveguide and the second photonic structure 120c may include a second portion of the photonic waveguide. The smooth dislocation stitching portion 130c may include a stitched waveguide portion optically coupling the first portion of the photonic waveguide to the second portion of the photonic waveguide. The width (e.g., in the x-direction) of the smooth dislocation stitching portion 130c may be substantially the same as a width of the first and second portions of the photonic waveguide.

[0028] As further illustrated in FIG. 1, the smooth dislocation stitching portion 130c may extend longitudinally in a first direction (e.g., the y-direction). In at least one embodiment, the first photonic structure 110c may be displaced from the second photonic structure 120c in a second direction perpendicular to the first direction (e.g., the x-direction), by a distance DI of10 nm or more, such as 10 nm to 100 nm due to an overlay error (e.g., misalignment in the x- direction in FIG. 1) between the first and second masks.

[0029] FIG. 2 is a schematic view of a lithographic scanner 200 according to one or more embodiments. The lithographic scanner 200 may be used, for example, to expose one or more photoresist layers used as an etch mask during the etching of the layers of the solid state device 100.

[0030] As illustrated in FIG. 2, the lithographic scanner 200 may include an exposure unit 210. The exposure unit 210 may include, for example, a radiation source such as an ultraviolet emitting lamp (e.g., LED or mercury lamp) or laser, or an X-ray emitter for X-ray lithography, for exposing a photoresist layer through a photomask in a lithographic (e.g., photolithography process). The photoresist layer overlies the in-process solid state device 100. The lithographic scanner 200 may also include a metrology tool 230 coupled to the exposure unit 210. The metrology tool 230 may generate wafer correction data that may typically be used to make adjustments to the exposure unit 210. The generated wafer correction data may include, for example, interwafer correction data and / or intrawafer correction data.

[0031] The lithographic scanner 200 may also include a correction adjustment unit 240 coupled to the metrology tool 230. The correction adjustment unit 240 may map optical performance to the generated wafer correction data. Based on the mapping, the correction adjustment unit 240 may generate correction adjustment data.

[0032] The lithographic scanner 200 may also include a setting device 220. The setting device 220 may generate a setting instruction for setting a condition in the exposure unit 210. In at least one embodiment, the setting instruction may include an instruction for performing alignment, optical proximity corrections (OPCs), etc. The OPCs may include, for example, corrections regarding design (e.g., design of the photomask). The optical proximity corrections may also include corrections to an operation of the exposure unit 210, such as dose corrections and focus corrections.

[0033] The setting device 220 may include, for example, a decomposition data generator 220a that generates structural decomposition data from incoming design data. The decomposition data generator 220a may decompose a patterning layout into structures that would benefit from a specific source (e.g., dipole for lines, quadrupole for curves and circles). This may allow for pattern fidelity to be independently tuned and improved to maximize overall device performance. The setting device 220 may also include a mapping data generator 220b that generates mapping data from the structural decomposition data. Thesetting device 220 may also include a predictive correction unit (PCU) 220c. The PCU 220c may, for example, perform OPC (e.g., interleaved lithography-aware OPC) based on the mapping data and based on the correction adjustment data from the correction adjustment unit 240. That is, the correction adjustment data from the correction adjustment unit 240 may be used to adjust the PCU 220c.

[0034] In at least one embodiment, the setting device 220 may be implemented by a computer, server, etc. including a processing device such as a central processing unit (CPU), microprocessor, etc., and a memory device (e.g., random access memory (RAM), read-only memory (ROM), etc.). The memory device may store data and programs including instructions for performing operations in the setting device 220. The processing device may access the data and programs in the memory device, and execute the program instructions in order to perform various methods including a method of forming a solid state device, such as the solid state device 100.

[0035] The correction adjustment data may include, for example, dose adjustment data for making an in-die radiation exposure dose correction and / or focus adjustment data for making in-die focus correction. The correction adjustment data may also include, for example, critical dimension correction data for the solid state device 100, such as a photonic structure. In at least one embodiment, the PCU 220c may apply the in-die dose correction based on a type of the photonic structure (e.g., source, waveguide, block, etc.). In at least one embodiment, the PCU 220c may apply the in-die focus correction based on the type of the photonic structure.

[0036] In at least one embodiment, the PCU 220c may receive incoming design data, structural decomposition data and structural component requirement mapping data as input. The exposure unit 210 may perform, for example, wafer exposure at level "x". The metrology tool 230 may perform metrology of the level "x" (e.g., critical dimension, line edge roughness, etc.) and generate correlation data. The correction adjustment unit 240 may generate correction adjustment data based on the wafer correction data from the metrology tool 230, and feed the correction adjustment data forward to the PCU 220c for adjusting the PCU 220c. The correction adjustment unit 240 may also generate feedback data that is combined with the correlation data from the metrology tool 230, and fed back to the exposure unit 210.

[0037] FIG. 3 is a flow chart illustrating a method of forming the solid state device 100 according to one or more embodiments. The method may be performed, for example, by using the lithographic scanner 200 in FIG. 2. Step 310 of the method includes exposing to radiation a first area (e.g., first mask area) and an overlapping boundary region of the solid state device through a first mask having a first taper design overlying the overlapping boundary region. Step 320 of the method includes exposing to radiation a second area (e.g., second mask area) and the overlapping boundary region of the solid state device through a second mask having a second taper design or a V-shape design overlying the overlapping boundary region. In one embodiment, a photoresist material located over at least one device layer of the solid state device is exposed to radiation in steps 310 and 320. Step 330 of the method includes developing the photoresist material, and etching the at least one device layer of the solid state device underlying the developed photoresist material.

[0038] In general, the method of FIG. 3 includes using the first and the second masks to expose at least one photoresist layer over the solid state device 100 to form the first and second patterned photoresist structures, and then using the first and second patterned photoresist structures as an etch mask to etch one or more device layers of the underlying solid state device 100 in one or more etching steps.

[0039] FIG. 4A is a plan view (e.g., top-down view) of a mask overlay design (e.g., mask design) for forming the solid state device 100, according to one or more embodiments. As illustrated in FIG. 4 A, the mask overlay design may include a first mask 410 including a first patterning structure 510. The first patterning structure 510 may comprise a radiation opaque pattern (e.g., chromium pattern) located on a radiation transparent substrate (e.g., quartz, etc.) substrate. The first patterning structure 510 may include a first rectangular portion 510a and a first tapered portion 510b. The mask overlay design may also include a second mask 420 including a second patterning structure 520. The second patterning structure 520 may comprise a radiation opaque pattern (e.g., chromium pattern) located on a radiation transparent substrate (e.g., quartz, etc.) substrate. The second patterning structure 520 may include a second rectangular portion 520a and a second tapered portion 520b.

[0040] The mask overlay design may also include an overlapping boundary region 430 in which the first mask 410 may overlap the second mask 420. In particular, the location of the first tapered portion 510b of the first patterning structure 510 of the first mask 410 may overlap (e.g., at least partially overlap) the location second tapered portion 520b of thesecond patterning structure 520 of the second mask 420 when thew first and second masks are sequentially overlayed over the in-process solid-state device 100. The first tapered portion 510b and the second tapered portion 520b may together constitute an overlapping boundary region patterning structure 530.

[0041] FIG. 4B is a plan view (e.g., top-down view) of the stitched photonic structure 10 (e.g., a photonic waveguide located over the substrate 105 of the solid-state device 100) that may be formed by the mask overlay design in FIG. 4A, according to one or more embodiments. As illustrated in FIG. 4B, the smooth dislocation stitching portion 130c in the overlapping boundary region 130 may correspond to the location of the overlapping boundary region patterning structure 530 that includes the first tapered portion 510b overlapping (e.g., at least partially overlapping) the second tapered portion 520b.

[0042] Thus, in the one or more embodiments, in order to mitigate stitching induced dislocations as a result of overlay errors, an end of overlap lines (e.g., an end of first patterning structure 510 and an end of second patterning structure 520) may be tapered to soften a dislocation effect. This may help to reduce or minimize photon losses in the area of the photonic structure 10 at a boundary (e.g., overlapping boundary region) between masks. A length of the first tapered portion 510b may be dependent upon a width of the first rectangular portion 510a (e.g., incoming line). That is, the length of the first tapered portion 510b may increase with an increase in the width of the first rectangular portion 510a. A length of the second tapered portion 520b may be dependent upon the width of the second rectangular portion 520a (e.g., outgoing line). That is, the length of the second tapered portion 520b may increase with an increase in the width of the second rectangular portion 520a. The length of the first tapered portion 510b and the length of the second tapered portion 520b may, therefore, determine a length (e.g., in the y-direction) of the overlapping boundary region 430 in the patterning layout (e.g., may define the overlap area required to stitch).

[0043] Consideration of the dimensions of all stitched features may be used to determine the stitching area. The largest width may define a minimal overlap area. Smaller features may, of course, utilize less of the area.

[0044] FIG. 5 illustrates an embodiment of a first mask 610 and a second mask 620 that may be overlapped in order to produce the mask overlay design (e.g., mask design) of FIG. 4A, according to one or more embodiments. As illustrated in FIG. 5, the first mask 610 mayinclude a first mask pattern (i.e., radiation opaque material portion) including a stair step portion 611, optional sub-resolution assist features (SRAFs) 612 and an optional widened (e.g., hammerhead) portion 613 in the first tapered portion 510b of the first mask 610 corresponding to the overlapping boundary region 430. The first mask pattern is located on a radiation transparent substrate of the first mask 610. The second mask 620 may include a second mask pattern including the stair step portion 621, SRAFs 622 and a hammerhead 623 in the second tapered portion 520b of the second mask 620 corresponding to the overlapping boundary region 430.

[0045] As illustrated in FIG. 5, a portion of the first mask 610 may overlay the location of a portion of the second mask 620 so that the stair step portion 611, the sub-resolution assist features (SRAFs) 612 and the hammerhead portion 613 in the first mask 610, overlap the location of the stair step portion 621, the SRAFs 622 and the hammerhead portion 623 in the second mask 620, to produce the overlapping boundary region patterning structure 530 of the mask overlay design of FIG. 4 A.

[0046] Thus, as illustrated in FIG. 5, the design of the first mask 610 and second mask 620 may be used to create the taper (e.g., a long taper such as in the first tapered portion 510b and the second tapered portion 520b) in the mask overlay design of FIG. 4A. The taper in the mask overlay design may be used to create stitched structures, such as the stitched photonic structure 10. The first mask 610 and second mask 620 may utilize OPC to extend the tip to as fine a point as possible, utilizing stair-stepping, sub-resolution assist features (SRAFs) and hammerheads, etc. The length of the taper may be dependent upon the width of the main features (e.g., first rectangular portion 510a and second rectangular portion 520a). An overlap (e.g., the amount of overlap in the y-direction) of the first tapered portion 510b and the second tapered portion 520b may be dependent on a width of the main features.

[0047] The proposed design of the first mask 610 and the second mask 620 may be simulated, for example, in sLitho. In this case, the tapers may be shown to overlap. At zero displacement with no mask overlay error, a rectangular photoresist structure may be exposed. As displacement is increased to lOOnm (e.g., horizontally in the x-direction) due to a mask overlay error, a smooth curve may be created in the photoresist structure with the same CD as the main feature, as shown in FIG. 4B.

[0048] FIG. 6A is a plan view (e.g., top-down view) of an alternative mask overlay design (e.g., mask design) for forming the solid state device 100, according to one or moreembodiments. As illustrated in FIG. 6A, the mask overlay design may include a first mask 410 including a first patterning structure 510. In one embodiment, the first mask 410 may be the same as or different from the first mask 410 described above. The first patterning structure 510 may include a first rectangular portion 510a and a first tapered portion 510b. The mask overlay design may also include a second mask 820 including a second patterning structure 920. The second patterning structure 920 may include a second rectangular portion 920a and a V-shaped portion 920b. As used herein, a V-shaped portion is a portion which contains two elongated radiation opaque portions which extend away from the second rectangular portion 920a (e.g., in the y-direction toward the overlapping boundary region 830) separated from each other (in the x-direction perpendicular to the y-direction) by a radiation transparent area of the second mask substrate.

[0049] The mask overlay design may also include an overlapping boundary region 830 in which the first mask 410 may overlap the second mask 820 over the in-process solid-state device 100. In particular, the first tapered portion 910b of the first patterning structure 910 of the first mask 410 may overlap (e.g., at least partially overlap) the radiation transparent area of the V-shaped portion 920b of the second patterning structure 920 of the second mask 820. The first tapered portion 910b and the V-shaped portion 920b may together constitute an overlapping boundary region patterning structure 930.

[0050] FIG. 6B is a plan view (e.g., top-down view) of alternative stitched photonic structure 10 (e.g., on wafer print illustration) that may be formed by the mask overlay design in FIG. 6A, according an embodiment. As illustrated in FIG. 6B, the smooth dislocation stitching portion 130c in the overlapping boundary region 130 may correspond to the overlapping boundary region patterning structure 930 that includes the first tapered portion 910b overlapping (e.g., at least partially overlapping) the V-shaped portion 920b.

[0051] FIG. 7 illustrates an embodiment of a third mask 720 that may be overlapped with the first mask 610 in order to produce an alternative mask overlay design (e.g., alternative mask design) in FIG. 6A, according to one or more embodiments. As illustrated in FIG. 7, the first mask 610 may overlap the third mask 720 to form a lock-and-key configuration. That is, the third mask 720 may include a third mask pattern including a first stair step portion (i.e., first radiation opaque material pattern) 721a and a second stair step portion 721b adjacent to the first stair step portion 721a, the optional SRAFs 722 and the optional hammerheads 723. A radiation transparent area 724 may be located between the first andsecond stair step portions 721a and 721b. The first mask 610 may overlay the location of the third mask 720 over the solid-state device 100 so that the stair step portion 611, SRAFs 612 and hammerhead 613 in the first mask 610, overlap the first stair step portion 721a, second stair step portion 721b, SRAFs 722 and hammerheads 723 in the third mask 720, to produce the overlapping boundary region patterning structure 830. The SRAFs 722 are located adjacent to the first stair step radiation opaque material pattern 721a, adjacent to the stair step radiation opaque material pattern 721b, and between the first and the second stair step radiation opaque material patterns. Specifically, the stair step portion 611 may overlap the location of the radiation transparent area 724.

[0052] The lock-and-key configuration in FIG. 7, may include a taper and negative mirror interlocking ‘V’ feature that may be utilized to create a stitched structure. OPC may be designed to extend the tips to as fine a point as possible, utilizing stair-stepping, SRAFs and hammerheads, etc. A length of the taper and interlocking ‘V’ may be dependent upon the width of the main feature. Further, overlap of the tapered features may be dependent on the width of the main features.

[0053] The proposed design may be simulated in sLitho. In this case, the taper and interlocking ‘V’ may overlap. At zero displacement with no mask overlay error, a rectangular photoresist structure may be exposed. As displacement is increased to 40 nm (e.g., horizontally in the x-direction) due to a mask overlay error, a smooth curve may be created in the photoresist structure with the same CD as the main feature, as shown in FIG. 6B.

[0054] Therefore, in one or more embodiments, interlocking and / or extensively overlapping mask shapes may decrease the overlay control criterion for stitching structures. Interlocking and / or extensively overlapping mask shapes may also improve photon losses associated with overlay errors in stitched features. By reducing an impact of stitching errors on optical performance, the complexity of optical chips and the stitched structures may be expanded. Extensively overlapped tapers may increase overlay tolerance to 100 nm or more (see FIG. 4A-4B). Further, an interlocking taper plus a ‘V’ structure may increase overlay tolerance to 40 nm or more (see FIG. 6A-6B).

[0055] One or more embodiments may provide several advantages over typical systems and method for stitching photonic structures. In particular, the embodiments may correct all or most misalignments of stitched features in the x-direction and / or in the y-direction. Theembodiments may eliminate dislocation defects which could negatively affect optical transmission in the waveguide photonic structures. The embodiments may reduce control requirements for stitched devices, and may also enable high-performance optical interposers. The embodiments may also be utilized for any device fabrication involving stitching of fields, and may be used in the areas of optical quantum computers, augmented or virtual reality, optical telecommunications, optical components (interposers, data centers) or optically- enabled Al chips.

[0056] The following are example embodiments.

[0057] Example 1. A method of forming a solid state device comprises exposing to radiation a first area and an overlapping boundary region of the solid state device through a first mask having a first taper design overlying the overlapping boundary region; and exposing to radiation a second area and the overlapping boundary region of the solid state device through a second mask having a second taper design or a V-shape design overlying the overlapping boundary region.

[0058] Example 2. The method of example 1, wherein a photoresist material is exposed to the radiation through the first mask and through the second mask.

[0059] Example 3. The method of example 1 or 2, further comprising developing the photoresist material, and etching at least one device layer of the solid state device underlying the developed photoresist material.

[0060] Example 4. The method of any of examples 1-3, wherein the etching the at least one device layer forms a first portion of a photonic structure in the first area, a second portion of the photonic structure in the second area, and a dislocation stitching portion located in overlapping boundary region and connecting the first portion of the photonic structure to the second portion of the photonic structure.

[0061] Example 5. The method of any of examples 1-4, wherein the photonic structure comprises a photonic waveguide.

[0062] Example 6. The method of any of examples 1-5, wherein the dislocation stitching portion comprises a first sidewall having an angle between a line tangent to the first sidewall and a line corresponding to an extension of a corresponding sidewall of the first portion of the photonic structure of less than 45°.

[0063] Example 7. The method claim 1-6, wherein the dislocation stitching portion extends longitudinally in a first direction, and the first portion of the photonic structure isdisplaced from the second portion of the photonic structure in a second direction perpendicular to the first direction by a distance between 10 nm and 100 nm.

[0064] Example 8. The method of any of examples 1-7, further comprising: depositing a first photoresist layer over at least one device layer of the solid state device, wherein the first photoresist layer is exposed to the radiation through the first mask; developing the exposed first photoresist layer to form a first patterned photoresist structure located in the first area and in the overlapping boundary region; etching the at least one device layer using the first patterned photoresist structure as an etch mask; removing the first patterned photoresist structure after the etching the at least one device layer; depositing a second photoresist layer over the at least one device layer after removing the first patterned photoresist structure, wherein the second photoresist layer is exposed to the radiation through the second mask; developing the exposed second photoresist layer to form a second patterned photoresist structure located in the second area and in the overlapping boundary region; further etching the at least one device layer using the second patterned photoresist structure as an etch mask; and removing the second patterned photoresist structure after the further etching the at least one device layer.

[0065] Example 9. The method of any of examples 1-8, further comprising: depositing a first photoresist layer over at least one device layer of the solid state device, wherein the first photoresist layer is exposed to the radiation through the first mask in the first area and in the overlapping boundary region, and is subsequently exposed to the radiation through the second mask in the second area and in the overlapping boundary region; developing the exposed first photoresist layer to form a first patterned photoresist structure located in the first area, a second patterned photoresist structure located in the second area, and a third patterned photoresist structure located in the overlapping boundary region; etching the at least one device layer using the first, second and third patterned photoresist structures as an etch mask; and removing the first, second and third patterned photoresist structures.

[0066] Example 10. The method of any of examples 1-9, wherein the second mask has the second taper design, and a location of the first taper design of the first mask overlaps a location of the second taper design of the second mask in the overlapping boundary region.

[0067] Example 11. The method of any of examples 1-10, wherein the first taper design comprises a first stair step radiation opaque material pattern located on a radiation transparent substrate of the first mask, and the second first taper design comprises a second stair stepradiation opaque material pattern located on a radiation transparent substrate of the second mask.

[0068] Example 12. The method of any of examples 1-11, wherein the first taper design further comprises sub-resolution assist features located adjacent to the first stair step radiation opaque material pattern.

[0069] Example 13. The method of any of examples 1-12, wherein the first taper design further comprises a widened radiation opaque material pattern portion located at a tip of the first stair step radiation opaque material pattern.

[0070] Example 14. The method of any of examples 1-13, wherein the second mask has the V-shape design, and a location of the first taper design of the first mask overlaps a location of the V-shape design of the second mask in the overlapping boundary region.

[0071] Example 15. The method of any of examples 1-14, wherein the V-shaped design comprises two elongated radiation opaque portions separated from each other by a radiation transparent substrate area of the second mask.

[0072] Example 16. The method of any of examples 1-15, wherein the first elongated portion comprises a first stair step radiation opaque material pattern located on the radiation transparent substrate of the first mask, and the second elongated portion comprises a second stair step radiation opaque material pattern located on the radiation transparent substrate of the second mask.

[0073] Example 17. The method of any of examples 1-16, wherein the V-shaped design further comprises sub-resolution assist features located adjacent to the first stair step radiation opaque material pattern, adjacent to the stair step radiation opaque material pattern, and between the first and the second stair step radiation opaque material patterns.

[0074] Example 18. The method of any of examples 1-17, wherein the V-shaped design further comprises a first widened radiation opaque material pattern portion located at a tip of the first stair step radiation opaque material pattern, and a second widened radiation opaque material pattern portion located at a tip of the second stair step radiation opaque material pattern.

[0075] Example 19. The method of any of examples 1-19, wherein the first mask is different from the second mask.

[0076] Example 20. The method of any of examples 1-19, wherein the second mask comprises the first mask which is laterally translated from over the first area to over the second area.

[0077] The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

CLAIMS1. A method of forming a solid state device, comprising: exposing to radiation a first area and an overlapping boundary region of the solid state device through a first mask having a first taper design overlying the overlapping boundary region; and exposing to radiation a second area and the overlapping boundary region of the solid state device through a second mask having a second taper design or a V-shape design overlying the overlapping boundary region.

2. The method of claim 1, wherein a photoresist material is exposed to the radiation through the first mask and through the second mask.

3. The method of claim 2, further comprising developing the photoresist material, and etching at least one device layer of the solid state device underlying the developed photoresist material.

4. The method of claim 3, wherein the etching the at least one device layer forms a first portion of a photonic structure in the first area, a second portion of the photonic structure in the second area, and a dislocation stitching portion located in overlapping boundary region and connecting the first portion of the photonic structure to the second portion of the photonic structure.

5. The method of claim 4, wherein the photonic structure comprises a photonic waveguide.

6. The method of claim 4, wherein the dislocation stitching portion comprises a first sidewall having an angle between a line tangent to the first sidewall and a line corresponding to an extension of a corresponding sidewall of the first portion of the photonic structure of less than 45°.

7. The method claim 4, wherein the dislocation stitching portion extends longitudinally in a first direction, and the first portion of the photonic structure is displaced from the second portion of the photonic structure in a second direction perpendicular to the first direction by a distance between 10 nm and 100 nm.

8. The method of claim 1, further comprising: depositing a first photoresist layer over at least one device layer of the solid state device, wherein the first photoresist layer is exposed to the radiation through the first mask; developing the exposed first photoresist layer to form a first patterned photoresist structure located in the first area and in the overlapping boundary region; etching the at least one device layer using the first patterned photoresist structure as an etch mask; removing the first patterned photoresist structure after the etching the at least one device layer; depositing a second photoresist layer over the at least one device layer after removing the first patterned photoresist structure, wherein the second photoresist layer is exposed to the radiation through the second mask; developing the exposed second photoresist layer to form a second patterned photoresist structure located in the second area and in the overlapping boundary region; further etching the at least one device layer using the second patterned photoresist structure as an etch mask; and removing the second patterned photoresist structure after the further etching the at least one device layer.

9. The method of claim 1, further comprising: depositing a first photoresist layer over at least one device layer of the solid state device, wherein the first photoresist layer is exposed to the radiation through the first mask in the first area and in the overlapping boundary region, and is subsequently exposed to the radiation through the second mask in the second area and in the overlapping boundary region; developing the exposed first photoresist layer to form a first patterned photoresist structure located in the first area, a second patterned photoresist structure located in thesecond area, and a third patterned photoresist structure located in the overlapping boundary region; etching the at least one device layer using the first, second and third patterned photoresist structures as an etch mask; and removing the first, second and third patterned photoresist structures.

10. The method of claim 1, wherein the second mask has the second taper design, and a location of the first taper design of the first mask overlaps a location of the second taper design of the second mask in the overlapping boundary region.

11. The method of claim 1, wherein the first taper design comprises a first stair step radiation opaque material pattern located on a radiation transparent substrate of the first mask, and the second first taper design comprises a second stair step radiation opaque material pattern located on a radiation transparent substrate of the second mask.

12. The method of claim 11, wherein the first taper design further comprises subresolution assist features located adjacent to the first stair step radiation opaque material pattern.

13. The method of claim 12, wherein the first taper design further comprises a widened radiation opaque material pattern portion located at a tip of the first stair step radiation opaque material pattern.

14. The method of claim 1, wherein the second mask has the V-shape design, and a location of the first taper design of the first mask overlaps a location of the V-shape design of the second mask in the overlapping boundary region.

15. The method of claim 14, wherein the V-shaped design comprises two elongated radiation opaque portions separated from each other by a radiation transparent substrate area of the second mask.

16. The method of claim 15, wherein the first elongated portion comprises a first stair step radiation opaque material pattern located on the radiation transparent substrate of the first mask, and the second elongated portion comprises a second stair step radiation opaque material pattern located on the radiation transparent substrate of the second mask.

17. The method of claim 16, wherein the V-shaped design further comprises subresolution assist features located adjacent to the first stair step radiation opaque material pattern, adjacent to the stair step radiation opaque material pattern, and between the first and the second stair step radiation opaque material patterns.

18. The method of claim 17, wherein the V-shaped design further comprises a first widened radiation opaque material pattern portion located at a tip of the first stair step radiation opaque material pattern, and a second widened radiation opaque material pattern portion located at a tip of the second stair step radiation opaque material pattern.

19. The method of claim 1, wherein the first mask is different from the second mask.

20. The method of claim 1, wherein the second mask comprises the first mask which is laterally translated from over the first area to over the second area.

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