Display panel and display apparatus

Abstract

Disclosed in the present application are a display panel and a display apparatus. The display panel comprises a first thin film transistor and a second thin film transistor, the first thin film transistor comprising a first source electrode and a first drain electrode, and the second thin film transistor comprising a second source electrode and a second drain electrode. At least one of the first source electrode and the first drain electrode is arranged on the same layer as one of the second source electrode and the second drain electrode, and the first thin film transistor and the second thin film transistor at least partially overlap in the thickness direction of the display panel.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410446612.7, filed on April 12, 2024, with the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] With the continuous improvement of display technology, people's daily life, entertainment and work have put forward higher requirements for display products. For example, in VR products, the lack of resolution often seriously affects the user's experience.

[0004] At present, due to process limitations, it is difficult to reduce the size of the devices in the display panel. For example, the number of thin film transistor devices in the display panel is large, and the size of the thin film transistor devices is an important factor restricting the resolution of the display panel. SUMMARY

[0005] The embodiments of the present application provide a display panel and a display device, which can effectively reduce the occupied area of the first thin film transistor and the second thin film transistor, and improve the resolution of the display panel.

[0006] The embodiments of the present application provide a display panel, which comprises a first thin film transistor and a second thin film transistor, the first thin film transistor comprises a first source electrode and a first drain electrode, and the second thin film transistor comprises a second source electrode and a second drain electrode.

[0007] At least one of the first source electrode and the first drain electrode is arranged in the same layer as one of the second source electrode and the second drain electrode, and the first thin film transistor and the second thin film transistor are at least partially overlapped in the thickness direction of the display panel.

[0008] According to the above-mentioned purposes of the present application, the embodiments of the present application further provide a display device, which comprises a backlight module and a display panel, and the display panel is arranged on the light emitting side of the backlight module.

[0009] The display panel comprises a first thin film transistor and a second thin film transistor, the first thin film transistor comprises a first source electrode and a first drain electrode, and the second thin film transistor comprises a second source electrode and a second drain electrode.

[0010] At least one of the first source and the first drain is arranged in the same layer as one of the second source and the second drain, and the first thin film transistor and the second thin film transistor are arranged at least partially overlapping in a thickness direction of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0011] FIG. 1 is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0012] FIG. 2 is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0013] FIG. 3 is a schematic diagram of a structure of a first thin film transistor according to an embodiment of the present application;

[0014] FIG. 4 is a schematic diagram of a structure of a display panel according to an embodiment of the present application;

[0015] FIG. 5 is a schematic diagram of a structure of a first thin film transistor according to an embodiment of the present application;

[0016] FIG. 6 is a schematic diagram of a structure of a display device according to an embodiment of the present application. EMBODIMENTS OF THE INVENTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0018] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplifying the present application, the components and arrangements of the specific examples are described in the following. Of course, they are only examples and are not intended to limit the present application. Furthermore, the present application can repeatedly refer to the reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides various specific examples of processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0019] Referring to FIG. 1, in an embodiment, a display panel includes a substrate 1 and a thin film transistor array layer disposed on the substrate 1, the thin film transistor array layer includes a thin film transistor 2 disposed on the substrate 1, and the thin film transistor 2 includes an active layer 3, a gate 4 disposed on the active layer 3, a source 5 and a drain 6 disposed on a side of the gate 4 away from the active layer 3, and the source 5 and the drain 6 are respectively overlapped with two sides of the active layer 3; wherein, due to the limitation of process precision, the size of the thin film transistor 2 cannot be further reduced, and thus the number of the thin film transistor 2 in the display panel of a preset size cannot be further increased, which limits the increase of the number of pixels in the display panel, and thus limits the improvement of the resolution of the display panel, and affects the display effect of the display panel.

[0020] Referring to FIG. 2, an embodiment of the present application provides a display panel, which includes a first thin film transistor 20 and a second thin film transistor 30; the first thin film transistor 20 includes a first source 22 and a first drain 23, and the second thin film transistor 30 includes a second source 32 and a second drain 33.

[0021] At least one of the first source 22 and the first drain 23 is disposed in the same layer as one of the second source 32 and the second drain 33, and the first thin film transistor 20 and the second thin film transistor 30 are at least partially overlapped in the thickness direction of the display panel.

[0022] In the process of implementation, the embodiment of the present application can reduce the occupied area of the first thin film transistor 20 and the second thin film transistor 30 by at least partially overlapping the first thin film transistor 20 and the second thin film transistor 30, and can set more numbers of the first thin film transistor 20 and the second thin film transistor 30 in the display panel, which can effectively improve the resolution of the display panel; in addition, the embodiment of the present application also sets part of the source-drain electrodes of the first thin film transistor 20 and the second thin film transistor 30 in the same layer to reduce the process procedure and reduce the process cost.

[0023] In an embodiment of the present application, the display panel further includes:

[0024] a substrate;

[0025] a first conductive layer disposed on the substrate, the first conductive layer includes at least one of the first source and the first drain, and one of the second source and the second drain;

[0026] The first thin film transistor further includes a first active layer and a first gate electrode, and the second thin film transistor further includes a second active layer and a second gate electrode, at least part of the first active layer and at least part of the first gate electrode are located between the first conductive layer and the substrate, and the second active layer and the second gate electrode are located on a side of the first conductive layer away from the substrate.

[0027] In an embodiment of the present application, the first active layer and the second active layer at least partially overlap in a direction perpendicular to the substrate.

[0028] In an embodiment of the present application, the display panel further includes:

[0029] A first insulating layer is arranged between the substrate and the first conductive layer, and a first opening is formed in the first insulating layer;

[0030] The first active layer is arranged in the first opening and partially extends to a side of the first insulating layer away from the substrate, one of the first source electrode and the first drain electrode is connected to the part of the first active layer in the first opening, and the other of the first source electrode and the first drain electrode is connected to the part of the first active layer on the side of the first insulating layer away from the substrate.

[0031] In an embodiment of the present application, the first active layer includes a first connecting portion arranged in the first opening, a second connecting portion arranged on the side of the first insulating layer away from the substrate, and a channel portion connected between the first connecting portion and the second connecting portion;

[0032] The first source electrode is connected to the first connecting portion, the first drain electrode is connected to the second connecting portion, the channel portion covers a sidewall of the first opening, and the first gate electrode is located on one side of the channel portion.

[0033] In an embodiment of the present application, the display panel further includes a first gate insulating layer arranged on the side of the first active layer away from the substrate, the first gate insulating layer covers the first active layer and the side of the first insulating layer away from the substrate, and the first gate electrode is located on at least one side of the first gate insulating layer away from the channel portion.

[0034] In an embodiment of the present application, the first conductive layer is located on a side of the first gate insulating layer away from the first active layer, and the first conductive layer includes the first source electrode and the first drain electrode.

[0035] The first source electrode is connected to the first connecting portion through the first gate insulating layer, and the first drain electrode is connected to the second connecting portion through the first gate insulating layer.

[0036] In an embodiment of the present application, the first conductive layer is located between the first gate insulating layer and the first insulating layer, and the first conductive layer comprises the first drain electrode;

[0037] The first source electrode is located between the first connecting portion and the substrate and connected to the first connecting portion, and the first drain electrode is located between the second connecting portion and the first insulating layer and connected to the second connecting portion.

[0038] In an embodiment of the present application, the number of the first drain electrodes is at least two.

[0039] In an embodiment of the present application, the width-length ratio of the channel portion increases with the increase of the depth of the first opening.

[0040] In an embodiment of the present application, the display panel further comprises:

[0041] A second insulating layer is arranged on the side of the first conductive layer away from the substrate, and a second opening is formed in the second insulating layer;

[0042] The second active layer is arranged in the second opening and partially extends to the side of the second insulating layer away from the substrate; one of the second source electrode and the second drain electrode is connected to the part of the second active layer located in the second opening, and the other of the second source electrode and the second drain electrode is connected to the part of the second active layer located on the side of the second insulating layer away from the substrate.

[0043] In an embodiment of the present application, the first conductive layer comprises the second source electrode, the second source electrode is located at the bottom of the second opening and connected to the part of the second active layer located in the second opening, the second drain electrode is located on the side of the second insulating layer away from the substrate and connected to the part of the second active layer located on the side of the second insulating layer away from the substrate, and the material of the second drain electrode comprises a transparent conductive material.

[0044] In an embodiment of the present application, the second active layer is located on the side of the second source electrode away from the substrate and on the side of the second drain electrode away from the substrate, and the display panel further comprises a second gate insulating layer arranged on the side of the second active layer away from the second source electrode and the second drain electrode, and the second gate electrode is arranged in the second opening and located on the side of the second gate insulating layer away from the second active layer.

[0045] It should be noted that the display panel further comprises a substrate 10 and a first conductive layer 11 disposed on the substrate 10, and the first conductive layer 11 comprises at least one of a first source electrode 22 and a first drain electrode 23, and one of a second source electrode 32 and a second drain electrode 33.

[0046] Further, the first thin film transistor 20 further comprises a first active layer 21 and a first gate electrode 24, and the second thin film transistor 30 further comprises a second active layer 31 and a second gate electrode 34, and at least part of the first active layer 21 and at least part of the first gate electrode 24 are located between the first conductive layer 11 and the substrate 10, and the second active layer 31 and the second gate electrode 34 are located on a side of the first conductive layer 11 away from the substrate 10.

[0047] In an embodiment, the first active layer 21 and the second active layer 31 at least partially overlap in a direction perpendicular to the substrate 10; for example, the first active layer 21 and the second active layer 31 partially overlap in the direction perpendicular to the substrate 10, or a projection of the second active layer 31 on the substrate 10 is located within a projection of the first active layer 21 on the substrate 10; further, the second source electrode 32 and / or the second drain electrode 33 partially overlap with the first active layer 21 in the direction perpendicular to the substrate 10.

[0048] Specifically, please continue to refer to FIG. 2, in an embodiment of the present application, the display panel comprises a substrate 10 and a thin film transistor array layer disposed on the substrate 10.

[0049] In an embodiment, the thin film transistor array layer comprises a buffer layer 53 disposed on the substrate 10, a first insulating layer 41 disposed on a side of the buffer layer 53 away from the substrate 10, a first gate insulating layer 51 disposed on a side of the first insulating layer 41 away from the buffer layer 53, a first interlayer dielectric layer 54 disposed on a side of the first gate insulating layer 51 away from the first insulating layer 41, a second insulating layer 42 disposed on a side of the first interlayer dielectric layer 54 away from the first gate insulating layer 51, a second gate insulating layer 52 disposed on a side of the second insulating layer 42 away from the first interlayer dielectric layer 54, a second interlayer dielectric layer 55 disposed on a side of the second gate insulating layer 52 away from the second insulating layer 42, and the first thin film transistor 20 and the second thin film transistor 30 wrapped in the above-mentioned multiple insulating layers; the first conductive layer 11 is disposed on a side of the first gate insulating layer 51 away from the first active layer 21, further, the first conductive layer 11 is disposed on a side of the first interlayer dielectric layer 54 away from the first gate insulating layer 51, and is covered by the second insulating layer 42.

[0050] In an embodiment, the first thin film transistor 20 can be located between the second thin film transistor 30 and the substrate 10, and the first thin film transistor 20 and the second thin film transistor 30 are at least partially overlapped in a direction perpendicular to the substrate 10, thereby reducing the area occupied by the first thin film transistor 20 and the second thin film transistor 30 in a direction parallel to the substrate 10, and in a display panel of a predetermined size, a larger number of first thin film transistors 20 and second thin film transistors 30 can be arranged, thereby effectively improving the resolution of the display panel.

[0051] Further, the first insulating layer 41 has a first opening 410 formed therein, and the first opening 410 at least partially penetrates the first insulating layer 41. In an embodiment of the present application, the first opening 410 penetrates the first insulating layer 41, i.e., the depth of the first opening 410 is equal to the thickness of the first insulating layer 41.

[0052] For the first thin film transistor 20, the first conductive layer 11 includes a first source 22 and a first drain 23; the first active layer 21 is disposed in the first opening 410 and partially extends to a side of the first insulating layer 41 away from the substrate 10, and the first active layer 21 covers the bottom and the sidewall of the first opening 410 and extends to the surface of the side of the first insulating layer 41 away from the substrate 10; the first gate insulating layer 51 covers the surface of the side of the first active layer 21 away from the substrate 10 and covers the surface of the side of the first insulating layer 41 away from the substrate 10 outside the first opening 410; the first gate 24 is located in the first opening 410 and partially extends to the side of the first gate insulating layer 51 away from the first active layer 21, specifically, the first gate 24 has a through hole at the bottom of the first opening 410, and the first gate 24 is continuously disposed on the side of the first gate insulating layer 51 away from the first active layer 21 at the sidewall of the first opening 410; the first interlayer dielectric layer 54 covers the side of the first gate 24 and the first gate insulating layer 51 away from the substrate 10 and fills in the first opening 410; the first source 22 is disposed on the side of the first interlayer dielectric layer 54 away from the first gate insulating layer 51 and is connected through the first interlayer dielectric layer 54, the through hole of the first gate 24 in the first opening 410, and the part of the first gate insulating layer 51 and the first active layer 21 located in the first opening 410; and the first drain 23 is disposed on the side of the first interlayer dielectric layer 54 away from the first gate insulating layer 51 and is connected through the first interlayer dielectric layer 54 and the part of the first gate insulating layer 51 and the first active layer 21 located on the side of the first insulating layer 41 away from the substrate 10.

[0053] It can be understood that, in the embodiment of the present application, the first opening 410 is formed in the first insulating layer 41, and the first active layer 21 is arranged in the first opening 410 and covers the sidewall of the first opening 410, so that the size of the first active layer 21 in the direction parallel to the substrate 10 can be reduced, and the size of the first thin film transistor 20 is effectively reduced; the first source electrode 22 and the first drain electrode 23 are connected to the part of the first active layer 21 located at the bottom of the first opening 410 and the part of the first active layer 21 located outside the first opening 410 respectively, so that the part of the first active layer 21 covering the sidewall of the first opening 410 constitutes a channel, and the actual size of the channel will not be affected and will not be limited by the process precision on the basis of reducing the size of the first thin film transistor 20; therefore, the size of the first thin film transistor 20 can be effectively reduced in the embodiment of the present application, and in the display panel with a preset size, the number of the first thin film transistor 20 can be increased, the number of pixels in the display panel can be increased, and the resolution of the display panel can be improved.

[0054] In an embodiment, the first active layer 21 includes a first connecting portion 211 arranged in the first opening 410, a second connecting portion 212 arranged on the side of the first insulating layer 41 away from the substrate 10, and a channel portion 213 connected between the first connecting portion 211 and the second connecting portion 212; the first source electrode 22 is connected to the first connecting portion 211 through the first interlayer dielectric layer 54, the through hole of the first gate electrode 24 in the first opening 410, and the first gate insulating layer 51, the first drain electrode 23 is connected to the second connecting portion 212 through the first interlayer dielectric layer 54 and the first gate insulating layer 51, the channel portion 213 at least covers the sidewall of the first opening 410, and the first gate electrode 24 is located on one side of the channel portion 213.

[0055] Specifically, the first source electrode 22 is arranged on the side of the first interlayer dielectric layer 54 away from the first gate insulating layer 51 and is connected to the first connecting portion 211 through the first interlayer dielectric layer 54 and the first gate insulating layer 51, the first drain electrode 23 is arranged on the side of the first interlayer dielectric layer 54 away from the first gate insulating layer 51 and is connected to the second connecting portion 212 through the first interlayer dielectric layer 54 and the first gate insulating layer 51, and the first gate electrode 24 is at least located on the side of the first gate insulating layer 51 away from the channel portion 213.

[0056] It should be noted that, in other embodiments of the present application, the positions of the first source electrode 22 and the first drain electrode 23 can be interchanged, and the structure shown in FIG. 2 is taken as an example for description in the embodiment of the present application.

[0057] In one embodiment, the width-length ratio of the channel portion 213 increases with the increase of the depth of the first opening 410, and thus the width-length ratio of the channel portion 213 can be increased by controlling the depth of the first opening 410 to reduce the VDS (source-drain on-state voltage) of the first thin film transistor 20, and thus the power consumption of the display panel can be reduced.

[0058] Further, the second insulating layer 42 is disposed on the side of the first interlayer dielectric layer 54 away from the substrate 10, and the second insulating layer 42 is provided with a second opening 420, the second opening 420 at least passes through part of the second insulating layer 42, and in the embodiment of the present application, the second opening 420 penetrates through the second insulating layer 42, that is, the depth of the second opening 420 is equal to the thickness of the second insulating layer 42.

[0059] For the second thin film transistor 30, the first conductive layer 11 further includes a second source 32; the second thin film transistor 30 is disposed on the side of the first interlayer dielectric layer 54 away from the first gate insulating layer 51; wherein the second active layer 31 is disposed in the second opening 420 and partially extends to the side of the second insulating layer 42 away from the substrate 10, one of the second source 32 and the second drain 33 is connected to the part of the second active layer 31 located in the second opening 420, and the other of the second source 32 and the second drain 33 is connected to the part of the second active layer 31 located on the side of the second insulating layer 42 away from the substrate 10.

[0060] In one embodiment, the second active layer 31 is located on the side of the second source 32 away from the substrate 10 and on the side of the second drain 33 away from the substrate 10; the second source 32 is located at the bottom of the second opening 420, that is, on the surface of the second interlayer dielectric layer 55 away from the substrate 10 and is disposed corresponding to the second opening 420, and thus the second source 32 is located between the second active layer 31 and the first interlayer dielectric layer 54 and is connected to the part of the second active layer 31 located in the second opening 420; the second drain 33 is located on the surface of the second insulating layer 42 away from the first interlayer dielectric layer 54, and thus the second drain 33 is located between the second active layer 31 and the first interlayer dielectric layer 54 and is connected to the part of the second active layer 31 located on the side of the second insulating layer 42 away from the substrate 10; the second gate insulating layer 52 covers the side of the second active layer 31 away from the second insulating layer 42, the second source 32 and the second drain 33; the second gate 34 is disposed in the second opening 420 and located on the side of the second active layer 31; wherein the second gate 34 fills in the second opening 420 and is located on the side of the channel of the second active layer 31; it can be understood that the first part of the second active layer 31 connected to the second source 32, the second part of the second active layer 31 connected to the second drain 33, and the channel of the second active layer 31 are between the first part and the second part.

[0061] It should be noted that in other embodiments of the present application, the positions of the second source 32 and the second drain 33 can be interchanged, and in the embodiments of the present application, the structure shown in FIG. 2 is taken as an example for description.

[0062] Similarly, in the embodiments of the present application, the second opening 420 is formed in the second insulating layer 42, and the second active layer 31 is arranged in the second opening 420 and covers the sidewall of the second opening 420, so as to reduce the size of the second active layer 31 in the direction parallel to the substrate 10, and effectively reduce the size of the second thin film transistor 30; the second source 32 and the second drain 33 are connected with the part of the second active layer 31 located at the bottom of the second opening 420 and the part of the second active layer 31 located outside the second opening 420, respectively, so that the part of the second active layer 31 covering the sidewall of the second opening 420 constitutes a channel. On the basis of reducing the size of the second thin film transistor 30, the actual size of the channel will not be affected and will not be limited by the process precision. Therefore, the embodiments of the present application can effectively reduce the size of the second thin film transistor 30, and in the display panel with a predetermined size, the number of the second thin film transistor 30 can be increased, the number of pixels in the display panel can be increased, and the resolution of the display panel can be improved.

[0063] It can be understood that the first conductive layer 11 includes the second source 32, the first source 22 and the first drain 23, that is, the second source 32, the first source 22 and the first drain 23 are arranged in the same layer, so as to simplify the process and reduce the process cost.

[0064] In the embodiments, the orthographic projection of the second active layer 31 on the substrate 10 is located in the orthographic projection of the first active layer 21 on the substrate 10; further, the orthographic projection of the second source 32 on the substrate 10 is located in the orthographic projection of the first active layer 21 on the substrate 10, and the orthographic projection of the second drain 33 on the substrate 10 is located in the orthographic projection of the first active layer 21 on the substrate 10.

[0065] The material of the second drain 33 includes a transparent conductive material, such as ITO and the like, so as to effectively improve the aperture ratio of the display panel.

[0066] Further, the display panel provided by the embodiments of the present application can further include a second interlayer dielectric layer 55 arranged on the side of the second thin film transistor 30 away from the first interlayer dielectric layer 54 and away from the substrate 10, and a functional electrode 61 and a signal line 62 arranged on the second interlayer dielectric layer 55.

[0067] In an embodiment, the functional electrode 61 is connected with the second drain electrode 33 through the second interlayer dielectric layer 55, and the functional electrode 61 can be a pixel electrode or a common electrode, and the second thin film transistor 30 can transmit an electrical signal for the pixel electrode or the common electrode; the signal line 62 can be connected with the first drain electrode 23 through the second interlayer dielectric layer 55, the second gate insulating layer 52 and the second insulating layer 42, and the signal line 62 can be used for signal switching, i.e. connecting the first thin film transistor 20 with other devices of a driving circuit in the display panel through a via, and the first thin film transistor 20 can be a switching transistor.

[0068] In an embodiment, the functional electrode 61 and the signal line 62 can be made of a transparent conductive material, such as ITO, etc., which can effectively improve the light transmittance and aperture ratio of the display panel. The materials of the first active layer 21 and the second active layer 31 both include IGZO material, which can reduce the leakage current of the first thin film transistor 20 and the second thin film transistor 30, and improve the off-state ability of the first thin film transistor 20 and the second thin film transistor 30.

[0069] In an embodiment, the display panel can be a liquid crystal display panel, and the display panel includes an array substrate and a color film substrate arranged oppositely, and a liquid crystal layer between the array substrate and the color film substrate, and the structure shown in FIG. 2 is the structure of the array substrate, and the color film substrate and the liquid crystal layer are not shown in the embodiment.

[0070] In other embodiments, the display panel can also be an organic light-emitting diode display panel, and the structure shown in FIG. 2 is the array substrate in the display panel, and the first thin film transistor 20 and the second thin film transistor 30 can be a switching transistor and a driving transistor in a pixel driving circuit, respectively.

[0071] Further, in the embodiment, the manufacturing method of the display panel shown in FIG. 2 can include the following steps:

[0072] A buffer layer 53 is formed on the substrate 10, and the material of the buffer layer 53 can include at least one of silicon nitride and silicon oxide.

[0073] A first insulating layer 41 is formed on the side of the buffer layer 53 away from the substrate 10, and the first insulating layer 41 is patterned to form a first opening 410 in the first insulating layer 41.

[0074] A first semiconductor material layer is formed on the side of the first insulating layer 41 away from the substrate 10, and the first semiconductor material is patterned to obtain a first active layer 21, and the first active layer 21 is located in the first opening 410 and partially extends to the side of the first insulating layer 41 away from the substrate 10.

[0075] A first gate insulating layer 51 is formed on the side of the first insulating layer 41 away from the substrate 10.

[0076] A first metal material layer is formed on the side of the first gate insulating layer 51 away from the substrate 10, and the first metal material layer is patterned to form a first gate 24 located in the first opening 410 and partially extending out of the first opening 410, and the first gate 24 has a via hole formed at the bottom of the first opening 410.

[0077] A first interlayer dielectric layer 54 is formed on the side of the first gate 24 away from the first gate insulating layer 51, and the first interlayer dielectric layer 54 covers the first gate 24 and the first gate insulating layer 51 and fills in the first opening 410.

[0078] A second metal material layer is formed on the side of the first interlayer dielectric layer 54 away from the substrate 10, and the second metal material layer is patterned to form a first conductive layer 11, and the first conductive layer 11 includes a first source 22, a first drain 23, and a second source 32, and the first source 22 is connected through the first interlayer dielectric layer 54, the first gate insulating layer 51, and the part of the first active layer 21 located in the first opening 410, and the first drain 23 is connected through the first interlayer dielectric layer 54, the first gate insulating layer 51, and the part of the first active layer 21 located on the side of the first insulating layer 41 away from the substrate 10.

[0079] A second insulating layer 42 is formed on the first interlayer dielectric layer 54, and the second insulating layer 42 is patterned to form a second opening 420 in the second insulating layer 42, and the second opening 420 corresponds to the second source 32 to expose the surface of the second source 32 away from the first interlayer dielectric layer 54.

[0080] A first transparent conductive material layer is formed on the side of the second insulating layer 42 away from the first interlayer dielectric layer 54, and the first transparent conductive material layer is patterned to form a second drain 33, and the second drain 33 is located outside the second opening 420 and at the edge of the second opening 420.

[0081] A second semiconductor material layer is formed on the side of the second insulating layer 42 away from the first interlayer dielectric layer 54, and the second semiconductor material layer is patterned to form a second active layer 31, and the second active layer 31 is located in the second opening 420 and partially extends out of the second opening 420, and the part of the second active layer 31 located in the second opening 420 is located on the surface of the second source 32 away from the second interlayer dielectric layer 55, and the part of the second active layer 31 located outside the second opening 420 is located on the surface of the second drain 33 away from the second insulating layer 42.

[0082] A second gate insulating layer 52 is formed on a side of the second insulating layer 42 away from the first interlayer dielectric layer 54, and the second gate insulating layer 52 covers the second active layer 31.

[0083] A third metal material layer is formed on a side of the second gate insulating layer 52 away from the second insulating layer 42, and the third metal material layer is patterned to form the second gate 34 in the second opening 420.

[0084] A second interlayer dielectric layer 55 is formed on a side of the second gate insulating layer 52 away from the second insulating layer 42, and the second interlayer dielectric layer 55 covers the second gate 34.

[0085] A second transparent conductive material is formed on a side of the second interlayer dielectric layer 55 away from the second gate insulating layer 52, and the second transparent conductive material is patterned to form a functional electrode 61 and a signal line 62, and the functional electrode 61 passes through the second interlayer dielectric layer 55 and is connected to the second drain 33, and the signal line 62 passes through the second interlayer dielectric layer 55, the second gate insulating layer 52, and the second insulating layer 42 and is connected to the first drain 23.

[0086] In summary, the first thin film transistor 20 and the second thin film transistor 30 are at least partially overlapped in the embodiment of the present application, so that the area occupied by the first thin film transistor 20 and the second thin film transistor 30 can be reduced, and more first thin film transistors 20 and second thin film transistors 30 can be arranged in the display panel, so that the resolution of the display panel can be effectively improved. In addition, the source / drain of the first thin film transistor 20 and the source / drain of the second thin film transistor 30 are arranged in the same layer in the embodiment of the present application, so that the process procedure can be reduced and the process cost can be reduced. Further, the first active layer 21 and the second active layer 31 are arranged in the opening in the embodiment of the present application, so that the channel of the first active layer 21 and the channel of the second active layer 31 are at least partially located at the sidewall of the opening, the size of the first active layer 21 and the second active layer 31 in the direction parallel to the substrate 10 can be reduced, the size of the first thin film transistor 20 and the second thin film transistor 30 can be reduced, so that the number of the first thin film transistor 20 and the second thin film transistor 30 can be effectively increased in the display panel with a preset size, the number of pixels in the display panel can be increased, and the resolution of the display panel can be improved. Further, the size of the first thin film transistor 20 and the second thin film transistor 30 is reduced in the embodiment of the present application, so that the area occupied by the first thin film transistor 20 and the second thin film transistor 30 can be reduced, and the aperture ratio of the display panel can be improved. In addition, the second source 32 and the second drain 33 are arranged in different film layer structures, so that the wiring area of the same conductive layer can be reduced.

[0087] In another embodiment of the present application, please refer to FIG. 3, the difference between this embodiment and the embodiment shown in FIG. 2 is that one first active layer 21, one first source electrode 22 and one first gate electrode 24 are shared by at least two first thin film transistors 20, wherein the number of first drain electrodes 23 connected to the part of the first active layer 21 located on the side of the first insulating layer 41 away from the substrate 10 is at least two.

[0088] Since the first active layer 21 is located at the bottom of the first opening 410 and partially extends to the position outside the first opening 410, the part of the first active layer 21 located on the side of the first opening 410 can be connected to at least two first drain electrodes 23, thereby obtaining at least two first thin film transistors 20, such as the first thin film transistor 201 and the first thin film transistor 202 shown in FIG. 3.

[0089] In another embodiment of the present application, please refer to FIG. 4, the difference between this embodiment and the embodiment shown in FIG. 2 is that the film layer structure of the first thin film transistor 20 is different.

[0090] Specifically, in this embodiment, the display panel comprises a first insulating layer 41 disposed on the side of the buffer layer 53 away from the substrate 10, a first gate insulating layer 51 disposed on the side of the first insulating layer 41 away from the buffer layer 53, a second insulating layer 42 disposed on the side of the first gate insulating layer 51 away from the first insulating layer 41, a second gate insulating layer 52 disposed on the side of the second insulating layer 42 away from the first gate insulating layer 51, and a second interlayer dielectric layer 55 disposed on the side of the second gate insulating layer 52 away from the second insulating layer 42; the first conductive layer 11 is disposed on the side of the first insulating layer 41 away from the substrate 10 and is covered by the first gate insulating layer 51.

[0091] For the first thin film transistor 20, the first conductive layer 11 comprises the first drain electrode 23; the first insulating layer 41 is provided with the first opening 410, and the first source electrode 22 is located at the bottom of the first opening 410, i.e. on the side of the buffer layer 53 away from the substrate 10, the first drain electrode 23 is located on the side of the first insulating layer 41 away from the substrate 10, and at least two first drain electrodes 23 are arranged around the side of the first opening 410.

[0092] The first active layer 21 is partially located in the first opening 410 and partially extends to the outside of the first opening 410; specifically, the part of the first active layer 21 located in the opening is located on the surface of the first source electrode 22 away from the substrate 10, the part of the first active layer 21 located outside the first opening 410 is located on the surface of the first drain electrode 23 away from the first insulating layer 41, and the other part of the first active layer 21 can cover the sidewall of the first opening 410.

[0093] The first gate insulating layer 51 covers a side of the first active layer 21 away from the first source electrode 22 and the first drain electrode 23, and the first gate electrode 24 is located in the first opening 410 and partially extends out of the first opening 410, and the first gate electrode 24 is located at a side of the first gate insulating layer 51 away from the first active layer 21.

[0094] In an embodiment, the first active layer 21 includes a first connecting portion 211 arranged in the first opening 410, a second connecting portion 212 arranged at a side of the first insulating layer 41 away from the substrate 10, and a channel portion 213 connected between the first connecting portion 211 and the second connecting portion 212; wherein the first source electrode 22 is located between the first connecting portion 211 and the substrate 10 and connected to the first connecting portion 211, the first drain electrode 23 is located between the second connecting portion 212 and the first insulating layer 41 and connected to the second connecting portion 212, and the first gate electrode 24 is arranged at a side of the first gate insulating layer 51 away from the channel portion 213.

[0095] The second insulating layer 42 is arranged at a side of the second gate electrode 34 away from the first gate insulating layer 51, and the second insulating layer 42 is provided with a second opening 420.

[0096] For the second thin film transistor 30, the first conductive layer 11 includes the second source electrode 32; the second source electrode 32 is arranged on a surface of the first insulating layer 41 away from the substrate 10, that is, the second source electrode 32 and the first drain electrode 23 can be arranged in the same layer.

[0097] The second opening 420 penetrates the second insulating layer 42 and the first gate insulating layer 51 and is arranged corresponding to the second source electrode 32, and a bottom of the second opening 420 exposes a surface of the second source electrode 32.

[0098] The second drain electrode 33 is arranged on a surface of the second insulating layer 42 away from the substrate 10 and surrounds the second opening 420.

[0099] The second active layer 31 is arranged in the second opening 420 and partially extends out of the second opening 420, a portion of the second active layer 31 in the second opening 420 is arranged on a surface of the second source electrode 32 away from the first insulating layer 41, and a portion of the second active layer 31 out of the second opening 420 is arranged on a surface of the second drain electrode 33 away from the second insulating layer 42.

[0100] The second gate insulating layer 52 covers a side of the second active layer 31 away from the second source electrode 32 and the second drain electrode 33, and the second gate electrode 34 is located at a side of the second gate insulating layer 52 away from the second active layer 31 and fills in the second opening 420.

[0101] A second interlayer dielectric layer 55 is located on the side of the second gate insulating layer 52 away from the second insulating layer 42, and covers the second gate 34, the second active layer 31, and the second drain 33.

[0102] A functional electrode 61 and a signal line 62 are disposed on the side of the second interlayer dielectric layer 55 away from the second gate insulating layer 52, the functional electrode 61 penetrates through the second interlayer dielectric layer 55 and is connected with the second drain 33, and the signal line 62 penetrates through the second interlayer dielectric layer 55, the second gate insulating layer 52, the second insulating layer 42, and the first gate insulating layer 51 and is connected with the first drain 23.

[0103] In the embodiment, the first active layer 21 and the second active layer 31 partially overlap in the direction perpendicular to the substrate 10; further, the second drain 33 and the first active layer 21 partially overlap in the direction perpendicular to the substrate 10.

[0104] Further, in the embodiment, the manufacturing method of the display panel shown in FIG. 4 can include the following steps:

[0105] A buffer layer 53 is formed on the substrate 10, and the material of the buffer layer 53 can include at least one of silicon nitride and silicon oxide.

[0106] A first insulating layer 41 is formed on the side of the buffer layer 53 away from the substrate 10, and the first insulating layer 41 is subjected to a patterning process to form a first opening 410 in the first insulating layer 41.

[0107] A first metal material layer is formed on the side of the first insulating layer 41 away from the substrate 10, and the first metal material layer is subjected to a patterning process to form a first source electrode 22 at the bottom of the first opening 410.

[0108] A second metal material layer is formed on the side of the first insulating layer 41 away from the substrate 10, and the second metal material layer is subjected to a patterning process to form a first conductive layer 11, which includes a first drain electrode 23 disposed outside the first opening 410 and surrounding the first opening 410, and a second source electrode 32 disposed apart from the first drain electrode 23.

[0109] A first semiconductor material layer is formed on the side of the first insulating layer 41 away from the substrate 10, and the first semiconductor material is subjected to a patterning process to obtain a first active layer 21, which is located in the first opening 410 and partially extends outside the first opening 410, and the part of the first active layer 21 located in the first opening 410 is located on the surface of the first source electrode 22 away from the substrate 10, and the part of the first active layer 21 extending outside the first opening 410 is located on the surface of the first drain electrode 23 away from the first insulating layer 41.

[0110] A first gate insulating layer 51 is formed on the side of the first insulating layer 41 away from the substrate 10.

[0111] A third metal material layer is formed on the side of the first gate insulating layer 51 away from the substrate 10, and the third metal material layer is patterned to form a first gate 24 located in the first opening 410 and partially extending out of the first opening 410, the first gate 24 being located on the side of the first gate insulating layer 51 away from the first active layer 21.

[0112] A second insulating layer 42 is formed on the side of the first gate 24 away from the first gate insulating layer 51, and the second insulating layer 42 is patterned to form a second opening 420 in the second insulating layer 42, the second opening 420 corresponding to the second source 32 to expose the surface of the second source 32 on the side away from the first insulating layer 41.

[0113] A first transparent conductive material layer is formed on the side of the second insulating layer 42 away from the first gate insulating layer 51, and the first transparent conductive material layer is patterned to form a second drain 33, the second drain 33 being located outside the second opening 420 and at the edge of the second opening 420.

[0114] A second semiconductor material layer is formed on the side of the second insulating layer 42 away from the first gate insulating layer 51, and the second semiconductor material layer is patterned to form a second active layer 31, the second active layer 31 being located in the second opening 420 and partially extending out of the second opening 420, the part of the second active layer 31 located in the second opening 420 being located on the surface of the second source 32 on the side away from the second interlayer dielectric layer 55, and the part of the second active layer 31 located outside the second opening 420 being located on the surface of the second drain 33 on the side away from the second insulating layer 42.

[0115] A second gate insulating layer 52 is formed on the side of the second insulating layer 42 away from the first gate insulating layer 51, and the second gate insulating layer 52 covers the second active layer 31.

[0116] A third metal material layer is formed on the side of the second gate insulating layer 52 away from the second insulating layer 42, and the third metal material layer is patterned to form a second gate 34 located in the second opening 420.

[0117] A second interlayer dielectric layer 55 is formed on the side of the second gate insulating layer 52 away from the second insulating layer 42, and the second interlayer dielectric layer 55 covers the second gate 34.

[0118] A second transparent conductive material is formed on a side of the second interlayer dielectric layer 55 away from the second gate insulating layer 52, and the second transparent conductive material is subjected to a patterning process to form a functional electrode 61 and a signal line 62, and the functional electrode 61 passes through the second interlayer dielectric layer 55 and is connected to the second drain electrode 33, and the signal line 62 passes through the second interlayer dielectric layer 55, the second gate insulating layer 52, and the second insulating layer 42 and is connected to the first drain electrode 23.

[0119] As described above, in the embodiments of the present application, the first thin film transistor 20 and the second thin film transistor 30 are at least partially overlapped, so that the area occupied by the first thin film transistor 20 and the second thin film transistor 30 can be reduced, and more first thin film transistors 20 and second thin film transistors 30 can be arranged in the display panel, so that the resolution of the display panel can be effectively improved. In addition, in the embodiments of the present application, the source / drain electrodes of the first thin film transistor 20 and the source / drain electrodes of the second thin film transistor 30 are arranged in the same layer, so that the process steps can be reduced and the process cost can be reduced. Furthermore, in the embodiments of the present application, the first active layer 21 and the second active layer 31 are arranged in the opening, so that the channel of the first active layer 21 and the channel of the second active layer 31 are at least partially located at the sidewall of the opening, the size of the first active layer 21 and the second active layer 31 in the direction parallel to the substrate 10 can be reduced, the size of the first thin film transistor 20 and the second thin film transistor 30 can be reduced, so that in the display panel with a predetermined size, the number of the first thin film transistors 20 and the second thin film transistors 30 can be effectively increased, the number of pixels in the display panel can be increased, and the resolution of the display panel can be improved. Furthermore, since the size of the first thin film transistor 20 and the second thin film transistor 30 is reduced in the embodiments of the present application, the area occupied by the first thin film transistor 20 and the second thin film transistor 30 can be reduced, and the aperture ratio of the display panel can be improved. In addition, the first source electrode 22 and the first drain electrode 23 are arranged in different film layers, and the second source electrode 32 and the second drain electrode 33 are arranged in different film layers, so that the wiring area of the same conductive layer can be reduced.

[0120] In another embodiment of the present application, please refer to FIG. 5, the difference between the embodiment shown in FIG. 5 and the embodiment shown in FIG. 4 is that each at least two first thin film transistors 20 share one first active layer 21, one first source electrode 22, and one first gate electrode 24.

[0121] Since the first active layer 21 is located at the bottom of the first opening 410 and partially extends to the position of the periphery of the first opening 410, the part of the first active layer 21 located at the periphery of the first opening 410 can be connected to at least two first drain electrodes 23, so that at least two first thin film transistors 20 can be obtained, for example, the first thin film transistor 201 and the first thin film transistor 202 shown in FIG. 3.

[0122] In addition, referring to FIG. 6, the embodiment of the present application further provides a display device 70, which comprises a backlight module 72 and a display panel 71 arranged on the light emitting side of the backlight module 72.

[0123] It should be noted that the display panel 71 in the display device 70 can be the display panel described in the above embodiment. Since the display device 70 has the same display panel as the above embodiment, the display device 70 has the same beneficial effects as the display panel in the above embodiment, which will not be described here again.

[0124] In the above embodiment, the description of each embodiment has its own focus, and the part not described in detail in a certain embodiment can refer to the related description of other embodiments.

[0125] The display panel and the display device provided by the embodiment of the present application are described in detail above, and the principle and implementation manner of the present application are described by applying specific examples. The above embodiment is only used to help understand the technical solution of the present application and its core idea; the person skilled in the art should understand that the technical solution recorded in the above embodiments can be modified or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A display panel, comprising a first thin film transistor and a second thin film transistor, wherein the first thin film transistor comprises a first source electrode and a first drain electrode, and the second thin film transistor comprises a second source electrode and a second drain electrode; in, At least one of the first source electrode and the first drain electrode is provided in the same layer as one of the second source electrode and the second drain electrode, and the first thin film transistor and the second thin film transistor are at least partially overlapped along the thickness direction of the display panel.

2. The display panel according to claim 1, wherein The display panel further includes: substrate; a first conductive layer disposed on the substrate, the first conductive layer including at least one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode; In which, the first thin film transistor also includes a first active layer and a first gate, the second thin film transistor also includes a second active layer and a second gate, at least part of the first active layer and at least part of the first gate are located between the first conductive layer and the substrate, and the second active layer and the second gate are located on the side of the first conductive layer away from the substrate.

3. The display panel according to claim 2, wherein: The first active layer and the second active layer at least partially overlap along a direction perpendicular to the substrate.

4. The display panel according to claim 2, wherein: The display panel further includes: a first insulating layer, disposed between the substrate and the first conductive layer, wherein the first insulating layer has a first opening; The first active layer is arranged in the first opening and partially extends to the side of the first insulating layer away from the substrate; one of the first source and the first drain is connected to the part of the first active layer located in the first opening, and the other of the first source and the first drain is connected to the part of the first active layer located on the side of the first insulating layer away from the substrate.

5. The display panel according to claim 4, wherein: The first active layer includes a first connecting portion disposed in the first opening, a second connecting portion disposed on a side of the first insulating layer away from the substrate, and a channel portion connected between the first connecting portion and the second connecting portion; The first source is connected to the first connection portion, the first drain is connected to the second connection portion, the channel portion covers the sidewall of the first opening, and the first gate is located on one side of the channel portion. The display panel according to claim 5 , wherein: The display panel also includes a first gate insulating layer arranged on the side of the first active layer away from the substrate, the first gate insulating layer covers the first active layer and the side of the first insulating layer away from the substrate, and the first gate is at least located on the side of the first gate insulating layer away from the channel portion.

7. The display panel according to claim 6, wherein: The first conductive layer is located on a side of the first gate insulating layer away from the first active layer, and the first conductive layer includes the first source electrode and the first drain electrode; The first source electrode is connected to the first connection portion through the first gate insulating layer, and the first drain electrode is connected to the second connection portion through the first gate insulating layer.

8. The display panel according to claim 6, wherein: The first conductive layer is located between the first gate insulating layer and the first insulating layer, and the first conductive layer includes the first drain electrode; The first source electrode is located between the first connection portion and the substrate and is connected to the first connection portion, and the first drain electrode is located between the second connection portion and the first insulating layer and is connected to the second connection portion.

9. The display panel according to claim 7 or 8, wherein: The number of the first drain electrodes is at least two.

10. The display panel according to claim 9, wherein: At least two first drains surround the first opening.

11. The display panel according to any one of claims 5 to 8, wherein: The width-to-length ratio of the channel portion increases as the depth of the first opening increases.

12. The display panel according to claim 2, wherein: The display panel further includes: a second insulating layer, disposed on a side of the first conductive layer away from the substrate, wherein the second insulating layer has a second opening; The second active layer is arranged in the second opening and partially extends to the side of the second insulating layer away from the substrate; one of the second source and the second drain is connected to the portion of the second active layer located in the second opening, and the other of the second source and the second drain is connected to the portion of the second active layer located on the side of the second insulating layer away from the substrate.

13. The display panel according to claim 12, wherein: The first conductive layer includes the second source electrode, which is located at the bottom of the second opening and connected to the portion of the second active layer located in the second opening. The second drain electrode is located on the side of the second insulating layer away from the substrate and connected to the portion of the second active layer located on the side of the second insulating layer away from the substrate. The material of the second drain electrode includes a transparent conductive material.

14. The display panel according to claim 12, wherein: The second active layer is located on a side of the second source electrode away from the substrate and on a side of the second drain electrode away from the substrate. The display panel also includes a second gate insulating layer arranged on a side of the second active layer away from the second source electrode and the second drain. The second gate is arranged in the second opening and is located on a side of the second gate insulating layer away from the second active layer.

15. A display device comprising a backlight module and a display panel, wherein the display panel is disposed on a light-emitting side of the backlight module; The display panel includes a first thin film transistor and a second thin film transistor, the first thin film transistor includes a first source electrode and a first drain electrode, and the second thin film transistor includes a second source electrode and a second drain electrode; in, At least one of the first source electrode and the first drain electrode is provided in the same layer as one of the second source electrode and the second drain electrode, and the first thin film transistor and the second thin film transistor are at least partially overlapped along the thickness direction of the display panel.

16. The display device according to claim 15, wherein The display panel further includes: substrate; a first conductive layer disposed on the substrate, the first conductive layer including at least one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode; In which, the first thin film transistor also includes a first active layer and a first gate, the second thin film transistor also includes a second active layer and a second gate, at least part of the first active layer and at least part of the first gate are located between the first conductive layer and the substrate, and the second active layer and the second gate are located on the side of the first conductive layer away from the substrate.

17. The display device according to claim 16, wherein: The first active layer and the second active layer at least partially overlap along a direction perpendicular to the substrate.

18. The display device according to claim 16, wherein: The display panel further includes: a first insulating layer, disposed between the substrate and the first conductive layer, wherein the first insulating layer has a first opening; The first active layer is arranged in the first opening and partially extends to the side of the first insulating layer away from the substrate; one of the first source and the first drain is connected to the part of the first active layer located in the first opening, and the other of the first source and the first drain is connected to the part of the first active layer located on the side of the first insulating layer away from the substrate.

19. The display device according to claim 18, wherein The first active layer includes a first connecting portion disposed in the first opening, a second connecting portion disposed on a side of the first insulating layer away from the substrate, and a channel portion connected between the first connecting portion and the second connecting portion; The first source is connected to the first connection portion, the first drain is connected to the second connection portion, the channel portion covers the sidewall of the first opening, and the first gate is located on one side of the channel portion.

20. The display device according to claim 16, wherein The display panel further includes: a second insulating layer, disposed on a side of the first conductive layer away from the substrate, wherein the second insulating layer has a second opening; The second active layer is arranged in the second opening and partially extends to the side of the second insulating layer away from the substrate; one of the second source and the second drain is connected to the portion of the second active layer located in the second opening, and the other of the second source and the second drain is connected to the portion of the second active layer located on the side of the second insulating layer away from the substrate.

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