DML driver

Abstract

A DML driver (2a) comprises: a CMOS inverter circuit (INV) that modulates the current flowing through a laser diode (1) in accordance with an input signal; and an inductor (L0) in which a first terminal is connected to a signal input terminal (S0) to which a signal is input from the outside, and a second terminal is connected to the input of the CMOS inverter circuit (INV).

Description

DML Driver

[0001] The present invention relates to a technology for driving a directly modulated laser (DML), and more particularly to a DML driver having a frequency peaking function.

[0002] 16 shows the configuration of a transmission front end using a conventional DML driver (Patent Document 1). The DML driver 2 includes a PMOS transistor M １ and an NMOS transistor M ２ and resistance R ０ The DML driver 2 is configured as a shunt type LD driver that is connected in parallel to a laser diode (LD) 1. FIG. 17A shows the input signal D ０ , FIG. 17B shows a PMOS transistor M １ The current I ＤＲＶＰ , and FIG. 17C shows an NMOS transistor M ２ The current I ＤＲＶＮ , FIG. 17D shows the current I supplied to LD1. ＬＤ Shows.

[0003] The shunt type LD driver receives the input signal D ０ The current I to LD1 is ＬＤ The shunt type LD driver is a driver that modulates the LD1 by modulating the LD1. Because the shunt type LD driver has a high output resistance, it is either monolithically integrated with the LD1 or mounted in the same package as the LD1. Therefore, it is not necessary to match the impedance with the LD1, and it can operate at high speed with low power consumption. In addition, the shunt type LD driver is configured using a CMOS inverter, and the PMOS transistor M １ and NMOS transistor M ２ Since both of these components contribute to the modulation of LD1, it is possible to modulate LD1 with a low input amplitude.

[0004] However, in a transmission front-end configuration using a driver such as that shown in FIG. 16, there is a problem in that the eye opening of the optical output waveform of the LD 1 becomes small.

[0005] Japanese Patent Application Laid-Open No. 2019-165131

[0006] The present invention has been made to solve the above-mentioned problems, and has an object to provide a DML driver that can improve the eye opening of the optical output waveform.

[0007] The DML driver of the present invention is characterized by comprising: a CMOS inverter circuit configured to modulate a current flowing through a laser diode in response to an input signal; and a first inductor having a first terminal connected to a signal input terminal to which a signal is input from outside and a second terminal connected to the input of the CMOS inverter circuit.

[0008] According to the present invention, by providing the first inductor, the bandwidth of the transmission front end consisting of the DML driver and the laser diode can be improved, and the eye opening of the optical output waveform of the laser diode can be improved.

[0009] FIG. 1 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a first embodiment of the present invention. FIG. 2 is a diagram showing the results of simulating the EO response characteristics of the transmission front-end for a conventional configuration and the first embodiment of the present invention. FIGS. 3A and 3B are diagrams showing the optical output waveforms of the LD for the conventional configuration and the first embodiment of the present invention. FIG. 4 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a second embodiment of the present invention. FIG. 5 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a third embodiment of the present invention. FIG. 6 is a circuit diagram showing another configuration of a transmission front-end using a DML driver according to the third embodiment of the present invention. FIG. 7 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a fourth embodiment of the present invention. FIG. 8 is a circuit diagram showing another configuration of a transmission front-end using a DML driver according to the fourth embodiment of the present invention. FIG. 9 is a circuit diagram showing the configuration of a transmission front-end using a DML driver according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing another configuration of a transmission front-end using a DML driver according to the fifth embodiment of the present invention. FIG. 11 is a circuit diagram showing the configuration of a transmission front end using a DML driver according to a sixth embodiment of the present invention. FIGS. 12A and 12B are diagrams showing the optical output waveforms of LDs for a conventional configuration and the sixth embodiment of the present invention. FIG. 13 is a circuit diagram showing another configuration of a transmission front end using a DML driver according to the sixth embodiment of the present invention. FIG. 14 is a circuit diagram showing the configuration of a transmission front end using a DML driver according to a seventh embodiment of the present invention. FIG. 15 is a circuit diagram showing another configuration of a transmission front end using a DML driver according to the seventh embodiment of the present invention. FIG. 16 is a circuit diagram showing the configuration of a transmission front end using a conventional DML driver. FIGS. 17A to 17D are diagrams showing the voltages and currents of the various components of FIG. 16.

[0010] [First embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 shows the configuration of a transmission front end using a DML driver according to a first embodiment of the present invention. A DML driver 2a has one end connected to a bias voltage D ０ｂｉａｓThe other end is connected to the external signal D ０ The signal input terminal S ０ Resistor R connected to ０ and the input signal D ０ A current I flows through LD1 according to ＬＤ A CMOS inverter circuit INV modulates the signal input terminal S. ０ and an inductor L whose second terminal is connected to the input of a CMOS inverter circuit INV. ０ The input signal D ０ takes the value "1" (high level) or "0" (low level).

[0011] The CMOS inverter circuit INV has a gate connected to an inductor L ０ and the source is connected to the second terminal of the power supply voltage V ＳＳＰ and a PMOS transistor M １ and the gate is connected to the inductor L ０ and the source is connected to the second terminal of the power supply voltage V ＳＳＮ (V ＳＳＰ >V ＳＳＮ ), and the drain of an NMOS transistor M ２ The cathode of LD1 is connected to ground.

[0012] In this embodiment, an inductor L is connected in series with the input of the CMOS inverter circuit INV. ０ By connecting the inductor L ０ As a result, the bandwidth of the DML driver 2a is improved, and the EO (Electrical-to-Optical) bandwidth and the eye opening of the optical output waveform of the transmission front end formed by the DML driver 2a and the LD 1 are improved.

[0013] The effects of this embodiment are shown in Figures 2, 3A, and 3B. Creating an electrical equivalent circuit for the LD 1 and using a rate equation representing the electrical-to-optical conversion of the LD 1 enabled simulation in the optical domain. Figure 2 shows the results of simulating the EO (Electrical-to-Optical) response characteristics of the transmission front end for a conventional configuration and this embodiment. Reference numeral 100 in Figure 2 indicates the EO response characteristics of the conventional configuration shown in Figure 16, while reference numeral 101 indicates the EO response characteristics of this embodiment. Comparing the conventional configuration and this embodiment with the focus on the -3 dB frequency, which is an index of the EO band, it can be seen that the EO band is improved by approximately 5 GHz when using the DML driver 2a of this embodiment.

[0014] FIG. 3A shows the results of a simulation of the optical output waveform of the LD 1 for a conventional configuration, and FIG. 3B shows the results of a simulation of the optical output waveform of the LD 1 for the configuration of this embodiment. The examples in FIGS. 3A and 3B show the case where NRZ (Non Return to Zero) signal light with a signal speed of 25 Gbps is output from the LD 1. The amplitude scale on the vertical axis is 200 μW / div, and the time scale on the horizontal axis is 10 ps / div. In the conventional configuration, the horizontal axis magnitude of the eye opening, ΔX, is 37.15 ps, and the vertical axis magnitude, ΔY, is 0.388 mW. In the configuration of this embodiment, ΔX is 38.52 ps, and ΔY is 0.411 mW. As can be seen, compared to the conventional configuration, in this embodiment, ΔX is improved by more than 1 ps, and ΔY is improved by more than 0.02 mW.

[0015] 4 shows the configuration of a transmission front end using a DML driver according to a second embodiment of the present invention. A DML driver 2b of this embodiment differs from the configuration of the DML driver 2a of the first embodiment in that it has an inductor L ０ and the second terminal of the PMOS transistor M １ An inductor L inserted between the gate of ２ and inductor L ０ and the second terminal of the NMOS transistor M ２ An inductor L inserted between the gate of ３As a result, in this embodiment, a configuration with a stronger frequency peaking effect can be achieved.

[0016] In addition, the inductor L ２ , L ３ By individually adjusting the inductance values ​​of the inductors L, it is possible to adjust the rise time and fall time of the optical output waveform of the LD 1. ０ Without using the inductor L ２ , L ３ A configuration using the following is also conceivable.

[0017] 5 shows the configuration of a transmission front end using a DML driver according to a third embodiment of the present invention. The DML driver 2c of this embodiment differs from the configuration of the DML driver 2a of the first embodiment in that the gate is connected to the power supply voltage V ＣＮＴ and the source is connected to the power supply voltage V ＳＳＰ and a PMOS transistor M ３ One end is the power supply voltage V ＳＳＰ A capacitor C connected to ｆ and one end is a capacitor C ｆ and the other end of a resistor R ｆ and the power supply voltage V ＳＳＰ and PMOS transistor M １ A resistor R is inserted between the source of ２ and the power supply voltage V ＳＳＮ and NMOS transistor M ２ A resistor R is inserted between the source of ３ This is the addition of the following.

[0018] PMOS transistor M ３ By turning on the bias voltage D, it is possible to supply a bias current to the LD1. ０ｂｉａｓ and the NMOS transistor M ２ In the linear operating region, the DML driver 2c can be operated linearly. ０ｂｉａｓ When increasing, the PMOS transistor M １ is turned off, but the PMOS transistor M３ A bias current is supplied to the LD1 from the power supply voltage V ＣＮＴ By adjusting the above, it is possible to adjust the linearity of the DML driver 2c.

[0019] Series-connected capacitors C ｆ and resistance R ｆ The PMOS transistor M functions as an RC filter that suppresses overshoot in the optical output waveform of the LD 1. １ When the power supply is turned on, the current to the LD1 increases, and an overshoot appears in the optical output waveform of the LD1. In order to prevent the deterioration of the eye opening of the optical output waveform due to the influence of the overshoot, the capacitor C ｆ and resistance R ｆ By adding the above, it is possible to suppress overshooting by the effect of the RC filter.

[0020] Resistance R ２ , R ３ has the function of suppressing resonance in the power line. ２ , R ３ By adding this, it is possible to suppress changes in the impedance of the power supply due to LC resonance of the parasitic capacitance component and parasitic inductance component of the power supply line. This embodiment may be applied to the second embodiment. The configuration of the DML driver 2h in this case is shown in FIG.

[0021] 7 shows the configuration of a transmission front end using a DML driver according to a fourth embodiment of the present invention. A DML driver 2d of this embodiment differs from the configuration of the DML driver 2c of the third embodiment in that one end is connected to a bias voltage D ０ｂｉａｓ and the other end of a capacitor C ０ One end is the power supply voltage V ＳＳＰ and the other end of a capacitor C ２ One end is the power supply voltage V ＳＳＮ and the other end of a capacitor C ３ One end is the power supply voltage V ＣＮＴ and the other end of a capacitor C ４In this embodiment, a decoupling capacitor C ０ , C ２ ~C ４ By adding this, it is possible to suppress resonance in the power supply line. This embodiment may be applied to the second embodiment. The configuration of the DML driver 2i in this case is shown in FIG.

[0022] 9 shows the configuration of a transmission front end using a DML driver according to a fifth embodiment of the present invention. A DML driver 2e of this embodiment differs from the configuration of the DML driver 2c of the third embodiment in that it has an NMOS transistor M ２ Source resistance R ３ A capacitor C ５ The capacitor C ５ By adding the above, in this embodiment, it is possible to improve the high frequency characteristics of the DML driver 2e. This embodiment may be applied to the second and fourth embodiments. The configuration of the DML driver 2j in this case is shown in FIG. 10.

[0023] 11 shows the configuration of a PAM4 (4-level Pulse Amplitude Modulation) transmission front end using a DML driver according to a sixth embodiment of the present invention. A DML driver 2f of this embodiment has one end connected to a bias voltage D ０ｂｉａｓ , and the other end is connected to the signal input terminal S ０ Resistor R connected to ０ and one end is bias voltage D １ｂｉａｓ , and the other end is connected to the MSB (Most Significant Bit) side signal input terminal S １ Resistor R connected to １ and a CMOS inverter circuit INV ０ , INV １ and the first terminal is a signal input terminal S ０ and the second terminal is connected to a CMOS inverter circuit INV ０ Inductor L connected to the input of ０ and the first terminal is a signal input terminal S １and the second terminal is connected to a CMOS inverter circuit INV １ Inductor L connected to the input of １ The input signal D ０ , D １ Each of these takes a value of "1" (high level) or "0" (low level).

[0024] CMOS inverter circuit INV ０ The gate is connected to the inductor L ０ and the source is connected to the second terminal of the power supply voltage V ＳＳＰ and a PMOS transistor M １ and the gate is connected to the inductor L ０ and the source is connected to the second terminal of the power supply voltage V ＳＳＮ and an NMOS transistor M whose drain is connected to the anode of LD1. ２ It consists of:

[0025] CMOS inverter circuit INV １ The gate is connected to the inductor L １ and the source is connected to the second terminal of the power supply voltage V ＳＳＰ and a PMOS transistor M ４ and the gate is connected to the inductor L １ and the source is connected to the second terminal of the power supply voltage V ＳＳＮ and an NMOS transistor M whose drain is connected to the anode of LD1. ５ It consists of:

[0026] In this embodiment, the signal input terminal S ０ , S １ The LSB side input signal D ０ and MSB side input signal D １ For each of these, a CMOS inverter circuit INV ０ , INV １ Furthermore, according to this embodiment, the eye openings of the PAM4 optical output waveform are improved compared to the configuration of a PAM4 transmission front end using a conventional DML driver, and the delay between the eye openings is also improved.

[0027] FIG. 12A shows the results of a simulation of the optical output waveform of the LD1 for a PAM4 transmission front-end configuration using a conventional DML driver, and FIG. 12B shows the results of a simulation of the optical output waveform of the LD1 for the configuration of this embodiment. The examples in FIGS. 12A and 12B show the case where a PAM4 signal light with a signal speed of 50 Gbps is output from the LD1. The amplitude scale on the vertical axis is 200 μW / div, and the time scale on the horizontal axis is 10 ps / div. In each of FIGS. 12A and 12B, a delay occurs as the eye opening moves from the upper to the lower eye opening. Comparing FIGS. 12A and 12B, it can be seen that the eye openings of the PAM4 optical output waveform for the configuration of this embodiment are improved compared to the conventional configuration, and the delay between each eye opening is also improved.

[0028] This embodiment may be applied to the second embodiment. The configuration of the DML driver 2k in this case is shown in FIG. 13. The DML driver 2k is connected to the DML driver 2f via an inductor L ０ and the second terminal of the PMOS transistor M １ An inductor L inserted between the gate of ２ and inductor L ０ and the second terminal of the NMOS transistor M ２ An inductor L inserted between the gate of ３ and inductor L １ and the second terminal of the PMOS transistor M ４ An inductor L inserted between the gate of ４ and inductor L １ and the second terminal of the NMOS transistor M ５ An inductor L inserted between the gate of ５ This is the addition of the following.

[0029] 14 shows the configuration of a PAM4 transmission front end using a DML driver according to a seventh embodiment of the present invention. A DML driver 2g of this embodiment differs from the DML driver 2f of the sixth embodiment in that one end is connected to a power supply voltage V ＳＳＰ A capacitor C connected to ｆ０ , C ｆ１and one end is a capacitor C ｆ 0 and the other end of resistor R ｆ０ and one end is a capacitor C ｆ１ and the other end of a resistor R ｆ１ and the power supply voltage V ＳＳＰ and PMOS transistor M １ A resistor R is inserted between the source of ２ and the power supply voltage V ＳＳＮ and NMOS transistor M ２ A resistor R is inserted between the source of ３ and the power supply voltage V ＳＳＰ and PMOS transistor M ４ A resistor R is inserted between the source of ４ and the power supply voltage V ＳＳＮ and NMOS transistor M ５ A resistor R is inserted between the source of ５ and one end is bias voltage D ０ｂｉａｓ and the other end of a capacitor C ０ and one end is bias voltage D １ｂｉａｓ and the other end of a capacitor C １ One end is the power supply voltage V ＳＳＰ and the other end of a capacitor C ２ One end is the power supply voltage V ＳＳＮ and the other end of a capacitor C ３ and an NMOS transistor M ２ Source resistance R ３ and a capacitor C connected in parallel ５ and an NMOS transistor M ５ Source resistance R ５ and a capacitor C connected in parallel ６ This is the addition of the following.

[0030] In this embodiment, the capacitor C ｆ０ , C ｆ１ , C ０ ~C ６ and resistance R ｆ０ , R ｆ１ , R ２ ~R５ By adding the above, it is possible to improve the overshoot and high frequency characteristics of the optical output waveform.

[0031] This embodiment may be applied to the second embodiment. The configuration of the DML driver 2l in this case is shown in FIG. 15. The DML driver 2l is connected to the DML driver 2g via an inductor L ２ ~L ５ This is an addition of the above.

[0032] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0033] (Supplementary Note 1) The DML driver of the present invention comprises a CMOS inverter circuit configured to modulate a current flowing through a laser diode in accordance with an input signal, and a first inductor having a first terminal connected to a signal input terminal to which a signal is input from outside and a second terminal connected to the input of the CMOS inverter circuit.

[0034] (Supplementary Note 2) In the DML driver described in Supplementary Note 1, the CMOS inverter circuit comprises a first PMOS transistor having a gate connected to the second terminal of the first inductor, a source connected to a first power supply voltage, and a drain connected to the anode of the laser diode, and a first NMOS transistor having a gate connected to the second terminal of the first inductor, a source connected to a second power supply voltage, and a drain connected to the anode of the laser diode.

[0035] (Supplementary Note 3) The DML driver described in Supplementary Note 2 further includes a second inductor inserted between a second terminal of the first inductor and a gate of the first PMOS transistor, and a third inductor inserted between the second terminal of the first inductor and a gate of the first NMOS transistor.

[0036] (Supplementary Note 4) The DML driver described in Supplementary Note 2 or 3 further includes: a second PMOS transistor having a gate connected to a third power supply voltage, a source connected to the first power supply voltage, and a drain connected to an anode of the laser diode; a first resistor inserted between the first power supply voltage and the source of the first PMOS transistor; a second resistor inserted between the second power supply voltage and the source of the first NMOS transistor; a first capacitor having one end connected to the first power supply voltage; and a third resistor having one end connected to the other end of the first capacitor and the other end connected to the anode of the laser diode.

[0037] (Supplementary Note 5) The DML driver described in Supplementary Note 4 further includes a second capacitor having one end connected to the first power supply voltage and the other end connected to ground, a third capacitor having one end connected to the second power supply voltage and the other end connected to ground, and a fourth capacitor having one end connected to the third power supply voltage and the other end connected to ground.

[0038] (Supplementary Note 6) The DML driver according to Supplementary Note 4 further includes a second capacitor connected in parallel with the second resistor.

[0039] (Supplementary Note 7) In the DML driver described in Supplementary Note 2, the CMOS inverter circuit and the first inductor are provided for a first signal input terminal to which a first signal is input and a second signal input terminal to which a second signal is input, respectively.

[0040] (Supplementary Note 8) The DML driver described in Supplementary Note 7 further includes a second inductor inserted between the second terminal of the first inductor and the gate of the first PMOS transistor, and a third inductor inserted between the second terminal of the first inductor and the gate of the first NMOS transistor, for the CMOS inverter circuit on the first signal input terminal side and the first inductor on the first signal input terminal side, and for the CMOS inverter circuit on the second signal input terminal side and the first inductor on the second signal input terminal side.

[0041] The present invention can be applied to a technique for directly modulating the optical output of an LD.

[0042] 1...LD, 2a to 2l...DML drivers, INV, INV ０ , INV １ ...CMOS inverter circuit, M １ , M ３ , M ４ ...PMOS transistor, M ２ , M ５ ...NMOS transistor, L ０ ~L ５ ...inductor, R ０ ~R ５ , R ｆ , R ｆ０ , R ｆ１ ...Resistance, C ０ ~C ６ , C ｆ , C ｆ０ , C ｆ１ ...Capacitor.

Claims

1. A DML driver comprising: a CMOS inverter circuit configured to modulate the current flowing through a laser diode in response to an input signal; and a first inductor having a first terminal connected to a signal input terminal to which a signal is input from an external device and a second terminal connected to the input of the CMOS inverter circuit.

2. A DML driver according to claim 1, wherein the CMOS inverter circuit comprises: a first PMOS transistor having a gate connected to the second terminal of the first inductor, a source connected to a first power supply voltage, and a drain connected to the anode of the laser diode; and a first NMOS transistor having a gate connected to the second terminal of the first inductor, a source connected to a second power supply voltage, and a drain connected to the anode of the laser diode.

3. A DML driver according to claim 2, further comprising: a second inductor inserted between the second terminal of the first inductor and the gate of the first PMOS transistor; and a third inductor inserted between the second terminal of the first inductor and the gate of the first NMOS transistor.

4. A DML driver according to claim 2 or 3, further comprising: a second PMOS transistor having a gate connected to a third power supply voltage, a source connected to the first power supply voltage, and a drain connected to the anode of the laser diode; a first resistor inserted between the first power supply voltage and the source of the first PMOS transistor; a second resistor inserted between the second power supply voltage and the source of the first NMOS transistor; a first capacitor having one end connected to the first power supply voltage; and a third resistor having one end connected to the other end of the first capacitor and the other end connected to the anode of the laser diode.

5. A DML driver according to claim 4, further comprising: a second capacitor having one end connected to the first power supply voltage and the other end connected to ground; a third capacitor having one end connected to the second power supply voltage and the other end connected to ground; and a fourth capacitor having one end connected to the third power supply voltage and the other end connected to ground.

6. The DML driver according to claim 4, further comprising a second capacitor connected in parallel with said second resistor.

7. A DML driver according to claim 2, wherein the CMOS inverter circuit and the first inductor are provided for a first signal input terminal to which a first signal is input and a second signal input terminal to which a second signal is input, respectively.

8. A DML driver according to claim 7, further comprising a second inductor inserted between the second terminal of the first inductor and the gate of the first PMOS transistor, and a third inductor inserted between the second terminal of the first inductor and the gate of the first NMOS transistor, for the CMOS inverter circuit on the first signal input terminal side and the first inductor on the first signal input terminal side, and for the CMOS inverter circuit on the second signal input terminal side and the first inductor on the second signal input terminal side.

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