CMOS-compatible system and method for solving boolean satisfiability problems

Abstract

In one aspect, a network comprises a plurality of computation nodes, each comprising an input, an output, connections to first and second voltage rails, a capacitor electrically connected to the input configured to store state information as a state voltage, a comparator electrically connected to the capacitor and the output, configured to connect the output to the first voltage rail when the state voltage exceeds the threshold, and the second voltage rail when the state voltage is below the threshold, a plurality of programming units, a plurality of outputs, a network of NOR gates connected to the plurality of inputs and the plurality of outputs, each comprising an input electrically connected to the output of at least one of the plurality of clause formation units, an output connected to an input of at least one computation node, and a current conversion circuit.

Description

Attorney docket # 204606-0186-00WO CMOS-COMPATIBLE SYSTEM AND METHOD FOR SOLVING BOOLEAN SATISFIABILITY PROBLEMS CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to US Provisional Patent Application No.63 / 633,922, filed on April 15, 2024, incorporated herein by reference in its entirety. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under FA8650‐23‐C‐7312 awarded by the Air Force Research Laboratory. The government has certain rights in the invention. BACKGROUND OF THE INVENTION

[0003] Satisfiability (SAT) is among the most attractive NP-complete problems that computer scientists aim to solve using various algorithms. Although finding an analytical solution to SAT is deemed unlikely, this unlikelihood remains a topic of debate and an unanswered question. Due to the nature of the SAT / MaxSAT problems, solvers often incorporate smart trial and error, informed choices, and annealing. These methods are delivering better results each year, thanks to advancements in algorithms and hardware. However, the polynomial time constraint limits these algorithms to a relatively small number of inputs for a complete solution or lengthy solution times.

[0004] In recent years, various Ising machines have emerged as a hardware alternative to solve quadratic unconstrained binary optimization (QUBO) problems, such as max-cut problems. However, not all NP optimization problems can be expressed in QUBO form; many include cubic or even higher-order terms. These more complex problems require additional hardware, potentially reducing the effectiveness of an Ising machine when attempting to map suchAttorney docket # 204606-0186-00WO problems to its architecture. Additional information about such Ising machines may be found in US Patent Application No.17 / 996,283, filed on October 14, 2022, incorporated herein by reference.

[0005] Solving a SAT problem can be described as answering a question of whether a Boolean (i.e., logic) function evaluates true for at least one assignment of its input variables. A SAT problem is typically presented in a so-called conjuctive normal form (CNF), where the CNF of a Boolean function contains a conjunction of clauses each consisting of logical disconjuction of k literals, in which case a SAT problem is typically termed k-SAT problem. For example, in case of a 3-SAT problem (i.e., k = 3) where each clause contains exactly three literals, the literals in each of the NCclauses may take any one of the N variables or their complements, as shown inEquation 1 below:ℓ^,^ ∈ ^ ^^,^ଶ, … ,^ே,തതത ^^,ത^തଶത, … ,ത^തതேത^, 1 ≤ ^ ≤ ^^ , 1 ≤ ^ ≤ 3Equation 1 3-variable clauses are created by a disjunction of any three literals as shown in Equation 2: ^^ = ൫ℓ^,^ ∨ ℓ^,ଶ ∨ ℓ^,ଷ൯The CNF form F of a 3-SAT problem can then be written as shown in Equation 3:^^ ^^,^ଶ, … ,^ே^ = ^^ ∧ ^ଶ ∧ …∧ ^ே^

[0006] A generalization of the Boolean Satisfiability problem (or SAT problem) described above is a so-called Maximum Satisfiability problem (or MaxSAT problem). Unlike a SAT problem which asks whether there is at least one assignment of all variables Xi ,1 ≤ i ≤ N that renders allclauses ^^ , 1 ≤ ^ ≤ ^^ true, a MaxSAT problem asks for an assignment of variables Xi thatmaximizes the number of clauses that are made true with that assignment.Attorney docket # 204606-0186-00WO

[0007] Thus, there is a need in the art for a CMOS-based solution that is configured to solve a SAT problem and / or a MaxSAT problem, to vastly improve the performance of computational systems dependent on such solutions. SUMMARY OF THE INVENTION

[0008] In one aspect, a network comprises a plurality of computation nodes, each comprising an input, an output, connections to first and second voltage rails, a capacitor electrically connected to the input configured to store state information as a state voltage; a comparator electrically connected to the capacitor and the output, configured to connect the output to the first voltage rail when the state voltage exceeds the threshold, and the second voltage rail when the state voltage is below the threshold, a plurality of programming units, each comprising an input connected to the output of one of the plurality of computation nodes, a plurality of outputs, a plurality of memory cells configured to store digital values, a network of logic gates configured to connect the input to one of the plurality of outputs based on the stored digital values in the plurality of memory cells, a plurality of clause formation units, each comprising a plurality of k inputs, each electrically connected to at least one of the outputs of one of the plurality of programming units, a plurality of k outputs, andva network of NOR gates connected to the plurality of inputs and the plurality of outputs such that each output of index i between 1 and k in the plurality of outputs is the NOR of all inputs except the input of index i; and a plurality of coupling units, each comprising an input electrically connected to the output of at least one of the plurality of clause formation units, an output connected to an input of at least one computation node, and a current conversion circuit electrically connected to the input and the output, configured to convert a voltage at the input to a current at the output.

[0009] In one embodiment, the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a resistor. In one embodiment, the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a transistor having a drain terminal connected to the output of the coupling unit via switches controlled by the voltage at the input of the coupling unit. In one embodiment, the network further comprises a spin perturbation control circuit configured to change a polarity of a state voltage in at least one computation node of the plurality of computation nodes.Attorney docket # 204606-0186-00WO

[0010] In one embodiment, the spin perturbation control circuit is configured to generate a perturbation signal from a random source or a pseudo-random source. In one embodiment, the spin perturbation control circuit is configured to generate a perturbation signal such that the rate of spin perturbation events diminishes over time. In one embodiment, the rate of spin perturbation events is configured to have an exponential decay over time. In one embodiment, the rate of spin perturbation events is configured to have a linear decay over time. In one embodiment, the network further comprises a clause perturbation control circuit configured to switch a polarity of at least one of the outputs at least one clause formation unit. In one embodiment, the network further comprises a clause perturbation control circuit configured such that clauses that are satisfied do not contribute to the coupling currents during a perturbation event. In one embodiment, the clause perturbation control circuit is configured to decrease a rate of perturbation events over time. In one embodiment, the clause perturbation control circuit is configured to decrease a rate of perturbation events exponentially over time. In one embodiment, the clause perturbation control circuit is configured to decrease a rate of perturbation events linearly over time. In one embodiment, the clause perturbation control circuit is configured to maintain a constant rate of perturbation events over time. In one embodiment, the network further comprises a digital logic that evaluates clauses’ logical values and if all clauses are true (or satisfied) triggers the early termination signal to sample logic states of variables and disconnect the nodes from the coupling units for power saving.

[0011] In one aspect, a network comprises a plurality of computation nodes, a plurality of programming units, a plurality of clause formation units, and a plurality of coupling units, wherein each of the plurality of computation nodes comprises an input configured to receive currents from at least one of the coupling units, an output configured to have at least two discrete output voltages, a capacitor for storing an internal state as a voltage, a comparator configured to compare the voltage across the capacitor against a threshold to produce a first discrete voltage value at the output if the voltage across the capacitor exceeds the threshold, and a second, different discrete voltage value at the output if the voltage across the capacitor is lower than the threshold, and a current conveyor circuit having an input connected to the input of the computation node and an output connected to the capacitor of the computation node, the current conveyor circuit configured to mirror a scaled version of the current received at the input into the capacitor, wherein each of the plurality of programming units comprises at least one inputAttorney docket # 204606-0186-00WO electrically connected to an the output of at least one computation node, a plurality of outputs, a plurality of one-bit memory cells configured to store polarity and address bits, and a network of logic gates connecting the at least one input to one of the plurality of outputs based on the content of the memory cells, wherein each of the plurality of clause formation units comprises a plurality of inputs electrically connected to the output of at least one of the plurality of programming units, a plurality of outputs, and a network of logic gates that take as inputs INithe voltages at the plurality of inputs and generate the plurality of outputs OUT(i) such that OUT(i) = NOR(IN1,..,INj,..,INk) where 1 ≤ i ≤ k , j ≠ i, and wherein each of the plurality of coupling units comprises an input electrically connected to the output of at least one clause formation unit, an output configured to have at least two discrete output current values and connected to an input of at least one computation node, and means to convert voltage values at the input to currents and produce current proportional to the input voltage at the output of the coupling unit.

[0012] In one embodiment, a current conveyor circuit of each computation node is configured to hold its input at a constant voltage while mirroring the current received to the capacitor. In one embodiment, the plurality of memory cells in the plurality of programming units comprise flip- flops. In one embodiment, the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a resistor. In one embodiment, the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a transistor having a drain terminal connected to the output of the coupling unit via switches controlled by the voltage at the input of the coupling unit. In one embodiment, the network further comprises a spin perturbation control circuit configured to change a polarity of a state voltage in at least one computation node of the plurality of computation nodes.

[0013] In one embodiment, the spin perturbation control circuit is configured to generate a perturbation signal from a random source or a pseudo-random source. In one embodiment, the spin perturbation control circuit is configured to generate a perturbation signal such that the rate of spin perturbation events diminishes over time. In one embodiment, the rate of spin perturbation events is configured to have an exponential decay over time. In one embodiment, the rate of spin perturbation events is configured to have a linear decay over time. In one embodiment, the network further comprises a clause perturbation control circuit configured to switch a polarity of at least one of the outputs at least one clause formation unit.Attorney docket # 204606-0186-00WO

[0014] In one embodiment, the network further comprises a clause perturbation control circuit configured such that clauses that are satisfied do not contribute to the coupling currents during a perturbation event. In one embodiment, the clause perturbation control circuit is configured to decrease a rate of perturbation events over time. In one embodiment, the clause perturbation control circuit is configured to decrease a rate of perturbation events exponentially over time. In one embodiment, the clause perturbation control circuit is configured to decrease a rate of perturbation events linearly over time. In one embodiment, the clause perturbation control circuit is configured to maintain a constant rate of perturbation events over time. In one embodiment, the network further comprises a digital logic that evaluates clauses’ logical values and if all clauses are true (or satisfied) triggers the early termination signal to sample logic states of variables and disconnect the nodes from the coupling units for power saving. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The foregoing purposes and features, as well as other purposes and features, will become apparent with reference to the description and accompanying figures below, which are included to provide an understanding of the invention and constitute a part of the specification, in which like numerals represent like elements, and in which: Fig.1 is an example CMOS circuit for a computational node in SKI-SAT. The reset voltage VCMis typically chosen to be equal or close to threshold Vth of the comparator; Fig.2 is a SKI-SAT top-level circuit architecture; Fig.3A, Fig.3B, and Fig.3C are an example unit element of the Variables-to-Clauses N×NCarray for a 3-SAT implementation; Fig.4 is a CFCCS unit for a 3 literal clause with satisfiability signal Tj; Fig.5A, Fig.5B, and Fig.5C are a clause to the coupling current (C2CC) unit for a 3 literal SAT solver; Fig.6 is an example circuit schematic of SKI-SAT node, which includes a class-AB current conveyor, node capacitor C, and a comparator circuit implemented as an inverter logic gate;Attorney docket # 204606-0186-00WO Fig.7 is a CFCSS unit with clause perturbation logic and perturbation signal P, satisfiability signal Tj and early termination signal ETSB; Fig.8 is an exemplary distributed NOR gate implementation; Fig.9 is an exemplary computing system for use with the disclosed system and method; Fig.10 is a set of graphs relating to a circuit-level simulation of SKI-SAT finding a solution for uf50-218 / 05; Fig.11 is a pie chart showing power ratings of individual blocks while solving the uf50-218 / 05; Fig.12 is a set of graphs showing a SATLIB instance uf20-91 / 014 settling into a correct assignment; Fig. 13 is a set of graphs of penalty function over time for a 20-variable 3-SAT instance (uf20- 91 / 014) as solved by SKI-SAT solver for 10 iterations resulting in 50% success rate; Fig.14 is a solution histogram for 1,000 iterations of SKI-SAT MATLAB model solving uf20- 91 / 014 with 45.1% success rate; Fig.15 is a graph showing that SKI-SAT perturbation is effective in improving the success rate; Fig.16 is a graph of TtS in microseconds across the number of variables, and a graph of EtS in nanojoules across the number of variables in SATLIB benchmark sets; Fig.17 is a photograph of a fabricated integrated circuit die; and Fig.18 is a diagram of an integrated circuit layout. DETAILED DESCRIPTION

[0016] It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for the purpose of clarity, many other elements found in relatedAttorney docket # 204606-0186-00WO systems and methods. Those of ordinary skill in the art may recognize that other elements and / or steps are desirable and / or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein. The disclosure herein is directed to all such variations and modifications to such elements and methods known to those skilled in the art.

[0017] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, exemplary methods and materials are described.

[0018] As used herein, each of the following terms has the meaning associated with it in this section.

[0019] The articles “a” and “an” are used herein to refer to one or to more than one (i.e., to at least one) of the grammatical object of the article. By way of example, “an element” means one element or more than one element.

[0020] “About” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, is meant to encompass variations of ±20%, ±10%, ±5%, ±1%, and ±0.1% from the specified value, as such variations are appropriate.

[0021] Throughout this disclosure, various aspects of the invention can be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 2.7, 3, 4, 5, 5.3, 6 and any whole and partial increments therebetween. This applies regardless of the breadth of the range.Attorney docket # 204606-0186-00WO

[0022] The device and methods disclosed herein, which may be referred to herein as “SKI- SAT,” comprises a method or a Complementary Metal-oxide Semiconductor (CMOS) compatible hardware for solving Boolean satisfiability problems of any number of logic variables and clauses. Firstly, a SAT problem is mapped onto the hardware. The mapping procedure comprises assigning computation nodes of SKI-SAT to each logic variable present in the SAT problem (i.e., for a SAT problem with N variables, N nodes are required). The mapping further comprises programming a programmable array that associates variables presented at the outputs of computation nodes to literals of each of the clauses in the SAT problem. Once programmed, the array connects literals to clause-formation and coupling control signal generation logic. The mapping of a SAT problem onto the hardware may also comprise programming an area of coupling units so that the coupling units receive appropriate control signals from the clause-formation and coupling control signals generation logic. Depending on the state of the control signals, the coupling units may produce coupling currents at their outputs, which are connected to the inputs of the computation nodes. After the completion of SAT problem mapping onto SKI-SAT hardware, the nodes are initialized to initial states followed by a time period (sometimes referred to herein as an “annealing time”) during which interaction between the computation nodes is enabled. At the completion of the annealing time, the outputs from the computation nodes are sampled as a solution to the mapped SAT problem. For the purpose of escaping local minima in a penalty function minimized by the disclosed SKI-SAT system in its search for a global minimum solution to a SAT problem, some embodiments of the disclosed device also include random or pseudo-random perturbations acting on either nodal states directly or clause formation and coupling control signal generation logic instead.

[0023] To construct a SKI-SAT solver machine (i.e., a CMOS circuit topology that minimizes the number of unsatisfied clauses in F from Equation 3 above), it is first necessary to derive an appropriate penalty (or cost) function. For this purpose, one such potential cost function is a negation of the CNF form as shown in Equation 4 below, i.e., a satisfiability of the CNF form Fis converted to a “dissatisfiability” of a logical Boolean function ^ത):^ത^ ^^,^ଶ, … ,^ே^ = ത ^ത^ത ∨ ത ^തଶത ∨ …∨ ത ^തതேത^തAttorney docket # 204606-0186-00WO

[0024] The negated CNF form ^തis then converted into a penalty (or cost) function H byreplacing logical OR and AND operations in ^തwith addition and multiplication operations,respectively, as well as replacing complemented variablesത^ത^തwith (1 − Xk). By way of example,Equation 5 shows the conversion of ^തcontaining 3 clauses and 6 variables into the corresponding penalty function H. ^= ^^ ∨ ത ^തଶത ∨ ^ହ ∧ ത^തଷത ^^^௧^^^^ ^ ^ ^ ∨ ത ^തସത ∨ ^ହ^ ∧ ^ത^ത^ത ∨ ^ସ ∨ ^ଶ^ ^ۛ ۛۛ ۛۛ ^ത തതത ^^^௩^^௧௧^ ^^^௧^ = ^ ^^ ∧ ^ଶ ∧ ത ^തହത^ ∨ ^^ଷ ∧ ^ସ ∧ ത ^തହത^ ∨ ^^^ ∧ ത ^തସത ∧ ത ^തଶത^ ^ۛ ۛۛ ۛۛ ۛۛ ۛۛ ^ۛ^1 − ^^^^ଶ^1 − ^ହ^ + ^ଷ^ସ^1 − ^ହ^ + ^^^1 − ^ସ^^1 − ^ଶ^Equation 5

[0025] The next step in constructing a SKI-SAT circuit topology that minimizes penalty function H is to derive a gradient vector of H within the Hamming space {0,1}Nspanned by variables Xk,1 ≥ k ≥ N, as shown in Equation 6. ^^ ^^ ^ ்∇^ = ^ … ^^^ ^^ ^ ൨

[0026] Following the example in Equation 5, the gradient of H becomes: −^ଶ^1 − ^ହ^ −^ଶത^തହതې ۑAttorney docket # 204606-0186-00WO

[0027] Since all variables in Equation 7 are binary (i.e., 0 or 1), the multiplicative terms can be replaced with logical AND or, alternatively, with logical NOR as shown in Equation 8. −^ ∧ ത ^തത തۍ −ത^തതതଶതതത ∨തത ^തതହതۍ ଶ ହ ې^^ ∧ − ^^ ∧ ത ^തത ێ ^^ ∨ ^ − ത ^തത^തത ∨തതതതതېതതത ത തതതതതതതതത തതത ۑۑ ۑ

[0028] It is now possible to define an N-dimensional real vector ^^^ that resides in a unit hypercube ΩN(i.e., for each element viof ^^^, vi∈ [0,1]). It is also possible to develop a surjective function f : ΩN → {0,1}Nsuch that the real vector ^^^is mapped onto a Hamming vector X following the mapping rule in Equation 9. ^= ^^^^^^ ^. ^. 0, ^^ < 0.5^^ = ^1, ^ , 1 ≤ ^ ≤ ^^ ≥ 0.5

[0029] By following the construction ^^^ ^^^ = ^∇^, it is possible to define a set of differentialequations (see Equation 10) that govern the operation of a SKI-SAT circuit and describe its gradient decent capability in minimizing penalty function H. ^^^ ^^^^ = −^^^ , 1 ≤ ^ ≤ ^^Equation 10 Following the example of a SAT problem with 3 clauses and 6 variables defined in Equation 5, Equation 7, and Equation 8, the corresponding set of differential equations is shown in Equation 11:Attorney docket # 204606-0186-00WO ^^1 ^^= − തതതതതതതതതതതതത^^ ^^^ = +^^ଶ ∨ ^ହ1

[0030] The gradient descent nature of the system described by Equation 10 and Equation 11 and its ability to minimize the cost function H (i.e., enforcing the number of dissatisfied clauses ^^in F to be non-increasing over time) can be demonstrated by calculating the rate of change of H, as shown in Equation 12. Since the rate of change of real variables vi and their corresponding logic variables Xiare of the same polarity, the summation term to the right of Equation 12 is non- negative. Therefore, the resulting rate of change of H is non-positive (i.e., cost function H is non- increasing over time). ேே^^^ ^^ ^^^ 1 ^^− ^ ^ ^^= ^ = ^ 0

[0031] The constant α in Equation 10 could be chosen to be equal toூ^^^^ , where Irefis somereference / constant current and C is a capacitance value.10 produces a set of equations in Equation 13 below describing currents into a set of capacitors Ci,1 ≤ i ≤ N, where the voltage viacross a capacitor Cirepresents its state, which can range from 0V to Vdd(or a normalized range from 0 to 1). The corresponding logical variable Xi is produced at the output ofa comparator circuit which compares vi against a threshold Vth (typically ௧^^ = ௗ^ௗ⁄ 2 , ornormalized to 0.5), as previously described in Equation 9.Attorney docket # 204606-0186-00WO ^^^ ^^^^^ = ^^^ = −^^^^ ^^ , 1 ≤ ^ ≤ ^^

[0032] For example, a SKI-SAT circuit solving a 3-SAT problem with 6 variables in 3 clausesdefined in Equation 5 could be described by the set of equations in Equation 14 below.^^భ = −^ ^^^^^ ^^ = +^^^^തത^തതതଶതതത ∨തതത ^തହത1

[0033] In one embodiment of the disclosed device a SKI-SAT circuit topology comprises a set of N nodes, each node comprising a nodal capacitor with voltage vi across its terminals, an input to supply a charging / discharging current to the nodal capacitor, and a comparator that compares the capacitor voltage viagainst a threshold voltage Vth. In some embodiments, Vthis the midpoint of the power rails. In some embodiments, for example in a unipolar system where there is a positive voltage rail and a ground, Vth may be half the positive voltage rail. In other embodiments, Vth may be 5% above the midpoint between the voltage rails, 5% below the midpoint between the voltage rails, 10% above the midpoint between the voltage rails, 10% below the midpoint between the voltage rails, or any other suitable value.

[0034] Application of the threshold voltage produces a binary output variable Xi(e.g., 0V or Vdd)and its complement ഥ ప^ . An example schematic of a SKI-SAT node is shown in Fig. 1, where thecomparator 101 is implemented as a pair of inverters 102a and 102b. The first inverter 102a serves to threshold and invert the voltage value of the nodal capacitor 103, and produces theAttorney docket # 204606-0186-00WOcomplement value ഥ ప^ . The second inverter 102b then inverts the complement value to producethe binary output value Xi. The node 100 shown in Fig.1 further comprises a reset transistor 104 which resets the voltage of the nodal capacitor 103 to VCM, where VCM may be the high voltage rail, the low voltage rail, a ground, or an intermediate voltage between the two voltage rails. In some embodiments, the reset voltage VCMmay be equal to the threshold voltage Vthof the comparator 101. In some embodiments, VCM may be within ±1%, ±3%, ±5%, ±10%, or ±20% of Vth.

[0035] In one embodiment, shown as a top-level circuit architecture in Fig.2, the two outputs203 from the node 100 (Xi and ഥ ప^ ) are connected to a programmable Variables-to-Clauses (V2C)array 204 containing N × Ncunits. The V2C array provides digital outputs to clause formation and coupling control signal generation array (CFCCS) array 202 of size 1 × Ncto form clauses and generate control signals associated with those clauses, as described below. Each unit cell in the V2C array 204 contains memory elements to store a polarity bit as well as an address appliedto the input of a digital address decoder. If the variable Xi (or its complemented variable ഥ ప^ ) ispresent in the Cj clause of the CNF form F, the cell at the (i,j) location in the V2C array is activated to connect the variable to the clause Cj. Depending on the polarity bit stored in amemory cell of the V2C unit, either variable Xi or its complement ഥ ప^ is selected for connection toclause CF array. The selection between a variable Xi or its complement ഥ ప^ could be achievedthrough a digital multiplexer (MUX) which may be controlled by the polarity bit.

[0036] With reference to Fig.3A, Fig.3B, and Fig.3C, an example unit element of a V2C N x NCarray for a 3-SAT implementation is shown. In some embodiments, the V2C unit further comprises an output buffer (Fig.3C) that buffers the variable selected through a MUX 301 to one of the k readout lines 302 (where k is the number of literals in the clause Cj) that run through all rows of the jthcolumn and are connected to the inputs of CFCCS array 202, where the CFCCS array is preferably located at the periphery of the V2C array 204. The output buffer in the V2C unit may be implemented with a total of k 3-state inverter-based buffers 303 with their inputs connected to the output of the polarity selection MUX 301 and with output-enable (OE) ports connected to outputs of an address decoder 304 (see Fig.3B). The digital address decoder 304 located within the V2C cell converts the address stored in the memory of the V2C unit into at least k control signals 305 connected to the OE ports of the output buffer 303 such that at mostAttorney docket # 204606-0186-00WO one of the 3-state inverter-based buffers 303 is enabled at any time. Conversely, if a literal isn’t present in a clause, none of the OE ports 305 is activated and the variable present at the input of the V2C cell remains disconnected from a clause. The example V2C circuit shown in Fig.3A, Fig.3B, and Fig.3C corresponds to a clause with three literals, but it is understood that any suitable number of literals could be used by expanding the circuitry. The unit contains 3 memory elements (Fig.3A, implemented as latches 306a, 306b, 306c with access switches 307a and 307b) to store bits for polarity selection (bit s in the schematic, stored in latch 306c) as well as a 2-bit address (bits D0 and D1 in the schematic, stored in latches 306b and 306a, respectively) for readout line selection. A 2-to-4 address decoder 304 is used to either connect the variable (or its complement) to one of the three readout lines 305 (lines L1, L2, and L3 in the schematic) or allow the unit (and its corresponding variable) to remain unconnected to the corresponding clause in the CFCSS array 202.

[0037] The CFCCS array 202 contains NCCFCCS units (Fig.4) where each CFCCS unit 401 has a total of k inputs 402 connected to k readout lines of the corresponding jthcolumn in the V2C array 204. The depicted CFCCS unit in Fig.4 is for a 3 literal clause, with a satisfiability signal Tj. Each unit 401 in the CFCCS area contains a total of k NOR logic gates 403 (i.e., one NOR gate 403 for each literal in clause Cj) each with k −1 inputs connected to the inputs 402 of the CFCCS unit 401 such that a k −1-input NOR gate 403 that corresponds to mthliteral in clause Cj takes all literals at its inputs except the mthliteral (i.e., the inputs to a k−1-input NOR gate corresponding to mthliteral are connected to all of the readout lines from the jthcolumn in the V2C array except the readout line corresponding to the mthliteral. Each NOR gate 403 in the jth column produces a digital output Zj,m (404) (where 1 ≤ m ≤ k) which is connected to Clause-to- Coupling-Current (C2CC) array 205 of size N × Nc. Each unit in the CFCCS array 202 may contain additional logic that receives outputs from the NOR gates to calculate a satisfiability signal Tj of clause Cj. The logic producing satisfiability signal Tj may be configured so that Tj is equal to logic one if Cjis satisfied (or evaluates as TRUE) or Tj= 0, otherwise. For example, in the case of a clause with 3 literals (k = 3), the satisfiability signal Tj of clause Cj may be formed by applying a 2-input NAND gate on the outputs from any of the two NOR gates in the jth CFCCS unit as shown in Fig.4. Alternatively, a satisfiability signal Tjmay be produced by using a k-input OR gate whose inputs are connected to all of the readout lines from the jthcolumn in the V2C array.Attorney docket # 204606-0186-00WO

[0038] Outputs from all NOR gates 403 (a total of k outputs 404) in a jthCFCCS unit 401 are connected to corresponding jthcolumn of the Clause-to-Coupling-Current (C2CC) array 205 containing N × Nccoupling units. For example, if clause Cjhas three literals (k = 3), the jthCFCCS unit produces three output signals Zj,m1 ≤ m ≤ 3 that are sent to the coupling units in the jth column of the C2CC array 205. For the purposes of the depicted array, the cells shaded in gray 201 constitute a column. A coupling unit at (i,j) location within the C2CC array 205 corresponds to ithnode and jthclause. The coupling units are provided with an output supplying either a positive or negative reference current Iref or zero current depending on the polarity bit stored in the unit as well as the control signal supplied by the corresponding CFCCS units 401. Outputs from all coupling units in one row of the C2CC array 205 are connected together for current summing and connected to the input of the node corresponding to that row. In addition, each coupling unit in the C2CC array may contain memory elements to store, for example, a polarity bit and / or an address for a digital multiplexer (MUX). For example, if the variable Xiis present in the Cj clause as an mthliteral, a coupling unit at the (i,j) location in the C2CC array 205 may be configured through its MUX to receive a control signal on Zj,m, with its polarity bit set to logic 1. In this configuration, each time the control signal Zj,mis logic 1, the coupling unit at location (i,j) provides a positive reference current Iref at its output. Otherwise, when Zj,m= 0 is received by the coupling unit (i,j), its output current is set to zero.

[0039] In some embodiments, a V2C array 204 (see Fig.2) and a C2CC array 205 may overlap physically, so that corresponding V2C units and C2CC units (i.e., those that have the same row and column number) are collocated. In such a configuration, the corresponding units would effectively merge into a single unit that could share the same 3 bits of memory and save area in the process.

[0040] Likewise, in the case when a complemented variable ഥ thప^ is an m literal in clause Cj, thepolarity bit stored in the coupling unit (i,j) may be set to zero and each time Zj,m= 1 is received, the coupling unit may provide a negative reference current (−Iref) at its output. Otherwise, when Zj,m = 0 is received, the coupling unit produces no current at its output. The outputs from all coupling units in ithrow of the C2CC array 205 are connected together to the input of the ithnode.

[0041] An example schematic of a C2CC coupling unit for a 3 literal SAT solver is shown in Fig.5A, Fig.5B, and Fig.5C. In this circuit, three memory elements 506a, 506b, and 506c (Fig.Attorney docket # 204606-0186-00WO 5A) retain information about the polarity s (506c) and address bits (506a and 506b) for the selection of one of the inputs Zj,m supplied by the corresponding CFCCS unit 401 in the jthcolumn. The address bits (bits D0 and D1) are utilized for selection through the multiplexer 504 (see Fig.5B). Depending on the polarity of s, either the NAND gate 508a or 508b will be activated to pull down either PHIP or PHIPb, respectively, if Zj is set to high.

[0042] An exemplary current conversion circuit is shown in Fig.5C, whereby an input voltage is converted to a current. When the polarity is positive (indicating s is high), transistors 510a and 509b are turned on, while 509a and 510b are turned off. This setup creates a low impedance path between the current source (transistor 511a) and the output 512, leading to a positive current at the output of the coupling unit. Conversely, if the polarity is negative, 510a and 509b are turned off, and 509a and 510b will turn on, thereby creating a low impedance path between the output node 512 and the current sink (transistor 511b) producing a negative current at the output 512. In the case where Zjis set to low, the switches 509a and 509b are engaged and connected to the current source 511a and current sink 511b to virtual ground 513, while switches 510a and 510b are turned off leaving the output 512 floating. It should be noted that switches 509a and 509b are not always required for the operation of the coupling unit (i.e., they can in some configurations be an auxiliary feature), however, employing these switches improves the linearity and settling speed of the current sources in some embodiments. In some embodiments, the polarity of the current generated at the output is positive or negative based on the polarity of the voltage at the input. In some embodiments, the polarity of the current generated at the output is positive or negative based on the level of voltage at the input relative to some pre-defined threshold.

[0043] In some embodiments of the disclosed device, for example as shown in Fig.6, one or more nodes of the SKI-SAT circuit may further comprise a current summing circuit 602 (e.g., a current conveyor or class-AB current conveyor) that sums up the currents from the coupling units and supplies the total current to the nodal capacitors for better linearity and improved MaxSAT problem solution quality. In addition to summing the currents from the coupling units, the current conveyor 602 may maintain a virtual ground at its input (i.e., forcing the potential at its input to be VCM while summing up all the currents from the outputs of the coupling units in the ithrow of the C2CC array). The node shown in Fig.6 further comprises a nodal capacitor and aAttorney docket # 204606-0186-00WO comparator circuit implemented as a pair of inverters providing an output 603 and its complement 604.

[0044] In some embodiments of the disclosed device, a SKI-SAT circuit disclosed herein may further comprise a perturbation logic that flips one or more capacitors’ states vi at random to escape local minima in search for the optimal solution to a MaxSAT problem. The perturbation logic may contain a circuit that monitors each variable Xias well as a perturbation signal Pisupplied to the ithnode. When, for example, a rising-edge in Pi is detected, the perturbation logic may sample the current value Xi at the output of the ithnode (e.g., storing it in a flip-flop type register) and charge the capacitor’s voltage vito the power rail opposite to the stored Xivalue as well as continuing to hold the new value vipreventing its change for a certain time period (e.g., the new value of vi could be held for a duration of a pulse in Pi, which may be a few hundreds of picoseconds, several nanoseconds, or a few hundreds of nanoseconds depending on the size of the SAT problem). Each perturbation signal Pithat is distributed to each of the nodes might be generated from and independent random or pseudo-random source, including but not limited to a linear-feedback-shift register, or they could all be derived from a single source. The Pi perturbation signals might be generated such that the density of pulses (i.e., rate of rising-edges in Pi) diminishes over the SKI-SAT’s operation time (so-called annealing time), or such that the density stays constant or roughly constant over the SKI-SAT’s operation time. In embodiments where the pulse density diminishes over time, the rate at which the pulse density diminishes over time can be a linear or exponential function of time.

[0045] With reference to Fig.7, a CFCCS unit is shown with clause perturbation logic and a perturbation signal P (702), satisfiability signal (705) and early termination signal (704) is shown. In some embodiments of the device disclosed herein, the SKI-SAT circuit may further comprise a perturbation circuit that perturbs the clause formation and coupling control signal generation logic in the CFCCS array 202 as opposed to perturbing the nodal capacitors’ states vi. In these embodiments, each CFCCS unit may be supplied with additional logic gates that monitor the satisfiability signal Tj and a perturbation control signal P (702, Fig.7) shared among all CFCCS units. To achieve perturbations in the embodiment of SKI-SAT depicted in Fig.7, which allows for escaping local minima in the penalty function, each time a pulse in P is detected by the CFCCS units, all CFCSS units whose satisfiability signals Tjindicate that clauseAttorney docket # 204606-0186-00WO Cj is TRUE (or satisfied) output logic zero on all of their output lines Zj,m so that all satisfied clauses during the pulse duration in P do not contribute to the coupling currents and, therefore, do not contribute to the changes in nodal states vi. In the absence of a pulse in P, all CFCCS units (regardless of the value of their satisfiability signals Tj) contribute to the coupling currents, as described in the first and second embodiments. The perturbation control signal P may be implemented as a random (or pseudo-random) pulse stream and may be generated by a random (or pseudo-random) source. The pulse stream P may be generated so that the start of each pulse (i.e., the rising-edge of the pulse) is random (or pseudo-random) in time, while the duration of the pulse is fixed (e.g., hundreds of picoseconds). In addition, the pulse stream P may be generated such that the average pulse rate (i.e., number of pulses per second) diminishes over the annealing time. For instance, to generate a pulse steam P whose average pulse rate diminishes over the annealing time, an LFSR (Linear Feedback Shift Register) may be used to generate an N-bit pseudo-random bit stream that can be compared against an N-bit binary threshold using a combinatorial circuit producing a logic one if the input is greater than the threshold and logic 0 otherwise. Varying the threshold over time (e.g., increasing the N-bit threshold) results in fewer pulses in the pulse stream P – i.e., reduced average pulse rate. For example, the pulse rate in P may start at 0.75 pulses per nanosecond (which corresponds to producing a 330ps-long pulse with 25% probability every 330 ps), at the beginning of the annealing time and then diminishes linearly to 0 pulses / ns over the duration of the annealing time. In some embodiments, when allclauses are satisfied, an early termination signal^ത^ത^തത^ത^704 is activated, indicating the solution isfound.

[0046] In some embodiments of the disclosed device, the SKI-SAT circuit may comprise NOR logic gates that are distributed between the V2C units and CCCS units as shown in Fig.8 for reduced circuit area. Each one of the distributed NOR gates (a total of k gates per CFCCS unit) may be implemented as an NMOS-logic gate, where k − 1 input NMOS transistors are located within separate V2C units in one column of the V2C array, while the gate’s load (e.g., PMOS transistor 802 biased in triode region in Fig.8) is located within the CFCCS unit of the same column.

[0047] In some embodiments, a method of solving a MaxSAT problem using the system disclosed herein may comprise the following steps:Attorney docket # 204606-0186-00WO

[0048] (1) Assign variables Xi to individual computational nodes. It should be noted that the number of variables in a MaxSAT problem assigned to computation nodes cannot exceed the number of computation nodes N. In addition, if the number of computation nodes exceeds the number of variables, nodes that are not utilized could be powered down (i.e., disconnected from the network to save power).

[0049] (2) Program the SKI-SAT circuit to solve a specific MaxSAT problem by writing polarity and address bits into the memory elements of the V2C array 204 and C2CC array 205.

[0050] (3) Reset all nodal capacitor voltages to VCM (which may in some embodiments be Vdd / 2) and then release to permit interactions between the nodes.

[0051] (4) Allow the circuit sufficient time (i.e., termed an annealing time) to evolve and reach a stable state. Suitable annealing times include, but are not limited to, 0.1 microseconds to a few milliseconds depending on the size and complexity of the ST problem solved by the device.

[0052] (5) Sample the variables Xi,1 ≤ i ≤ N at the completion of the annealing time and store (or readout) the sampled variables as a solution to the programmed MaxSAT problem.

[0053] To validate that an individual clause in the MaxSAT problem is satisfied, the satisfiability signal Tjof the corresponding clause may be utilized.

[0054] If the solution obtained in step (5) does not satisfy all clauses Cj,1 ≤ j ≤ Nc, steps (2) through (5) may be repeated in search for a better solution to the programmed MaxSAT problem, where a better solution is defined as one with more satisfied clauses.

[0055] In some aspects of the present invention, software executing the instructions provided herein may be stored on a non-transitory computer-readable medium, wherein the software performs some or all of the steps of the present invention when executed on a processor.

[0056] Aspects of the invention relate to algorithms executed in computer software. Though certain embodiments may be described as written in particular programming languages, or executed on particular operating systems or computing platforms, it is understood that the system and method of the present invention is not limited to any particular computing language, platform, or combination thereof. Software executing the algorithms described herein may beAttorney docket # 204606-0186-00WO written in any programming language known in the art, compiled or interpreted, including but not limited to C, C++, C#, Objective-C, Java, JavaScript, MATLAB, Python, PHP, Perl, Ruby, or Visual Basic. It is further understood that elements of the present invention may be executed on any acceptable computing platform, including but not limited to a server, a cloud instance, a workstation, a thin client, a mobile device, an embedded microcontroller, a television, or any other suitable computing device known in the art.

[0057] Parts of this invention are described as software running on a computing device. Though software described herein may be disclosed as operating on one particular computing device (e.g. a dedicated server or a workstation), it is understood in the art that software is intrinsically portable and that most software running on a dedicated server may also be run, for the purposes of the present invention, on any of a wide range of devices including desktop or mobile devices, laptops, tablets, smartphones, watches, wearable electronics or other wireless digital / cellular phones, televisions, cloud instances, embedded microcontrollers, thin client devices, or any other suitable computing device known in the art.

[0058] Similarly, parts of this invention are described as communicating over a variety of wireless or wired computer networks. For the purposes of this invention, the words “network”, “networked”, and “networking” are understood to encompass wired Ethernet, fiber optic connections, wireless connections including any of the various 802.11 standards, cellular WAN infrastructures such as 3G, 4G / LTE, or 5G networks, Bluetooth®, Bluetooth® Low Energy (BLE) or Zigbee® communication links, or any other method by which one electronic device is capable of communicating with another. In some embodiments, elements of the networked portion of the invention may be implemented over a Virtual Private Network (VPN).

[0059] Fig.9 and the following discussion are intended to provide a brief, general description of a suitable computing environment in which the invention may be implemented. While the invention is described above in the general context of program modules that execute in conjunction with an application program that runs on an operating system on a computer, those skilled in the art will recognize that the invention may also be implemented in combination with other program modules.Attorney docket # 204606-0186-00WO

[0060] Generally, program modules include routines, programs, components, data structures, and other types of structures that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the invention may be practiced with other computer system configurations, including hand-held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0061] Fig.9 depicts an illustrative computer architecture for a computer 900 for practicing the various embodiments of the invention. The computer architecture shown in Fig.9 illustrates a conventional personal computer, including a central processing unit 950 (“CPU”), a system memory905, including a random access memory 910 (“RAM”) and a read-only memory (“ROM”) 915, and a system bus 935 that couples the system memory 905 to the CPU 950. A basic input / output system containing the basic routines that help to transfer information between elements within the computer, such as during startup, is stored in the ROM 915. The computer 900 further includes a storage device 920 for storing an operating system 925, application / program 930, and data.

[0062] The storage device 920 is connected to the CPU 950 through a storage controller (not shown) connected to the bus 935. The storage device 920 and its associated computer-readable media provide non-volatile storage for the computer 900. Although the description of computer- readable media contained herein refers to a storage device, such as a hard disk or CD-ROM drive, it should be appreciated by those skilled in the art that computer-readable media can be any available media that can be accessed by the computer 900.

[0063] By way of example, and not to be limiting, computer-readable media may comprise computer storage media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EPROM, EEPROM, flashAttorney docket # 204606-0186-00WO memory or other solid state memory technology, CD-ROM, DVD, or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer.

[0064] According to various embodiments of the invention, the computer 900 may operate in a networked environment using logical connections to remote computers through a network 940, such as TCP / IP network such as the Internet or an intranet. The computer 900 may connect to the network 940 through a network interface unit 945 connected to the bus 935. It should be appreciated that the network interface unit 945 may also be utilized to connect to other types of networks and remote computer systems.

[0065] The computer 900 may also include an input / output controller 955 for receiving and processing input from a number of input / output devices 960, including a keyboard, a mouse, a touchscreen, a camera, a microphone, a controller, a joystick, or other type of input device. Similarly, the input / output controller 955 may provide output to a display screen, a printer, a speaker, or other type of output device. The computer 900 can connect to the input / output device 960 via a wired connection including, but not limited to, fiber optic, Ethernet, or copper wire or wireless means including, but not limited to, Wi-Fi, Bluetooth, Near-Field Communication (NFC), infrared, or other suitable wired or wireless connections.

[0066] As mentioned briefly above, a number of program modules and data files may be stored in the storage device 920 and / or RAM 910 of the computer 900, including an operating system 925 suitable for controlling the operation of a networked computer. The storage device 920 and RAM 910 may also store one or more applications / programs 930. In particular, the storage device 920 and RAM 910 may store an application / program 930 for providing a variety of functionalities to a user. For instance, the application / program 930 may comprise many types of programs such as a word processing application, a spreadsheet application, a desktop publishing application, a database application, a gaming application, internet browsing application, electronic mail application, messaging application, and the like. According to an embodiment of the present invention, the application / program 930 comprises a multiple functionality softwareAttorney docket # 204606-0186-00WO application for providing word processing functionality, slide presentation functionality, spreadsheet functionality, database functionality and the like.

[0067] The computer 900 in some embodiments can include a variety of sensors 965 for monitoring the environment surrounding and the environment internal to the computer 900. These sensors 965 can include a Global Positioning System (GPS) sensor, a photosensitive sensor, a gyroscope, a magnetometer, thermometer, a proximity sensor, an accelerometer, a microphone, biometric sensor, barometer, humidity sensor, radiation sensor, or any other suitable sensor. EXPERIMENTAL EXAMPLES

[0068] The invention is further described in detail by reference to the following experimental examples. These examples are provided for purposes of illustration only, and are not intended to be limiting unless otherwise specified. Thus, the invention should in no way be construed as being limited to the following examples, but rather, should be construed to encompass any and all variations which become evident as a result of the teaching provided herein.

[0069] Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the following illustrative examples, make and utilize the system and method of the present invention. The following working examples therefore, specifically point out the exemplary embodiments of the present invention, and are not to be construed as limiting in any way the remainder of the disclosure. Simulation Results and Discussion

[0070] This section presents the simulations performed on the proposed system and compares its performance to related work. The performance of the proposed design is evaluated both at the circuit and behavioral levels: the former ensures the circuit's integrity, while the latter offers insights into the statistical performance of the system at larger scales.

[0071] The circuits described herein were implemented in the Cadence Virtuoso environment using the TSMC 65nm process design kit. To reduce netlist size and simulation complexity, ideal components were used for the memory units (i.e., the memory latches in V2C unit of Fig.3A -Attorney docket # 204606-0186-00WO Fig.3B and C2CC unit of Fig.5A – Fig.5C were replaced with DC voltage sources). Since memory does not affect system performance and is merely required for programmability (i.e., it is accessed only once to program the SAT problem onto the hardware), using ideal components does not compromise the reliability of the simulations.

[0072] A uniform random 3-SAT Boolean function consisting of 50 literals and 218 clauses was chosen from the SATLIB (H. Hoos, et al., SAT, 2000) to evaluate the performance of the SKI- SAT circuit solver. SATLIB (H. Hoos, et al., SAT, 2000) a widely adopted benchmark, was used in this example due to its incorporation of hard randomly generated formulas; such formulas arise when the ratio of clauses to variables is at a certain critical ratio (B. Selman, et al., Artificial Intelligence, 1996). In the following step, a circuit with 50 nodes, 50 by 218 units of V2C and C2CC, and 218 units of CFCCS was instantiated and programmed using a SKILL code to implement the function.

[0073] The circuit was initialized by resetting the nodal capacitors at each node to the common mode voltage, which is half the power supply — 0.6V for this process. Graph 1001 in Fig.10 illustrates the potential difference across the nodal capacitors, starting from the middle rail and progressively diverging toward either the ground or power supply levels, with the exception of a few variables, which remains in the vicinity of the middle rail while being slightly higher or lower than the comparator's approximate threshold of 0.6V. This behavior was expected and commonly observed in simulations, as some variables may cease charging or discharging once the system reaches a stable equilibrium. Graph 1002 in Fig.10 depicts the quantized outputs of the nodal capacitors, which correspond to the digital values of the literals. Finally, the bottom strip shows the number of false clauses gradually decreasing, eventually reaching zero, indicating that the function is satisfied with the final combination of 1s and 0s present at the nodal outputs.

[0074] Although SKI-SAT is designed to decrease the number of unsatisfied clauses over time through its gradient decent nature, perturbations are needed to escape local minima in search of a variable assignment that maximizes the number of satisfied clauses. The particular perturbation scheme used in SKI-SAT introduces a “don't care” state, during which the currents from satisfied clauses are disconnected from nodal capacitors. Temporarily disconnecting the satisfied clauses from contributing to the charging currents effectively allows the system to enforce an assignmentAttorney docket # 204606-0186-00WO of variables that would satisfy the remaining unsatisfied clauses while disregarding the already satisfied clauses, which can in some embodiments push the system to a higher energy state. Graph 1003 in Fig.10 shows that the number of unsatisfied clauses does not decrease monotonically, but occasionally increases to a higher energy level during the “don't care” phases. This behavior is critical to maintain a robust solver that avoids getting stuck at local minima, which is a common issue for all stochastic solvers.

[0075] For this particular function, the system reaches the global minimum within 15 ns, consuming an average current of 24.23 mA during the 50 ns annealing period from a 1.2 V supply, resulting in 29.07 mW power demand, excluding the memory elements and perturbation unit. When the pseudo-random number generator circuit described in (J. Wu, et al., https: / / arxiv.org / abs / 2501.00193, 2024) is used to generate the perturbation signal P, the total active power requirement increases to 30.21 mW. The breakdown of contributions from the major blocks is illustrated in Fig.11. The majority of energy consumption occurs before the machine settles into a local or global minimum. During this period, variables rapidly change values to satisfy more clauses. The machine reaches the global minimum around 13 ns, marked by the most significant switching activity observed in Fig.10. After this, the current consumption of the nodes and V2C becomes insignificant, as literals no longer change values, eliminating the need for current drawn by the inverters within the nodes and V2C units. Meanwhile, the C2CC continuously supplies current to the nodal capacitors to maintain the found solution. The ETS shown in Fig.7 can flag the solution is found and halt the system before the annealing period is over which further enhances the power efficiency by removing the need for replenishing the nodal capacitors.

[0076] A similar experiment is run on the SATLIB (H. Hoos, et al., SAT, 2000) instance uf20- 91 / 014 for the purposes of investigating the probabilistic characteristics of the SKI-SAT on a commonly used benchmark item. Fig.12 shows the 20 variables diverging and eventually settling into one of the global minima, thereby finding a satisfying assignment. For brevity, the initialization phase during the first 10 ns is omitted. Stochastic solvers inherently possess a probabilistic chance of solving a given function, and SKI-SAT is not an exception. To analyze the statistical properties of such solvers, it is necessary to perform a large number of runs. Circuit simulations, however, are notoriously computationally expensive and call for realisticAttorney docket # 204606-0186-00WO simplifications. With this in mind, circuit simulations are only carried out on SAT problems with a smaller number of variables and a smaller number of runs. The obtained statistical results are used to verify the validity of the SKI-SAT behavioral model developed in MATLAB, which is then used to estimate SKI-SAT performance for large scale SAT problems.

[0077] Fig.13 demonstrates five successful evaluations and five unsuccessful evaluations out of ten iterations with different perturbation sequences for the uf20-91 / 014, resulting in a success rate of 0.5 for SKI-SAT for this particular function.

[0078] Furthermore, simulations show that the absence of perturbations causes the solver to become stuck in a local minimum due to the greedy gradient descent even when the transient noise is included in simulations. This observation highlights the importance of random perturbations to system performance. In addition, including the transient noise in simulations does not change the success rate, demonstrating the proposed circuit’s resilience against inherently present electronic noise. Further, certain instances from SATLIB are quite trivial such that the correct solution is found rapidly without any perturbation. However, such instances are rare and unlikely to exist for instances with larger energy landscapes that contain far more literals and clauses. High-Level Model

[0079] The SKI-SAT behavioral model was implemented in MATLAB as a fixed-step solverwith discrete states. The fixed time step of Δ^ = 20 ^^ is chosen for this experiment. This valuewas empirically determined to balance numerical stability and computational efficiency. It ensures that the cost function during gradient descent (i.e., the number of unsatisfied clauses) remains stable and monotonically non-increasing, addressing potential numerical instability associated with the Forward Euler method (E. Hairer, et al., Berlin, 1996). Additionally, the chosen time step is not excessively small, avoiding prohibitively high simulation costs. In each time step, discrete voltage values on nodal capacitors are incremented or decremented by an integer multiple of Δ^. Assuming the nodal capacitance value of 200 fF and a reference current of 10 μA (i.e., current produced by the current source ^^^and current sink ^^ଶof the C2CC unit in Fig.5A – Fig.5C), the voltage increment Δ^ isasAttorney docket # 204606-0186-00WO ^ref × Δ^Δ^ =^ = 1 mV15

[0080] The MATLAB script starts with fetching the Boolean function and initializes two sets of variables for the analog voltage values across the nodal capacitors and digitized outputs of the literals. In this model, the capacitor voltages are initialized to mid-rail value ofௗ^ௗ / 2 with additional random components to account for ^^ / ^ noise present in the circuit. Additionally, a random perturbation sequence is generated, clocked at a period of 320 ps, meaning the perturbation may change state every 16 simulation steps, establishing a realistic clocking speed. The code keeps track of how many clauses remain unsatisfied at each step and records the first step where all clauses are satisfied while simulating a system where the capacitor voltages are updated based on the satisfaction of clauses at every step. The model utilizes discrete voltage increments and decrements to simulate analog behavior. The literal values are updated by comparing the voltage values against the threshold. The system is in greedy mode when there is no perturbation and tries to diminish the number of unsatisfied clauses. On the other hand, the perturbation stops the greedy behavior and lets some of the satisfied clauses break by aborting the inputs from satisfied clauses. The perturbation increases the likelihood of the system eventually descending into global minima. Running the uf20-91 / 014 for 1,000 repeats with the described behavioral model reveals the success rate of 45.1%, as shown in Fig.14, which is fairly consistent with the 50% success rate obtained through circuit simulations.

[0081] A key feature of SKI-SAT is related to how it escapes local minima through the utilization of random perturbations. The primary goal of perturbation is to allow the system to occasionally choose a random path through the energy landscape, which does not align with the steepest gradient descent direction and does not necessarily lead to a reduction in the number of unsatisfied clauses. SKI-SAT employs a highly-effective and resource-efficient solution to achieve this through the use of a single and global random (or pseudo-random) signal P. As shown in Fig.7, the CFCCS units generate coupling signals^^,^either to change variable assignments to achieve satisfiability or, if only one variable satisfies the clause, to maintain its current state. When a pulse is detected at P, the coupling signals^^,^for satisfied clauses cease, allowing only unsatisfied clauses to generate coupling signals. During this phase, some of theAttorney docket # 204606-0186-00WO satisfied clauses are expected to become unsatisfied while previously unsatisfied clauses will turn into satisfied, which will ultimately assist the system in finding the global minimum.

[0082] Table 1 illustrates the function of the perturbation signal P in the CFCCS unit with its truth table. The truth table for the CFCCS unit that summarizes the function of the perturbation signal P is depicted in Table 1. The perturbation signal P is configured such that the perturbation pulse length is constant (e.g., 320 ps) and the pulse density (i.e., probability of entering perturbation mode) decays linearly over time. InputsOutputsP L1 L2 L3 Tj Zj1 Zj2 Zj3 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 Table 1

[0083] In order to demonstrate the significance of the perturbations to system performance, various perturbation scenarios have been considered. A SATLIB instance, specifically uf50- 218 / 0100, was simulated using the MATLAB model 1,000 times with three different approaches. First, when no perturbations were introduced forcing the machine to rely solely on its gradient descent in search for a global minimum, the success rate was quite low, with only 2 successfulruns out of 1,000. Second, an alternative perturbation strategy was implemented, where 8^ ோ^ெௌGaussian-distributed noise was randomly injected into the nodal capacitors. The RMS value of8^ ோ^ெௌ for injected noise was determined as optimal to maximize the success rate in thisexperiment. This approach improved the outcome, yielding 5 successful cases with zeroAttorney docket # 204606-0186-00WO unsatisfied clauses at the end of the annealing periods. Finally, with SKI-SAT's own perturbation mechanism, a success rate of 29.3% was achieved. The efficiency of the SKI-SAT perturbation as compared to the alternative method and the no-perturbation case is illustrated in Fig.15. Performance Comparison

[0084] A number of selected benchmark instances from SATLIB were used for comparison between a SAT solving IM (H. Cılasun, et al., Scientific Reports, 2024), a hardware implementation of AmoebaSAT (K. Hara, et al., ISQED, 2019), WalkSAT (B. Selman, et al., AAAI, 1994), and SKI-SAT. AmoebaSAT (M. Aono, et al., Langmuir, 2013) is a bio-inspired algorithm that has been demonstrated to solve SAT problems using nanoelectromechanical devices. Hara et al. (K. Hara, et al., ISQED, 2019) report the clock frequency and average number of cycles required for solution over 100 repeats of an FPGA implementation of AmoebaSAT. The provided information allows the calculation of the total time to solution (TtS) by multiplying the clock period by the average number of cycles. Furthermore, the latest version of the WalkSAT solver, found in the GitLab repository (H. Kautz, GitLab, 2024), was executed with the default settings on an Apple Silicon M1 CPU with 8 GB of RAM. The WalkSAT algorithm sets a predefined number of steps, known as the cutoff number, after which it either finds a solution or exits the iteration and restarts with a new initial assignment. Sweeping the cutoff parameter shows that the default cutoff setting provides a good balance. The instances tested for this work neither suffer from a low cutoff rate, which leads to a low success rate, nor from an excessively large limit that causes the solver to get stuck in a cycle, taking millions of flips to escape without success. However, it is not guaranteed that WalkSAT will find a solution in every trial. Therefore, it is necessary to calculate the TtS in a way that accounts for unsuccessful cases. The number of repetitions required to solve a function with a 99% probability given a certain success rate (SR) is determined as log ^0.01^= ^ ^^Attorney docket # 204606-0186-00WO

[0085] The average time per assignment multiplied by the number of runs needed to solve an instance with 99% probability is used to estimate TtS for WalkSAT as shown in (R. Hamerly, et al., Science Advances, 2019). Lastly, the SKI-SAT behavioral model in MATLAB wasemployed to solve the same instances. The simulations assume a 300 ns annealing period, a15 μ^ reference current, and a 320 ps perturbation clock period, with the probability of enteringperturbation mode decreasing from 90% to 50% during the annealing period. This model was used to project solution times for SKI-SAT, taking into account the success rate in the same manner as for WalkSAT. Table 2 summarizes the benchmarking results for the four methods. Benchmark IM AmoebaSAT WalkSAT SKI-SAT uf20-91 / 011 12830 - 8 0.6 uf20-91 / 012 6300 - 6 0.3 uf20-91 / 013 27580 - 19 1.8 uf20-91 / 014 28070 - 16 1.2 uf20-91 / 015 4090 - 9 0.9 uf50-218 / 0100 - 4.13 187 4.2 uf50-218 / 0410 - 4.36 141 4.2 uf50-218 / 0767 - 8.30 365 10.8 uf100-430 / 0285 - 356 5872 344.7 uf150-645 / 0100 - 1832 6026 137.7 uf225-960 / 028 - 3078 1508 27.6 Table 2

[0086] All values in Table 2 are in µs. The IM results were from H. Cılasun, et al., Scientific Reports, 2024. The AmoebaSAT results were from K. Hara, et al., ISQED, 2019. The WalkSAT results correspond to H. Kautz, GitLab, 2024.

[0087] SKI-SAT outperformed the advanced WalkSAT, achieving solution times that were more than 10 times faster. In addition, a crucial figure of merit to compare different solvers is the energy to solution (EtS). EtS is determined by multiplying the time to solution (TtS) with theaverage power demand (P) to determine the energy required to solve a function as^^^ = ^^^ × ^Equation 17Attorney docket # 204606-0186-00WO

[0088] While WalkSAT solvers executed on von Neumann computing platforms consume energy on the order of Watts, the SKI-SAT circuit described above consumes about 14.27 mW (including perturbation sequence generation logic (J. Wu, et al., https: / / arxiv.org / abs / 2501.00193, 2024)) while solving the uf20-91 / 0143-SAT instance. Apple’s M1 CPU consumes about 7.5 W of power while executing the WalkSAT solver for the same instance, indicating hundreds of times power efficiency improvement. In order to estimate the power consumption, the powermetrics feature (powermetrics Manual, 2024) was used to sample the average power drawn by the CPU with certain intervals. The idle CPU power was then subtracted from the CPU power observed while WalkSAT was running. It should be noted the EtS is slightly better when the CPU is operated in low power mode, however, this case yields a curtailed performance in terms of TtS. Consequently, the EtS figure of merit for SKI-SAT is up to thousands of times better than that of WalkSAT, offering a high-performance and low-power hardware alternative.

[0089] To further corroborate performance of SKI-SAT, particularly from a statistical perspective, and enable a broader comparison with existing published work, SKI-SAT was tested on 100 instances of uf20, uf50, uf100, and uf150 from SATLIB (H. Hoos, et al., SAT, 2000) with every instance run 1000 times. Fig.16 shows the median TtS is 1.2 µs for 20 variable instances and increases to 68.7 µs for 150 variables, shown with corresponding inter-quartile ranges (IQR). Although the observed TtS growth in this result appears polynomial rather than exponential, this is attributed to the limited sample size (i.e, 100 instances per batch) and the small problem sizes used in the experiment. An exponential growth trend is expected instead, consistent with all known software or hardware based solvers for SAT problems with the constraint density^^ / ^ around critical value, as proved by Karp et.al (R. M. Karp, Springer, 1972) and empirically verified in (B. Selman, et al., Artificial Intelligence, 1996) and (B. Selman, et al., Artificial Intelligence, 1996). A similar trend is observed in EtS which starts from single-digit nJ for 20-variable instances and climbs to µJs for 150-variable instances.

[0090] The presented SKI-SAT performance and scalable architecture merits a detailed comparison with existing work in the literature. Table 3 offers extensive studies with custom integrated circuit implementations that summarize the hardware and performance specifications. The TtS and EtS values are derived from the plots and data provided in the referenced papers, asAttorney docket # 204606-0186-00WO these metrics were not always explicitly reported. These values are considered key figures of merit for this study. For instance, while SKI-SAT consumes more power per iteration than (M. Hizzani, et al., ISCAS, 2024) for 50-variable instances, its significantly shorter TtS results in a much lower EtS, reflecting the energy required to reach a solution with 99% probability. CICC 2022 ISCAS 2024 ISSCC 2023A ISSCC 2023B Technology 65 nm CMOS 28 nm CMOS 65 nm CMOS 65 nm CMOS Supply Voltage 1-1.2V Not reported 1.2V 0.7-1.2V Power 27 mW Not reported 32.5 mW Not reported Signal Domain Mixed Mixed Mixed Digital Active area (mm2) 4bNot reported 0.4 0.93 Maximum # of Variables 50 Not reported 60 128 Maximum # of Clauses 212 Not reported 252 1024 Experimented Problem (# of Hard 3-SAT Hard 3-SAT Hard 3-SAT Hard 3-SAT variable / # of clauses) (10 / 42) (50 / 218 & (30 / 126 & 60 / 252) (60 / 258) 150 / 645) TtS 18 msa14 & 400 µsac11.25 & 125 ms 2.852 ms EtS Not reported 80 & 5500 nJ Not reported 4392 nJ ISSCC 2024 Nature 2024A Nature 2024B This Work Technology 65 nm CMOS 65 nm CMOS 32 nm CMOS 65 nm CMOS Supply Voltage 1-1.4V Not reported Not reported 1.2V Power Not reported Not reported 13.35 mW 30.21 mW Signal Domain Digital Mixed Digital Mixed Active area (mm2) 1.116 0.28 0.0214d1.2369dMaximum # of Variables Not reported Not reported 100 50 Maximum # of Clauses Not reported Not reported 430 218 Experimented Problem (# of Hard 3-SAT Hard 3-SAT Hard 3-SAT (20 / 91 Hard 3-SAT variable / # of clauses) (20 / 91 & 50 / 218) (20 / 91) & 100 / 430) (50 / 218 & 150 / 645) TtS 7 & 37.4 µs 12.83 ms 1.8 & 51.8 µsc4.2 & 68.7 µscEtS 2.1 & 41.6 nJ 128 µJ 24 & 3430 nJc54.6 & 8293 nJcTable 3

[0091] Variables marked withawere estimated from plots. Variables marked withbwere estimated from die micrographs. Variables marked withcwere simulation results. Variables marked withdwere estimated areas.

[0092] The CICC 2022 result was reported in M. Chang, et al., CICC, 2022. The ISCAS 2024 result was reported in M. Hizzani, et al., ISCAS, 2024. The ISSCC 2023A result was reported in D. Kim, et al., ISSCC, 2023. The ISSCC 2023B result was reported in S. Xie, et al., ISSCC, 2023. The ISSCC 2024 result was reported in C. Shim, et al., ISSCC, 2024. The Nature 2024A result was reported in H. Cılasun, et al., Scientific Reports, 2024. The Nature 2024B result was reported in T. Bhattacharya, et al., Nat. Comm., 2024.Attorney docket # 204606-0186-00WO Hardware Implementation

[0093] A hardware implementation of SKI-SAT, featuring a 50 variable, 300 clause Max 3-SAT solver, was fabricated and experimentally verified on a 3mm x 2mm die. A photograph of the fabricated die is shown in Fig.17 and a diagram of the layout is shown in Fig.18. With reference to Fig.18, the diagram shows a 50 x 300 literal selection array and gradient computing logic in region 1801, which occupies an area of 1500 µm x 580 µm. Region 1802 includes a 50 variable array, which occupies an area of 84 µm x 503 µm. Region 1803 is a 50 x 300 coupling current array, which occupies an area of 1500 µm x 503 µm. Region 1804 is a memory buffer, which occupies an area of 45 µm x 1083 µm. Region 1805 includes the spin perturbation logic, which occupies an area of 45 µm x 503 µm. Conclusion

[0094] A new power-efficient hardware-based SAT solver, SKI-SAT, is proposed in this disclosure that is capable of solving problems with more than quadratic terms and optimized for seamless CMOS implementation. The work demonstrates a highly scalable architecture that inherently supports third-order polynomials found in SAT problems’ cost functions. The circuit implementation validates the architecture as an effective solution for SAT problems, requiring over 300 times less power as compared to software-based solvers such as WalkSAT. Also as compared to WalkSAT, the behavioral model shows that SKI-SAT achieves at least a 10-fold reduction in solution time for the selected benchmark instances. Finally, the key performance metric, energy to solution (EtS), is orders of magnitude better than that of conventional SAT- solving algorithms. In conclusion, the proposed SKI-SAT solver demonstrates significant improvements in solution time and power efficiency while supporting seamless CMOS implementation.

[0095] The disclosures of each and every patent, patent application, and publication cited herein are hereby incorporated herein by reference in their entirety. While this invention has been disclosed with reference to specific embodiments, it is apparent that other embodiments and variations of this invention may be devised by others skilled in the art without departing from the true spirit and scope of the invention. The appended claims are intended to be construed to include all such embodiments and equivalent variations.Attorney docket # 204606-0186-00WO References

[0096] The following publications are incorporated herein by reference in their entireties:

[0097] Y. Zhang, U. K. R. Vengalam, A. Sharma, M. Huang, and Z. Ignjatovic, “QuBRIM: A CMOS compatible resistively-coupled Ising machine with quantized nodal interactions,” in 2022 IEEE / ACM International Conference On Computer Aided Design (ICCAD), 2022, pp.1–8.

[0098] H. Cılasun, Z. Zeng, R. S., and et al., “3SAT on an all-to-all-connected CMOS Ising solver chip,” Scientific Reports, vol.14, no.10757, 2024.

[0099] M. Hizzani, A. Heittmann, G. Hutchinson, D. Dobrynin, T. V. Vaerenbergh, T. Bhattacharya, A. Renaudineau, D. Strukov, and J. P. Strachan, “Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines,” in 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, pp. 1–5.

[0100] E. Elmitwalli, Z. Ignjatovic, and S. Köse, “Utilizing multi-body interactions in a CMOS- based Ising machine for LDPC decoding,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.71, no.1, pp.40–50, 2024.

[0101] Y. Vizel, G. Weissenbacher, and S. Malik, “Boolean satisfiability solvers and their applications in model checking,” Proceedings of the IEEE, vol.103, no.11, pp.2021–2035, Nov 2015.

[0102] F. Legendre, G. Dequen, and M. Krajecki, “Encoding hash functions as a SAT problem,” in 2012 IEEE 24th International Conference on Tools with Artificial Intelligence, 2012, pp.916– 921.

[0103] J. Wu, A. Y. Salim, E. Elmitwalli, S. Köse, and Z. Ignjatovic, “A pseudo-random number generator for multi-sequence generation with programmable statistics,” 2024. [Online]. Available: https: / / arxiv.org / abs / 2501.00193

[0104] H. Hoos and T. Stützle, “SATLIB: An online resource for research on SAT,” in SAT 2000, 2000, pp.283–292.Attorney docket # 204606-0186-00WO

[0105] B. Selman and S. Kirkpatrick, “Critical behavior in the computational cost of satisfiability testing,” Artificial Intelligence, vol.81, no.1, pp.273–295, 1996, frontiers in Problem Solving: Phase Transitions and Complexity.

[0106] E. Hairer and G. Wanner, Solving Ordinary Differential Equations II: Stiff and Differential-Algebraic Problems, 2nd ed., ser. Springer Series in Computational Mathematics. Berlin, Heidelberg: Springer-Verlag, 1996, vol.14.

[0107] K. Hara, N. Takeuchi, M. Aono, and Y. Hara-Azumi, “Amoeba-inspired stochastic hardware SAT solver,” in 20th International Symposium on Quality Electronic Design (ISQED), 2019, pp.151–156.

[0108] B. Selman, H. A. Kautz, and B. Cohen, “Noise strategies for improving local search,” in Proceedings of the AAAI, Seattle, WA, USA, 1994, pp.337–343.

[0109] M. Aono, M. Hara, T. Yamasaki, N. Hirano, M. Saito, and K. Nakajima, “Amoeba- inspired nanoarchitectonic computing: Solving intractable computational problems using nanoscale photoexcitation transfer dynamics,” Langmuir, vol.29, no.24, pp.7557–7564, 2013.

[0110] H. Kautz, “Walksat,” GitLab Repository, accessed: Sep.25, 2024. [Online]. Available: https: / / gitlab.com / HenryKautz / Walksat

[0111] R. Hamerly, T. Inagaki, P. L. McMahon, D. Venturelli, A. Marandi, T. Onodera, E. Ng, C. Langrock, K. Inaba, T. Honjo, K. Enbutsu, T. Umeki, R. Kasahara, S. Utsunomiya, S. Kako, K.-i. Kawarabayashi, R. L. Byer, M. M. Fejer, H. Mabuchi, D. Englund, E. Rieffel, H. Takesue, and Y. Yamamoto, “Experimental investigation of performance differences between coherent Ising machines and a quantum annealer,” Science Advances, vol.5, no.5, p. eaau0823, 2019.

[0112] powermetrics Manual Page, Apple Inc., 2024, available: https: / / www.unix.com / man- page / osx / 1 / powermetrics / [Accessed: Oct.30, 2024].

[0113] R. M. Karp, “Reducibility among combinatorial problems,” in Complexity of Computer Computations. Springer, 1972, pp.85–103.

[0114] B. Selman, D. G. Mitchell, and H. J. Levesque, “Generating hard satisfiability problems,” Artificial Intelligence, vol.81, no.1-2, pp.17–29, 1996.Attorney docket # 204606-0186-00WO

[0115] M. Chang, X. Yin, Z. Toroczkai, X. Hu, and A. Raychowdhury, “An analog clock-free compute fabric base on continuous-time dynamical system for solving combinatorial optimization problems,” in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, pp. 1–2.

[0116] D. Kim, N. M. Rahman, and S. Mukhopadhyay, “29.1 a 32.5mW mixed signal processing-in-memory-based k-SAT solver in 65nm CMOS with 74.0% solvability for 30- variable 126-clause 3-SAT problems,” in 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023, pp.28–30.

[0117] S. Xie, M. Yang, S. A. Lanham, Y. Wang, M. Wang, S. Oruganti, and J. P. Kulkarni, “29.2 Snap-SAT: A one-shot energy-performanceaware all-digital compute-in-memory solver for large-scale hard boolean satisfiability problems,” in 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023, pp.420–422.

[0118] C. Shim, J. Bae, and B. Kim, “30.3 VIP-SAT: A boolean satisfiability solver featuring 5×12 variable in-memory processing elements with 98% solvability for 50-variable 218-clause 3-SAT problems,” in 2024 IEEE International Solid-State Circuits Conference (ISSCC), vol.67, 2024, pp.486–488.

[0119] T. Bhattacharya, G. H. Hutchinson, G. Pedretti et al., “Computing high-degree polynomial gradients in memory,” Nature Communications, vol.15, p.8211, 2024. [Online]. Available: https: / / doi.org / 10.1038 / s41467-024-52488-y

Claims

Attorney docket # 204606-0186-00WO CLAIMS What is claimed is:

1. A network, comprising: a plurality of computation nodes, each comprising: an input; an output; connections to first and second voltage rails; a capacitor electrically connected to the input configured to store state information as a state voltage; a comparator electrically connected to the capacitor and the output, configured to connect the output to the first voltage rail when the state voltage exceeds the threshold, and the second voltage rail when the state voltage is below the threshold; a plurality of programming units, each comprising: an input connected to the output of one of the plurality of computation nodes; a plurality of outputs; a plurality of memory cells configured to store digital values; a network of logic gates configured to connect the input to one of the plurality of outputs based on the stored digital values in the plurality of memory cells; a plurality of clause formation units, each comprising: a plurality of k inputs, each electrically connected to at least one of the outputs of one of the plurality of programming units; a plurality of k outputs; and a network of NOR gates connected to the plurality of inputs and the plurality of outputs such that each output of index i between 1 and k in the plurality of outputs is the NOR of all inputs except the input of index i; and a plurality of coupling units, each comprising: an input electrically connected to the output of at least one of the plurality of clause formation units; an output connected to an input of at least one computation node; andAttorney docket # 204606-0186-00WO a current conversion circuit electrically connected to the input and the output, configured to convert a voltage at the input to a current at the output.

2. The network of claim 1, wherein the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a resistor.

3. The network of claim 1 or 2, wherein the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a transistor having a drain terminal connected to the output of the coupling unit via switches controlled by the voltage at the input of the coupling unit.

4. The network of any of claims 1-3, further comprising a spin perturbation control circuit configured to change a polarity of a state voltage in at least one computation node of the plurality of computation nodes.

5. The network of claim 4, wherein the spin perturbation control circuit is configured to generate a perturbation signal from a random source or a pseudo-random source.

6. The network of claim 4 or 5, wherein the spin perturbation control circuit is configured to generate a perturbation signal such that the rate of spin perturbation events diminishes over time.

7. The network of and of claims 4-6, wherein the rate of spin perturbation events is configured to have an exponential decay over time.

8. The network of any of claims 4-7, wherein the rate of spin perturbation events is configured to have a linear decay over time.

9. The network of any of claims 1-8, further comprising a clause perturbation control circuit configured to switch a polarity of at least one of the outputs at least one clause formation unit.Attorney docket # 204606-0186-00WO 10. The network of any of claims 1-8, further comprising a clause perturbation control circuit configured such that clauses that are satisfied do not contribute to the coupling currents during a perturbation event.

11. The network of claim 9 or 10, wherein the clause perturbation control circuit is configured to decrease a rate of perturbation events over time.

12. The network of any of claims 9-11, wherein the clause perturbation control circuit is configured to decrease a rate of perturbation events exponentially over time.

13. The network of any of claims 9-11, wherein the clause perturbation control circuit is configured to decrease a rate of perturbation events linearly over time.

14. The network of claim 9 or 10, wherein the clause perturbation control circuit is configured to maintain a constant rate of perturbation events over time.

15. The network of any of claims 1-14, further comprising a digital logic that evaluates clauses’ logical values and if all clauses are true (or satisfied) triggers the early termination signal to sample logic states of variables and disconnect the nodes from the coupling units for power saving.

16. A network, comprising: a plurality of computation nodes; a plurality of programming units; a plurality of clause formation units; and a plurality of coupling units; wherein each of the plurality of computation nodes comprises: an input configured to receive currents from at least one of the coupling units; an output configured to have at least two discrete output voltages; a capacitor for storing an internal state as a voltage;Attorney docket # 204606-0186-00WO a comparator configured to compare the voltage across the capacitor against a threshold to produce a first discrete voltage value at the output if the voltage across the capacitor exceeds the threshold, and a second, different discrete voltage value at the output if the voltage across the capacitor is lower than the threshold; and a current conveyor circuit having an input connected to the input of the computation node and an output connected to the capacitor of the computation node, the current conveyor circuit configured to mirror a scaled version of the current received at the input into the capacitor; wherein each of the plurality of programming units comprises: at least one input electrically connected to an the output of at least one computation node; a plurality of outputs; a plurality of one-bit memory cells configured to store polarity and address bits; and a network of logic gates connecting the at least one input to one of the plurality of outputs based on the content of the memory cells; wherein each of the plurality of clause formation units comprises: a plurality of inputs electrically connected to the output of at least one of the plurality of programming units; a plurality of outputs; and a network of logic gates that take as inputs INi the voltages at the plurality of inputs and generate the plurality of outputs OUT(i) such that OUT(i) = NOR(IN1,..,INj,..,INk) where 1 ≤ i ≤ k , j ≠ i; andcomprises: an input electrically connected to the output of at least one clause formation unit; an output configured to have at least two discrete output current values and connected to an input of at least one computation node; and means to convert voltage values at the input to currents and produce current proportional to the input voltage at the output of the coupling unit.Attorney docket # 204606-0186-00WO 17. The network of claim 16, wherein the current conveyor circuit of each computation node is configured to hold its input at a constant voltage while mirroring the current received to the capacitor.

18. The network of claim 16 or 17, wherein the plurality of memory cells in the plurality of programming units comprise flip-flops.

19. The network of any of claims 16-18, wherein the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a resistor.

20. The network of any of claims 16-19, wherein the current conversion circuit of at least one coupling unit of the plurality of coupling units comprises a transistor having a drain terminal connected to the output of the coupling unit via switches controlled by the voltage at the input of the coupling unit.

21. The network of any of claims 16-20, further comprising a spin perturbation control circuit configured to change a polarity of a state voltage in at least one computation node of the plurality of computation nodes.

22. The network of claim 21, wherein the spin perturbation control circuit is configured to generate a perturbation signal from a random source or a pseudo-random source.

23. The network of claim 21 or 22, wherein the spin perturbation control circuit is configured to generate a perturbation signal such that the rate of spin perturbation events diminishes over time.

24. The network of any of claims 21-23, wherein the rate of spin perturbation events is configured to have an exponential decay over time.

25. The network of any of claims 11-24, wherein the rate of spin perturbation events is configured to have a linear decay over time.Attorney docket # 204606-0186-00WO 26. The network of any of claims 16-25, further comprising a clause perturbation control circuit configured to switch a polarity of at least one of the outputs at least one clause formation unit.

27. The network of claim 26, further comprising a clause perturbation control circuit configured such that clauses that are satisfied do not contribute to the coupling currents during a perturbation event.

28. The network of claim 26 or 27, wherein the clause perturbation control circuit is configured to decrease a rate of perturbation events over time.

29. The network of any of claims 26-28, wherein the clause perturbation control circuit is configured to decrease a rate of perturbation events exponentially over time.

30. The network of any of claims 26-29, wherein the clause perturbation control circuit is configured to decrease a rate of perturbation events linearly over time.

31. The network claims 26 or 27, wherein the clause perturbation control circuit is configured to maintain a constant rate of perturbation events over time.

32. The network of any of claims 16-31, further comprising a digital logic that evaluates clauses’ logical values and if all clauses are true (or satisfied) triggers the early termination signal to sample logic states of variables and disconnect the nodes from the coupling units for power saving.

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