Methods to enhance glass substrate handling in semiconductor processing

Abstract

Certain embodiments pertain to methods and systems for fabricating an electronic device that deposit a conductive or semiconductive film on the back side of a substrate where the substrate is either a substantially resistive substrate such as a glass substrate or a transparent, conductive substrate.

Description

METHODS TO ENHANCE GLASS SUBSTRATE HANDLING IN SEMICONDUCTOR PROCESSINGRELATED APPLICATION(S)

[0000] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0001] Glass substrates have been used in micro-electromechanical system (MEMS) actuators and sensors as well as in complementary metal-oxide-semiconductor (CMOS) image sensors. Most recently, glass substrates are being considered for use as carriers for thin silicon in memory or logic devices. Using glass substrates in semiconductor equipment primarily designed to handle silicon substrates can present challenges. On one hand, glass substrates are substantially transparent, which makes the detection of their position by optical sensors non-trivial. On the other hand, semiconductor device fabrication operations can involve the use an electrostatic chuck (ESC) to apply a clamping force to maintain the substrate in position during processing. The ESC applies a voltage to one or more electrodes within the ESC. These electrodes with the substrate act as a capacitive circuit completed by the existence of plasma in the vacuum chamber or by additional cathodes or anodes in the ESC. The electrostatic force arising due to the capacitive effect provides the clamping force to the glass substrate. Since glass substrates generally have, however, low electrical conductivity properties, extremely high voltages may be needed to generate the minimum clamping force needed to keep the substrate in place. For example, the voltage required to generate the minimum clamping force for a glass substrate may be as much as 10 times the voltage required for a silicon substrate. Applying such a high voltage to the glass substrate could result in defects in a film being deposited thereon and could lead to damage of the glass substrate and the ESC pedestal.

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0003] Certain embodiments pertain to methods of fabricating an electronic device. The methods include receiving a substrate having a front side and a back side, depositing a conductive or semiconductive film on the back side of the substrate, positioning the substrate on an electrostatic chuck with the back side of the substrate facing the electrostatic chuck, electrostatically clamping the substrate to the electrostatic chuck; and conducting an electronic device fabrication operation on the front side of the substrate. In some cases, the substrate is a substantially resistive substrate. In other cases, the substrate is a transparent, conductive substrate.

[0004] Certain embodiments pertain to systems for fabricating an electronic device. The systems include a back side deposition reactor including a vacuum chamber, a process gas delivery apparatus for supplying a process gas, a substrate support, and a first controller. The first controller is configured to cause the back side deposition reactor to position a substrate on the substrate support in a manner that exposes a back side of the substrate to the process gas, and deposit a conductive or semiconductive film on the back side of the substrate. The systems also include an electronic device fabrication tool having an electrostatic chuck and a second controller. The electronic device fabrication tool is configured to position the substrate on an electrostatic chuck with the back side of the substrate facing the electrostatic chuck, electrostatically clamp the substrate to the electrostatic chuck, and conduct an electronic device fabrication operation on a front side of the substrate. In some cases, the substrate is a substantially resistive substrate. In other cases, the substrate is a transparent, conductive substrate.

[0005] These and other aspects are described in further detail below with reference to the drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 depicts a block diagram of components of a process chamber, according to various embodiments.

[0007] FIGS. 2A - 2C depict a cross-section and plan view of example configurations of electrode pairs, according to some embodiments.

[0008] FIG. 3 is a block diagram depicting a substrate processing system for backside deposition, according to some embodiments.

[0009] FIG. 4 is a block diagram depicting a substrate processing system for backside deposition, according to some embodiments.

[0010] FIG. 5A is a cross-sectional view of an example of features in a portion of the process chamber in FIG. 3.

[0011] FIG. 5B is a plan view of an example of the carrier ring in FIG. 3.

[0012] FIG. 6 is a flow diagram depicting a method of fabricating an electronic device, according to some embodiments.

[0013] FIG. 7 is a flow diagram depicting a method of fabricating an electronic device, according to some embodiments.

[0014] FIG. 8 is a flow diagram depicting a method of fabricating an electronic device, according to some embodiments.

[0015] FIGS. 9A-9C depict example cross sections of substrates with backside films deposited thereon according to various embodiments.

[0016] FIGS. 10A-10D depict schematic illustrations of exemplary cross sections of a substrate after different operations of depositing layers of a multilayer stack on a back side of the substrate, according to various embodiments.

[0017] FIGS. 11A-11C depict plots of clamping test data for a glass substrate with an unoptimized a-Si / poly-Si backside film according to an embodiment, for a glass substrate optimized a-Si / Poly-Si backside film according to an embodiment, and for a silicon substrate.

[0018] FIG. 12 is a plot of optical transmission data versus wavelength for a glass substrate and a glass substrate with a-Si / poly-Si backside film, according to embodiments.

[0019] FIG. 13 depicts a graph with X-ray diffraction data for a glass substrate with a P-doped poly-Si layer deposited thereon, according to embodiments.

[0020] FIG. 14 depicts a plot of electrical resistivity for glass substrates with P-doped poly-Si layer deposited thereon, according to embodiments.DETAILED DESCRIPTION

[0021] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.I. Introduction

[0022] Wafer handling in integrated circuit fabrication processes typically involves positioning the wafers using optical sensors. For example, to position the wafers, the boundaries of the wafers may be detected using a measured intensity of light passing through the wafers. Since glass substrates are essentially transparent, their detection by optical sensors can be challenging. Also, integrated circuit fabrication processing may employ an electrostatic chuck (ESC) to generate an electrostatic clamping force to keep the substrate in place during processing. Glass substrates are essentially dielectric with low electrical conductivity, and may not have adequate charge carriers to generate a minimum clamping force without having to apply large ESC voltages, which could potentially damage the substrate and the ESC. Moreover, glass substrates may be electrically insulating, which could hinder the evacuation of charge from the substrates during the declamping process, which might result in the glass substrates failing to dechuck properly.

[0023] In various embodiments, a conductive or semiconductive film is deposited on the back side of a substantially resistive substrate (e.g., a glass substrate) to advantageously improve the electrostatic clamping (chucking) and declamping (de-chucking) of the substrate. The substantially resistive substrate may be substantially transparent (e.g., a glass substrate) according to some aspects or may be opaque (e.g., a ceramic substrate) according to other aspects. In some cases, the conductive or semiconductive film may include a single layer or a multi-layer stack with optical transmissivity properties that make the substrate opaque, which makes it easier to detect with optical sensors. In some of these embodiments, the single layer or multi-layer stack on the back side of the substrate ensures both opacity of the substrate and the presence of a conductive or semiconductive film for easier ESC clamping. In some cases, an entire multi-layer stack is deposited in-situ in a single pass without breaking vacuum. In certain examples, the opacity required for detectability can be achieved by depositing a single layer of a- Si or poly-Si and with either Silicon oxide or Silicon nitride. In some cases, a doped or undoped a-Si or Poly-Si capping layer is included in the conductive or semiconductive film to provide adequate charge carriers for providing a minimum clamping force.

[0024] In various embodiments, a conductive or semiconductive film is deposited on the back side of a transparent, conductive substrate (e.g., a ZnO substrate) to increase opacity to advantageously improve detectability. In some cases, a single layer or a multi-layer stack with optical transmissivity properties that increase opacity may be deposited on the back side of the substrate. For example, the opacity required for detectability can be achieved by depositing a single layer of a-Si or poly-Si and with either Silicon oxide or Silicon nitride. An example of atransparent, conductive substrate is a glass or other substantially transparent material with a transparent conductive oxide (TCO) layer deposited thereon. Some examples of TCOs include ZnO and Indium-Tin-Oxide (ITO). Some examples of transparent conductive substrates include a ZnO substrate and an ITO substrate.

[0025] In alternate approaches, a frontside deposition tool or a furnace could be employed to deposit the conductive or semiconductive film. For example, a fabrication procedure may include (i) frontside deposition of a sacrificial capping layer in a frontside deposition tool, removing from the frontside deposition tool and placing in a cleaning tool, (ii) backside cleaning of the substrate in the cleaning tool, (iii) wafer flip and returning to the frontside deposition tool, (iv) frontside deposition of a conductive or semiconductive film in the frontside deposition tool, and removing from the frontside deposition tool (v) wafer flip and returning to the frontside deposition tool, and (vi) removal of sacrificial capping layer. FIG. 6 illustrates a flow diagram of an example of such a fabrication procedure, which is described in more detail in Section V. This alternative approach involves additional operations (e.g., wafer flip operations and deposition and removal of sacrificial capping layer) as compared to the backside deposition approach. In another example, a furnace may be employed to deposit the conductive or semiconductive film simultaneously on both the front side and back side of the substrate. In this example, the film is removed from one side of the substrate before depositing the electronic device on that side. Thus, these alternative approaches involve additional operations as compared to the backside deposition approach, which may increase cycle time and cost.IL Terminology

[0026] As used herein, an “electrostatic chuck” (ESC) refers to a chuck that uses electrostatic force to clamp a substrate to the chuck during processing. The ESC may use one or more electrodes. Voltages may be applied to the one or more electrodes. The applied voltage may cause current to flow, thereby causing charge to migrate through a dielectric layer between the chuck and the substrate being processed. Opposite charges accumulated at an electrode relative to the substrate therefore causing the substrate to be gripped or clamped to the chuck by the electrostatic force. In some cases, the one or more electrodes may be integrated into the ESC, or may be separate from the ESC.

[0027] In certain embodiments, an ESC may refer to the one or more electrodes that generate the electrostatic force. In some embodiments, the ESC may employ a plasma in the circuit. In some embodiments, an ESC may be of a monopolar design that employs one or more electrodes to concurrently apply the same potential to the substrate. In other embodiments, the ESC may beof a multipolar design (e.g., bipolar, tripolar, etc.) to apply different potentials to the substrate.For example, an ESC may be a bipolar design that employs two electrodes to concurrently apply opposing potentials to the substrate.

[0028] A “platen” as used herein refers to a top surface of an ESC on which a substrate undergoing fabrication is positioned. There may be a gap between the substrate and the platen surface (e.g., the upper surface), which is generally referred to herein as “d.”

[0029] A “pedestal” as used herein may refer to a structure or housing that supports, or includes, the platen.

[0030] The terms “wafer,” “substrate,” and “wafer substrate” may be used interchangeably. Those of ordinary skill in the art understand that these terms can refer to a substrate during any of many stages of electronic device fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, or 300 mm, or 450 mm. Besides semiconductor devices, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components such as backplanes for pixelated display devices, flat-panel displays, micro-electromechanical devices (e.g., actuators and sensors), image sensors (e.g., complementary metal-oxide-semiconductor (CMOS) sensor), and the like. The work piece may be of various shapes, sizes, and materials.

[0031] An “electronic device fabrication operation” as used herein is an operation performed during fabrication of electronic devices (e.g., semiconductor devices). As referred to herein, such an electronic device fabrication operation is sometimes simply referred to as a “process” or as “processing.” Examples of processing include deposition of a material on a substrate, selectively etching material from a substrate, and ashing of photoresist on a substrate. Typically, the overall fabrication process includes multiple electronic device fabrication operations, each performed in its own fabrication tool such as a plasma reactor, an electroplating cell, a chemical mechanical planarization tool, a wet etch tool, and the like. Categories of electronic device fabrication operations include subtractive processes, such as etch processes and planarization processes, and material additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etch processes, a substrate etch process includes processes that etch a mask layer or, more generally, processes that etch any layer of material previously deposited on and / or otherwise residing on a substrate surface. Such an etch process may etch a stack of layers in the substrate.

[0032] As used herein, “manufacturing equipment” refers generally to equipment in which a manufacturing process takes place. Manufacturing equipment often includes a process chamber in which the workpiece resides during processing. Typically, when in use, manufacturing equipment performs one or more semiconductor device fabrication operations. Examples of manufacturing equipment for semiconductor device fabrication include deposition reactors such as electroplating cells, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and subtractive process reactors such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0033] In certain examples herein, manufacturing equipment may be referred to as a “process chamber.” In some examples, the process chamber may be a sealed enclosure in which a substrate is immobilized during processing. The process chamber may include components associated with delivery of and removal of gases. It may also include components associated with generating a plasma and controlling properties of the plasma within the chamber. It may include components for controlling the pressure, including pulling a vacuum within the chamber. In the context of this disclosure, the process chamber may include a pedestal on which the substrate sits while it is being processed. A pedestal may be outfitted with a chuck such as an ESC to hold the wafer in position during processing.

[0034] As used herein, “wafer declamped” refers to a state in which a wafer is no longer clamped to a platen of an ESC and “wafer clamped” refers to a state in which the wafer is clamped to the platen of the ESC. The change from a clamped state to a declamped state may be detected by a drop in the capacitance measured at the backside deposition tool.

[0035] As used herein, “substantially resistive” refers to an electrical resistivity property that does not provide sufficient charge carriers for a minimum clamping force under nominal applied ESC voltage and / or does not provide sufficient charge carrier for discharge for effective declamping. In some cases, a substrate is substantially resistive if it has an electrical resistivity of greater than 107Qm. For example, a substantially resistive substrate may have an electrical resistivity of up to 107Qm. As another example, a substantially resistive substrate may have an electrical resistivity of up to 109Qm. In some embodiments, a substrate is substantially resistive if it has an electrical resistivity of greater than 108Qm. In some embodiments, a substrate is substantially resistive if it has an electrical resistivity in a range of between 108Qm and 1014Qm. In some embodiments, substantially resistive substantially refers to an electrical resistivity in a range of between 109Qm and 1011Qm. In some embodiments, a substrate is substantially resistive if it has an electrical resistivity greater than 1014Qm. In some embodiments, a substantially resistive substrate may have an optical transmissivity property for certain visiblewavelengths (400nm to 800nm) in a particular range for minimum opacity, for example, between, 92%-94 %.

[0036] A substantially resistive substrate may include various materials. In some embodiments, a substantially resistive substrate includes a glass such as float glass. In some embodiments, a substantially resistive substrate includes a silicon oxide. In some embodiments, a substantially resistive substrate comprises a quartz. In some embodiments, a substantially resistive substrate comprises a ceramic or alumina including sapphire.

[0037] As used herein, “glass” refers to a non-crystalline (amorphous) product formed by a rapidly cooled melt. Some examples of glass include borosilicate glass, soda-lime glass, and silicon dioxide (SiCh) or fused silica. In some embodiments, glass includes one or more additives, which can alter its properties. For example, barium may be included to increase refractive index. As another example, iron may be included to increase absorption of infrared light. As another example, cerium(IV) oxide may be included to increase absorption of ultraviolet light. In certain embodiments, glass has an electrical resistivity in a range between IxlO9O.m and IxlO14Qm. In some embodiments, glass has optical transmissivity of certain visible wavelengths (400nm to 800nm) in a range between 92%-94 %. In some embodiments, glass has optical transmissivity of certain visible wavelengths (400nm to 800nm) in a range between 70% and 94%. In some embodiments, glass has optical transmissivity of certain visible wavelengths (400nm to 800nm) in a range between 70%-85%.

[0038] In certain embodiments, “glass substrates” or “glass wafers” are thin discs of glass made of, e.g., borosilicate glass or fused silica. Using glass wafers as a substrate for an electronic device may be advantageous over using traditional silicon wafers. Some potential advantages include reduced electrical loss since glass is an electrical insulator (high electrical resistivity), better warp management due to increased stiffness and lower thermal expansion coefficient, and more cost efficient.

[0039] As used herein, “semiconductive” refers to having an electrical resistivity property between about 105Qm and about 106Qm. In some cases, a material is considered “semiconductive” if it provides an amount of charge carriers greater than required to enable (i) a minimum effective clamping force under nominal applied ESC voltage and / or (ii) discharge for effective declamping of the integrated circuit fabrication procedure.

[0040] As used herein, “conductive” refers to having an electrical resistivity property below IO-5Sm-1. In some embodiments, electrical conductivity is considered conductive if it is below 10"6Sm1. In some embodiments, electrical conductivity is considered conductive if it is below IO’7Sm’1.

[0041] As used herein, “a conductive or semiconductive film” refers to a film having one or more material layers, which together, have an electrical resistive property that is conductive or semiconductive.III. Electrostatic Chuck

[0042] Multiple variations and configurations of ESCs can be used in various embodiments. Monopolar and bipolar designs are two examples of an ESC that can be used.

[0043] FIG. 1 is a block diagram illustrating a side view of a process chamber 100, according to various embodiments. Process chamber 100 may be used in conjunction with systems or components used for various plasma processing techniques, such as plasma-enhanced chemical vapor deposition (PECVD), plasma etching, plasma stripping or ashing, sputtering, plasma spraying, and the like. Process chamber 100 includes an electrostatic chuck (ESC) 102 configured to support a substrate 120. An ESC is sometimes referred to herein as a “pedestal.”

[0044] In some embodiments, an ESC may include a collection of electrodes with one or more clamping electrodes and / or one or more blocking electrodes. For example, in FIG. 1, ESC 102 has a collection of electrodes 118 including clamping electrodes 106 and 107 and a blocking electrode 108. Blocking electrode 108 and clamping electrodes 106, 107 may be electrically connected to one or more electrical leads 116. The one or more electrical leads 116 are configured to electrically connect, either directly or indirectly, to at least one radio frequency (RF) power supply 132, which may provide direct current (DC) and / or RF power to the electrodes.

[0045] In some implementations, the clamping electrodes (e.g., clamping electrodes 106, 107) and / or the blocking electrode (e.g., blocking electrode 108) of an ESC may be a thin sheet of electrically conductive material, e.g., metal, machined to have shapes as described herein. In some implementations, an electrode may have multiple components. In some implementations, the electrodes may have slots or holes or be made of a mesh that allow the movement of particles therethrough; this may reduce the risk of delamination after sintering, as the ceramic particles may sinter through the electrodes rather than merely around them. In some implementations, the electrodes may be a metallic mesh, e.g., a woven mesh having multiple metal strands that overlap and are electrically connected. Regardless of the particular details of the electrode material, the electrodes may be machined into shapes such as are discussed herein.

[0046] Returning to FIG. 1, ESC 102 is an example of a monopolar design having two clamping electrodes 106 and 107 that apply identical voltages to substrate 120 to pull (clamp) substrate 120 against ESC 102 during operation. In an alternate example, ESC 102 may be abipolar design where clamping electrodes 106 and 107 have opposite voltages (e.g., -500 V and +500 V) to pull substrate 120 against ESC 102.

[0047] Returning to FIG. 1, generally, blocking electrode 108 (also may be known as an “outer electrode,” “edge electrode,” or “averaging electrode”) may improve the uniformity of processing operations performed on the substrate. In some embodiments, blocking electrode 108 may extend around clamping electrodes 106, 107. In some embodiments, blocking electrode 108 may have an annular shape or an annular portion associated with blocking electrode 108. In some implementations, the annular portion, when viewed from above, may encircle clamping electrodes 106, 107.

[0048] In certain instances, a blocking electrode may average anomalies associated with the positive and negative polarities of the clamping electrodes, smoothing the interaction of the clamping electrodes with the substrate. The blocking electrode may also interact with a plasma above the substrate during substrate processing operations to improve processing uniformity. More specifically, RF power provided to the blocking electrode (e.g., blocking electrode 108) may control the area where a plasma forms, particularly the radius of the plasma. As plasma processes may have non-uniformities from center-to-edge resulting from the plasma, the RF power delivered to the blocking electrode (e.g., blocking electrode 108) and the clamping electrodes (e.g., 106, 107 clamping electrodes) may be tuned to control the plasma and improve uniformity.

[0049] In some embodiments, ESC (e.g., ESC 102) may be configured to support a substrate (e.g., substrate 120) that may be provided to a substrate processing environment, e.g., process chamber 100. The substrate may be a glass substrate also referred to herein as a glass wafer, e.g., a 200-mm glass wafer, a 300-mm glass wafer, or a 450-mm glass wafer, including glass wafers having one or more layers of material, such as dielectric, conducting, or semi-conducting material, deposited thereon.

[0050] It should be understood that the process chamber 100 and ESC 102 described with reference to FIG. 1 may be designed for a 300-mm wafer according to one implementation. Suitable modifications may be made to scale various elements for larger or smaller wafers (e.g., the electrodes may be scaled to correspond with the wafer diameter to be processed).

[0051] Returning to FIG. 1, a ring 114, e.g., an edge ring or exclusion ring, may also be positioned on ESC 102. In some implementations, ring 114 may be a ceramic ring placed so as to protect, e.g., the pedestal / ESC in the process chamber from damage from the plasma and / or may assist in controlling the plasma. In some implementations, ring 114 may be a replaceable component.

[0052] In FIG. 1, a showerhead 104 may be positioned above the ESC 102. During processing operations, process gases may be flowed through showerhead 104 toward substrate 120. In some embodiments, a plasma 110 may be formed above substrate 120 during operation. In some embodiments, the showerhead 104 may include or otherwise be coupled to a plasma generation system (not shown) that may be used to generate plasma 110. Showerhead 104 (or a plasma generator system) and ESC 102 (including the clamping electrodes and blocking electrode) may be electrically coupled to RF power supply 132 and a matching network 130 for powering plasma 110. During operation, RF power supply 132 and matching network 130 may be operated at any suitable power that can form plasma 110 with a desired composition of species. Plasma 110 may have a plasma edge region 112 that is positioned proximate an outer edge of substrate 120.

[0053] In some embodiments, to control a manner in which an RF power supply operates, a controller may be operatively coupled therewith. In FIG. 1, for example, a controller 111 is operatively coupled to RF power supply 132 to control one or more of its operations. The controller (e.g., controller 111) may be an analog controller, a discrete logic controller, a programmable array controller (PAL), a programmable logic controller (PLC), a microprocessor, a computer, or any other device capable of carrying out operations for effecting processing operations. In some exemplary implementations, the controller may be configured to determine a magnitude of power to be supplied to the showerhead, clamping electrodes, and blocking electrodes, and provide commands to the RF power supply. Returning to FIG. 1, in addition to controlling the RF power supply 132, controller 111 may also be operatively coupled to a gas distribution system 177 and may be configured to provide commands thereto to supply a prescribed amount of processing gas towards substrate 120.

[0054] In some embodiments, gas distribution system 177 may also be coupled to one or more gas sources and may include one or more corresponding valves or other flow control components (e.g., mass flow controllers and / or liquid flow controllers). In some embodiments, controller 111 may be connected to the one or more valves or other flow control components to cause them to switch states and thereby allow different gases or combinations of gases to be flowed at different times and / or flow rates. In some embodiments, the one or more gas sources may be fluidically connected to a mixing vessel to allow for blending and / or conditioning of process gases prior to flow over the wafer.

[0055] In some implementations, RF power supply 132 may be a radio frequency (RF) energy source or other source of energy capable of supplying power to and energizing electrodes to form an electric field. In some exemplary embodiments, RF power supply 132 may include an RFgenerator (not shown) that is configured to operate at a desired frequency. For example, the RF generator may be configured to operate within a frequency range of 0.2 MHz to 20.0 MHz. In some exemplary embodiments, the RF generator may operate at 13.56 MHz. In some exemplary embodiments, RF power supply 132 may include matching network 130 disposed between the RF generator and one or more elements described herein, e.g., the plasma generator system or ESC 102. The matching network 130 may be an impedance matching network that is configured to match an impedance of the RF generator to an impedance of electrodes connected to the RF generator. In this regard, matching network 130 may be made up of a combination of components, such as a phase angle detector and a control motor; however, in other embodiments, it will be appreciated that the matching network may include other or additional components as well.

[0056] In some embodiments, ESCs, including ESC 102, may be manufactured using a sintering process. The clamping electrodes 106, 107 and the blocking electrode 108, as well as other elements in the pedestal / ESC and electrical connectors, e.g., metal wires, may be positioned in a powder that may be heated and / or compressed to sinter the powders together, forming a pedestal having the components noted above embedded within. The powder may be a ceramic, e.g., alumina or alumina nitride, that forms a single piece during sintering. In some embodiments, the powder may be in an “unfired” state that may be easily machinable. An ESC may be built by layering components and powder together and then firing the entire ESC to sinter the ceramic powder. As the sintering process results in expansion and contraction of various elements in the pedestal and thus movement of those elements (and potential defects due to such movement), manufacturing may be simplified by aligning components in fewer planes. Thus, clamping electrodes 106, 107 and blocking electrode 108 may be co-planar to reduce manufacturing costs. Furthermore, connections to the components, e.g., electrical connections to clamping electrodes 106, 107 and blocking electrode 108, may be positioned along a vertical central axis to reduce manufacturing complexity.

[0057] FIGS. 2A - 2C are illustrations of example configurations of electrode pairs, according to various embodiments. FIG. 2A depicts plan and cross-sectional views of a pair of “D-shaped” electrodes 201 including a first electrode 202 and a second electrode 204 that are coplanar. According to one implementation, first electrode 202 and second electrode 204 may be examples of the clamping electrodes 106 and 107 shown in FIG. 1. FIG. 2B depicts plan and cross- sectional views of a pair of concentric electrodes 211 including a first electrode 212 and a second electrode 214. First electrode 212 may encircle second electrode 214. According to one implementation, first electrode 212 and second electrode 214 may be examples of the clampingelectrodes 106 and 107 shown in FIG. 1. FIG. 2C depicts plan and cross-sectional views of a pair of interdigitated electrodes 221 including a first electrode 222 and a second electrode 224. The first electrode 222 and second electrode 224 may have a particular shape that allows them to be disposed relative to each other in an interlocking or interleaving fashion without making physical contact. According to one implementation, first electrode 222 and second electrode 224 may be examples of the clamping electrodes 106 and 107 shown in FIG. 1.IV. Backside Deposition Tool

[0058] FIG. 3 is a block diagram depicting a substrate processing system 300 (also sometimes referred to herein as “a system for fabricating an electronic device,” “fabrication system” or simply as a “system”) for performing frontside and backside deposition on a substrate 320, according to embodiments. Substrate processing system 300 includes a back side deposition reactor 305 having a single process chamber 302 with a center column configured to support a showerhead pedestal (“ShoPed”) 306 in an interior volume 301. Process chamber 302 includes a backside deposition tool 303 including a showerhead 304 configured for frontside deposition and a showerhead pedestal (“ShoPed”) 306 configured for backside deposition.

[0059] Process chamber 302 may be a vacuum or low pressure chamber maintained under a low-pressure environment by a vacuum pump (not shown) such as, e.g., a one or two stage mechanical dry pump and / or a turbomolecular pump. In one example, process chamber 302 is held at a single digit millitorr level (less than 10 millitorr).

[0060] The process chamber 302 may include a center column configured to support ShoPed 306. In certain implementations, ShoPed 306 may be employed to deposit a film, such as a conductive or semiconductive film, from the backside (underside) of substrate 320. The process chamber 302 also includes showerhead 304 disposed over ShoPed 306. Showerhead 304 may be employed when a film being deposited on a top surface (front side) of substrate 320 to, for example, form an electronic device.

[0061] For simplicity, process chamber 302 is depicted with a single process station that may be maintained under a low-pressure environment (e.g., under vacuum). However, it will be appreciated that a plurality of process stations may be included in a common process tool environment — e.g., within a common reaction chamber. For example, one implementation is a multi-station processing tool. Further, it will be appreciated that, in some implementations, substrate processing system 300 may be controlled by one or more system controllers.

[0062] Showerhead 304 may be electrically coupled to a power supply 338 via a match network 340 to provide power to showerhead 304. Power supply 338 may be controlled by a controller 342. In some embodiments, power may be provided to ShoPed 306 instead ofshowerhead 304, or power may be provided to both ShoPed 306 and showerhead 304. Controller 342 may be configured to operate substrate processing system 300 by executing process input and control instructions for specific process recipes. Depending on whether the top surface of the substrate 320 is receiving a deposited layer or layer stack or the bottom surface of the substrate 320 is receiving a deposited layer or layer stack, controller 342 may set various operational inputs for a process recipe, such as power levels, timing parameters, process gasses, mechanical movement of a substrate 320, and / or the height of substrate 320 relative to ShoPed 306 and / or the distance between substrate 320 and showerhead 304. An apparatus for positioning the substrate 320 onto carrier ring 354 may also be controller by controller 342.

[0063] In some embodiments, the center column may also include lift pins, which are controlled by a lift pin control. Such lift pins may be used to raise substrate 320 from ShoPed 306 to allow an end effector (not shown) to pick the substrate and to lower substrate 320 after being placed by the end effector. The end effector may also place substrate 320 over a plurality of spacers 344. As will be described below, the plurality of spacers 344 may be sized to provide a controlled separation of substrate 320 between a bottom surface of showerhead 304 (facing the substrate 320) and a top surface of the ShoPed 306 (facing substrate 320).

[0064] Back side deposition reactor 305 also includes process gas delivery apparatus for supplying process gas to the showerhead 304 and / or ShoPed 306. The process gas delivery apparatus includes a first gas manifold 346 that is connected to first gas sources 348, e.g., gas chemistry supplies from a facility and / or inert gases. Depending on the purposes and processing being performed over a top surface of the substrate 320, controller 342 may control the delivery of gases from first gas sources 348 via the first gas manifold 346. The chosen gases may then be flown into showerhead 304 and distributed in a space volume defined between a face of the showerhead 304 that faces that substrate 320 when the substrate is resting over the pedestal or ShoPed.

[0065] Process gas delivery apparatus also includes a second gas manifold 350 that is connected to second gas sources 352, e.g., gas chemistry supplies from a facility and / or inert gases. Depending on the processing being performed over a bottom (backside) surface of substrate 320, controller 342 may control the delivery of second gas sources 352 via the second gas manifold 350. The chosen gases may then be flown into ShoPed 306 and distributed in a space volume defined between a face of ShoPed 306 that faces a bottom surface or under side (e.g., backside) of substrate 320 when the substrate is resting over ShoPed 306 and / or spacers 344. Spacers 344 may provide for a separation that optimizes deposition to the underside of substrate 320, while reducing deposition on the top surface of substrate 320. In someembodiments, while deposition is targeted for the underside (backside) of substrate 320, an inert gas may be flown over the top surface of the substrate 320 via showerhead 304, which may push reactant gases away from the top surface and enable reactant gases provided from ShoPed 306 to be directed to the underside of the substrate 320. Spacers 344 and / or other similar substrate support features may be used to provide controlled separation between the substrate 320 and ShoPed 306 and showerhead 304.

[0066] Further, the gases may be premixed or not. Appropriate valving and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. Process gases may exit the process chamber 302 via one or more exhausts or outlets. A vacuum pump (e.g., a one or two stage mechanical dry pump and / or a turbomolecular pump) may draw process gases out and maintains a suitably low pressure within the reactor by a close loop-controlled flow restriction device, such as a throttle valve or a pendulum valve.

[0067] Returning to FIG. 3, a carrier ring 354 may encircle an outer region of ShoPed 306. When the top surface of the substrate 320 is being processed, e.g., a material is being deposited thereon, the carrier ring 354 may be configured to sit over a carrier ring support region that is a step down from a substrate support region in the center of ShoPed 306. The top surface of the carrier ring 354 is generally coplanar with the top surface of substrate 320. The carrier ring 354 may include an outer edge side of its disk structure, e.g., outer radius, and a substrate edge side of its disk structure, e.g., inner radius, that is closest to where the substrate 320 sits. The carrier ring 354 may be associated with an inner diameter (ID). The inner diameter may extend to an inner perimeter of the carrier ring and generally surround a substrate (e.g., substrate 320) in a process chamber. The wafer edge side of carrier ring 354 may also include a plurality of contact support structures or “tabs” which may be configured to lift the substrate 320 when carrier ring 354 is held by spacers 344. Carrier ring 354 may include a plurality of tabs with a quantity selected from a range to support the substrate 320 during processing. Additional details regarding embodiments of the tabs will follow. In alternative embodiments, a substrate may be placed directly upon, or supported directly by, spacers or other similar substrate support features without a carrier ring.

[0068] FIG. 4 is a block diagram depicting a substrate processing system 400 used to perform processing on the substrate 420, according to some embodiments. Some of the elements shown in FIG. 4 are similar or analogous to elements shown in FIG. 3. For the sake of brevity, the prior discussion of such similar or analogous elements with regard to FIG.3 may be assumed to be equally applicable, unless indicated otherwise in the following discussion, to the similar oranalogous counterparts of those elements in FIG. 4 that share the same last two digits in their respective callouts as in FIG. 3.

[0069] The implementation of FIG. 4, however, is different from the implementation of FIG.3 at least in some regards. For example, in FIG. 4, spider forks 456 may be used to lift and maintain carrier ring 454 in its process height, e.g., to allow depositing in the under surface (backside) of the substrate 420. Carrier ring 454 may therefore be lifted along with substrate 420. In some implementations, carrier ring 454 may be rotated to another station, e.g., in a multi-station system. In some embodiments, a spider forks 456 or any other transfer mechanism may be used to lift or move the substrate directly without a carrier ring.

[0070] FIG. 5A shows a cross-sectional view of a portion of process chamber 302 in FIG. 3. This view provides a cross-sectional representation of an edge region of ShoPed 306 and carrier ring 354. Carrier ring 354 has a carrier ring inner radius 354a and a carrier ring outer radius 354b. Carrier ring 354 includes support extensions 354c, which extend below the substantial flat surface of carrier ring 354.

[0071] Support extensions 354c are configured to mate and sit within support surfaces 354d defined in a top surface of spacers 344. The support surfaces 354d provide a complementary mating surface for support extensions 354c, such that carrier ring 354 is prevented from sliding or moving when supported by the spacers 344. Although three spacers are shown as spacers 344 in FIG. 5A, it is envisioned that any number of spacers may be provided, so long as the carrier ring 354 can be supported substantially parallel to the surface of ShoPed 306, and spacing is defined for supporting substrate 320 at a spaced apart relationship from a top surface of the ShoPed 306.

[0072] Further shown is that a top surface of ShoPed 306 includes a hole pattern 306a with a plurality of orifices that may be distributed throughout the surface to provide even distribution and output of gases during operation. In one implementation, hole pattern 306a is arranged in a plurality of concentric rings that start at the center of the top surface of the ShoPed 306 and extend to an outer periphery of the ShoPed 306. Hole pattern 306a is provided at an edge hole region 307, and orifices defined in the edge hole region 307 are preferably angled with respect to the top surface of ShoPed 306 to provide gases non-perpendicular to the top surface.

[0073] In one example, the angle or tilt at which the orifices in edge hole region 307 is defined to tilt or angle away from the center of the ShoPed 306. In one embodiment, the angle is approximately 45° from horizontal. In other embodiments, the angle can vary between 20° from horizontal to about 80° from horizontal. In one embodiment, by providing the angled orifices in the edge hole region 307, additional distribution of process gases can be provided duringbackside deposition of the substrate 320. In one embodiment, the remaining orifices 306d of hole pattern 306a are oriented substantially perpendicular to the top surface of the ShoPed 306 and directed toward the underside of substrate 320.

[0074] FIG. 5B illustrates that when substrate 320 is held by carrier ring 354, the edge of substrate 320 will sit on an edge region closer to carrier ring inner radius 354a of the carrier ring 354. The surface of showerhead 304 facing the top surface of substrate 320, when positioned using spacers 344, may be substantially close to prevent deposition during a mode where deposition is being carried out to the backside of the substrate 320.

[0075] In some embodiments, the showerhead 304 is configured to supply an inert gas flow over the top side of the substrate 320 during when the backside of the substrate is being deposited and deposition gases are being supplied by the ShoPed 306.Any suitable chamber may be used to implement the disclosed embodiments. Example deposition apparatuses include various systems, e.g., VECTOR® DT product lines and ALTUS® and ALTUS® Max, available from Lam Research Corp., of Fremont, California, or any of a variety of other commercially available processing systems. In some cases, deposition apparatus may be configured to detect both silicon and transparent substrates. In addition or alternatively, the film deposited on the glass may have doping chemistries for optical film resistivity. Doping chemistries may include, but are not limited to, phosphine (PH3) and diborane (B2H6). In some cases, the deposition apparatus may use a different purge gas passing through the top showerhead that is compatible with thin film silicon deposition. The purge gas may be a noble gas (Ar, He, Ne, etc.) which, e.g., does not react with the deposition gases going through ShoPed.V. Methods and Systems for Fabricating Electronic Devices- Electrostatic Clamping

[0076] A certain amount of static electrostatic force (minimum clamping force) may need to be applied by the ESC to hold a substrate in place during certain IC fabrication processes. The clamping force is generated by the charge carriers in the substrate and the voltage applied by the ESC. When the fabrication process is finished, the substrate may be declamped by discontinuing the voltage applied by the ESC, which allows the substrate to discharge.

[0077] In certain IC fabrication procedures, the pressure in the process chamber is held to less than 10 millitorr. A helium gas flow may be provided between the pedestal and the backside of the substrate to conduct excess heat generated during plasma processing from the substrate to the pedestal. The clamping force generated by the charge carriers in the substrate and the voltageapplied by the ESC may seal the substrate to the pedestal creating a pocket of backside helium gas between the pedestal and the substrate. The backside helium pressure in the pocket may varies during the fabrication procedures. In some cases, the backside helium pressure may vary up to 20 torr. To be able to hold the backside Helium pressure against the low pressure of the process chamber to keep the substrate in place may require a minimum amount of clamping force. The capacity of the substrate to create the clamping force is directly related to the charge carriers in the substrate.

[0078] An ESC can apply a voltage to the substrate which results in a clamping force based on the available charge carriers in the substrate, which is related to the electrical capacitance of the substrate material(s). Silicon wafers have many charge carriers and are very effective when applying a clamping force and when declamping through discharge. Glass substrates and other substantially resistive substrates, on the other hand, do not have charge carriers inherently. Also, these substantially resistive substrates may electrically insulate a charge carrying film on the substrate preventing discharge and thus may slow down the declamping process.

[0079] The results of clamping tests performed on a glass substrate with an un-optimized a- Si / Poly-Si backside film, a glass substrate with an optimized a-Si / Poly-Si backside film, and a silicon wafer are shown in FIGS. 11A-11C. During the clamping tests, a plasma is run through the process chamber and a helium pressure is applied to ramp up to a level of 20 torr and ramp down according to an integrated circuit fabrication procedure. The charges are then evacuated from the substrate by flowing charge out of the capacitance circuit to the ESC to declamp the substrate. During the clamping test, a tool measures a “capacitance sense,” which is a measure of the charge carriers in the substrate. During a normal declamp process, the capacitance sense drops indicating the evacuation of charges from the substrate.

[0080] FIG. 11A depicts clamping test data including a plot of capacitance sense data 1110 and a plot of backside He pressure data 1120 during a fabrication procedure for glass substrate with an un-optimized a-Si / Poly-Si backside film. FIG. 11B depicts clamping test data including a plot of capacitance sense data 1130 and a plot of backside He pressure data 1140 during a fabrication procedure for a glass substrate with an optimized a-Si / Poly-Si backside film. The un- optimized a-Si / Poly-Si backside film includes a multi-layer stack with a-Si / Poly-Si capping layer. The optimized a-Si / Poly-Si backside film includes a multi-layer stack with a-Si / Poly-Si capping layer comprising a doped a-Si / Poly-Si capping layer. Some examples of dopants that may be used include Phosphine (PH3) or diborane (B2H6).

[0081] FIG. 11C depicts clamping test data including a plot of capacitance sense data 1150 and a plot of backside He pressure data 1160 during a fabrication procedure for a siliconsubstrate for comparison. “Capacitance sense’’ is a measure of the substrate capacitance using a capacitance circuit in the pedestal. The same voltage is applied by the ESC in each of the examples.

[0082] In FIG. 11C, the level 1151 of the plot of capacitance sense data 1150 for the reference silicon wafer is sufficient to provide adequate charge carriers for a minimum clamping force that can hold the backside Helium pressure against the low pressure of the process chamber to keep the silicon wafer in place during the fabrication procedure.

[0083] In FIG. 11B, the plot of capacitance sense data 1130 shows a level 1131 for the glass substrate with the optimized a-Si / Poly-Si backside film. Since this level 1131 is higher than the level 1151 for the reference silicon wafer, the electrical capacitance of the glass substrate with the optimized a-Si / Poly-Si backside film has more than adequate charge carriers for the minimum clamping force needed to hold the backside Helium pressure against the low pressure of the process chamber to keep the substrate in place during the fabrication procedure.

[0084] In FIG. 11A, the plot of capacitance sense data 1110 shows a level 1111 for the glass substrate with the un-optimized a-Si / Poly-Si backside film. Level 1111 is significantly lower than the level 1151 of the reference silicon wafer. The level 1111 may not be adequate to provide the minimum clamping force.

[0085] As shown in FIG. 11A, during the clamping test, the glass substrate with the unoptimized a-Si / Poly-Si backside film exhibited an abnormal declamp 1112 with an increase in capacitance sense. In contrast, as shown in FIG. 11B, during the clamping test of the glass substrate with the optimized a-Si / Poly-Si backside film, a normal declamp occurred at a drop of capacitance sense 1132 indicating a discharge. Similarly, as shown in FIG. 11C, during the clamping test of the silicon wafer, a normal declamp occurred at a drop of capacitance sense 1152 indicating a discharge. The capacity for clamping is directly related to the charge carriers, as depicted in FIGS. 11A-11C, by the similar clamping behavior of the glass substrate with the optimized a-Si / Poly-Si backside film and the reference silicon wafer- Optical transmissivity

[0086] Wafer handling in integrated circuit processing may require positioning the wafers, which generally involves detection of the wafers by one or more optical sensors. For example, an optical sensor may detect the wafer boundaries and corresponding position of the wafer based on light transmitted through the wafer, which is associated with the optical transmissivity properties of the wafer. In certain embodiments, a single or multi-layer stack of materials may be depositedon a transparent substrate (e.g., glass substrate) to make the substrate opaque (lower optical transmissivity), which advantageously improves the detectability of the glass substrate.

[0087] FIG. 12 is a graph having a first curve 1210 of optical transmission versus wavelength for a glass substrate and a second curve 1220 of optical transmission versus wavelength for a glass substrate with a-Si / poly-Si backside film. According to the second curve 1220, the optical transmission is nearly zero up to 600 nm, which includes much of the visible spectrum (400 nm to 800 nm), for the glass substrate with a-Si / poly-Si backside film. The opacity of the glass substrate with a-Si / poly-Si backside film generally increases as the wavelength decreases. By comparison, the optical transmission is over 90% for the glass substrate in the visible spectrum. Between the wavelengths of 400-600 nm, the glass substrate with a-Si / poly-Si backside film is shown in be essentially opaque (0 % optical transmission).- Example method using frontside deposition tool

[0088] FIG. 6 is a flow diagram depicting a method of fabricating an electronic device on a substantially resistive substrate (e.g., a glass wafer), which involves using a frontside deposition tool, according to some embodiments. The substantially resistive substrate includes a first side (e.g., first side 912 of substantially resistive substrate 910 in FIG. 9A) and a second side (e.g., second side 914 of substantially resistive substrate 910 in FIG. 9A). The substantially resistive substrate is initially positioned with its first side facing the showerhead and with the second side facing a pedestal.

[0089] At operation 610, one or more upstream processes are performed. At operation 620, a sacrificial capping layer is deposited from the frontside (from the showerhead) onto the first side of the substantially resistive substrate. The sacrificial capping layer may serve to protect the substantially resistive substrate during, e.g., flipping operations. The substantially resistive substrate is then removed from the frontside deposition tool and placed in another tool for cleaning. At operation 630, the second side of the substantially resistive substrate is cleaned from the back side. At operation 640, the substantially resistive substrate returned is flipped (e.g., rotated 180 degrees) and returned to the frontside deposition tool such that that the second side is facing the showerhead. At operation 650, a conductive or semiconductive film is deposited on the second side via frontside deposition. The film may include, e.g., one or more of a metal, a poly-Si / SiO2, and a SiN. The substantially resistive substrate is removed from the frontside deposition tool, flipped, and returned to the frontside deposition tool such that that first side is once again facing upward. At operation 670, the sacrificial capping layer may be removed from the second side of the substrate and / or the second side cleaned from the backside. At operation 680, various processes are performed such as, e.g., a cleaning process and one or moredownstream processes. For example, one or more operations may be performed to form an electronic device on the first side of the substantially resistive substrate.- Example method using furnace

[0090] In another example, a furnace may be employed to deposit the conductive or semiconductive film simultaneously on opposing surfaces (first side and second side) of the substantially resistive substrate. In this approach, the conductive or semiconductive film is removed from one of the sides, e.g., the first side, before depositing the electronic device on that side. For example, the film may be removed from a first side facing a showerhead and then one or more upstream processes includes depositing the electronic device on the first side facing the showerhead via frontside deposition.- Methods using backside deposition tool

[0091] FIG. 7 is a flow diagram depicting a method of fabricating an electronic device on a substrate, which involves using a backside deposition tool (e.g., backside deposition tool 303 in FIG. 3), according to some embodiments. The substrate may be (i) a transparent, conductive substrate (e.g., a ZnO substrate), (ii) a transparent, substantially resistive substrate (e.g., a glass substrate, a quartz substrate, a sapphire substrate, etc.), or (iii) an opaque, substantially resistive substrate (e.g., ceramic substrate such as AI2O3). The substrate includes a first side (e.g., first side 912 of substrate 910 in FIG. 9A) and a second side (e.g., first side 913 of substrate 910 in FIG. 9A). The substrate is initially positioned with its first side facing the showerhead (e.g., showerhead 304 in FIG. 3) and with the second side facing the showerhead pedestal (e.g., ShoPed 306 in FIG. 3).

[0092] At operation 710, one or more upstream processes are performed. At operation 730, the second side of the substrate is cleaned from the back side at a cleaning tool. At operation 750, the substrate is removed from the cleaning tool and placed in a backside deposition tool with the second facing the showerhead pedestal, and a conductive or semiconductive film is deposited on the second side via backside deposition. The conductive or semiconductive film may include, e.g., one or more of a metal, a a-Si / Poly-Si / SiCF, and a SiN. At operation 780, various processes are performed such as, e.g., a cleaning process and one or more downstream processes. For example, one or more operations may be performed to form an electronic device on the first side of the substrate. As compared with the method described with reference to FIG. 6, the method described with reference to FIG. 7 does not require flipping operations or operations for depositing and removing a sacrificial capping layer, which advantageously simplifies the fabrication process and provides a more cost effective approach.

[0093] FIG. 8 is a flow diagram depicting a method of fabricating an electronic device on a substrate, according to some embodiments. The substrate may be (i) a transparent, conductive substrate (e.g., a ZnO substrate), (ii) a transparent, substantially resistive substrate (e.g., a glass substrate, a quartz substrate, a sapphire substrate, etc.), or (iii) an opaque, substantially resistive substrate (e.g., ceramic substrate such as AI2O3).

[0094] At operation 810, the substrate (e.g., transparent, conductive substrate, transparent, substantially resistive substrate, or transparent, substantially resistive substrate) is received at a backside deposition tool (e.g., backside deposition tool 303) in a process chamber (e.g., process chamber 302). The substrate includes a first side (e.g., first side 912 of substrate 910 in FIG. 9A, FIG. 9B, and FIG. 9C) and a second side (e.g., second side 914 of substrate 910 in FIG. 9A, FIG. 9B, and FIG. 9C). The substrate is positioned with its first (front) side facing the showerhead (e.g., showerhead 304 in FIG. 3) and with the second (back) side facing the showerhead pedestal (e.g., ShoPed 306 in FIG. 3).

[0095] At operation 820, a conductive or semiconductive film (e.g., a single a-Si layer, a single poly-Si layer, a multilayer stack including a silicon oxide or silicon nitride layer alternating with a poly-Si or a-Si layer including a poly-Si or a-Si caping layer) is deposited on the back side of the substrate. The mixture of process gases, precursors, chamber pressure, chamber temperature, wafer temperature controlled during the deposition operation is based on the layer or layers of the conductive or semiconductive film being deposited. Some examples of process parameters for various materials that may be included in a conductive or semiconductive film are provided in Section VIII.

[0096] Generally speaking, deposition of the conductive or semiconductive film by PECVD, for example, may proceed by flowing a reactant into the process chamber, and optionally with a co-reactant, while exposing the substrate to plasma. The plasma may drive a gas phase reaction that results in deposition of the conductive or semiconductive film. The PECVD reactions may generally involve delivering reactant(s) to the semiconductor substrate continuously while the semiconductor substrate is exposed to plasma.

[0097] In some embodiments, a Silicon nitride film deposited on the backside of the substrate includes exposing the backside of the substrate to a silicon-containing precursor and a nitrogencontaining reactant, and exposing the backside of the semiconductor substrate to plasma to drive a reaction between the silicon-containing precursor and the nitrogen-containing reactant to deposit the nitride film. To protect the frontside of the semiconductor substrate on which circuits, transistors, and other device components are patterned during the backside processes, the frontside is protected from being exposed to plasma and / or reactant or process gases, forexample, by keeping the gap between the frontside of the semiconductor substrate and the showerhead to less than plasma sheath and by flowing inert gas(es) onto the frontside of the semiconductor substrate. By depositing on the backside of the semiconductor substrate, the nitride film avoids being deposited on circuits, transistors, and other device components on the frontside of the bowed semiconductor substrate.

[0098] At operation 830, the substrate is positioned to load onto an electrostatic chuck (ESC) such that the back side of the substrate faces the ESC. The positioning of the substrate may be accomplished using one or more optical sensors. In some cases, positioning involves controlling the spacing between the substrate and other parts of the process chamber.

[0099] At operation 840, an electrostatically clamping operation is performed on the substrate. During an exemplary electrostatically clamping operation, the substrate is secured in place by applying voltage(s) to one or more clamping electrodes within the ESC such that the clamping electrode(s) and the substrate act as a capacitive circuit. The capacitive circuit may be completed by the existence of a plasma within the process chamber or by anodes and cathodes in different regions of the ESC.

[0100] At operation 850, an electronic device fabrication operation is conducted on a front side of the substrate. The electronic device fabrication operation includes a number of suboperations. Categories of semiconductor device fabrication suboperations include subtractive processes, such as etch processes and planarization processes, and material additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etch processes, a substrate etch process includes processes that etch a mask layer or, more generally, processes that etch any layer of material previously deposited on and / or otherwise residing on a substrate surface. Such an etch process may etch a stack of layers in the substrate.VI. Conductive or semiconductive film configurations

[0101] Semiconductor device or other electronic device fabrication often involves deposition of a stack of layers (multilayer stack) on a substrate. Typically, most deposition and other processing used to form these devices occurs on the top (upper) side of the substrate, often referred to as the front surface or front side of the substrate.

[0102] In various embodiments discussed herein, a conductive or semiconductive film is deposited on a back side (opposing the front side) of a substrate prior to depositing the multilayer stack forming the electronic device on the front side. The conductive or semiconductive film may be a single layer or may be a multilayer stack. Backside deposition of this conductive orsemiconductive film can increase the available charge carriers in the substrate, which may advantageously increase the clamping force by an ESC (as compared to an uncoated substrate) and increase discharge to the plasma during declamping. In addition or alternatively, the conductive or semiconductive film may have an optical transmissivity property that lowers the optical transmissivity (increases opacity) of the substrate which may advantageously improve its detectability by optical sensors during substrate processing.

[0103] One or more of the material layers in the backside and frontside films may be deposited through chemical vapor deposition (CVD) techniques such as, e.g., plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or plasma enhanced atomic layer deposition (PEALD), or through direct metal deposition (DMD), etc. These examples are not intended to be limiting.

[0104] The multilayer stack of the frontside film may be deposited to any number of layers and thicknesses. In one example, the multilayer stack may include about 20 or more layers, and have a total thickness of about 2 pm to about 4 pm. In some cases, multilayer stacks may include about one hundred or more layers. In some embodiments, multilayer stacks may have about five hundred or more layers. In some embodiments, the multilayer stacks may have about one thousand or more layers. Such stacks may have a thickness of about 4 pm to 12 pm, for example.

[0105] According to various embodiments, the single layer or layers of a multilayer stack of a conductive or semiconductive film deposited on the backside of the substrate may have various thicknesses. For example, each layer of the conductive or semiconductive film may have a thickness between 0. 1 pm to about 0.2 pm. In one example, the conductive or semiconductive film may include a multilayer stack having about 20 or more layers, and have a total thickness of about 2 pm to about 4 pm. In some cases, multilayer stacks may include about one hundred or more layers. In some embodiments, multilayer stacks may have about five hundred or more layers. In some embodiments, the multilayer stacks may have about one thousand or more layers. Such stacks may have a thickness of about 4 pm to 12 pm, for example.

[0106] In some embodiments, to increase opacity for easier detectability and / or to increase electrical conductivity for easier electrostatic chucking and dechucking, the substrate has a backside conductive or semiconductive film that includes a single a-Si layer, a single poly-Si layer, or a multilayer stack that alternates between a-Si layer or a poly-Si layer and a silicon oxide layer or a silicon nitride layer. In some embodiments, to improve ESC chucking and dechucking, the backside conductive film or a semiconductive film includes a doped or undoped a-Si or poly-Si capping layer. In some embodiments, the backside conductive or semiconductive film may include a multilayer stack that is deposited entirely in-situ in the backside deposition tool without breaking vacuum (e.g., in a single pass), which may advantageously reduce cost and cycle time.

[0107] The backside conductive or semiconductive film may include one or more layers. An example of a backside film is a single a-Si layer. Another example of a backside film is single poly-Si layer. Other examples of suitable backside conductive or semiconductive films include a multilayer stack. In some of these multilayer examples, the multilayer stack includes an a-Si layer or a poly-Si layer alternating with either Silicon Oxide (e.g., SiO2) or Silicon Nitride layers. In some cases, the multilayer stack includes a capping layer of poly-Si or a-Si layer.

[0108] FIGS. 9A-9C depict example cross sections of a substrate 910 with different backside films deposited thereon, according to various embodiments. The substrate 910 includes a first side 912 and a second side 914 opposing the first side 912. The second side 914 is depicted as facing downward, e.g., toward a showerhead pedestal, for backside deposition. The substrate may be (i) a transparent, conductive substrate (e.g., a ZnO substrate), (ii) a transparent, substantially resistive substrate (e.g., a glass substrate, a quartz substrate, a sapphire substrate, etc.), or (iii) an opaque, substantially resistive substrate (e.g., ceramic substrate such as AI2O3).

[0109] FIG. 9A depicts an example of a cross section of substrate 910 having a single a-Si layer 920 deposited on second side 914 of substrate 910 via backside deposition. In an alternate implementation, the substrate 910 may have a single poly-Si layer.

[0110] FIG. 9B depicts an example of a cross section of substrate 910 having multi-layer stack901. Multi-layer stack 901 includes a silicon oxide or silicon nitride layer 930 and a capping layer 940 of a poly-Si or a-Si.

[0111] FIG. 9C depicts an example of a cross section of substrate 910 having multi-layer stack902. Multi-layer stack 902 includes an a-Si layer 920, a silicon oxide or silicon nitride layer 930 and a capping layer 940 of a poly-Si or a-Si.VII. Properties of various layers of backside conductive or semiconductive films

[0112] Some examples of materials in the conductive or semiconductive films include the following: metal, amorphous silicon (a-Si), silicon oxide (e.g., SiCh), silicon nitride (SiN), and polycrystalline silicon (poly-Si). Variations may be used, such as, e.g., doped amorphous silicon, doped silicon oxide, doped silicon nitride, and doped polycrystalline silicon. Some examples of dopants that can be used include phosphorous and boron. The materials may be formed under different deposition conditions and with one or more dopants to tune the electricalresistivity and optical transmissivity properties for easier electrostatic clamping / declamping and optical detection. An example of tuned / optimized conductive or semiconductive film with a P- doped Poly-Si capping layer is discussed with respect to FIGS. 13 and 14. FIG. 13 is plot of x- ray diffraction analysis data for the tuned / optimized conductive or semiconductive film with the P-doped Poly-Si capping layer. FIG. 14 is a plot of electrical resistivity for tuned / optimized conductive or semiconductive films with P-doped Poly-Si capping layers. As shown, the tuned / optimized conductive or semiconductive films have relatively low electrical resistivity (high conductivity) for improved chucking / dechucking. An electrical resistivity of less than 0.02 is shown for most of the tested tuned / optimized conductive or semiconductive films.

[0113] In some embodiments, the conductive or semiconductive film includes a-Si or Poly-Si capping layer. In some cases, the a-Si or poly-Si material may include one or more dopants to increase the electrical conductivity, e.g., to create charge carriers to enable a minimum clamping force and / or effective declamping. Some examples of dopants include Phosphorus, Arsenic, Antimony, Bismuth, and Lithium. An example of a range of doping concentration levels that can be used is E19 to E22 atoms / cm3.

[0114] In certain embodiments, a backside conductive or semiconductive film has electrical conductivity properties that provide sufficient charge carriers to be conductive or semiconductive to allow for a minimum clamping force needed during the fabrication procedures.

[0115] In certain embodiments, a backside conductive or semiconductive film has optical transmissivity properties below a maximum transmissivity level to provide sufficient opacity for detectability by one or more optical sensors. In some cases, the transmissivity properties are below a maximum transmissivity level in the visible spectrum.VIII. Processes for backside deposition of conductive or semiconductive film

[0116] FIGS. 10A-10D show schematic illustrations of exemplary cross sections of a substrate 1010 after different operations of backside deposition of layers of a multilayer stack 1001 of a conductive or semiconductive film onto a second side (back side) 1014 of a substrate 1010, according to various embodiments. The substrate may be (i) a transparent, conductive substrate (e.g., a ZnO substrate), (ii) a transparent, substantially resistive substrate (e.g., a glass substrate, a quartz substrate, a sapphire substrate, etc.), or (iii) an opaque, substantially resistive substrate (e.g., ceramic substrate such as AI2O3). Second side 1014 is opposing a first side (front side) 1012 of the substrate 1010. In other implementations, the deposition of conductive or semiconductive film may include hackside deposition of a different multilayer stack (e.g., multilayer stack 902 in FIG. 9B) or of a single layer (e.g., an a-Si layer or a poly-Si layer).

[0117] Returning to FIGS. 10A-10D, multilayer stack 1001 includes an a-Si layer 1020, a silicon oxide or silicon nitride layer 1030, and a poly-Si or a-Si capping layer 1040. In an alternate implementation, a single layer (e.g., an a-Si layer) is deposited on the back side 1014 of the substrate 1010. In yet another alternate implementation a multilayer stack including a silicon oxide or silicon nitride layer 1030 and a poly-Si or a-Si capping layer 1040 is deposited.

[0118] FIG. 10A shows the cross section of substrate 1010 after it is received in a reaction chamber (e.g., process chamber 100 in FIG. 1, process chamber 334 in FIG. 3, or process chamber 434 in FIG. 4) for backside deposition. In some embodiments, one or more layers (not shown) are formed on a front side 1012 of the substrate 1010 prior to the illustrated operations. In some embodiments, one or more layers are formed on the front side 1012 of substrate 1010 after the illustrated operations.

[0119] FIG. 10B shows the substrate 1010 after the a-Si layer 1020 is deposited on the backside 1014 of the substrate 1010. The a-Si layer 1020 may provide reduced surface roughness. Crystallites in the a-Si layer 1020 may be amorphous.

[0120] FIG. 10C shows the substrate 1010 after a silicon oxide or silicon nitride layer 1030 is deposited on the backside 1014 of the substrate 1010.

[0121] FIG. 10D shows the substrate 1010 after a poly-Si layer 1040 is deposited on the backside 1014 of the substrate 1010. In one example, poly-Si layer 1040 is deposited on the substrate 1010 with a columnar grain growth extending in a direction perpendicular to the substrate 1010. While FIG. 10B shows poly-Si layer 1040 formed, in another implementation, an a-Si layer may be formed.Amorphous silicon (a-Si) layerPrecursors

[0122] An amorphous silicon (a-Si) layer may be formed on the backside of a substrate by a low temperature process (e.g., PECVD or PEALD) by using one or more silicon-containing precursors. In some embodiments, silicon-containing precursors may include one or more Si-H bonds. In some cases, silicon-containing precursors include one or more Si-Si bonds. Silicon- containing precursors suitable for use in accordance with disclosed embodiments may include silanes, including polysilanes (HaSi-GSiFE n-SiFh), where n > 0. Examples of silanes include silane (SiFU), disilane (SizHe), trisilane (SisHs), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, .vw-butylsilane, thexylsilane, isoamylsilane, t-butyldisilane, di-t-butyldisilane, and the like.

[0123] In some embodiments, a silicon-containing precursor may also include a halosilane. A halosilane includes at least one halogen atom and may or may not include hydrogens and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, and the like.

[0124] In some embodiments, silicon-containing precursors may also include an aminosilane. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogens, oxygens, halogens, and carbons. Examples of aminosilanes are mono-, di-, tri- and tetra-aminosilane (H3Si(NH2), EhSi / NEh) , HSi / NEE and Si(NE )4, respectively), as well as substituted mono-, di-, tri- and tetra- aminosilanes, for example, t-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tert-butylamino)silane (SiE NHC / CEEhh (BTBAS), tert-butyl silylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3and the like. A further example of an aminosilane is trisilylamine (N(SiH3)). In some embodiments, an aminosilane that has two or more amine groups attached to the central Si atom may be used. These may result in less damage than aminosilanes having only a single amine group attached.

[0125] In addition to the silicon-containing precursor, one or more carrier gas may be flowed to the environment adjacent to the substrate. Examples of the carrier gas include but not limited to helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), deuterium (D2), hydrogen (H2), and nitrogen (N2). In some embodiments, a gas mixture of one or more source gases (e.g., a silicon-containing precursor) and one or more of the inert carrier gas may be provided. In some embodiments, the ratio of flow rate of silicon-containing precursor to carrier gas may range between about 1 / 1 and about 1 / 1,000, or between about 1 / 3 and about 1 / 300. In some embodiments, a-Si layer may be a hydrogenated amorphous silicon (a-Si:H) layer.Pressure

[0126] In some embodiments, the chamber pressure during the deposition of an a-Si layer may be about 1-9 Torr, or about 2-6 Torr, or about 3-5 Torr.Temperature

[0127] In some embodiments, the deposition temperature may be about 200-600°C, or about 250-450°C, or about 300-420°C, or about 350-400°C.Plasma parameters

[0128] Where an a-Si layer is deposited by a plasma assisted deposition process (e.g., PECVD or PEALD), the plasma may be generated by applying radio frequency (RF) power to the process chamber. In some embodiments, the RF power has a high frequency (e.g., 13-40 MHz) and / or a low frequency (e.g., < 1MHz). In some embodiments, high frequency RF power is provided at a frequency of about 13.56 MHz or about 27 MHz. A plasma power (i.e., RF power) may be about 50 to 1,000 watts (W), or 100-500 W per wafer being processed (e.g., per station in a multi-station deposition chamber).Film thickness

[0129] An a-Si layer formed according to some embodiments herein may have various thicknesses. In one example, a thickness of an a-Si layer may be in a range of about 20nm -2000 nm. In one example, a thickness of an a-Si layer may be in a range of about 5-50 nm. In another example, a thickness of an a-Si layer may be in in a range of about 10-20 nm.Electrical Conductivity

[0130] In some cases, an a-Si layer has an electrical conductivity in range of 270- 3 x 10-5 S / m.Doping Concentrations

[0131] An example of a range of doping concentration levels that can be used in an a-Si layer is El 9 to E22 atoms / cm3.Polycrystalline silicon (poly-Si) layerPrecursor

[0132] A poly-Si layer may be formed by providing one or more silicon-containing precursors to a substrate in a reaction chamber. In some embodiments, a silicon-containing precursor includes one or more Si-H bonds. In some embodiments, a silicon-containing precursor includes one or more Si-Si bonds. Silicon-containing precursors suitable for use in accordance with disclosed embodiments may include silanes, including polysilanes (H Si-(SiH2)n-SiH ), where n > 0. Examples of silanes are silane (SiH4), disilane (Si2He), trisilane (SisHs), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec -butylsilane, thexylsilane, isoamylsilane, t-butyldisilane, di-t-butyldisilane, and the like.

[0133] In some embodiments, silicon-containing precursors may also include a halosilane. A halosilane includes at least one halogen atom and may or may not include hydrogens and / orcarbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane , chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, and the like.

[0134] In some embodiments, silicon-containing precursors may also include an aminosilane. An aminosilane includes at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogens, oxygens, halogens, and carbons. Examples of aminosilanes are mono-, di-, tri- and tetra-aminosilane (H3Si(NH2,), H2Si(NH2)2, HSi(NH2)3 and Si(NH2)4, respectively), as well as substituted mono-, di-, tri- and tetra- aminosilanes, for example, t-butylaminosilane, methylaminosilane, tert-butylsilanamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2(BTBAS), tert-butyl silylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3and the like. A further example of an aminosilane is trisilylamine (N(SiH3)). In some embodiments, an aminosilane that has two or more amine groups attached to the central Si atom may be used. These may result in less damage than aminosilanes having only a single amine group attached.

[0135] In some embodiments, a silicon-containing precursor for poly-Si layer may be the same as a silicon-containing precursor for depositing a-Si layer. In some embodiments, different silicon-containing precursors may be provided in depositing poly-Si layer and a-Si layer.

[0136] In addition to the silicon-containing precursor, one or more carrier gas may be flowed to the environment adjacent to the substrate for depositing poly-Si layer. Examples of the carrier gas include but not limited to helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), deuterium (D2), and hydrogen (H2). In some embodiments, a gas mixture of one or more source gases and one or more of the inert carrier gases may be provided. Alternatively, a silicon- containing precursor and inert carrier gases may be separately provided into the reaction chamber. In some embodiments, the ratio of flow rate of silicon-containing precursor to carrier gas may range between about 1 / 1 and about 1 / 1,000, or between about 1 / 3 and about 1 / 300, or between about 1 / 100 and about 1 / 300.Pressure

[0137] In some embodiments, the chamber pressure during the deposition of poly-Si layer may be about 1 -9 Torr, or about 2-6 Torr, or about 3-5 Torr.Temperature

[0138] In some embodiments, the deposition temperature may be about 200-600°C, or about 250-450°C, or about 300-420°C, or about 350-400°C.Plasma parameters

[0139] Where a poly-Si layer is deposited by a plasma assisted deposition process (e.g., PECVD or PEALD), the plasma may be generated by applying radio frequency (RF) power to the process chamber. In some embodiments, the RF power has a high frequency (e.g., 13-40 MHz) and / or a low frequency (e.g., < 1MHz). In some embodiments, high frequency RF power is provided at a frequency of about 13.56 MHz or about 27 MHz. A plasma power (i.e., RF power) may be about 50 to 1,000 watts (W), or 100 to500 W per wafer being processed (e.g., per station in a multi-station deposition chamber).Film thickness

[0140] A poly-Si layer formed according to some embodiments herein has a thickness of about 5-50 nm, or about 10-20 nm.Electrical Conductivity

[0141] In some cases, a poly-Si layer has an electrical conductivity in range of 0.001 to 10000 S / m.Doping Concentrations

[0142] An example of a range of doping concentration levels that can be used is E19 to E22 atoms / cm3.

[0143] Example Embodiments:

[0144] Embodiment 1 : A method of fabricating an electronic device, the method comprising: (a) receiving a substrate having a front side and a back side; (b) depositing a conductive or semiconductive film on the back side of the substrate; (c) positioning the substrate on an electrostatic chuck with the back side of the substrate facing the electrostatic chuck; (d) electrostatically clamping the substrate to the electrostatic chuck; and (e) conducting an electronic device fabrication operation on the front side of the substrate.

[0145] Embodiment 2: The method of embodiment 1, wherein the substrate is a substantially resistive substrate.

[0146] Embodiment 3: The method of embodiment 2, wherein the substantially resistive substrate has a resistivity of at least about 1,000,000 Ohm-m prior to depositing the conductiveor semiconductive film.

[0147] Embodiment 4: The method of embodiment 2, wherein the substantially resistive substrate comprises a glass.

[0148] Embodiment 5: The method of embodiment 2, wherein the substantially resistive substrate comprises a silicon oxide.

[0149] Embodiment 6: The method of embodiment 2, wherein the substantially resistive substrate comprises a quartz.

[0150] Embodiment 7: The method of embodiment 2, wherein the substantially resistive substrate comprises a ceramic or alumina.

[0151] Embodiment 8: The method of embodiment 7, wherein the ceramic or alumina comprises sapphire.

[0152] Embodiment 9: The method of embodiment 1, wherein the substrate is a transparent, conductive substrate.

[0153] Embodiment 10: The method of embodiment 9, wherein the transparent, conductive substrate comprises ZnO.

[0154] Embodiment 11 : The method of embodiment 1 , wherein the substrate is substantially transparent in a visible region.

[0155] Embodiment 12: The method of embodiment 2 or embodiment 9, wherein depositing the conductive or semiconductive film comprises a chemical vapor deposition process.

[0156] Embodiment 13: The method of embodiment 2 or embodiment 9, wherein the conductive or semiconductive film has a resistivity of at most about 100 Ohm-m.

[0157] Embodiment 14: The method of embodiment 2 or embodiment 9, wherein the conductive or semiconductive film is substantially opaque in a visible region.

[0158] Embodiment 15: The method of embodiment 2 or embodiment 9, wherein the conductive or semiconductive film comprises a layer of silicon.

[0159] Embodiment 16: The method of embodiment 15, wherein the layer of silicon is a layer of amorphous or polycrystalline silicon.

[0160] Embodiment 17: The method of embodiment 15, wherein the layer of silicon is doped to a concentration level of at least about E19 atoms / cm3.

[0161] Embodiment 18: The method of embodiment 2 or embodiment 9, wherein the conductive or semiconductive film comprises a multilayer stack.

[0162] Embodiment 19: The method of embodiment 18, wherein the multilayer stack comprises a first layer of silicon, a second layer silicon oxide or silicon nitride, and an outer layer of silicon.

[0163] Embodiment 20: The method of embodiment 18, wherein the multilayer stack comprises alternating layers of silicon and a resistive material.

[0164] Embodiment 21 : The method of embodiment 18, wherein the multilayer stack comprises alternating layers of silicon and a resistive material.

[0165] Embodiment 22: The method of embodiment 1, wherein electrostatically clamping comprises monopolar electrostatic clamping.

[0166] Embodiment 23: The method of embodiment 1, wherein the electronic device fabrication operation comprises chemical vapor deposition, physical vapor deposition, etching, epitaxial growth, photolithography, spin-coating, and / or atomic layer deposition.

[0167] Embodiment 24: The method of embodiment 1, wherein the electronic device fabrication operation comprises a plasma assisted process.

[0168] Embodiment 25: The method of embodiment 1, wherein the electronic device comprises an integrated circuit.

[0169] Embodiment 26: A system for fabricating an electronic device, the system comprising: (a) a back side deposition reactor comprising: a vacuum chamber; a process gas delivery apparatus for supplying a process gas; a substrate support; and a first controller configured to cause the back side deposition reactor to:(i) position a substrate on the substrate support in a manner that exposes a back side of the substrate to the process gas, and (ii) deposit a conductive or semiconductive film on the back side of the substrate; and (b) an electronic device fabrication tool comprising an electrostatic chuck and a second controller, the electronic device fabrication tool configured to: (i) position the substrate on an electrostatic chuck with the back side of the substrate facing the electrostatic chuck, (ii) electrostatically clamp the substrate to the electrostatic chuck, and (iii) conduct an electronic device fabrication operation on a front side of the substrate.

[0170] Embodiment 27: The system of embodiment 26, wherein the substrate is a substantially resistive substrate.

[0171] Embodiment 28: The system of embodiment 27, wherein the substantially resistive substrate has a resistivity of at least about 1,000,000 Ohm-m prior to depositing the conductive or semiconductive film.

[0172] Embodiment 29: The system of embodiment 27, wherein the substantially resistive substrate comprises a glass.

[0173] Embodiment 30: The system of embodiment 27, wherein the substantially resistive substrate comprises a silicon oxide.

[0174] Embodiment 31 : The system of embodiment 27, wherein the substantially resistive substrate comprises a quartz.

[0175] Embodiment 32: The system of embodiment 27, wherein the substantially resistive substrate comprises a ceramic or alumina.

[0176] Embodiment 33: The system of embodiment 32, wherein the ceramic or alumina comprises sapphire.

[0177] Embodiment 34: The system of embodiment 26, wherein the substrate is a transparent, conductive substrate.

[0178] Embodiment 35: The system of embodiment 34, wherein the substrate comprises ZnO.

[0179] Embodiment 36: The system of embodiment 26 or embodiment 34, wherein the substrate is substantially transparent in a visible region.

[0180] Embodiment 37: The system of embodiment 26 or embodiment 34, wherein depositing the conductive or semiconductive film comprises a chemical vapor deposition process.

[0181] Embodiment 38: The system of embodiment 26 or embodiment 34, wherein the conductive or semiconductive film has a resistivity of at most about 100 Ohm-m.

[0182] Embodiment 39: The system of embodiment 26 or embodiment 34, wherein the conductive or semiconductive film is substantially opaque in a visible region.

[0183] Embodiment 40: The system of embodiment 26 or embodiment 34, wherein the conductive or semiconductive film comprises a layer of silicon.

[0184] Embodiment 41: The system of embodiment 40, wherein the layer of silicon is a layer of amorphous or polycrystalline silicon.

[0185] Embodiment 42: The system of embodiment 40, wherein the silicon is doped to a concentration of at level of least about E19 atoms / cm3.

[0186] Embodiment 43: The system of embodiment 26 or embodiment 34, wherein the conductive or semiconductive film comprises a multilayer stack.

[0187] Embodiment 44: The system of embodiment 43, wherein the multilayer stack comprises a first layer of silicon, a second layer silicon oxide or silicon nitride, and an outerlayer of silicon.

[0188] Embodiment 45: The system of embodiment 43, wherein the multilayer stack comprises alternating layers of silicon and a resistive material.

[0189] Embodiment 46: The system of embodiment 43, wherein the multilayer stack comprises alternating layers of silicon and a resistive material.

[0190] Embodiment 47: The system of embodiment 26, wherein the electronic device comprises an integrated circuit.CONCLUSION

[0191] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

CLAIMSWhat is claimed is:

1. A method of fabricating an electronic device, the method comprising:(a) receiving a substrate having a front side and a back side;(b) depositing a conductive or semiconductive film on the back side of the substrate;(c) positioning the substrate on an electrostatic chuck with the back side of the substrate facing the electrostatic chuck;(d) electrostatically clamping the substrate to the electrostatic chuck; and(e) conducting an electronic device fabrication operation on the front side of the substrate.

2. The method of claim 1 , wherein the substrate is a substantially resistive substrate.

3. The method of claim 2, wherein the substantially resistive substrate has a resistivity of at least about 1,000,000 Ohm-m prior to depositing the conductive or semiconductive film.

4. The method of claim 2, wherein the substantially resistive substrate comprises one or more of (i) a glass, (ii) a silicon oxide, (iii) a quartz, and (iv) a ceramic or alumina.

5. The method of claim 2, wherein the substantially resistive substrate comprises a ceramic or alumina comprising sapphire.

6. The method of claim 1 , wherein the substrate is a transparent, conductive substrate.

7. The method of claim 6, wherein the transparent, conductive substrate comprises ZnO.

8. The method of claim 1, wherein the substrate is substantially transparent in a visible region.

9. The method of claim 2 or claim 6, wherein depositing the conductive or semiconductive film comprises a chemical vapor deposition process.

10. The method of claim 2 or claim 6, wherein the conductive or semiconductive film (i) has a resistivity of at most about 100 Ohm-m, (ii) is substantially opaque in a visible region, and / or (iii) comprises a layer of silicon.

11. The method of claim 2 or claim 6, wherein the conductive or semiconductive filmcomprises a layer of silicon, wherein the layer of silicon is (i) a layer of amorphous or polycrystalline silicon or (ii) is doped to a concentration level of at least about E19 atoms / cm3.

12. The method of claim 2 or claim 6, wherein the conductive or semiconductive film comprises a multilayer stack.

13. The method of claim 12, wherein the multilayer stack comprises (i) a first layer of silicon, a second layer silicon oxide or silicon nitride, and an outer layer of silicon, (ii) alternating layers of silicon and a resistive material, or (iii) alternating layers of silicon and a resistive material.

14. The method of claim 1, wherein the electronic device fabrication operation comprises chemical vapor deposition, physical vapor deposition, etching, epitaxial growth, photolithography, spin-coating, and / or atomic layer deposition.

15. The method of claim 1, wherein the electronic device fabrication operation comprises a plasma assisted process.

16. A system for fabricating an electronic device, the system comprising:(a) a back side deposition reactor comprising: a vacuum chamber; a process gas delivery apparatus for supplying a process gas; a substrate support; and a first controller configured to cause the back side deposition reactor to:(i) position a substrate on the substrate support in a manner that exposes a back side of the substrate to the process gas, and(ii) deposit a conductive or semiconductive film on the back side of the substrate; and(b) an electronic device fabrication tool comprising an electrostatic chuck and a second controller, the electronic device fabrication tool configured to:(i) position the substrate on an electrostatic chuck with the back side of the substrate facing the electrostatic chuck,(ii) electrostatically clamp the substrate to the electrostatic chuck, and(iii) conduct an electronic device fabrication operation on a front side of the substrate.

17. The system of claim 16, wherein the substrate is a substantially resistive substrate.

18. The system of claim 17, wherein the substantially resistive substrate has a resistivity of at least about 1,000,000 Ohm-m prior to depositing the conductive orsemiconductive film.

19. The system of claim 17, wherein the substantially resistive substrate comprises one or more of (I) a glass, (II) a silicon oxide, (III) a quartz, and (IV) a ceramic or alumina.

20. The system of claim 17, wherein the substantially resistive substrate comprises a ceramic or alumina comprising sapphire.

21. The system of claim 16, wherein the substrate is a transparent, conductive substrate.

22. The system of claim 21 , wherein the substrate comprises ZnO.

23. The system of claim 16 or claim 21, wherein the substrate is substantially transparent in a visible region.

24. The system of claim 16 or claim 21, wherein depositing the conductive or semiconductive film comprises a chemical vapor deposition process.

25. The system of claim 16 or claim 21, wherein the conductive or semiconductive film (I) has a resistivity of at most about 100 Ohm-m, (II) is substantially opaque in a visible region, and / or (III) comprises a layer of silicon.

26. The system of claim 16 or claim 21, wherein the conductive or semiconductive film comprises a layer of silicon, wherein the layer of silicon is (I) a layer of amorphous or polycrystalline silicon or (II) is doped to a concentration level of at least about E19 atoms / cm3.

27. The system of claim 16 or claim 21, wherein the conductive or semiconductive film comprises a multilayer stack.

28. The system of claim 27, wherein the multilayer stack comprises (I) a first layer of silicon, a second layer silicon oxide or silicon nitride, and an outer layer of silicon, (II) alternating layers of silicon and a resistive material, or (III) alternating layers of silicon and a resistive material.

Images