Methods and apparatus for distortion and bow compensation

Abstract

Methods and apparatus for mitigating distortion associated with a semiconductor substrate are provided. In some embodiments, techniques may include: obtaining a frontside profile associated with a frontside of the semiconductor substrate, the frontside profile being representative of warpage associated with the semiconductor substrate, overlay error associated with the semiconductor substrate, or both; determining, based on the frontside profile, a backside profile associated with a backside of the semiconductor substrate; and modifying a stress associated with at least portions of a backside film according to the backside profile, wherein the modifying of the stress associated with the at least portions compensates for at least a portion of the warpage, at least a portion of the overlay error, or both.

Description

METHODS AND APPARATUS FOR DISTORTION AND BOW COMPENSATIONINCORPORATION BY REFERENCE

[0000] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0001] Semiconductor substrates often suffer from warpage characterized by, for example, inplane distortion (IPD), wafer bow, deposition defects and errors, spatially inconsistent forces and irregular surface topography induced by deposited materials and devices formed on the substrate, and / or various other reasons. Currently, reduction of IPD is mostly done using lithography, which involves a complex model, is time consuming and costly, and cannot correct complex wafer shapes.

[0002] What is more, as fabrication processes and nodes continue to shrink (below 3 nanometers (nm), 20 angstroms, 16 angstroms, etc.), current lithography and backside deposition techniques become more limited in accurately and effectively mitigating warpage. As another example, as computing needs become more complex and taller stacks are formed on the substrate (e.g., chips enabling training and performance of tasks using artificial intelligence), the effects of stresses and IPD introduced to the substrate become more pronounced. Devices and chips are becoming larger and may have different regions with different patterning densities, increasing the complexity of the topography, stresses, and forces experienced by the substrate. As another example, IPD overlay requirements have also become more stringent with advanced logic and wafer bonding applications. IPD errors can come from heterogenous die structures that cause complex intra-field overlays that cannot be easily corrected by lithography. Irregular wafer shapes from non-uniform frontside processes can also cause higher-order IPDs that are difficult to correct using lithography.

[0003] In other words, current solutions are falling behind the progression of semiconductor technology. It would be highly desirable to enable localized correction of distortions, bowing, and other types of warpage using accurate, convenient, and cost- and time-efficient techniques.

[0004] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor implicitly admitted as prior art against the present disclosure.SUMMARY

[0005] In one aspect of the present disclosure, a method of mitigating distortion associated with a semiconductor substrate is disclosed. In some embodiments, the method may include: obtaining a frontside profile associated with a frontside of the semiconductor substrate, the frontside profile being representative of warpage associated with the semiconductor substrate, overlay error associated with the semiconductor substrate, or both; determining, based on the frontside profile, a backside profile associated with a backside of the semiconductor substrate; and modifying a stress associated with at least portions of a backside film according to the backside profile, wherein the modifying of the stress associated with the at least portions compensates for at least a portion of the warpage, at least a portion of the overlay error, or both.

[0006] In some embodiments, the method may include: depositing a backside film on a backside of the semiconductor substrate, the deposited backside film having a stress that is spatially uniform; and tuning a stress of at least a portion of the deposited backside film according to a backside profile associated with a backside of the semiconductor substrate, the backside profile determined based on a frontside profile associated with a frontside of the semiconductor substrate.

[0007] In another aspect of the present disclosure, a processing apparatus is disclosed. In some embodiments, the processing apparatus may include: a showerhead configured to deliver at least one process gas to a backside of a semiconductor substrate; and a controller apparatus communicatively coupled to at least the showerhead and configured to cause the processing apparatus to: obtain a frontside profile associated with a frontside of the semiconductor substrate, the frontside profile being representative of warpage associated with the semiconductor substrate, overlay error associated with the semiconductor substrate, or both; determine, based on the frontside profile, a backside profile associated with a backside of the semiconductor substrate; and modify a stress associated with at least portions of the deposited backside film according to the backside profile, wherein the modification of the stress associated with the at least portions compensates for at least a portion of the warpage, at least a portion of the overlay error, or both.

[0008] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings.BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1A is an example cross-sectional view of a substrate with a frontside layer and a backside layer.

[0010] FIGS. IB and 1C illustrate simplified cross-sectional views of a substrate without any bowing and with bowing.

[0011] ID and IE show examples of unbowed and bowed semiconductor wafers on an electrostatic chuck.

[0012] FIG. 2A depicts a cross-sectional diagram of an example die having a complex intra-die patterning.

[0013] FIG. 2B shows a simplified top-down diagram of example forces present in the example die of FIG. 2A.

[0014] FIG. 2C shows a simplified cross-sectional diagram of at least a portion of a cell portion depicted in FIG. 2A

[0015] FIG. 2D shows a simplified top-down diagram of example forces present in the at least portion of the cell portion, corresponding to the simplified cross-sectional diagram of FIG. 2C.

[0016] FIG. 2E depicts a top view of an example semiconductor substrate having an irregular shape caused by warpage.

[0017] FIG. 2F depicts an example overlay indicative of the magnitude of and direction of forces spatially varying across the example semiconductor substrate of FIG. 2C.

[0018] FIG. 3 is a diagram of an example process for wafer warpage and overlay reduction, according to some embodiments.

[0019] FIG. 4A shows a simplified cross-sectional diagram of an example of a semiconductor substrate having frontside films disposed thereon.

[0020] FIGS. 4B - 4D show simplified cross-sectional diagrams of examples of a semiconductor substrate having frontside films and backside films, according to some approaches.

[0021] FIG. 5A shows a graphical representation of forces present on an example of a semiconductor substrate having frontside films disposed thereon, and a simplified cross-sectional diagram of the semiconductor substrate.

[0022] FIG. 5B and 5C show graphical representations of forces present on examples of a semiconductor substrate having frontside films and backside films, according to some approaches, and simplified cross-sectional diagrams of the semiconductor substrate.

[0023] FIG. 6A shows diagrams indicating different areas on which different magnitudes of stress are present on an example semiconductor substrate having a frontside film disposed thereon.

[0024] FIG. 6B shows a diagram of an overlay indicative of overlay errors, and a portion thereof, corresponding to the example semiconductor substrate of FIG. 6A.

[0025] FIG. 7A shows diagrams indicating different areas on which different magnitudes of stress are present on an example semiconductor substrate having a frontside film and a compensating backside film disposed thereon.

[0026] FIG. 7B shows a diagram of an overlay indicative of overlay errors corresponding to the example semiconductor substrate of FIG. 7A.

[0027] FIG. 8 illustrates an example frontside profile and an example backside profile associated with a semiconductor substrate.

[0028] FIG. 9 is a flow diagram of an example method for mitigating distortion associated with a semiconductor substrate, according to some embodiments.

[0029] FIG. 10 is a flow diagram of another example method of mitigating distortion associated with a semiconductor substrate, according to some embodiments.

[0030] FIG. 11 is a flow diagram of another example method of mitigating warpage of a semiconductor substrate, according to some embodiments.

[0031] FIGS. 12 and 13 show block diagrams of example substrate processing systems, according to some embodiments herein.

[0032] FIG. 14A shows an example cross section of an edge of a shower-pedestal.

[0033] FIG. 14B shows a top view of an example carrier ring.

[0034] FIG. 15 is a diagram of a cross-sectional view of a processing system for depositing film on a semiconductor substrate, according to some embodiments herein.

[0035] FIG. 16 shows a schematic of an example process system that may be used to perform the methods described herein.

[0036] FIG. 17A illustrates zones for depositing films having a curved bar profile and a curved channel profile according to various embodiments herein.

[0037] FIGS. 17B and 17C illustrate a side view and exploded side view of a wafer having backside layers having a curved bar profile and a curved channel profile according to various embodiments herein.DETAILED DESCRIPTION

[0038] The following terms are used throughout the instant specification:

[0039] The terms “semiconductor wafer,” “wafer,” “semiconductor substrate,” “substrate,” “wafer substrate” and “partially fabricated integrated circuit” may be used interchangeably. Those of ordinary skill in the art understand that the term “partially fabricated integrated circuit” can referto a semiconductor wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. Examples of wafer materials include silicon (Si), gallium arsenide (GaAs), and silicon germanium (SiGe). Besides semiconductor wafers, other workpieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components such as backplanes for pixelated display devices, flat panel displays, micromechanical devices and the like. The workpiece may be of various shapes, sizes, and materials. In some applications, a die may be created from a semiconductor substrate. A die may be a discrete physical device that includes circuitry, vias, channels, and / or stacks of material disposed on it as a result of, for example, integrated circuit fabrication, and may be a piece cut out of the semiconductor substrate that has one or more dice produced thereon. An example of a die may be a vertical NAND device, also known as a 3D NAND, which is a type of non-volatile flash memory in which flash memory cells in a transistor die are stacked vertically.

[0040] “Manufacturing equipment” or “fabrication tool” refers to equipment in which a manufacturing process takes place. Manufacturing equipment may include a processing chamber in which the workpiece resides during processing. Typically, when in use, manufacturing equipment performs one or more electronic device fabrication operations. Examples of manufacturing equipment for semiconductor device fabrication include subtractive process reactors and additive process reactors. Examples of subtractive process reactors include dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers. Examples of additive process reactors include chemical vapor deposition reactors, and atomic layer deposition reactors, physical vapor deposition reactors, wet chemical deposition reactors, electroless metal deposition cells, and electroplating cells.

[0041] In various embodiments, a process reactor or other manufacturing equipment includes a tool for holding a substrate during processing. Such tool is often a pedestal or chuck, and these terms are sometimes used herein as a shorthand for referring to all types of substrate holding or supporting tools that are included in manufacturing equipment.

[0042] A “semiconductor device fabrication operation” or “fabrication operation” as used herein may refer to an operation performed during fabrication of semiconductor devices. Typically, the overall fabrication process includes multiple semiconductor device fabrication operations, each performed in its own semiconductor fabrication tool such as a plasma reactor, an electroplating cell, a chemical mechanical planarization tool, a wet etch tool, and the like. Categories of semiconductor device fabrication operations include subtractive processes, such as etch processesand planarization processes, and material additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of etch processes, a substrate etch process includes processes that etch a mask layer or, more generally, processes that etch any layer of material previously deposited on and / or otherwise residing on a substrate surface. Such an etch process may etch a stack of layers in the substrate.

[0043] In various approaches, materials (such as the above) in stacks of layers (e.g., thin films) may be deposited through chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or through direct metal deposition (DMD), etc. These examples are not intended to be limiting. Different deposition techniques may be used for different ends. For example, deposition may be useful whenever wafer stress and / or bowing are induced due to material present on the frontside of the wafer. Notably, different deposition techniques may be associated with or subject to different temperatures, pressures, precursors, or other deposition processes, conditions, or recipes. For instance, certain deposition techniques may overlap in temperatures ranges that can be used, which may advantageously be used to strategically deposit multiple layers at once or certain layers only.

[0044] “Wafer bow” as used herein may refer to a deformation of a wafer. The deformation may have radial and / or azimuthal components. Examples of types of wafer bow include dome shapes, bowl shapes, dish shapes, potato chip shapes, and saddle shapes. Wafer bow may occur during fabrication, for example, as a result of stress to the wafer during deposition of materials on an active surface of a wafer substrate. Wafer bow may occur during various types of fabrication, such as when large stacks of materials are deposited. Wafer bow may cause complications in subsequent processing steps. For example, the wafer may fail to chuck correctly if an amount of bowing is too large. Moreover, some processing steps (e.g., photolithography) may produce poor results if performed on a wafer that is excessively bowed.

[0045] Wafer bow may be measured as a deviation of the mean or median distance of the surface of the wafer to a reference plane. In some approaches, the point of the median surface of the wafer may be the center point (e.g., in the case of concave or domed bowing), or an edge point of the wafer and / or an average edge point of the wafer (e.g., in the case of warping or convex bowing). In some embodiments, wafer bow may be measured from a reference plane such that when an edge point of the wafer is below the reference plane the edge point is considered to have a negative bow,and when the edge point of the wafer is above the reference plane the edge point is considered to have a positive bow. In some embodiments, positive or negative bow may be measured along a z axis perpendicular to the reference plane.

[0046] In some embodiments, wafer bow may vary between the two principal planar dimensions of a substrate, which are referred to as the x and y directions. For example, wafer bow along the x dimension may be in a positive z direction while wafer bow along the y dimension may be in a negative z direction, (the z axis being perpendicular to a plane formed by the planar x and y dimensions).

[0047] Generally speaking, backside deposition may form a dielectric film on the backside of the a substrate or wafer. FIG. 1 A is an example cross-sectional view of a semiconductor substrate 102 (e.g., a wafer) with a frontside layer 108 and a backside layer 110. If the backside layer 110 has opposite internal stress and of comparable magnitude to the internal stress created on the frontside, the backside film effectively counteracts and corrects the bow. A typical scenario might involve the following:

[0048] 1. Deposit one or more frontside layers with high internal stress that produce significant bowing (e.g., in chamber A).

[0049] 2. Deposit a backside layer having internal stress that counteracts the internal stress of the one or more frontside layers and reduces or eliminates the bowing (e.g., in chamber B).

[0050] 3. Pattern the frontside of the unbowed substrate by photolithography.

[0051] 4. Etch the unbowed, patterned substrate (e.g., chamber C).

[0052] Chambers A, B, and C may each be different, although this is not always the case. For example, in some embodiments, chambers A and C are the same.

[0053] For uniform bow, the aforementioned approaches are acceptable, but a growing area of interest is compensation for bow of a semiconductor substrate which has complex patterning and structure that cause nonuniform forces, stresses, thicknesses, distortions, etc. across the substrate (as will be discussed with respect to FIGS. 2A - 2C), as few techniques exist for compensating for irregular warpage of a substrate. Applying a uniform backside layer (where bow-compensating effect of a backside layer is the same everywhere on the substrate) to such a substrate may not produce a planar substrate. Due to different amounts of bowing on different axes and different portions of the substrate, some of the substrate will remain warped after uniform bow compensation.

[0054] FIG. IB shows a simplified cross-sectional view of a substrate 102 without any bowing. The substrate 102 may be associated with a midplane (or average midplane) 120, which may be a plane passing through the substrate 102 at a midpoint distance between the highest point of the substrate and the lowest point of the substrate. In FIG. IB, the midplane 120 passes through the substrate 102 in such a way as to divide the substrate 102 into symmetrical vertical halves. FIG. 1 C shows a simplified cross-sectional view of a substrate 102’ with bowing. Notably, the substrate 102’ is depicted as being slightly curved, which may be exaggerated or not to scale for illustrative purposes. Internal stress from such prior processing may cause the bowing, and it is desirable to mitigate the bow. Such bowing may have been the result of prior processing, such as frontside deposition or inadvertent or unintentional backside deposition. The substrate 102’ with bow may be associated with a midplane (or average midplane) 120’, which does not pass through the exact middle of the substrate 102.

[0055] Consider a scenario in which a film is disposed on the upper (frontside) surface of substrate 102’ is causing the bowing. Such a substrate 102’ would be experiencing tensile (positive) stress from the film because it is pulled by the film, as opposed to compressive (negative) stress from a compressing film.

[0056] Semiconductor device fabrication often involves deposition of a stack of layers on a wafer substrate. Typically, most deposition and other processing to form the devices occurs on one side of the substrate, often referred to as the front face or frontside of a wafer. As the deposited layers build up, they can introduce stress in the wafer. A large net tensile or compressive stress can cause the wafer to bow, which is undesirable.

[0057] Bowing is especially likely to occur where large stacks of materials are deposited, for example, in the context of 3D-NAND devices, or where a thick front side layer is deposited. Where bowing is significant, it can deleteriously affect subsequent processing steps. For instance, the wafer may fail to chuck correctly if the bowing is too great. FIGS. ID and IE show a wafer on an electrostatic chuck. FIG. ID shows a substrate 102 on an electrostatic chuck 104. When the substrate 102 is substantially flat for purposes of a particular process operation, e.g., having a bow of about 100 pm (microns) or less, the wafer may be properly clamped, securing the wafer for subsequent processing steps. FIG. IE shows a bowed substrate 102’ on the electrostatic chuck 104. When the bow is significant, the wafer may fail to secure properly on the electrostatic chuck. Wafer bow may cause other problems. For example, certain processing steps (e.g., photolithography) are very precise and produce poor results if the wafer is not substantially flat. The problem may be manifest as lithography defocus.

[0058] One example stack that may cause these problems is a stack having alternating layers of oxide and nitride (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example of a type of stack likely to cause bowing includes alternating layers of oxide and polysilicon (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of stack materials that may be problematic include, but are not limited to, tungsten and titanium nitride.

[0059] The materials in the stacks may be deposited through chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or through direct metal deposition (DMD), etc. These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or bowing are induced due to material present on the frontside of the wafer.

[0060] The frontside stacks may be deposited to any number of layers and thicknesses. In an example, the stack includes about 20 or more layers, and has a total thickness of about 2 pm to about 4 pm. However, in some cases, multiple-layer stacks have about one hundred or more layers. In some embodiments, multiple-layer stacks may have about five hundred or more layers. In some embodiments, the multiple-layer stacks may have about one thousand or more layers. Such stacks may have a thickness of about 4 pm to 12 pm, for example.

[0061] The stress induced in the wafer by the stack or other frontside deposition may be about -500 MPa to about +500 MPa. In some embodiments, the resulting in a bow is about 150 pm or greater, e.g., about 300 pm and above, about 400 pm and above, or about 200 pm to about 400 pm (for a 300 mm wafer).

[0062] Another cause of wafer bow may be frontside processing which uses thick hardmasks with limited etch selectivity. In these embodiments, at least one of the one or more frontside layers is a hardmask. The thick hardmasks may have an internal stress similar to those described above, e.g., have a magnitude of 0 MPa to about 500 MPa. The stress caused by the hardmask may be tensile stress or compressive. The thick hardmasks may cause wafers to have a significant wafer bow, e.g., about 150 pm or more.

[0063] Various techniques have been devised for combatting bowing. When bowing is more severe, deposition processes may be tuned to reduce or counteract internal stresses in deposited layers. However, any such tuning should not interfere with process requirements for fabricating devices. One commonly used technique to counteract bowing deposits a film on the back side of the wafer.

[0064] Backside deposition may form a high-stress film. If the backside layer has the same type of internal stress (tensile or compressive) and of comparable magnitude to the internal stress created on the frontside, the backside film effectively counteracts and reduces the bow.

[0065] Examples of backside films used to counteract bow include the following: amorphous silicon, silicon oxide, silicon nitride, and silicon oxynitride. Current backside films have high internal stress and can mitigate the stresses imparted on the wafer from the frontside layers to reduce or eliminate the wafer bow. Generally, backside layers are made of films with high stress.

[0066] “Silicon oxide” is referred to herein as including any and all stoichiometric possibilities for SixOy, including integer values of x and y and non-integer values of x and y. For example, “silicon oxide” includes compounds having the formula SiOn, where 1 < n < 2, where n can be an integer or non-integer values. “Silicon oxide” can include sub-stoichiometric compounds such as SiOi.8- “Silicon oxide” may also include silicon dioxide (SiCh) and silicon monoxide (SiO). Undoped silicate glass (USG) may be another example of “silicon oxide.” “Silicon oxide” may include both natural and synthetic variations and also includes any and all crystalline and molecular structures, including tetrahedral coordination of oxygen atoms surrounding a central silicon atom. “Silicon oxide” may include amorphous silicon oxide and silicates.

[0067] “Silicon nitride” is referred to herein as including any and all stoichiometric possibilities for SixNy, including integer values of x and y and non-integer values of x and y. For example, “silicon nitride” includes compounds having the formula SiN. “Silicon nitride” may include both natural and synthetic variations and also includes any and all crystalline and molecular structures. “Silicon nitride” may include amorphous silicon nitride and silicates.

[0068] Until relatively recently, the backside film thickness remained relatively thin (e.g., under 2 m) because the bow caused by depositing material on the frontside was relatively modest. Thus, downstream processes at previous technology nodes did not normally experience issues addressed by embodiments herein. However, modern integrated circuit (IC) fabrication techniques may produce substrates having frontside layers that produce much more severe wafer bow compared to previous nodes. For example, some modern processes use thick hardmask layers in operations where the etch selectivity between the hardmask and etched material is limited, yet deep trenches or vias are etched. In another example, frontside stacks have increased the number of layers. For example, in previous nodes stacks may have been about 32 to about 72 layers. Now, stacks may have hundreds or even thousands of layers, increasing the thickness of the frontside layer and the internal stress. Typically wafer bow compensation is achieved by depositing a single backside layer. Due to the increasing magnitude of wafer bow, thicker backside films must be deposited to compensate for wafer bow. This has caused certain issues. Due to large internal forces occurringwithin thick backside layers, the layers may spontaneously form film cracks. For many film materials (e.g., tensile silicon nitride films), cracks are observed in films of thicknesses necessary to compensate for bow values above a critical bow limit. These bow limits are commonly known as the “bow cracking limit” or “cracking margin.”

[0069] If a crack does form, it may create separations large enough to provide a pathway for contaminants to directly contact the backside of the wafer, potentially damaging it. For example, chemical wet etchants, which are often used to remove backside films, may penetrate through a film crack in a backside film leading to a non-uniform etch or wafer etching, which can cause particles issues such as film flaking. Furthermore, these film cracks may be so severe that they cause the wafer itself to crack, in some cases to a depth twice as great as the film thickness.

[0070] To avoid backside film cracking, wafer bowing may be limited to an amount well below the bow cracking limit of the film. This means that some wafer integration procedures are conducted in stages, with an operation that would normally be conducted in a single step being divided into a series of steps, each introducing a relatively small bow that is compensated by a commensurately thin backside layer. This adds complexity to device manufacturing and decreases overall throughput.

[0071] In some cases, backside film thickness may be relatively uniform because the bow caused by depositing material on the frontside is relatively uniform, forming a bowl or dome shape based on an isotropic internal stress. Thus, depositing a uniform profile film, either with tensile or compressive internal stress, could mitigate the stressed imparted on a wafer from the frontside layers. However, certain frontside deposition techniques may cause anisotropic stress, such that the internal stress on the front side of the wafer, and hence the resultant bowing, varies in one principal planar dimension compared to another principal planar dimension, e.g., x and y dimensions. In such embodiments, a wafer may have x-bow and y-bow that are different in magnitude as well as direction. A uniform backside layer may insufficiently address such wafer bow.

[0072] Thus far herein, it has been established and shown that semiconductor substrates such as wafers can have varied bow symmetry along x and / or y directions, where the bowing is induced as a result of, e.g., stress to the wafer during fabrication processes such as deposition of materials. In addition, it has been established that bowing can be counteracted via deposition of film on the substrate, such as on the opposite side (e.g., backside) of the side where stress was created (e.g., frontside). It would be desirable to induce opposing stresses that are customized and targeted according to the stresses present on the other side of the substrate. However, showerheads ofconventional substrate processing systems typically do not have the ability to customize film stress in specific areas of the wafer.

[0073] To these ends, disclosed herein are techniques for mitigating distortion and warpage of a semiconductor substrate, particularly concurrent mitigation in-plane distortion (IPD) and wafer bow. In some embodiments, a backside film can be deposited directly on the backside of a semiconductor substrate having structures, films, and / or other structures on the frontside. In some cases, a backside film may preexist on the backside of the semiconductor substrate. In some embodiments, mechanical or physical properties (such as stress) associated with specifically targeted portions of the backside film can be tuned using techniques such as ultraviolet (UV) annealing or laser raster processes, among other techniques mentioned elsewhere herein. The localized tuning may be done according to a frontside profile (for example, a stress profile of the frontside determined according to topographical measurements) obtained using metrology processes. Advantageously, this approach described further herein can significantly correct and compensate for both IPD and bow that may be present in a given substrate without costly and outdated lithography tools used currently, especially as ongoing advancements in fabrication processes and increases in irregular and nonuniform shapes due to complexities of devices require greater accuracy in correcting warpage.Modulation of Forces on Substrate

[0074] A semiconductor substrate may experience a variety of forces, as a result of, e.g., films, materials, devices deposited or otherwise formed on the substrate surface. The surface on which aforementioned materials are formed on may be referred to herein as the “frontside” of the semiconductor substrate. As noted above, one of various CVD techniques may be used to deposit and form the materials on the frontside of the semiconductor substrate.

[0075] Specifically, forces may be caused by frontside processes (e.g., film deposition) and complex structures and devices formed on the frontside, or when a substrate is bonded to another. Such forces may be applied on at least the frontside of the semiconductor substrate. When such forces exist in a nonuniform or irregular manner across the semiconductor substrate, they may induce in-plane distortion (IPD) and / or stress, including tensile stress and / or compressive stress. IPD may refer to distortion within a plane of a substrate (e.g., horizontal) caused by shrinkage or expansion in the plane of the substrate (while out-of-plane distortions (OPD), also known as bows, may refer to distortion in the out-of-plane direction, e.g., perpendicular to the IPD). For instance, intra-die patterning (and variations in density of structures formed on the substrate), or a thin film deposited on the frontside, may induce a variety of stresses on the substrate, in some cases, in intricate patterns that vary spatially across the substrate. Illustrative examples follow.

[0076] FIG. 2A depicts a cross-sectional diagram of an example die 200 having a complex intradie patterning. The example die 200 may be a portion of a semiconductor substrate and may include a cell portion 210 and a periphery portion 212. In the illustrated example die 200, different vertical (three-dimensional) structures may have been formed on the cell portion 210. For instance, a plurality of channels 202 may have been formed and present in a stack 204 (e.g., a gate stack). At least some parts of the cell portion 210 may include a first region 214 and a second region 216, discussed further with respect to FIGS. 2C and 2D. Some portions in the example die 200 may have at least a three-dimensional structure 206 formed thereon. It can also be seen that at least some parts of the stack 204 may have other structures such as structure 205 (including film(s), via(s), channel(s), conductive path(s), etc.) which contribute to the irregularities and nonuniformity. Density variations 208 present on the die may cause complex intra-die patterning.

[0077] Complex and / or irregular structures intrinsic to example die 200 can cause mismatch in stress on the frontside of the semiconductor substrate (prior to the example die 200 being cut out), especially when many dies are formed on the semiconductor substrate. Mismatches in coefficients of thermal expansion (CTE) and other material properties may also occur. CTE may refer to the rate at which a material’s volume expands when the temperature changes. A CTE mismatch can cause stress and reliability problems, as stress can arise and concentrate in the region between two mismatched materials. As patterns become more complex, the structure can become less stable.

[0078] FIG. 2B shows a simplified top-down diagram 220 of example forces present in the example die 200 of FIG. 2A. As shown in the simplified diagram 220, two regions of the example die 200, the cell portion 210 and the periphery portion 212, may have overall opposing forces toward each other, resembling tensile stress between the two portions. In some scenarios, the average stress of the cell portion 210 may be different compared to the average stress of the periphery portion 212. Such forces may arise because of structures, films, devices, etc. formed on the cell portion 210, on the frontside of the semiconductor substrate. On a larger scale in which multiple structures and portions across the semiconductor substrate are accounted for, many complex forces may interact with one another (see example overlay 240 in FIG. 2D). In some scenarios, errors may result in lithographic overlay that can be used, e.g., for aligning during manufacturing of semiconductor devices. Overlay errors in lithographic patterning or the like cannot be easily corrected via conventional lithography, at least not completely and / or cost- effectively.

[0079] FIG. 2C shows a simplified cross-sectional diagram 240 of at least a portion of the cell portion 210 depicted in FIG. 2A. In some examples, the at least portion of the cell portion 210 may include a first region 214 and a second region 216. The first region 214 may be a composite filmhaving a stack of materials (e.g., films, devices, and / or other structures), while the second region 216 may have a structure resembling a staircase, resulting in a nonuniform structure on the example die 200.

[0080] FIG. 2D shows a simplified top-down diagram 250 of example forces present in the at least portion of the cell portion 210, corresponding to the simplified cross-sectional diagram 240 of FIG. 2C. Similar to the simplified top-down diagram 220 of example forces in FIG. 2B, different forces and stresses may exist between the first region 214 and the second region 216. Even though the cell portion 210 may have different forces (e.g., average stress) compared to those associated with the periphery portion 212, the two regions 214, 216 within the cell portion 210 itself may have overall opposing forces toward each other, resembling tensile stress between the two regions. The existence of these forces can create warpage, including IPD and / or bowing of the semiconductor substrate on which the example die 200 (and likely other dice) is formed.

[0081] FIG. 2E depicts a top view of an example semiconductor substrate 270 having an irregular shape caused by warpage. It can be seen that at least a first portion 272 and a second portion 274 of the example semiconductor substrate 270 may have bow relative to each other or a midplane (e.g., different amount and / or direction of displacement relative to midplane 120’). In some examples, the example die 200 discussed above may be a portion of example semiconductor substrate 270.

[0082] FIG. 2F depicts an example overlay 280 indicative of the magnitude of and direction of forces spatially varying across the example semiconductor substrate 270 of FIG. 2E. The example overlay 280 may correspond to the example semiconductor substrate 270. As noted above, forces may arise from various frontside processing, irregular and nonuniform structures formed on the frontside, etc. This can cause warpage, which may include IPD and / or wafer bowing. Various indicators 282 are shown on the example overlay 280. Indicators 282 may each be, e.g., a vector that represents at least a magnitude and a direction of a force (which may be correspond to, e.g., the IPD, which is a deformation within the plane of the substrate as opposed to out of the plane or perpendicular) present on corresponding locations of the example semiconductor substrate 270. The forces in example overlay 280 could be indicative of distortion, movement, and / or relative movement of the wafer body. In some cases, the example overlay 280 (or overlays in general) can represent residual errors after some form of corrections done by lithography or a wafer bonder. Overlay errors can refer to displacements with respect to a location of a substrate, and can be indicated by vector arrows including direction, magnitude, a color scale, and / or other means. Overlay errors do not always correlate to local stress, as other part of the wafer can impact stress.The varying directions and magnitudes shown in the example overlay 280 indicate that there is a high level of IPD and / or bowing, possibly caused by an irregular and nonuniform wafer frontside.

[0083] As can be understood from the above, various irregularities in warpage can exist in wafers having complex structures formed thereon, specifically on the frontside, which cannot be easily corrected using conventional approaches, such as lithography.

[0084] One technique that may be implemented to correct or mitigate warpage, including IPD and bowing, is thermal annealing, is ultraviolet (UV) annealing. UV annealing may involve a heat treatment process that uses UV light to change the physical and chemical properties of a material. UV light can be directed at a specific location. Thus, properties of the material, such as film stress, can be modified at specific locations. However, such UV light may not be usable on the frontside of a processed semiconductor substrate, as doing so would detrimentally affect sensitive devices and components that may have been formed on the frontside.

[0085] Another technique that may be implemented to correct or mitigate warpage is a laser raster process. For example, by directing heat delivered via a laser to specific locations on a material, those locations may be treated so as to alter physical and chemical properties of the material (including, e.g., film stress).

[0086] Therein lies an advantage and an instrumental concept on which the present disclosure hinges. More specifically, these techniques (among others discussed herein) can be used in conjunction with backside deposition of a film to counteract the forces present on the frontside of a wafer by locally modifying specific portions of backside film. As established, the forces present on the frontside can be highly irregular and nonuniform, as a result of, e.g., formation and presence of complex structures on the frontside. Thus, in some embodiments, specific modifications (also referred to herein as modulating, tuning, adjusting, varying, altering, or changing) of properties of a backside film using one or more of aforementioned (and / or other) techniques may be performed according to the frontside profile, including types of stress, magnitudes of stress, thickness of materials (which may vary spatially across the frontside), and / or average magnitude of stress. Such granular modulation of forces can overcome the aforementioned limitations of current lithographic techniques to correct warpage caused by IPD, bow, etc.

[0087] FIG. 3 is a diagram of an example process 300 for wafer warpage and overlay reduction, according to some embodiments.

[0088] In some approaches, at 310 of example process 300, topographical measurements 314 associated with a semiconductor substrate 312 may be obtained. One or more of various metrology tools and processes known to those having ordinary skill in the relevant art may be used for thetopographical measurements 314. For instance, laser scanning, blue- light scanning, optical profilometry, coordinate-measuring machine (CMM), laser displacement sensor (LDS), digital image correlation (DIC), stylus profiling, reflectometry, etc. may be used to take high-density and high-resolution measurements and characterize the surface of semiconductor substrate 312, including thicknesses of thin films disposed thereon. Such measurements can be used to determine distortions (e.g., in-plane distortions (IPD), out-of-plane distortions (OPD)), depths, thicknesses, and / or distances at or relative to a plane or point on the semiconductor substrate 312 or another reference point or plane (e.g., midplane 120’). As illustrated in FIG. 3, the semiconductor substrate 312 may have a bow (not to scale) such that the semiconductor substrate 312 appears in a bowl shape. Bows can come in various shapes, e.g., dome shapes, bowl shapes, dish shapes, “potato chip” shapes, saddle shapes, “half pipe” (taco, cannoli) shapes, etc. depending on whether and how much bowing occurs in x and y dimensions. Less symmetrical bows can also occur, such as that shown in FIG. 2D, where more bowing and displacement with respect to a midplane can occur on one side or portion of the wafer. Each of these bows can be characterized based on distances and thicknesses along the surface of the semiconductor substrate 312. For example, distance or thickness values (or average values) may be determined at each point (or area that may be a sliding kernel or window of various sizes, e.g., 3x3, 5x5, 12x12 points) using aforesaid metrology approaches.

[0089] At 320, the example process 300 may include determining a frontside profile associated with semiconductor substrate 312. In some embodiments, the frontside profile may be determined based on the topographical measurements 314 obtained with respect to the semiconductor substrate 312 (e.g., at 310 or retrieved from elsewhere, e.g., storage).

[0090] In some embodiments, the frontside profile may be indicative of, or include information about, type of stress of a frontside layer, magnitude of stress of a frontside layer, thickness of one or more frontside layers or an average thickness thereof (or another statistically determined thickness, such as weighted average with respect to location, median, standard deviation, etc.), displacement of a given point or portion of semiconductor substrate 312 with respect to a reference plane or point, or a combination, where each of the foregoing may be with respect to spatial position (e.g., on an x-y plane) on semiconductor substrate 312. Other types of information may be determined and indicated by the frontside profile as well, e.g., average stress, type(s) of material on the frontside (e.g., metal-based films including tungsten (W), copper (Cu), aluminum (Al), etc., or polymers in packaging), type of structure, maximum and minimum displacements or a total amount of bow, number of dice, and similar information that may be relevant.

[0091] In different implementations, the frontside profile may be a frontside stress profile or a frontside thickness profile, each of which may contain or indicate respective types of information. In some implementations, a frontside stress profile may include information about the type of stress and / or the magnitude of stress with respect to spatial position on the semiconductor substrate 312, that is, information about how the stress is spatially varying. In some implementations, a frontside thickness profile may include information about thickness of the semiconductor substrate 12, thickness of a film (or other structures) disposed on the semiconductor substrate 312, and / or thickness of the frontside of the semiconductor substrate 312 with respect to spatial position on the semiconductor substrate 312.

[0092] An example of a frontside stress profile 322 is shown, which in this case may indicate the amount of stress at respective locations using a color scale. Note that there are different amounts of stress at different locations. For example, region 324 (which may correspond to a die) has a different stress than region 326 (which may correspond to an edge of a die). Stress values indicated by the color scale may represent an average or overall stress present at a region, or they may indicate the stress on a pixel-by-pixel, region-by -region, or kemel-by -kernel basis. Other regions, such as a scribe lane (an alignment mark on a semiconductor substrate that help position the substrate for patterning), may have different stress levels or types. In fact, even though the die regions appear to have similar stresses, every die may have different stresses associated with it, sometimes significant differences, especially if different structures are formed on the dice. In other examples, vectors similar to those depicted in FIG. 2F may be used to indicate the stresses with respect to spatial position. In other examples, types of stress may also be indicated, e.g., vector arrow directions or other indications that will be apparent to those having ordinary skill in the relevant arts.

[0093] In some implementations, the frontside profile may be an overlay 328, an example of which is shown, which may be usable for aligning and patterning of semiconductor substrate 312. In some cases, the overlay 328 can represent residual errors after some form of corrections done by lithography or a wafer bonder. Overlay errors can refer to displacements with respect to a location of a substrate, and can be indicated by vector arrows including direction, magnitude, a color scale, and / or other means. Overlay errors do not always correlate to local stress, as other part of the wafer can impact stress.

[0094] At 330, the example process 300 may include determining a target backside profile. The target backside profile may be used to reduce warpage and overlay. In some embodiments, a backside profile may be indicative of, or include information about, type of stress present or to be induced by a backside layer, magnitude of stress present or to be induced by a backside layer,thickness of one or more backside layers to be deposited or an average thickness thereof (or another statistically determined thickness, such as weighted average with respect to location, median, standard deviation, etc.), displacement of a given point or portion of semiconductor substrate 312 with respect to a reference plane or point, or a combination, where each of the foregoing may be with respect to spatial position (e.g., on an x-y plane) on semiconductor substrate 312. Other types of information may be determined and indicated by the backside profile as well, e.g., average stress, type(s) of material of the backside film (e.g., silicon nitride, silicon oxide, amorphous silicon), type of structure, maximum and minimum displacements or a total amount of bow, number of dice corresponding to the frontside, and similar information that may be relevant, such as those that may be included in the target backside profile as described below.

[0095] In some embodiments, the target backside profile may be determined based on the frontside profile. In some implementations, the target backside profile may be determined algorithmically, e.g., by a controller or other software associated with a deposition apparatus or tool (such as the type described with respect to FIGS. 12 - 16. In some cases, at least portions of the target backside profile may indicate opposite forces to what is indicated in the frontside profile, including the types and magnitude of stresses and overall or average stress.

[0096] In some implementations, the determination of the target backside profile may include (i) determining stress values for given pixels, regions, or kernel or windows that are equal or substantially equal to corresponding locations on the frontside; (ii) types of stress that are opposite of the types of stress on corresponding locations on the frontside (e.g., compressive stress on frontside can be counteracted with tensile stress, as will be explained below); (iii) directions of stress that oppose or substantially oppose to corresponding locations on the frontside (e.g., directions on corresponding locations between frontside and backside may be 180 degrees (or within a range) opposite to each other); (iv) average stress to be induced across the backside, which may be equal or substantially equal to the average stress on the frontside as discussed below; and / or (v) thicknesses of the backside film with respect to spatial position, which may or may not match the thicknesses of material on the frontside, as counterbalancing forces may involve and be proportional to stress, thickness, or both. In other words, the target backside profile may indicate information used as a basis to perform downstream deposition and / or tuning processes. Determination of the target backside profile will be described in further detail below with respect to FIG. 8.

[0097] At 340, the example process 300 may include performing a backside film deposition on a backside of the semiconductor substrate 312. In some embodiments, the backside film can be directly deposited to the backside, e.g., via CVD techniques using the apparatus described withrespect to FIGS. 12 - 16. Examples of the backside film that may be deposited include silicon nitride (SixNysuch as SiN), silicon oxide (SixOysuch as SiCh), or amorphous silicon (a-Si). Some other examples of the backside film may include boron-based films (e.g., boron-doped silicon), carbon-based films (SixOyCzof varying stoichiometric amounts of x, y and z, such as SiOC), tungsten-based films (e.g., W, W-doped C, WxNysuch as W2N, WN, WN2, WBN), aluminum- based films (e.g., AI2O3, AIN), or tungsten-based films (e.g., TiN).

[0098] Advantageously, no wafer flipping or movement may be required, unlike conventional backside deposition techniques in the art. In some approaches, however, rotational movement (but not flipping) may be involved if using so-called atmospheric pressure plasma jet (APPJ) technology. In some examples, APPJ may enable deposition of a layer (e.g., a film) to the backside of the semiconductor substrate 312, including nonuniform (e.g., at least in part radially symmetrical) layers or portions of layers directly to the backside. In some implementations, such deposition using APPJ may involve operating one or more nozzles at atmospheric or about atmospheric (e.g., 0.5 to 1.5 times atmospheric pressure) conditions to provide a pressurized jet of plasma radicals toward a semiconductor substrate being spun. An APPJ-deposited backside layer can have a bow-compensating effect varying in the azimuthal and / or radial direction.

[0099] In addition, in some embodiments, localized tuning of the deposited backside film may be performed. For example, UV annealing and / or laser rastering (or other techniques discussed herein) may be applied to modify the stress at specific locations on the backside film, e.g., according to the target backside profile, which may result in a backside film that mirrors in an opposing way. The resulting distribution of stresses on the backside may then counteract the stresses present on the frontside. In some embodiments, the average stress on the backside may be equal or substantially equal to the average stress on the frontside. That is, an average magnitude of stress induced by the deposited backside film may be within a prescribed range of an average magnitude of stress of the frontside of the semiconductor substrate 312. For example, the average magnitude of stress on the frontside may be 0.36 gigapascals (GPa), and the average magnitude of stress induced by the deposited backside film (which may be accounted for by the target backside profile and the distribution of stresses to be induced on the backside) may be 0.34 GPa, which is within 6% of the magnitude of the frontside stress. In other implementations, the prescribed range may be selected to be within other values, e.g., 10%, 5%, 2%, etc. Localized tuning may thereby result in the reduction of the warpage.

[0100] At 350, the example process 300 may include producing a tuned semiconductor substrate 312’ that possesses lower wafer bow. Such a tuned semiconductor substrate 312’ may be associated with an overlay 358 that has little to no stress as a result of the foregoing approach inwhich a backside film is directly formed on the backside and locally tuned using treatment techniques that can tune properties (e.g., stress) at specific locations.

[0101] In some embodiments, the example process 300 may further include depositing at least one additional backside film, wherein the at least one additional backside film further contribute to the reduction of the warpage. For example, combined with etching (discussed below) may increase or decrease thicknesses at certain locations of the backside film(s).

[0102] In some embodiments, the example process 300 may further include performing an etch process, e.g., to remove a portion of the backside film. For example, known etch processes such as selective dry or wet etching can be performed. This can modulate (e.g., reduce) the thickness of the film at certain regions of the backside film, which may be according to the target backside profile. In some cases, the etch process may include removing a portion of the backside film to create a spatial discontinuity in the backside film, which may reduce the thickness at the portion of the film to zero, where no film is present. In some cases, the thickness may be reduced to an acceptable small thickness that is close to zero, e.g., under 20 angstroms or under 10 angstroms thick. Etches that form a trench structure can relax the film stress in the direction perpendicular to the trench lines and make the stress anisotropic.

[0103] At least portions of the example process 300 may be further repeated to achieve the desired warpage.

[0104] FIG. 4A shows a simplified cross-sectional diagram 400 of an example of a semiconductor substrate 402 having frontside films disposed thereon. A first frontside film 404a (Fl) and a second frontside film 404b (F2) may be present on the frontside of the semiconductor substrate 402. Similar to the example die 200 shown in FIG. 2D, different forces and stresses may exist between the first and second frontside films 404a, 404b. In this example, at least compressive stress in first frontside film 404a may result in expansion of at least region 403 of the semiconductor substrate 402, causing warpage such as IPD and bowing. In other example scenarios, a tensile stress may be present instead, shrinking of at least region 403 and thereby causing warpage such as IPD and bowing. The following examples illustrate applications of the backside deposition and localized tuning to reduce the warpage as described elsewhere herein, including the example process 300.

[0105] FIG. 4B shows a simplified cross-sectional diagram 420 of an example of a semiconductor substrate 402 having frontside films and backside films, according to some approaches. In this example, the semiconductor substrate 402 may have first frontside film 404a and second frontside film 404b as established in FIG. 4A. In addition, a first backside film 424a (B 1) and a second backside film 424b (B2) may be present (e.g., via backside deposition). In someimplementations, the first backside film 424a may correspond in location to the first frontside film 404a, and the second frontside film 404b may correspond in location to the second frontside film 404b. That is, the first backside film 424a may be directly below the first frontside film 404a, and the second backside film 424b may be directly below the second frontside film 404b. In some implementations, the first backside film 424a and the second backside film 424b may have properties that counteract forces present on the semiconductor substrate 402, such as compressive stress at region 403, e.g., by opposing the type of stress on the frontside, mirroring the magnitude of stresses on the frontside, and / or mirroring the average magnitude of stress on the frontside. In some cases, the first backside film 424a may individually and specifically counteract forces caused by the first frontside film 404a, and the second backside film 424b may individually and specifically (separately from the first backside film 424a) counteract forces caused by the second frontside film 404b. Specific configurations of the backside films 424a, 424b are discussed below.

[0106] FIG. 4C shows a simplified cross-sectional diagram 430 of another example of a semiconductor substrate 402 having frontside films and backside films, according to some approaches. In this example, first and second backside films 434a, 434b may be examples of first and second backside films 424a, 424b, and may collectively create tensile stress. In some implementations, the first and second backside films 434a, 434b may each have their own magnitude, type, and direction of stress. In some specific configurations, the first backside film 434a may have the same magnitude as the first frontside film 404a, and the second backside film 434b may have the same magnitude as the second frontside film 404b. Since the first and second frontside films 404a, 404b cause compressive stress, the deposition (and / or tuning) of the first and second backside films 434a, 434b counteract the forces created by the first and second frontside films 404a, 404b. The semiconductor substrate 402 (or at least region 403) in this example is being stretched on the frontside surface while being compressed on the backside surface. As a result, the net overall forces present across at least region 403 of the semiconductor substrate 402 may be substantially limited, possibly to zero, or toward or near zero. Assuming other forces across the semiconductor substrate 402 are neutralized in the same manner, the semiconductor substrate 402 may have reduced warpage, including reduced IPD and / or reduced bow.

[0107] Contrast the example of FIG. 4C with FIG. 4D, which shows a simplified cross-sectional diagram 440 of another example of a semiconductor substrate 402 having frontside films and backside films, according to some approaches. In this example, first and second backside films 444a, 444b may be examples of first and second backside films 424a, 424b, and may collectively create compressive stress (same as the frontside films 404a, 404b). In this specific example, the backside films 444a, 444b may have the same magnitude as the frontside films 404a, 404b,respectively. The semiconductor substrate 402 (or at least region 403) in this example is being stretched on the frontside surface and also on the backside surface. Thus, the net overall forces may be increased at least at region 403 of the semiconductor substrate 402. While it may appear counterproductive to increase the forces on the semiconductor substrate 402 (and therefore warpage and wafer bow), the residual overlay errors can be successfully corrected in this way because a globally uniform increase of force resulting in overlay change can be easily corrected in lithography or wafer bonder.

[0108] FIG. 5A shows a graphical representation 500 of forces present on an example of a semiconductor substrate 502 having frontside films disposed thereon. The graphical representation 500 may be a heatmap with a color scale, but a variety of ways may be used to represent overlay errors or residual errors present on the semiconductor substrate 502. A simplified cross-sectional diagram 510 of the semiconductor substrate 502 is also shown. The semiconductor substrate 502 may include a region 503 on which a first frontside film 504a (Fl) and a second frontside film 504b (F2) may be disposed. In some examples, the first frontside film 504a may be associated with a magnitude of tensile stress that is 2 GPa, while the second frontside film 504b may have zero stress associated with it. Note that stress in one region can also cause other regions with no stress to distort, as the wafer is a rigid body. Similar to other examples discussed thus far, films may be deposited on the backside of the semiconductor substrate 502 to reduce the net effect of forces present on the frontside, e.g., those caused by frontside films 504a, 504b.

[0109] FIG. 5B shows a graphical representation 520 of forces present on an example of the semiconductor substrate 502 having frontside films and backside films, according to some approaches. A simplified cross-sectional diagram 530 of the semiconductor substrate 502 having frontside films and backside films is also shown. Here, 2 GPa of tensile stress is present on the frontside, and an additional 2 GPa of tensile stress is present on the backside, from a first backside film 534a. In some cases, a second backside film 534b may contribute to the tensile stress as well. The graphical representation 520 may indicate higher magnitudes of overlay errors on the semiconductor substrate 502 as compared to graphical representation 500 of FIG. 5A. Although such a backside film can correct wafer bow, it may not correct IPD. An opposite stress may be needed on the backside to correct both forms of warpage — IPD and wafer bow.

[0110] FIG. 5C shows a graphical representation 540 of forces present on an example of the semiconductor substrate 502 having frontside films and backside films, according to some approaches. A simplified cross-sectional diagram 550 of the semiconductor substrate 502 having frontside films and backside films is also shown. Here, 2 GPa of tensile stress is present on the backside, from a first backside film 554a, counterbalancing the same magnitude of 2 GPa ofcompressive stress from the first frontside film 504a. While in this example a second backside film 554b may not add stress, in other example scenarios, it may contribute stress as well. At least as a result of matching stress magnitudes (e.g., 2 GPa on frontside and backside), the graphical representation 540 indicates much lower magnitudes of overlay errors on the semiconductor substrate 502 as compared to graphical representation 500 of FIG. 5A and, certainly, graphical representation 520 of FIG. 5B. Tn addition, wafer bow may be corrected as a result of opposing types of stress.

[0111] Hence, this comparison of graphical representation 520 and graphical representation 540 confirms that an opposite stress pattern (e.g., tensile and compressive) can greatly contribute to minimizing differentials in overlay forces (e.g., overlay errors) and minimizing the net stress present at a semiconductor substrate, which advantageously may reduce warpage (e.g., IPD, bowing) of the substrate. The reduction in warpage gained from these approaches may be significant, as revealed in the following examples.

[0112] FIG. 6A shows diagrams 600a, 600b, 600c indicating different areas on which different magnitudes of stress are present on an example semiconductor substrate 602 having a frontside film disposed thereon. In diagram 600a, a plurality of dice 610 are shown. In diagram 600b, a plurality of edges 612 of dice are shown. In diagram 600c, a plurality of scribe lanes 614 between dice 610 are shown. In this example, each of dice 610 may be experiencing a stress magnitude of about 0.4 GPa on the frontside, edges 612 of dice may be experiencing a stress magnitude of about 0.4 GPa on the frontside, and scribe lanes 614 may be experiencing a stress magnitude of about 0.3 GPa on the frontside. It will, however, be appreciated that there may be slight (or more) variations between each of these elements in other examples. Further, in this example, the frontside film may have a uniform thickness of about 1 micron ( m).

[0113] The foregoing stresses present may result in a wafer bow of about 230 pm in this example.

[0114] FIG. 6B shows a diagram of an overlay 620 indicative of overlay errors, and a portion 621 thereof, corresponding to the example semiconductor substrate 602 of FIG. 6A. The overlay 620 may indicate overlay errors 611 (e.g., indicative of residual errors left after correction, e.g., third-order polynomial correction by lithography). It can be seen, particularly in portion 621 of the overlay 620 that there are indications of overlay errors 611 directed inward within dice 610. Indications of overlay errors 613 being directed outward can also be seen at edges 612.

[0115] Contrast FIGS. 6A - 6B with FIGS. 7A - 7B. FIG. 7A shows diagrams 700a, 700b, 700c indicating different areas on which different magnitudes of stress are present on an example semiconductor substrate 702 having a frontside film and a compensating backside film disposedthereon. In various embodiments, the backside film may be of a type of film discussed elsewhere herein deposited using apparatus described with respect to FIGS. 12 - 16. In this example, the stress magnitudes on the frontside of example semiconductor substrate 702 are the same as those of example semiconductor substrate 602. . In this example, the backside film may also have a uniform thickness of about 1 pm. However, on corresponding locations on the backside of example semiconductor substrate 702, a stress magnitude of about 0.3 GPa may be experienced on locations corresponding to (e.g., directly underneath) dice 710, a stress magnitude of about 0.4 GPa may be experienced on locations corresponding to edges 712 of dice, and a stress magnitude of about 0.4 GPa may be experienced on locations corresponding to scribe lanes 714. The average magnitude of stresses on the frontside may be about 0.36 GPa, while average magnitude of stresses on the backside may be about 0.34 GPa. As mentioned elsewhere herein, an average magnitude of stress induced by the deposited backside film may be within a prescribed range of an average magnitude of stress of the frontside of the semiconductor substrate, e.g., within 10%, 6%, 5%, 2%, etc.

[0116] The foregoing stresses present may result in a wafer bow of about 20 pm in this example, in contrast to 230 pm in example semiconductor substrate 602 of FIG. 6A. That is to say, a wafer bow is significantly reduced, by at least about 90%.

[0117] FIG. 7B shows a diagram of an overlay 720 indicative of overlay (residual) errors corresponding to the example semiconductor substrate 702 of FIG. 7 A. The overlay 720 may indicate the presence of any overlay errors or residual errors. It can be seen that there are substantially no indications of errors in all regions of example semiconductor substrate 702. More quantitatively, overlay errors are seen to be reduced by at least about 95% as compared to overlay errors 611 shown in FIG. 6B when a backside layer with localized tuning is deposited to compensate for forces present on the frontside.

[0118] The above comparisons of example semiconductor substrate 602 and example semiconductor substrate 702 demonstrate that large, significant reductions (at least about 90% or even 95%) in warpage, including IPD and bowing, can advantageously occur using a compensating backside layer that matches the frontside profile. Although not shown in this comparison, modulation of thickness of the backside film can further reduce warpage, as forces that contribute to warpage are governed by stress as well as thickness of film(s) present on the frontside and / or backside of the substrate. As noted elsewhere herein, thickness can be varied by depositing at least an additional backside film, etching portions of existing or additional films, etc.

[0119] In some embodiments, to reduce IPD and wafer bow at the same time (as opposed to solely wafer bow or solely IPD), two conditions are applied. First, the backside stress profile or distribution may be the opposite to the frontside stress profile or distribution to enable IPDreduction. Second, the average net forces (proportional to stress and thickness) on the backside layer are tuned (e.g., using treatment techniques mentioned elsewhere herein) to match to those on the frontside to enable reduction of wafer bow. In some approaches, the thickness of layers may be matched to keep the thickness constant and tune the stresses only. More specifically, the thickness or average thickness (e.g., 1 pm) of the frontside layer could be determined, and a layer of the same thickness (e.g., 1 m) on the backside could be directly deposited using any of the backside deposition techniques mentioned herein. Subsequently, the stresses on the backside may be locally tuned. In some cases, optimal wafer bow reduction may be achieved in this way, e.g., by modulating the stress distributions on substrates with similar frontside profiles to empirically determine which distribution results in the lowest wafer bow for that frontside profile.

[0120] Examples of a frontside profile and a backside profile are discussed with respect to FIG. 8, which illustrates an example frontside profile 800 and an example backside profile 810 associated with a semiconductor substrate.

[0121] As noted above, a frontside profile may be indicative of, or include information about, type of stress of a frontside layer, magnitude of stress of a frontside layer, thickness of one or more frontside layers or an average thickness thereof (or another statistically determined thickness, such as weighted average with respect to location, median, standard deviation, etc.), displacement of a given point or portion of a semiconductor substrate with respect to a reference plane or point, or a combination, where each of the foregoing may be with respect to spatial position (e.g., on an x-y plane) on the semiconductor substrate. In different implementations, the frontside profile may be a frontside stress profile or a frontside thickness profile, each of which may contain or indicate respective types of information (e.g., stress or thickness) about a frontside layer.

[0122] As noted above, a backside profile may be indicative of, or include information about, type of stress present or to be induced by a backside layer, magnitude of stress present or to be induced by a backside layer, thickness of one or more backside layers to be deposited or an average thickness thereof (or another statistically determined thickness, such as weighted average with respect to location, median, standard deviation, etc.), displacement of a given point or portion of a semiconductor substrate with respect to a reference plane or point, or a combination, where each of the foregoing may be with respect to spatial position (e.g., on an x-y plane) on the semiconductor substrate. In different implementations, the backside profile may be a backside stress profile or a backside thickness profile, each of which may contain or indicate respective types of information (e.g., stress or thickness) about a backside layer to be deposited.

[0123] In some cases, Stoney’s equation (Eqn. 1) can be used to quantify the surface stresses generated in thin films, layers, or other materials on a semiconductor substrate.O'surface — Et I (jR (Eqn. 1)

[0124] When a substance (such as a film) binds to the surface, it may induce a deflection, and hence stress, in an underlying structure (in this case, the semiconductor substrate). In Eqn. 1, R is the radius of curvature, E is the Young’s modulus, t is the thickness of the structure, and o is the surface stress generated by the substance. In other cases, other known methods of quantifying or measuring surface stresses may be used.

[0125] The example frontside profile 800 is a graphical representation of stresses present on a frontside layer on a semiconductor substrate. Stress level 802 may indicate a positive (tensile) stress having a first magnitude that is less than a second magnitude indicate by positive stress of stress level 804. Stress level 802 may correspond to a first region on the semiconductor substrate, while stress level 804 may correspond to a second, different region on the semiconductor substrate, where the regions may be along an x-axis on a given y-axis (or along a y-axis on a given x-axis). As an example, the first region corresponding to stress level 802 may be an edge of a die, and the second region corresponding to stress level 803 may be a die. In some cases, the stress may be an average (or other statistically determined) stress for that region. Stress level 803 may indicate a negative (compressive) stress having a third magnitude, corresponding to a third region on the semiconductor substrate, adjacent to the second region corresponding to stress level 803. That is, the example frontside profile 800 indicate that stresses vary spatially on the frontside of the semiconductor substrate.

[0126] The example backside profile 810 is a graphical representation of stresses that are either present (e.g., after deposition of a backside layer) or to be induced (e.g., by deposition of a backside layer) on a semiconductor substrate. In some embodiments, the example backside profile 810 may correspond spatially to the frontside (e.g., as represented by example frontside profile 800). That is, stress level 812 may correspond to stress level 802, stress level 814 may correspond to stress level 804, and stress level 813 may correspond to stress level 803. In fact, these corresponding stress level may mirror one another. For example, the magnitude indicated by stress level 812 may match the magnitude indicated by stress level 802, except the type of stress is opposite, so compressive for stress level 812. Similarly, the compressive stress indicated by stress level 814 may be greater in magnitude than that indicated by stress level 812. Similarly, stress level 813 may indicate a tensile stress matching the magnitude of stress level 803, which is compressive in this example.

[0127] The average stress 809 induced by the frontside layer may be substantially similar (e.g., within a range) in magnitude to the average stress 819 induced by the backside layer (e.g., 0.36 GPa and 0.34 GPa, respectively). The example backside profile 810 is specifically tuned to balancethe forces on the frontside of the semiconductor substrate. In some embodiments, a compensating backside layer may be deposited according to a backside profile (e.g., example backside profile 810) to advantageously achieve significant reductions in warpage, including IPD and wafer bow. The net stress on the semiconductor substrate resulting after deposition of a backside layer according to the example backside profile 810 may be close to zero.Methods

[0128] Various types of approaches may be considered for implementing the above-disclosed techniques to mitigate distortion of a wafer.

[0129] In some approaches, a uniform backside film may be deposited (or may be preexisting) on a wafer, where the backside film may have an average stress and / or average thickness that matches the frontside, which reduces bowing of the wafer. The backside film may be selected for the type and amount of stress that can be induced. Stresses of the backside film (which may vary spatially) may be tuned at specific locations (also referred to herein as localized tuning or local or locally tuning) while maintaining the average stress.

[0130] In some approaches, a uniform backside film may be deposited (or may be preexisting) on a wafer without consideration of stress, forces, etc., as convenient and available. Stresses across this backside film may be locally tuned. In the third step, another backside film may be deposited, which reduces bowing.

[0131] There are a few number of steps in the first approach, resulting in resource efficiency. However, an appropriate film is selected ahead of time, e.g., one having compressive or tensile properties based on the incoming wafer and amount of bowing. There is more flexibility in film choice in the second approach, despite the longer process. Nonetheless, each approach may result in highly reduced warpage and / or overlay error as discussed above.

[0132] Following are example methods that embody advantages of both types of approaches.

[0133] FIG. 9 is a flow diagram of an example method 900 for mitigating distortion associated with a semiconductor substrate, according to some embodiments. Structure for performing the functionality illustrated in one or more of the blocks shown in FIG. 9 may include a computerized apparatus or system, such as a deposition apparatus or deposition tool configured to perform deposition of material (e.g., film) on a substrate. One or more of the functions of the method 900 may be performed at least in part by or caused at least in part by hardware and / or software components of such computerized apparatus or system, such as, for example, a controller apparatus (which may include one or more controllers) and / or a computer-readable apparatus including a storage medium having computer-readable and / or computer-executable instructions that areconfigured to, when executed by a controller apparatus or a processor apparatus, cause the controller apparatus, the processor apparatus, or the computerized apparatus or system to perform the operations. In some cases, the controller apparatus or the processor apparatus may be one example of the computerized apparatus or system. A process chamber may be another example or component of the computerized apparatus or system. Example components of above apparatus are illustrated in, e.g., FIGS. 12 - 16, and described in more detail elsewhere herein.

[0134] It should also be noted that the operations of FIG. 9 may be performed in any suitable order, not necessarily the order depicted in FIG. 9. Further, the process shown in FIG. 9 may include additional or fewer operations than those depicted in FIG. 9.

[0135] At block 910, the method 900 may include measuring a topography of a semiconductor substrate. In some embodiments, a metrology process of the types discussed above (e.g., with respect to topographical measurements 314) may be used to measure a topography of a frontside of the semiconductor substrate. In some cases, this may measure the topography of a frontside film disposed on the frontside of the semiconductor substrate. Hence, the measured topography may include information including, e.g., thickness of the frontside film across the frontside.

[0136] At block 920, the method 900 may include determining a frontside profile 922 of the frontside of the semiconductor substrate based on the measured topography. In some embodiments, the frontside profile 922 stress profile may include a frontside stress profile, a frontside thickness profile, or some combination thereof (a frontside force profile including or being indicative of information about stress and thickness, which govern force). In some cases, a frontside IPD profile may be determined, which may indicate overlay errors on the semiconductor substrate.

[0137] At block 930, the method 900 may include determining a backside profile 932 of the backside of the semiconductor substrate based on the frontside profile 922. In some embodiments, the backside profile 932 may include information about stresses, forces, and / or thicknesses with respect to position of the semiconductor substrate to minimize warpage, IPD, overlay error, and / or wafer bow. In some implementations, the backside profile 932 may be a backside stress profile indicative of stresses to be induced on the backside.

[0138] Optionally, at block 940, the method 900 may include depositing a backside film on the backside of the semiconductor substrate. In some cases, a backside film may already exist on the backside of the semiconductor substrate. Hence, deposition of the backside film may not be needed prior to the local tuning of backside film stress (e.g., according to block 950), e.g., where the backside film is preexisting film. Omitting the deposition of the backside film prior to local tuning need not, however, preclude deposition of additional backside film(s), e.g., according to block 962discussed below. In some embodiments, the backside film may be a uniform layer of material, and may be of the type disclosed herein, such as silicon oxide, silicon nitride, amorphous silicon, or other as discussed above. In some implementations, the backside film may have the same thickness or average thickness as the frontside film.

[0139] At block 950, the method 900 may include performing localized tuning of backside stress according to the backside profile 932. In some embodiments, treatment methods mentioned above may be used on the backside film, such as UV annealing and / or laser raster, to modify stress at specific locations as specified by the backside profile 932, thereby creating a backside film that possesses a similar stress profile as the frontside. For example, the average stress of the backside film may be substantially similar (e.g., within a prescribed range) of the average stress of the frontside film. Thus, the tuned backside film may be a compensating layer that significantly reduces warpage, IPD, overlay error, and / or wafer bow.

[0140] Optionally, at block 960, the method 900 may further include performing lithography to further tune the stresses or forces on the backside.

[0141] Optionally, at block 962, the method 900 may further include depositing at least one additional backside film and / or etching the backside film(s) (which may include the additional backside film(s)). In some implementations, depositing and / or etching may be performed according to the backside profile 932. In some implementations, depositing and / or etching may be performed according to another backside profile that is generated according to the then-present frontside profile. In some cases, etching may be performed so as to create a spatial discontinuous backside film, wherein some portion(s) may be zero or close to zero. Such additional deposition and / or such etching can further tune the backside stress to achieve further reduction in wafer distortion.

[0142] At least portions of the method 900 may be repeated to achieve the desired distortion.

[0143] FIG. 10 is a flow diagram of another example method 1000 for mitigating distortion associated with a semiconductor substrate, according to some embodiments. Structure for performing the functionality illustrated in one or more of the blocks shown in FIG. 10 may include a computerized apparatus or system, such as a deposition apparatus or deposition tool configured to perform deposition of material (e.g., film) on a substrate. One or more of the functions of the method 1000 may be performed at least in part by or caused at least in part by hardware and / or software components of such computerized apparatus or system, such as, for example, a controller apparatus (which may include one or more controllers) and / or a computer-readable apparatus including a storage medium having computer-readable and / or computer-executable instructions that are configured to, when executed by a controller apparatus or a processor apparatus, cause thecontroller apparatus, the processor apparatus, or the computerized apparatus or system to perform the operations. In some cases, the controller apparatus or the processor apparatus may be one example of the computerized apparatus or system. A process chamber may be another example or component of the computerized apparatus or system. Example components of above apparatus are illustrated in, e.g., FIGS. 12 - 16, and described in more detail elsewhere herein.

[0144] It should also be noted that the operations of FIG. 10 may be performed in any suitable order, not necessarily the order depicted in FIG. 10. Further, the process shown in FIG. 10 may include additional or fewer operations than those depicted in FIG. 10.

[0145] At block 1010, the method 1000 may include obtaining a frontside profile associated with a frontside of the semiconductor substrate, the frontside profile being representative of warpage associated with the semiconductor substrate, overlay error associated with the semiconductor substrate, or both. In some embodiments, the obtaining of the frontside profile associated with the frontside of the semiconductor substrate may include using a metrology process to measure a topography of the frontside. Various example metrology processes are discussed above. In some cases, the frontside profile may be obtained from a storage, where the frontside profile may have been determined using a prior process (e.g., a prior metrology process), or may be retrievable or provided as known information.

[0146] At block 1020, the method 1000 may include determining, based on the frontside profile, a backside profile associated with a backside of the semiconductor substrate. In some implementations, the frontside profile may include (i) at least a first type of stress experienced by the frontside, (ii) a magnitude of stress, (iii) a thickness of a frontside film, or a combination thereof, each varying spatially with respect to the frontside of the semiconductor substrate; and the backside profile may include (i) at least a second type of stress opposing the first type of stress, (ii) a magnitude of stress, (iii) a thickness of the backside film, or a combination thereof, each varying spatially with respect to the backside of the semiconductor substrate and each to be induced to the backside during the modifying of the stress. In some cases, the frontside profile may be a frontside stress profile, such as example frontside profile 800, and the backside profile may be a backside stress profile, such as example backside profile 810. In different implementations, various other types of representations that are apparent and useful to those having ordinary skill in the relevant arts may be used.

[0147] In some implementations, an average magnitude of stress induced by the backside film may be within a prescribed range of an average magnitude of stress of the frontside of the semiconductor substrate, so as to contribute to the reduction of the distortion, such as warpage or overlay error. For example, the average magnitudes of stress may be within some percentage (e.g.,within 10%, 6%, 5%, 2%, 1%) or an amount (e.g., 0.05 GPa, 0.02 GPa, 0.01 GPa). The distortion or warpage of the semiconductor substrate may include an in-plane distortion (IPD) of the semiconductor substrate caused by the type of stress and the magnitude of stress, a bow of the semiconductor substrate, or a combination thereof.

[0148] In some implementations, the first type of stress experienced by the frontside may include a compressive stress, and the second type of stress experienced by the backside film at a corresponding location of the semiconductor substrate may include a tensile stress. In some implementations, the first type of stress experienced by the frontside may include a tensile stress, and the second type of stress experienced by the backside film at a corresponding location of the semiconductor substrate may include a compressive stress.

[0149] Optionally, at block 1030, the method 1000 may include depositing a backside film on the backside of the semiconductor substrate. As noted above, in some cases, a backside film may already exist on the backside of the semiconductor substrate. Hence, deposition of the backside film may not be needed prior to the modifying of backside film stress (e.g., according to block 1040), e.g., where there is preexisting backside film. Omission of deposition of the backside film prior to modifying the backside film stress need not, however, preclude deposition of additional backside film(s) as discussed above (e.g., according to block 962) and embodiments described below. In some embodiments, the backside film may be deposited directly to the backside of the semiconductor substrate using backside deposition apparatus and techniques described elsewhere herein, including with respect to FIGS. 12 - 16 and APPJ-based deposition. In some embodiments, the backside film may include a silicon-based film, a carbon-based film, a tungsten-based film, a titanium-based film, an aluminum-based film, or a boron-based film. In specific embodiments, the backside film may include silicon nitride, silicon oxide, or amorphous silicon.

[0150] At block 1040, the method 1000 may include modifying a stress associated with at least portions of a backside film according to the backside profile, wherein the modifying of the stress associated with the at least portions compensates for at least a portion of the warpage, at least a portion of the overlay error, or both (which may include IPD overlay error and / or wafer bow). In some embodiments, the modifying of the stress associated with the at least portions of the film may include applying an annealing process, a raster process, or a combination thereof, to the at least portions of the backside film. In some embodiments, the modifying the stress associated with the at least portions of the film may include selective deposition of a mask over the backside film, patterning of the backside film, ion implantation on the backside film, wet cleaning of at least a portion of the backside film, direct deposition of material at a specific location over the backside film, laser ablation to remove at least a portion of material, or a combination thereof.

[0151] In some embodiments, the method 1000 may further include modifying a thickness of at least portions of the film using an etch process, a film deposition process, or a combination thereof. In some implementations, the etch process may include removing a portion of the backside film to create a spatial discontinuity in the backside film, and to reduce the thickness at the portion of the backside film toward zero. For example, the thickness at the portion of the backside film may be zero (no film whatsoever) or have a minimal amount of backside film such that the thickness may be close to zero (e.g., under 20 angstroms or under 10 angstroms thick).

[0152] In some embodiments, the method 1000 may further include, subsequent to the modifying of the stress associated with the at least portions of the backside film, depositing at least one additional backside film; and the at least one additional backside film may further contribute to the reduction of the distortion, such as warpage or overlay error.

[0153] FIG. 11 is a flow diagram of an example method 1100 for mitigating distortion associated with a semiconductor substrate, according to some embodiments. Structure for performing the functionality illustrated in one or more of the blocks shown in FIG. 11 may include a computerized apparatus or system, such as a deposition apparatus or deposition tool configured to perform deposition of material (e.g., film) on a substrate. One or more of the functions of the method 1100 may be performed at least in part by or caused at least in part by hardware and / or software components of such computerized apparatus or system, such as, for example, a controller apparatus (which may include one or more controllers) and / or a computer-readable apparatus including a storage medium having computer-readable and / or computer-executable instructions that are configured to, when executed by a controller apparatus or a processor apparatus, cause the controller apparatus, the processor apparatus, or the computerized apparatus or system to perform the operations. In some cases, the controller apparatus or the processor apparatus may be one example of the computerized apparatus or system. A process chamber may be another example or component of the computerized apparatus or system. Example components of above apparatus are illustrated in, e.g., FIGS. 12 - 16, and described in more detail elsewhere herein.

[0154] It should also be noted that the operations of FIG. 11 may be performed in any suitable order, not necessarily the order depicted in FIG. 11. Further, the process shown in FIG. 11 may include additional or fewer operations than those depicted in FIG. 11.

[0155] At block 1110, the method 1100 may include depositing a backside film on a backside of the semiconductor substrate, the deposited backside film having a stress that is spatially uniform. In some embodiments, the backside film may be deposited directly to the backside of the semiconductor substrate using backside deposition apparatus and techniques described elsewhere herein, including with respect to FIGS. 12 - 16 and APPJ-based deposition. In some embodiments,the deposited backside film may include a silicon-based film, a carbon-based film, a tungsten- based film, a titanium-based film, an aluminum-based film, or a boron-based film. In specific embodiments, the deposited backside film may include silicon nitride, silicon oxide, or amorphous silicon.

[0156] In some approaches, the uniform backside film may have the same thickness or average thickness of a frontside film disposed on the semiconductor substrate.

[0157] At block 1120, the method 1100 may include tuning a stress of at least a portion of the deposited backside film according to a backside profile associated with a backside of the semiconductor substrate, the backside profile determined based on a frontside profile associated with a frontside of the semiconductor substrate. In some embodiments, the tuning of the stress may contribute to reduction of the warpage, IPD, overlay error, and / or wafer bow.

[0158] In some embodiments, the tuning of the stress may include applying an annealing process, a raster process, or a combination thereof, to the at least portions of the deposited backside film. In some embodiments, the tuning of the stress may include selective deposition of a mask over the deposited backside film, patterning of the deposited backside film, ion implantation on the deposited backside film, wet cleaning of at least a portion of the deposited backside film, direct deposition of material at a specific location over the deposited backside film, laser ablation to remove at least a portion of material, or a combination thereof.

[0159] In some cases, the frontside profile may be a frontside stress profile, such as example frontside profile 800, and the backside profile may be a backside stress profile, such as example backside profile 810.

[0160] In some embodiments, the method 1100 may further include, tuning a thickness of at least portions of the backside film using an etch process, a film deposition process, or a combination thereof. In some implementations, the etch process may include removing a portion of the backside film to create a spatial discontinuity in the backside film, and to reduce the thickness at the portion of the backside film toward zero. For example, the thickness at the portion of the backside film may be zero (no film whatsoever) or have a minimal amount of backside film such that the thickness may be close to zero (e.g., under 20 angstroms or under 10 angstroms thick).

[0161] In some embodiments, the method 1100 may further include, subsequent to the tuning of the stress, depositing at least one additional backside film; and the at least one additional backside film may further contribute to reduction of the distortion, such as warpage, IPD, overlay error, or wafer bow.Apparatus

[0162] In some embodiments, FIG. 12 is a block diagram that illustrates a substrate processing system 1200 used to perform processing on a semiconductor substrate 1202 (also referred to herein as a wafer), according to some embodiments. As shown, the substrate processing system 1200 may include a chamber 1234. A center column may be configured to support a pedestal for when a top surface of the semiconductor substrate 1202 is being processed, e.g., a film is being formed on the top surface of the semiconductor substrate 1202, or on the backside of the semiconductor substrate 1202. The pedestal, in accordance with some embodiments disclosed herein, may be referred to as a showerhead-pedestal (“ShoPed”) 1206. A showerhead 1236 may be disposed over the ShoPed 1206.

[0163] In some embodiments, the showerhead 1236 may be electrically coupled to power supply 1238 via a match network 1240. The power supply 1238 may be controlled by a control module 1242, e.g., a controller. In some embodiments, power may be provided to the ShoPed 1206 instead of the showerhead 1236. The control module 1242 may be configured to operate the substrate processing system 1200 by executing process input and control for specific process recipes. Depending on whether the top surface of the semiconductor substrate 1202 is receiving a deposited layer or layer stack or the bottom surface of the semiconductor substrate 1202 is receiving a deposited layer or layer stack, the controller module 1242 may set various operational inputs for a process recipe, such as power levels, timing parameters, process gasses, mechanical movement of a semiconductor substrate 1202, and / or the height of the semiconductor substrate 1202 relative to the ShoPed 1206.

[0164] In some embodiments, the center column may also include lift pins, which are controlled by a lift pin control. Such lift pins may be used to raise the semiconductor substrate 1202 from the ShoPed 1206 to allow an end effector (not shown) to pick the wafer and to lower the semiconductor substrate 1202 after being placed by the end effector. The end effector may also place the semiconductor substrate 1202 over spacers 1244. As will be described below, the spacers 1244 may be sized to provide a controlled separation of the semiconductor substrate 1202 between a top surface of the showerhead 1236 (facing the wafer) and a top surface of the ShoPed 1206 (facing the wafer).

[0165] In some embodiments, the substrate processing system 1232 may further include a first gas manifold 1246 that is connected to first gas sources 1248, e.g., gas chemistry supplies from a facility and / or inert gases. Depending on the processing being performed over a top surface of the semiconductor substrate 1202, the control module 1242 may controls the delivery of first gas sources 1248 via the first gas manifold 1246. The chosen gases may then be flown into theshowerhead 1236 and distributed in a space volume defined between a face of the showerhead 1236 that faces that semiconductor substrate 1202 when the wafer is resting over the pedestal.

[0166] In some embodiments, the substrate processing system 1232 may further include a second gas manifold 1250 that is connected to second gas sources 1252, e.g., gas chemistry supplies from a facility and / or inert gases. Depending on the processing being performed over a bottom surface of the semiconductor substrate 1202, the control module 1242 may control the delivery of second gas sources 1252 via the second gas manifold 1250. The chosen gases may then be flown into the showerhead 1236 and distributed in a space volume defined between a face of the ShoPed 1206 that faces an under surface or under side (e.g., backside) of the semiconductor substrate 1202 when the wafer is resting over the spacers 1244. The spacers 1244 may provide for a separation that optimizes deposition to the under surface of the semiconductor substrate 1202, while reducing deposition over the top surface of the semiconductor substrate 1202. In some embodiments, while deposition is targeted for the under surface of the semiconductor substrate 1202, an inert gas may be flown over the top surface of the semiconductor substrate 1202 via the showerhead 1236, which may push reactant gases away from the top surface and enable reactant gases provided from the ShoPed 1206 to be directed to the under surface of the semiconductor substrate 1202.

[0167] In some embodiments, either showerhead 1236 or ShoPed 1206 may have a zonal deposition design similar to that shown in FIG. 17A. For example, gas manifold 1250 may be fluidically linked to control the delivery of gases to either zones 1702 or zone 1704. By controlling the flow of gases to either zones 1702 or zone 1704 films may be deposited as shown in FIGS. 17B and 17C.

[0168] Further, the gases may be premixed or not. Appropriate valving and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. Process gases may exit the chamber 1234 via an outlet. A vacuum pump (e.g., a one or two stage mechanical dry pump and / or a turbomolecular pump) may draw process gases out and maintains a suitably low pressure within the reactor by a close loop-controlled flow restriction device, such as a throttle valve or a pendulum valve.

[0169] In some embodiments, a carrier ring 1254 may encircle an outer region of the ShoPed 1206. When the top surface of the semiconductor substrate 1202 is being processed, e.g., a material is being deposited thereon, the carrier ring 1254 may be configured to sit over a carrier ring support region that is a step down from a wafer support region in the center of the ShoPed 1206. The top surface of the carrier ring 1254 is generally coplanar with the top surface of the semiconductor substrate 1202. The carrier ring 1254 may include an outer edge side of its disk structure, e.g.,outer radius, and a wafer edge side of its disk structure, e.g., inner radius, that is closest to where the semiconductor substrate 1202 sits. The carrier ring 1254 may be associated with an inner diameter (ID). The inner diameter may extend to an inner perimeter of the carrier ring and generally surround a substrate (e.g., semiconductor substrate 1202) in a processing chamber. The wafer edge side of the carrier ring 1254 may also include a plurality of contact support structures or “tabs” which may be configured to lift the semiconductor substrate 1202 when the carrier ring 1254 is held by the spacers 1244. The carrier ring 1254 may include a plurality of tabs with a quantity selected from a range to support the semiconductor substrate 1202 during processing. Additional details regarding embodiments of the tabs will follow.

[0170] FIG. 13 is a block diagram that illustrates another substrate processing system 1300 used to perform processing on a semiconductor substrate 1302 (also referred to herein as a wafer), according to some embodiments. In some embodiments, spider forks 1356 may be used to lift and maintain the carrier ring 1354 in its process height, e.g., to allow depositing in the under surface (backside) of the semiconductor substrate 1302. The carrier ring 1354 may therefore be lifted along with the semiconductor substrate 1302. In some implementations, the carrier ring 1354 may be rotated to another station, e.g., in a multi-station system.

[0171] Broadly speaking, the embodiments disclosed herein are for a system to deposit PECVD films on the selective side of the wafer (front and / or back) with dynamic control. Some embodiments may include a dual gas-flowing electrode for defining a capacitively-coupled PECVD system. The system may include a gas-flowing showerhead (e.g., showerhead 1336) and a ShoPed 1306. In some embodiments, the gas-flowing pedestal (i.e., ShoPed) is a combination showerhead and pedestal, which enables deposition on a back-side of the wafer. The electrode geometry combines features of a showerhead, e.g., a gas mixing plenum, holes, hole-pattern, gas jet preventing baffle, and features of a pedestal. Examples of features of a pedestal include an embedded controlled heater, wafer-lift mechanisms, ability to hold plasma suppression rings, and movability. This enables the transfer of wafers and the processing of gasses with or without RF power from the pedestal.

[0172] In some embodiments, the system may have a wafer lift mechanism that tightly controls parallelism of the substrates against the electrodes. In one example, this may be achieved by setting up the lift mechanism parallel to the two electrodes and controlling manufacturing tolerances, e.g., spindle or lift pins mechanisms. In another example, the lift may be achieved by raising the wafer lift parts. This option may not allow dynamic control of the side that gets deposited.

[0173] In some configurations, the lift mechanism may allow dynamically controlling the substrate position during processing (before plasma, during plasma, after plasma) to control theside of the deposition, profile of the deposition, and deposition film properties. The system may further allow selective enabling / disabling of the side where reactants are flown. One side can flow the reactant and the other side can flow inert gases to suppress the deposition and plasma.

[0174] In some embodiments, the gap between the side of the wafer that does not need plasma / dep may be tightly controlled. This distance may be controlled to suppress plasma. By not controlling the distance, the wafer may be susceptible to plasma damage. For example, the system may allow a minimal gap from about 2 mm to about 0.5 mm, and in another embodiment from about 1 mm to about .05 (limited by the wafer bow), and such gap can be controlled. The gap maybe controlled depending on process conditions.

[0175] In some embodiments, the gas-flowing pedestal (i.e., ShoPed) may enable, without limitation: (a) thermal stabilization of the wafer to processing temperature prior to processing; (b) selective design of hole patterns on the ShoPed to selectively deposition film in different areas of the back-side of the wafer; (c) swappable rings can be attached to achieve appropriate plasma confinement and hole pattern; (d) stable wafer transfer mechanisms within chamber and for transferring wafer outside to another chamber or cassette - such as lift pins, RF-coupling features, minimum-contact arrays; (e) implement gas mixing features, e.g., such as inner plenum, baffle and manifold lines openings; and (f) add compartments in the gas-flowing pedestal (i.e., ShoPed) to enable selective gas flow to different regions of the back side of the wafer and control flow rates via flow controllers and / or multiple plenums.

[0176] In another embodiment, dynamic gap control using wafer lift mechanism enables: (a) control of the distance from deposition or reactant flowing electrode to the side of the wafer that needs deposition or in the middle so that both sides can be deposited; and (b) the lift mechanism to control the distance dynamically during the process (before plasma, during plasma, after plasma) to control the side of the deposition, profile of the deposition, and deposition film properties. In another embodiment, for a deposition mode used to deposit on the backside of the wafer, film edge exclusion control is highly desirable to avoid lithography-related overlay problems. The lift mechanism used in this system is done via a carrier ring 1354 that has a design feature to shadow the deposition on the edge. This specifies the edge exclusion control via the design and shape of the carrier ring.

[0177] FIG. 14A shows a cross-sectional view of an edge region of the ShoPed 1406 (e.g., 1206, 1306). This view provides a cross-sectional representation of a carrier ring 1454 (e.g., 1254, 1354), which has a carrier ring inner radius 1454a and a carrier ring outer radius 1454b. In some embodiments, the carrier ring 1454 includes support extensions 1454c, which extend below the substantial flat surface of the carrier ring 1454.

[0178] The support extensions 1454c are configured to mate and sit within support surfaces defined into a top surface of the spacers 1444. The support surfaces provide a complementary mating surface for the support extensions 1454c, such that the carrier ring 1454 is prevented from sliding or moving when supported by the spacers 1444. Although three spacers are shown as spacers 1444 are shown in FIG. 14, it is envisioned that any number of spacers may be provided, so long as the carrier ring can be supported substantially parallel to the surface of the ShoPed 1406, and spacing is defined for supporting semiconductor substrate 1402 at a spaced apart relationship from a top surface of the ShoPed 1406.

[0179] Further shown is that a top surface of the ShoPed 1406 will include a hole pattern 1406a that is distributed throughout the surface to provide even distribution and output of gases during operation. In one embodiment, the hole pattern 1406a is distributed in a plurality of concentric rings that start at the center of the top surface of the ShoPed 1406 and extend to an outer periphery of the ShoPed 1406. At least one hole pattern 1406a is provided at an edge hole region 1407 of the hole pattern, and orifices defined in the edge hole region 1407 are preferably angled to provide gases non-perpendicular to the surface of the ShoPed 1406.

[0180] In one example, the angle or tilt at which the orifices in the edge hole region 1407 is defined to tilt or angle away from the center of the ShoPed 1406. In one embodiment, the angle is approximately 45° from horizontal. In other embodiments, the angle can vary between 20° from horizontal to about 80° from horizontal. In one embodiment, by providing the angled orifices in the edge hole region 1407, additional distribution of process gases can be provided during backside deposition of the semiconductor substrate 1402. In one embodiment, the remainder orifices 1406d of the hole pattern 1406a are oriented substantially perpendicular to the surface of the ShoPed 1406 and directed toward the underside of the semiconductor substrate 1402.

[0181] FIG. 14B illustrates that when the semiconductor substrate 1402 is held by the carrier ring 1454, the semiconductor substrate 1402 edge will sit on an edge region closer to the carrier ring inner radius 1454a of the carrier ring 1454. The surface of the showerhead 1436 facing the top surface of the semiconductor substrate 1402, when positioned using spacers 1444, may be substantially close to prevent deposition during a mode where deposition is being carried out to the backside of the semiconductor substrate 1402.

[0182] By way of example, the distance between the top of the semiconductor substrate 1402 and the surface of the showerhead 1436 is preferably between about 2 mm to about .5 mm, and in some embodiments about 1 mm to about .5 mm, depending on the wafer bow. That is, if the wafer is bowed substantially, the separation will be about .5 mm or larger. If the wafer is not yet bowed substantially, the separation can be less than about .5 mm. In one embodiment, it is preferable thatthe separation be minimized to prevent deposition on the top side of the substrate when the backside of the substrate is being deposited with a layer of material. In some embodiments, the showerhead 1436 is configured to supply an inert gas flow over the top side of the semiconductor substrate 1402 during when the backside of the substrate is being deposited and deposition gases are being supplied by the ShoPed 1406.

[0183] Any suitable chamber may be used to implement the disclosed embodiments. Example deposition apparatuses include various systems, e.g., ALTUS® and ALTUS® Max, available from Lam Research Corp., of Fremont, California, or any of a variety of other commercially available processing systems.

[0184] FIG. 15 is a diagram of a cross-sectional view of a processing system 1500 for depositing film on a semiconductor substrate, according to some embodiments herein. In some embodiments, the processing system 1500 may include a showerhead 1502, a shower-pedestal (ShoPed) 1504, one or more support structures 1506 (e.g., a carrier ring 1254, 1354, 1454 and / or tabs of a carrier ring, or spider forks 1356). The one or more support structures 1506 may be configured to support a semiconductor substrate 1520. In some implementations, the one or more support structures 1506 may be coupled to the ShoPed 1504 and / or other structures associated with the processing system 1500, e.g., processing chamber wall(s). In some implementations, electrostatic chucking (e.g., biopolar chucking or monopolar chucking) may be used to further secure the semiconductor substrate 1520.

[0185] In some embodiments, the showerhead 1502 may include an electrode 1510 operable by providing RF power to a plurality of zones. For example, there may be two distinct zones configured to receive different amounts of RF power at different or substantially concurrent times. In another example, there may be three distinct zones. In other examples, there may be four or more. The RF power provided to two or more (or in some cases all) of the zones may be the same amount.

[0186] In some implementations, the electrode 1510 may be integrated or embedded into the showerhead 1502. The electrode 1510 may have a specific configuration of zones according to wafer bow and / or other requirements. Examples of zones are discussed above. In certain implementations, however, the electrode 1510 may be a distinct component that may be replaced and installed into the showerhead 1502 without breaking the showerhead 1502. Such interchangeable electrodes may be useful for performing different customized backside film deposition of the type discussed in the present disclosure. For instance, an electrode having three zones may be swapped for one having two zones to correct different types of wafer bow.

[0187] In some embodiments, the ShoPed 1504 may have one or more gas inlets 1505 configured to transport and emit process gas 1507. Examples of process gas 1507 may include silane (Si H4), nitrous oxide (N2O), and / or ammonia (NH3). Inert carrier gases (e.g., argon, neon, or helium) may also be transported through and out of the ShoPed 1504. In some cases, a mixture of process gas and carrier gas may be routed through the showerhead 1502 and emitted therefrom. Different types of film material may be deposited on the semiconductor substrate 1520 based on the type of process gas. The showerhead 1502 may have one or more gas inlets 1503 configured to receive and disperse purge gas 1508, such as nitrogen. Purge gas 1508 flowing along the top or front side of the semiconductor substrate 1520 may be used to prevent the process gas 1507 from the ShoPed 1504 or impurities from reaching the top or front side of the semiconductor substrate 1520.

[0188] In some embodiments, the semiconductor substrate 1520 may be placed and supported at a position that is closer to the showerhead 1502 than to the ShoPed 1504. In example implementation, the distance of the gap 1512 between the showerhead 1502 and the semiconductor substrate 1520 may be about 1 mm, while the distance of the gap 1514 between the ShoPed 1504 and the semiconductor substrate 1520 may be about 12 mm. Various distances may be used. However, it is notable and useful that the gap 1512 is small (e.g., small enough to not allow a plasma to form) and could be much smaller than the gap 1514. This is to prevent plasma 1515 from developing between the showerhead 1502 and the semiconductor substrate 1520 where the front side of the semiconductor substrate 1520 is. That is, the plasma 1515 is encouraged to form at the backside 1525 of the semiconductor substrate 1520, where the backside faces away from the showerhead 1502 and the electrode 1510, and faces toward the ShoPed 1504 and / or support structures 1506. The front side may have sensitive and expensive features (transistors, memory cells, wiring lines, etc.). In some implementations, a flowing purge gas out of holes in the showerhead 1502 may push away any process gas or precursor that might have been left or transported to the front side.

[0189] As already discussed herein, by specifying the amount of RF power provided to different zones of the electrode 1510, and at different times in some implementations, film material having properties varying spatially across the semiconductor substrate 1520 may be formed. Some examples of film properties include internal stress (e.g., tensile stress or a compressive stress) and film thickness.

[0190] FIG. 16 is a schematic of a process system suitable for conducting deposition processes, such as frontside deposition processes, in accordance with embodiments. The system 1600 includes a transfer module 1603. The transfer module 1603 provides a clean, pressurizedenvironment to minimize risk of contamination of substrates being processed as they are moved between various reactor modules. Mounted on the transfer module 1603 is a multi-station reactor 1609 capable of performing ALD, treatment, and CVD according to various embodiments. Multistation reactor 1609 may include multiple stations 1611, 1613, 1615, and 1617 that may sequentially perform operations in accordance with disclosed embodiments. Stations may include a heated pedestal or substrate support, one or more gas inlets or showerhead or dispersion plate.

[0191] Mounted on the transfer module 1603 may be one or more single or multi-station modules 1607 capable of performing plasma or chemical (non-plasma) pre-cleans, other deposition operations, or etch operations. The module may also be used for various treatments to, for example, prepare a substrate for a deposition process. The system 1600 also includes one or more wafer source modules 1601, where wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 1619 may first remove wafers from the wafer source modules 1601 to loadlocks 1621. A wafer transfer device (generally a robot arm unit) in the transfer module 1603 moves the wafers from loadlocks 1621 to and among the modules mounted on the transfer module 1603.

[0192] In various embodiments, a system controller 1642 is employed to control process conditions during deposition. The system controller 1642 will typically include one or more memory devices and one or more processors. A processor may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0193] The system controller 1642 may control all the activities of the deposition apparatus. The system controller 1642 executes system control software, including sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters of a particular process. Other computer programs stored on memory devices associated with the system controller 1642 may be employed in some embodiments.

[0194] The depicted embodiment includes a user interface associated with the system controller 1642. The user interface may include a display screen, graphical software displays of the apparatus and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0195] System control logic may be configured in any suitable way. In general, the logic can be designed or configured in hardware and / or software. The instructions for controlling the drive circuitry may be hard coded or provided as software. The instructions may be provided by “programming.” Such programming is understood to include logic of any form, including hard coded logic in digital signal processors, application-specific integrated circuits, and other deviceswhich have specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that may be executed on a general-purpose processor. System control software may be coded in any suitable computer readable programming language.

[0196] The computer program code for controlling the processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may be hard coded.

[0197] The controller parameters relate to process conditions, such as, for example, process gas composition and flow rates, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters are provided to the user in the form of a recipe and may be entered utilizing the user interface.

[0198] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 1642. The signals for controlling the process are output on the analog and digital output connections of the system 1600.

[0199] The system software may be designed or configured in different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the deposition processes in accordance with the disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0200] In some implementations, a system controller 1642 is part of a system, which may be part of the above -described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The system controller 1642, depending on the processing requirements and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional andoperation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0201] Anisotropic internal stress may be accomplished by depositing curved bar profile and curved channel profile films. FIGS. 17A - 17C illustrate curved bar and curved channel profile films. FIG. 17A is a top-side view of a semiconductor substrate (wafer) 1706 having a center zone 1704 and edge zones 1702. FIGS. 17B and 17C present a side view and exploded side view, respectively, along the x dimension of the wafer 1706 having a curved bar profile film 1708 and a curved channel profile film 1707. A film may be deposited such that the film is substantially deposited in either center zone 1704 or edge zones 1702. A film deposited substantially in center zone 1704 will have curved bar profile 1708, while a film deposited substantially in edge zones 1702 will have curved channel profile 1707. While films may be deposited substantially in either center zone 1704 or edge zones 1702, it should be understood that some deposition may occur across the wafer and in the other zone. Furthermore , the shapes of the curved bar profile and curved channel profile are mere examples and variations in profile shape may occur. In some embodiments, center zone 1704 may also be referred to as a curved bar profile deposition zone. In some embodiments, edge zones 1702 may also be referred to as a curved channel profile deposition zone.

[0202] The curved bar profile film 1708 has a decreasing thickness along an x dimension from center to edge of wafer 1706 and a uniform thickness along a y dimension of the wafer. Conversely, the curved channel profile film 1707 has an increasing thickness along the x dimension from center to edge of wafer 1706 and a uniform thickness along a y dimension of the wafer. Together, curved bar profile film 1708 and curved channel profile film 1707 may form a uniform profile film that is substantially flat.

[0203] As film 1707 and film 1708 are deposited independently, each film may be deposited under conditions to have a different internal stress. For example, curved bar profile film 1708 may have a compressive internal stress, while curved channel profile film 1707 may have a tensile internal stress. As film stresses may be superimposed, the stacked film may have a compressive internal stress in areas of the film having a small x / large y coordinate, i.e., corresponding to center zone 1704, while the stacked film also has a tensile internal stress in areas of the film having a large x / small y coordinate, i.e., coordinating to edge zones 1702.

[0204] While films 1707 and 1708 are discussed herein as having opposite types of internal stress, e.g., one film has a compressive internal stress and the other film has a tensile internal stress, in some embodiments both films may have a tensile or compressive internal stress, but different magnitudes of internal stress. This may address wafers that have different magnitudes of x-bowand y-bow even if the both bows are positive or negative. In some embodiments depositing same type stress films may increase throughput.System Controllers

[0205] Broadly speaking, a controller may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. Such controller may be used in or with any of the apparatus described herein. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0206] A system controller may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, a system controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or moreintegrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0207] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a CVD chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0208] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0209] A system controller may include various programs. A substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber such as a gas inlet and / or target. A process gas control program may include code for controlling gas composition, flow rates, pulse times, and optionally for flowing gas into the chamber prior to deposition in order to stabilize the pressure in the chamber. A pressure control program may include code for controlling the pressure in the chamber by regulating, e.g., a throttle valve in the exhaust system of the chamber. A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas such as helium to the wafer chuck.

[0210] Examples of chamber sensors that may be monitored during deposition include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain desired process conditions.

[0211] The foregoing describes implementation of disclosed embodiments in a single or multichamber semiconductor processing tool. The apparatus and process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like.Typically, though not necessarily, such tools / processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following steps, each step provided with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

[0212] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Embodiments disclosed herein may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. Further, while the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that the specific embodiments are not intended to limit the disclosed embodiments. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

CLAIMSWhat is claimed is:

1. A method of mitigating distortion associated with a semiconductor substrate, the method comprising: obtaining a frontside profile associated with a frontside of the semiconductor substrate, the frontside profile being representative of warpage associated with the semiconductor substrate, overlay error associated with the semiconductor substrate, or both; determining, based on the frontside profile, a backside profile associated with a backside of the semiconductor substrate; and modifying a stress associated with at least portions of a backside film according to the backside profile, wherein the modifying of the stress associated with the at least portions compensates for at least a portion of the warpage, at least a portion of the overlay error, or both.

2. The method of claim 1, wherein the modifying of the stress associated with the at least portions of the film comprises applying an annealing process, a raster process, or a combination thereof, to the at least portions of the backside film.

3. The method of claim 1, wherein the modifying of the stress associated with the at least portions of the film comprises selective deposition of a mask over the backside film, patterning of the backside film, ion implantation on the backside film, wet cleaning of at least a portion of the backside film, direct deposition of material at a specific location over the backside film, laser ablation to remove at least a portion of material, or a combination thereof.

4. The method of claim 1, wherein: the frontside profile comprises (i) at least a first type of stress experienced by the frontside, (ii) a magnitude of stress, (iii) a thickness of a frontside film, or a combination thereof, each varying spatially with respect to the frontside of the semiconductor substrate; and the backside profile comprises (i) at least a second type of stress opposing the first type of stress, (ii) a magnitude of stress, (iii) a thickness of the backside film, or a combination thereof, each varying spatially with respect to the backside of the semiconductor substrate and each to be induced to the backside during the modifying of the stress.

5. The method of claim 4, wherein an average magnitude of stress induced by the backside film is within a prescribed range of an average magnitude of stress of the frontside of the semiconductor substrate, so as to compensate for at least the portion of the warpage, at least the portion of the overlay error, or both.

6. The method of claim 5, wherein the warpage of the semiconductor substrate comprises an in-plane distortion (IPD) of the semiconductor substrate caused by the type of stress and the magnitude of stress, a bow of the semiconductor substrate, or a combination thereof.

7. The method of claim 4, wherein the first type of stress experienced by the frontside comprises a compressive stress, and the second type of stress experienced by the backside film at a corresponding location of the semiconductor substrate comprises a tensile stress.

8. The method of claim 4, wherein the first type of stress experienced by the frontside comprises a tensile stress, and the second type of stress experienced by the backside film at a corresponding location of the semiconductor substrate comprises a compressive stress.

9. The method of claim 1, wherein the obtaining of the frontside profile associated with the frontside of the semiconductor substrate comprises using a metrology process to measure a topography of the frontside.

10. The method of claim 1, further comprising modifying a thickness of at least portions of the backside film using an etch process, a film deposition process, or a combination thereof.

11. The method of claim 10, wherein the etch process comprises removing a portion of the backside film to create a spatial discontinuity in the backside film, and to reduce the thickness at the portion of the backside film toward zero.

12. The method of claim 1, further comprising depositing a backside film on the backside of the semiconductor substrate.

13. The method of claim 1, further comprising, subsequent to the modifying of the stress associated with the at least portions of the backside film, depositing at least one additional backside film; wherein the at least one additional backside film further compensates for at least the portion of the warpage, at least the portion of the overlay error, or both.

14. The method of claim 1, wherein the backside film comprises a silicon-based film, a carbon-based film, a tungsten-based film, a titanium-based film, an aluminum-based film, or a boron-based film.

15. The method of claim 1, wherein the backside film comprises silicon nitride, silicon oxide, or amorphous silicon.

16. A method of mitigating distortion associated with a semiconductor substrate, the method comprising: depositing a backside film on a backside of the semiconductor substrate, the deposited backside film having a stress that is spatially uniform; and tuning a stress of at least a portion of the deposited backside film according to a backside profile associated with a backside of the semiconductor substrate, the backside profile determined based on a frontside profile associated with a frontside of the semiconductor substrate.

17. The method of claim 16, wherein the tuning of the stress comprises applying an annealing process, a raster process, or a combination thereof, to the at least portion of the deposited backside film.

18. The method of claim 16, wherein the deposited backside film comprises silicon nitride, silicon oxide, or amorphous silicon.

19. The method of claim 16, wherein: the frontside profile comprises (i) at least a first type of stress experienced by the frontside, (ii) a magnitude of stress, (iii) a thickness of a frontside film, or a combination thereof, each varying spatially with respect to the frontside of the semiconductor substrate; and the backside profile comprises (i) at least a second type of stress opposing the first type of stress, (ii) a magnitude of stress, (iii) a thickness of the backside film, or a combination thereof,each varying spatially with respect to the backside of the semiconductor substrate and each to be induced to the backside during the modifying of the stress.

20. The method of claim 16, further comprising tuning a thickness of at least portions of the backside film using an etch process, a film deposition process, or a combination thereof.

21. A processing apparatus comprising: a showerhead configured to deliver at least one process gas to a backside of a semiconductor substrate; and a controller apparatus communicatively coupled to at least the showerhead and configured to cause the processing apparatus to: obtain a frontside profile associated with a frontside of the semiconductor substrate, the frontside profile being representative of warpage associated with the semiconductor substrate, overlay error associated with the semiconductor substrate, or both; determine, based on the frontside profile, a backside profile associated with a backside of the semiconductor substrate; and modify a stress associated with at least portions of the deposited backside film according to the backside profile, wherein the modification of the stress associated with the at least portions compensates for at least a portion of the warpage, at least a portion of the overlay error, or both.

22. The processing apparatus of claim 21, wherein the controller apparatus is further configured to cause the processing apparatus to deposit a backside film on the backside of the semiconductor substrate.

23. The processing apparatus of claim 21, wherein the backside film comprises silicon nitride, silicon oxide, or amorphous silicon.

24. The processing apparatus of claim 21, wherein the modification of the stress associated with the at least portions of the film comprises applying an annealing process, a raster process, or a combination thereof, to the at least portions of the backside film.

25. The processing apparatus of claim 21, wherein the modification of the stress associated with the at least portions of the film comprises selective deposition of a mask over thebackside film, patterning of the backside film, ion implantation on the backside film, wet cleaning of at least a portion of the backside film, direct deposition of material at a specific location over the backside film, laser ablation to remove at least a portion of material, or a combination thereof.

26. The processing apparatus of claim 21 , wherein the controller apparatus is further configured to cause the processing apparatus to modify a thickness of at least portions of the backside film using an etch process, a film deposition process, or a combination thereof.

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