Member for semiconductor manufacturing device

Abstract

Provided is a member for a semiconductor manufacturing device capable of suppressing generation of particles. This member for a semiconductor manufacturing device includes a ceramic substrate that has an upper surface having a plurality of projections for mounting a wafer, and a side wall forming an outer edge of the upper surface. An arithmetic average roughness Ra1 of a surface of the side wall is 0.4 μm or less.

Description

Semiconductor manufacturing equipment components

[0001] The present invention relates to a member for a semiconductor manufacturing device.

[0002] Conventionally, semiconductor manufacturing equipment components have been known that are used for holding wafers, controlling their temperature, transporting them, etc. These types of semiconductor manufacturing equipment components are also called wafer mounting tables, electrostatic chucks, susceptors, etc., and generally have the function of applying electrostatic attraction power to a built-in electrode to attract the wafer by electrostatic force, and some are also known to have the function of controlling the wafer temperature by flowing gas between the wafer mounting surface and the wafer to be attracted.

[0003] A semiconductor manufacturing equipment component generally includes a ceramic substrate having an upper surface on which a wafer can be placed. The upper surface is provided with a plurality of protrusions for supporting the wafer. The ceramic substrate may also have a sidewall that forms the outer edge of the upper surface on which the wafer can be placed. Furthermore, the ceramic substrate may also have an upper surface on which a focus ring, which is located on the outer periphery of the upper surface but lower than the upper surface, can be placed for the purpose of uniformly processing the wafer within its surface (see Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2023-27641

[0005] The top and side surfaces of ceramic substrates are exposed to the plasma and are susceptible to plasma during wafer processing, which can cause ceramic particles that compose the sidewalls to fall off. Furthermore, fluorination of alumina by fluorine-based corrosive gases can also cause ceramic particles to fall off. Even when a focus ring is mounted, a gap is often provided between the focus ring and the wafer to prevent the focus ring from interfering with the wafer. Because the sidewalls that form the step between the top surface on which the wafer can be placed and the top surface on which the focus ring can be placed are exposed to the plasma in this gap, they are subject to the plasma and corrosive gases during wafer processing. When ceramic particles fall off, they adhere to the wafer as particles, potentially affecting semiconductor quality and reducing yields.

[0006] Therefore, in one embodiment, an object of the present invention is to provide a semiconductor manufacturing equipment component including a ceramic substrate having an upper surface on which a wafer can be placed and a sidewall forming the outer edge of the upper surface, wherein the semiconductor manufacturing equipment component is capable of suppressing particle generation. In another embodiment, an object of the present invention is to provide a semiconductor manufacturing equipment component including a ceramic substrate having an upper surface on which a wafer can be placed, an upper surface on which a focus ring can be placed, and a sidewall forming a step between the upper surface and the focus ring, wherein the semiconductor manufacturing equipment component is capable of suppressing particle generation.

[0007] The present inventors have conducted extensive research to solve the above problems and have created the present invention, which is exemplified below.

[0008] [Aspect 1] A semiconductor manufacturing equipment member comprising a ceramic substrate having an upper surface with a plurality of protrusions for mounting a wafer thereon and sidewalls forming the outer edge of the upper surface, wherein the arithmetic mean roughness Ra1 of the surface of the sidewalls is 0.4 μm or less. [Aspect 2] The semiconductor manufacturing equipment member according to Aspect 1, wherein the surface of the sidewalls has a patterned uneven shape. [Aspect 3] The semiconductor manufacturing equipment member according to Aspect 2, wherein the patterned uneven shape is formed by laser processing. [Aspect 4] The semiconductor manufacturing equipment member according to Aspect 2 or 3, wherein the surface of the sidewalls has one or more of the following patterned uneven shapes i) to iv): i) a pattern composed of a plurality of streak-like protrusions, ii) a pattern composed of a plurality of dot-like protrusions, iii) a pattern composed of a plurality of dimples, or iv) a pattern composed of a network-like protrusion in which a plurality of linear protrusions intersect. [Aspect 5] A semiconductor manufacturing equipment member according to any one of Aspects 1 to 4, wherein the upper surface and the side wall are connected via a chamfer, and the arithmetic mean roughness Ra4 of the surface of the chamfer is 0.4 μm or less. [Aspect 6] An arithmetic mean height Sa1 of the surface of the side wall is 1.1 μm or less, and a protruding valley space volume Vvv1 of the surface of the side wall is 0.5 ml / m 2A semiconductor manufacturing equipment member according to any one of Aspects 1 to 5, wherein the arithmetic mean height Sa4 of the surface of the chamfer is 1.1 μm or less, and the protruding valley space volume Vvv4 of the surface of the chamfer is 0.5 ml / m or less. 2 Aspect 8: The semiconductor manufacturing equipment member according to aspect 5, wherein the standard deviation of the arithmetic mean height Sa1 of the side wall surface is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the side wall surface is 0.1 ml / m or less. 2 A semiconductor manufacturing equipment member according to any one of Aspects 1 to 7, wherein the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion is 0.1 ml / m or less. 2The semiconductor manufacturing equipment member according to any one of Aspects 5 or 7, wherein the arithmetic mean roughness Ra1 of the surface of the sidewall is smaller when measured in the circumferential direction of the ceramic substrate than when measured in the thickness direction of the ceramic substrate. [Aspect 11] The semiconductor manufacturing equipment member according to any one of Aspects 1 to 10, wherein at least a portion of the sidewall is covered with a coating layer, and the coating layer has a porosity of 2% or less. [Aspect 12] A semiconductor manufacturing equipment member comprising a ceramic substrate having: a central upper surface having a plurality of protrusions for mounting a wafer; an outer peripheral upper surface that is on the outer periphery of the central upper surface and is positioned lower than the central upper surface; and a central sidewall that forms a step between the central upper surface and the outer peripheral upper surface, wherein the arithmetic mean roughness Ra1 of the surface of the central sidewall is smaller than the arithmetic mean roughness Ra2 of the outer peripheral upper surface. [Aspect 13] The semiconductor manufacturing equipment member according to Aspect 12, wherein the arithmetic mean roughness Ra1 of the surface of the central sidewall is greater than the arithmetic mean roughness Ra3 of the upper end surfaces of the plurality of protrusions. [Aspect 14] The semiconductor manufacturing equipment member according to Aspect 12 or 13, wherein the arithmetic mean roughness Ra1 of the surface of the central sidewall is 0.4 μm or less. [Aspect 15] The semiconductor manufacturing equipment member according to any one of Aspects 12 to 14, wherein the central upper surface and the central sidewall are connected via a chamfered portion. [Aspect 16] The semiconductor manufacturing equipment member according to Aspect 15, wherein the arithmetic mean roughness Ra4 of the surface of the chamfered portion is smaller than the arithmetic mean roughness Ra2 of the upper surface of the outer periphery. [Aspect 17] The semiconductor manufacturing equipment member according to Aspect 15 or 16, wherein the arithmetic mean roughness Ra4 of the surface of the chamfered portion is greater than the arithmetic mean roughness Ra3 of the upper end surfaces of the plurality of protrusions. [Aspect 18] The member for semiconductor manufacturing equipment according to any one of Aspects 15 to 17, wherein the arithmetic mean roughness Ra4 of the surface of the chamfered portion is 0.4 μm or less. [Aspect 19] The member for semiconductor manufacturing equipment according to any one of Aspects 15 to 18, wherein the absolute value of the difference between the arithmetic mean roughness Ra4 of the surface of the chamfered portion and the arithmetic mean roughness Ra1 of the surface of the central side wall is 0.4 μm or less.[Aspect 20] The semiconductor manufacturing equipment member according to any one of Aspects 12 to 19, wherein the surface of the central sidewall has a patterned uneven shape. [Aspect 21] The semiconductor manufacturing equipment member according to Aspect 20, wherein the patterned uneven shape is formed by laser processing. [Aspect 22] The semiconductor manufacturing equipment member according to Aspect 20 or 21, wherein the surface of the central sidewall has one or more of the following patterned uneven shapes i) to iii): i) a pattern formed by a plurality of dot-like convex portions; ii) a pattern formed by a plurality of dimples; or iii) a pattern formed by a network-like convex portion formed by a plurality of intersecting linear convex portions. [Aspect 23] The semiconductor manufacturing equipment member according to any one of Aspects 20 to 22, wherein the surface of the central sidewall has an arithmetic mean roughness Ra1 of 0.4 μm or less. [Aspect 24] The semiconductor manufacturing equipment member according to any one of Aspects 12 to 23, wherein at least a portion of the central sidewall is covered with a coating layer, and the coating layer has a porosity of 2% or less. [Aspect 25] A semiconductor manufacturing equipment member comprising a ceramic substrate having an upper surface with a plurality of protrusions for mounting a wafer thereon and sidewalls forming the outer edge of the upper surface, wherein the arithmetic mean height Sa1 of the surface of the sidewalls is 1.1 μm or less. [Aspect 26] The semiconductor manufacturing equipment member of Aspect 25, wherein the upper surface and the sidewalls are connected via a chamfered portion, and the arithmetic mean height Sa4 of the surface of the chamfered portion is 0.1 μm or less. [Aspect 27] The semiconductor manufacturing equipment member of Aspect 25 or 26, wherein the standard deviation of the arithmetic mean height Sa1 of the surface of the sidewalls is 0.1 μm or less. [Aspect 28] The semiconductor manufacturing equipment member of Aspect 26 or Aspect 27 dependent on Aspect 26, wherein the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion is 0.1 μm or less. [Embodiment 29] The semiconductor manufacturing equipment member according to any one of embodiments 25 to 28, wherein at least a portion of the side wall is covered with a coating layer, and the coating layer has a porosity of 2% or less.

[0009] A semiconductor manufacturing equipment member according to one embodiment of the present invention includes a ceramic substrate that is less likely to generate particles even if its sidewall is affected by plasma.A semiconductor manufacturing equipment member according to another embodiment of the present invention includes a ceramic substrate that is less likely to generate particles due to the influence of plasma even if plasma enters a gap between a focus ring and a wafer.As a result, the semiconductor manufacturing equipment member can contribute to improving the stability of semiconductor quality and increasing yield.

[0010] 2-1 is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to a first embodiment of the present invention (a partial sectional view when cut along a plane including the central axis of the semiconductor manufacturing equipment member). FIG. 3 is a schematic partial enlarged view of the vicinity of the area surrounded by the bold frame shown in FIG. 1-1. FIG. 4 is a schematic partial plan view of a ceramic substrate according to a first embodiment of the present invention. FIG. 5 is a schematic partial longitudinal sectional view of a semiconductor manufacturing equipment member according to a second embodiment of the present invention (a partial sectional view when cut along a plane including the central axis of the semiconductor manufacturing equipment member). FIG. 6 is a schematic partial enlarged view of the vicinity of the area surrounded by the bold frame shown in FIG. 2-1. FIG. 7 is a schematic plan view of a ceramic substrate according to a second embodiment of the present invention. FIG. 8 shows an example of a patterned uneven shape provided on the surface of a side wall. FIG. 9 is a manufacturing process diagram of a semiconductor manufacturing equipment member according to a second embodiment of the present invention.

[0011] Next, embodiments of the present invention will be described in detail with reference to the drawings. It should be understood that the present invention is not limited to the following embodiments, and that appropriate design changes, improvements, and the like may be made based on the common knowledge of those skilled in the art without departing from the spirit of the present invention. Furthermore, in this specification, "upper" and "lower" are used for convenience to represent the relative positional relationship when the semiconductor manufacturing equipment component's ceramic substrate is placed on a horizontal surface with the upper surface facing up, and do not represent absolute positional relationships. Therefore, depending on the orientation of the semiconductor manufacturing equipment component, "upper" and "lower" may become "lower" and "upper," "left" and "right," or "front" and "rear."

[0012] 1-1 and 2-1 , a semiconductor manufacturing equipment member 10 according to a first embodiment and a second embodiment of the present invention can be used when performing processes such as CVD and etching on a wafer W using plasma. The semiconductor manufacturing equipment member 10 according to the first embodiment and the second embodiment includes a ceramic substrate 20 having an upper surface 21 on which a wafer W can be placed and a lower surface 23, and incorporating an electrode 26. The semiconductor manufacturing equipment member 10 according to the first embodiment and the second embodiment also includes a base plate 30 located on the lower surface 23 of the ceramic substrate 20 and incorporating a coolant flow path 32. The ceramic substrate 20 and the base plate 30 can be bonded via a bonding layer 40.

[0013] The ceramic substrate 20 of the semiconductor manufacturing equipment member 10 according to the first embodiment has a circular upper surface 21 in a plan view and a sidewall 28a that forms the outer edge of the upper surface 21. The ceramic substrate 20 may have a diameter of 300 to 400 mm and a thickness of 1 to 6 mm, for example. A wafer W can be placed on the upper surface 21.

[0014] The ceramic substrate 20 of the semiconductor manufacturing equipment member 10 according to the second embodiment includes a central portion 20a having a circular upper surface 21 in a planar view, and an outer peripheral portion 20b having an annular upper surface 27 in a planar view, surrounding the central portion 20a. The central portion 20a of the ceramic substrate 20 may have a diameter of 300 to 400 mm and a thickness of 1 to 6 mm, for example. A wafer W can be placed on the upper surface 21 of the central portion 20a, and a focus ring can be placed on the upper surface 27 of the outer peripheral portion 20b. Hereinafter, the focus ring may be abbreviated as "FR." A step is provided between the upper surface 21 of the central portion 20a and the upper surface 27 of the outer peripheral portion 20b, defined by the sidewall 28b of the central portion 20a, so that the upper surface 27 of the outer peripheral portion 20b is lower than the upper surface 21 of the central portion 20a. The height (step) of the sidewall 28b may be, for example, 0.5 to 5 mm. The lower surfaces 23 of the central portion 20a and the outer peripheral portion 20b may be flush with each other.

[0015] The upper surface 21 of the ceramic substrate 20 of the first embodiment and the upper surface 21 of the central portion 20a of the ceramic substrate 20 of the second embodiment are provided with a plurality of protrusions 22 for placing a wafer W on them. A seal band 25 may also be formed along the outer edge of the upper surface 21. In this case, the wafer W may be supported by the upper end surface 21c of the seal band 25 and the upper end surfaces 21a of the plurality of protrusions 22. It is preferable that the seal band 25 and the plurality of protrusions 22 have the same height. As shown in FIGS. 1-3 and 2-3 , in one embodiment, an annular seal band 25 is formed along the outer edge of the upper surface 21 of the ceramic substrate 20, and a plurality of protrusions 22 are formed over the entire inner surface of the seal band 25.

[0016] In the ceramic substrate 20 of the first embodiment, smoothing the surface of the sidewall 28a is effective in suppressing grain shedding. This is because smoothing reduces microscopic convex portions that are prone to chipping. Furthermore, microscopic concave portions accumulate slurry and processing residues used in the manufacturing process, becoming a particle source. Therefore, polishing to smooth the surface of the sidewall 28a is preferable. Polishing is also expected to suppress the formation of fractured layers and microcracks in the ceramic. More specifically, it is desirable to smooth the surface of the sidewall 28a to the extent that the fractured layers, which are the starting points for grain shedding, are removed from the surface of the sidewall 28a. Because the fractured layers are fragile surface layers with irregularities and cracks that occur during machining, removing the fractured layers and smoothing the surface can further reduce the risk of grain shedding. As a measure of whether the fractured layer has been removed, the arithmetic mean roughness Ra1 of the surface of the sidewall 28a is preferably 0.4 μm or less, more preferably 0.3 μm or less, and even more preferably 0.1 μm or less. While no particular lower limit is set for the arithmetic mean roughness Ra1 of the surface of the sidewall 28a, from the viewpoint of cost-effectiveness, it is preferable that it be 0.05 μm or more. Therefore, the arithmetic mean roughness Ra1 of the surface of the sidewall 28a is, for example, preferably 0.05 to 0.4 μm, more preferably 0.05 to 0.3 μm, and even more preferably 0.05 to 0.1 μm.

[0017] The preferred range of the arithmetic mean roughness Ra1 of the surface of the side wall 28a should be satisfied regardless of the measurement direction, but from the viewpoint of suppressing particles, it is preferable that the value of the arithmetic mean roughness Ra1 of the surface of the side wall 28a when measured in the circumferential direction of the ceramic substrate 20 is smaller than the value when measured in the thickness direction of the ceramic substrate 20.

[0018] Furthermore, the smoothness of the surface of the side wall 28a can be discussed using the arithmetic mean roughness Ra1, which is a line roughness parameter, as well as the arithmetic mean height Sa1 and the protruding valley spatial volume Vvv1, which are surface roughness parameters. In this case, the arithmetic mean height Sa1 of the surface of the side wall 28a being 1.1 μm or less and the protruding valley spatial volume Vvv1 of the surface of the side wall 28a being 0.5 ml / m are used as a guide to the removal of the fractured layer. 2 It is preferable that either or both of the following conditions be satisfied: the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.6 μm or less, and the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.2 ml / m or less. 2 It is more preferable that either or both of the following conditions be satisfied: the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.2 μm or less, and the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.1 ml / m or less. 2 Although no particular lower limit is set for the arithmetic mean height Sa1 of the surface of the side wall 28a and the protruding valley spatial volume Vvv1 of the surface of the side wall 28a, from the viewpoint of cost-effectiveness, it is preferable that the arithmetic mean height Sa1 of the surface of the side wall 28a be 0.05 μm or more and that the protruding valley spatial volume Vvv1 of the surface of the side wall 28a be 0.01 ml / m or less. 2 Therefore, for example, it is preferable that the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.05 to 1.1 μm, and the spatial volume Vvv1 of the protruding valley portion of the surface of the side wall 28a is 0.01 to 0.5 ml / m 2 It is preferable that one or both of the following conditions be satisfied: the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.05 to 0.6 μm, and the spatial volume Vvv1 of the protruding valley portion of the surface of the side wall 28a is 0.01 to 0.2 ml / m 2It is more preferable that one or both of the following conditions be satisfied: the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.05 to 0.2 μm, and the spatial volume Vvv1 of the protruding valley portion of the surface of the side wall 28a is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0019] From the viewpoint of quality stability, it is desirable that the surface of the side wall 28a is uniformly smooth. Therefore, for example, it is desirable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.1 ml / m or less. 2 It is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.02 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.03 ml / m or less. 2 It is more preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.005 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.02 ml / m or less. 2 Although there are no particular lower limits set for the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a and the standard deviation of the protruding valley spatial volume Vvv1 of the surface of the side wall 28a, from the viewpoint of cost-effectiveness, it is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a be 0.001 μm or more and that the standard deviation of the protruding valley spatial volume Vvv1 of the surface of the side wall 28a be 0.001 ml / m or less. 2 Therefore, for example, it is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.001 to 0.1 μm, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.001 to 0.1 ml / m 2 It is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.001 to 0.02 μm, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.001 to 0.03 ml / m 2It is more preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28a is 0.001 to 0.005 μm, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28a is 0.001 to 0.02 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0020] The same can be said for the ceramic substrate 20 of the second embodiment. Typically, the sidewall 28b of the central portion 20a and the top surface 27 of the peripheral portion 20b of the ceramic substrate 20 of the second embodiment are both formed by machining, such as cutting. Unless special polishing is performed after machining, the sidewall 28b of the central portion 20a and the top surface 27 of the peripheral portion 20b have similar surface roughness. It is preferable that the ceramic particles constituting the sidewall 28b of the central portion 20a are less likely to shed when affected by plasma. Smoothing the surface of the sidewall 28b is effective in suppressing particle shedding. This is because smoothing reduces microscopic convex portions that are prone to chipping. On the other hand, since the top surface 27 of the peripheral portion 20b is the mounting surface for a focus ring, it is protected by the focus ring, and therefore there is little need to smooth it. From the viewpoint of manufacturing costs, it is also desirable to avoid unnecessary polishing of the top surface 27 of the peripheral portion 20b.

[0021] Therefore, when polishing is performed to smooth the surface of the sidewall 28b of the central portion 20a, the arithmetic mean roughness Ra1 of the surface of the sidewall 28b of the central portion 20a becomes smaller than the arithmetic mean roughness Ra2 of the upper surface 27 of the peripheral portion 20b. More specifically, it is desirable to smooth the surface of the sidewall 28b of the central portion 20a to the extent that the fractured layer, which is the starting point for grain shedding, is removed from the surface of the sidewall 28b of the central portion 20a. Because the fractured layer is a brittle surface layer with irregularities and cracks that occur during machining, removing the fractured layer and leaving the surface can further reduce the risk of grain shedding. As a measure of whether the fractured layer has been removed, the arithmetic mean roughness Ra1 of the surface of the sidewall 28b of the central portion 20a is preferably 0.4 μm or less, more preferably 0.3 μm or less, and even more preferably 0.1 μm or less. Although no particular lower limit is set for the arithmetic mean roughness Ra1 of the surface of the sidewall 28b of the central portion 20a, from the viewpoint of cost-effectiveness, it is preferable that it be 0.05 μm or more. Therefore, the arithmetic mean roughness Ra1 of the surface of the sidewall 28b of the central portion 20a is, for example, preferably 0.05 to 0.4 μm, more preferably 0.05 to 0.3 μm, and even more preferably 0.05 to 0.1 μm.

[0022] The preferred range of the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central portion 20a should be satisfied regardless of the measurement direction, but from the viewpoint of suppressing particles, it is preferable that the value of the arithmetic mean roughness Ra1 of the surface of the side wall 28b of the central portion 20a when measured in the circumferential direction of the ceramic substrate 20 is smaller than the value when measured in the thickness direction of the ceramic substrate 20.

[0023] Furthermore, the smoothness of the surface of the sidewall 28b of the central portion 20a can also be discussed using the arithmetic mean height Sa and the protruding valley spatial volume Vvv1, which are surface roughness parameters, in addition to the arithmetic mean roughness Ra1, which is a line roughness parameter. Therefore, when polishing is performed to smooth the surface of the sidewall 28b of the central portion 20a, the arithmetic mean height Sa1 of the surface of the sidewall 28b of the central portion 20a becomes smaller than the arithmetic mean height Sa2 of the upper surface 27 of the outer peripheral portion 20b, and the protruding valley spatial volume Vvv1 of the surface of the sidewall 28b of the central portion 20a becomes smaller than the protruding valley spatial volume Vvv2 of the upper surface 27 of the outer peripheral portion 20b. As a measure of whether the crushed layer has been removed, the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 1.1 μm or less, and the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.5 ml / m 2 It is preferable that either or both of the following conditions be satisfied: the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.6 μm or less, and the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.2 ml / m or less. 2 It is more preferable that either or both of the following conditions be satisfied: the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.2 μm or less, and the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.1 ml / m or less. 2 Although no particular lower limit is set for the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a and the protruding valley spatial volume Vvv1 of the surface of the side wall 28b of the central portion 20a, from the viewpoint of cost-effectiveness, it is preferable that the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a be 0.05 μm or more and that the protruding valley spatial volume Vvv1 of the surface of the side wall 28b of the central portion 20a be 0.01 ml / m or less. 2 Therefore, for example, it is preferable that the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.05 to 1.1 μm, and the spatial volume Vvv1 of the protruding valley portion of the surface of the side wall 28b of the central portion 20a is 0.01 to 0.5 ml / m 2It is preferable that the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.05 to 0.6 μm, and the spatial volume Vvv1 of the protruding valley portion of the surface of the side wall 28b of the central portion 20a is 0.01 to 0.2 ml / m 2 It is more preferable that one or both of the following conditions be satisfied: the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.05 to 0.2 μm, and the spatial volume Vvv1 of the protruding valley portion of the surface of the side wall 28b of the central portion 20a is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0024] From the viewpoint of quality stability, it is desirable that the surface of the side wall 28b of the central portion 20a is uniformly smooth. Therefore, for example, it is desirable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.1 ml / m or less. 2 It is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.02 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.003 ml / m or less. 2 It is more preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.005 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.002 ml / m or less. 2 Although no particular lower limit is set for the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a and the standard deviation of the protruding valley spatial volume Vvv1 of the surface of the side wall 28b of the central portion 20a, from the viewpoint of cost-effectiveness, it is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.001 μm or more and the standard deviation of the protruding valley spatial volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.001 ml / m or less. 2Therefore, for example, it is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.001 to 0.1 μm, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.001 to 0.1 ml / m 2 It is preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.001 to 0.02 μm, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.001 to 0.003 ml / m 2 It is more preferable that the standard deviation of the arithmetic mean height Sa1 of the surface of the side wall 28b of the central portion 20a is 0.001 to 0.005 μm, and the standard deviation of the protruding valley space volume Vvv1 of the surface of the side wall 28b of the central portion 20a is 0.001 to 0.002 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0025] The surface of the sidewall 28a of the ceramic substrate 20 of the first embodiment and the surface of the sidewall 28b of the central portion 20a of the ceramic substrate 20 of the second embodiment preferably have a patterned uneven shape. The patterned uneven shape can be formed, for example, by performing laser processing after polishing. Alternatively, after forming a pattern by laser processing, the pattern may be mirror-finished by soft blasting. By-products flying from the chamber interior during wafer processing may adhere to the sidewalls 28a, 28b like a film. In this case, the presence of a patterned uneven shape on the sidewalls 28a, 28b has the advantage of preventing particles from falling off due to an anchor effect. However, even if the sidewalls 28a, 28b have a patterned uneven shape, it is preferable that the surfaces of the sidewalls 28a, 28b satisfy the above-mentioned arithmetic mean roughness condition. This is to suppress particle shedding from the surfaces of the sidewalls 28a, 28b.

[0026] The structure of the patterned uneven shape is not particularly limited, and five specific examples of the patterned uneven shape on the surfaces of the side walls 28a and 28b are shown in FIG.

[0027] The uneven shape of No. 1 has a pattern made up of a plurality of streak-like protrusions. The line width of each streak-like protrusion can be, for example, 20 to 200 μm.

[0028] The uneven shape of No. 2 has a pattern consisting of a plurality of dot-like protrusions. Each dot-like protrusion in No. 2 is relatively small. It is preferable that the plurality of dot-like protrusions are arranged evenly on the surfaces of the side walls 28a and 28b. When observed from a direction perpendicular to the surface, the area per dot-like protrusion is, for example, 200 to 25,000 μm 2 It can be said that:

[0029] The uneven shape of No. 3 also has a pattern consisting of a plurality of dot-like protrusions. Each dot-like protrusion in No. 3 is relatively large. It is preferable that the plurality of dot-like protrusions are arranged evenly on the surfaces of the side walls 28a and 28b. When observed from a direction perpendicular to the surface, the area per dot-like protrusion is, for example, 2000 to 250,000 μm. 2 The uneven shape of No. 2 and the uneven shape of No. 3 differ in the area of ​​each dot-like protrusion.

[0030] The uneven shape of No. 4 has a pattern consisting of a reference surface and a plurality of dimples (point-like recesses) provided on the reference surface. The plurality of dimples are preferably arranged evenly on the surfaces of the side walls 28a and 28b. When observed from a direction perpendicular to the surface, the area per dimple is, for example, 200 to 25,000 μm. 2 It can be said that:

[0031] The uneven shape of No. 5 has a pattern composed of a network of protrusions in which a plurality of linear protrusions intersect. In the illustrated embodiment, each mesh of the network of protrusions is hexagonal (honeycomb-shaped), but each mesh of the network of protrusions may be other polygonal shapes such as triangles, squares, pentagons, or octagons, or may be a combination of multiple polygonal shapes such as pentagons and triangles. The line width of each linear protrusion when observed from a direction perpendicular to the surface can be, for example, 20 to 200 μm. The area of ​​each mesh when observed from a direction perpendicular to the surface can be, for example, 2,000 to 250,000 μm. 2 It can be said that:

[0032] The upper surface 21 and the sidewall 28a of the ceramic substrate 20 of the first embodiment are preferably connected via a chamfered portion 29. Similarly, the upper surface 21 and the sidewall 28b of the central portion 20a of the ceramic substrate 20 of the second embodiment are preferably connected via a chamfered portion 29. Chamfering the corners of the wafer-mounting surface is advantageous from the viewpoint of suppressing the formation of a crushed layer at the corners and preventing grain shedding. Examples of the shape of the chamfered portion 29 include, but are not limited to, a C-chamfer and an R-chamfer. Although the chamfered portion 29 has a small area, it is a location that may be affected by plasma during wafer processing, and therefore it is desirable to smooth the surface. Therefore, for example, in the ceramic substrate 20 of the second embodiment, the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 is preferably smaller than the arithmetic mean roughness Ra2 of the upper surface 27 of the peripheral portion 20b. In the ceramic substrate 20 of the second embodiment, the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is preferably smaller than the arithmetic mean height Sa2 of the upper surface 27 of the outer peripheral portion 20 b. In the ceramic substrate 20 of the second embodiment, the protruding valley spatial volume Vvv4 of the surface of the chamfered portion 29 is preferably smaller than the protruding valley spatial volume Vvv2 of the upper surface 27 of the outer peripheral portion 20 b.

[0033] In both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 is preferably 0.4 μm or less, more preferably 0.3 μm or less, and even more preferably 0.1 μm or less. Although no particular lower limit is set for the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29, from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 is preferably, for example, 0.05 to 0.4 μm, more preferably 0.05 to 0.3 μm, and even more preferably 0.05 to 0.1 μm.

[0034] In both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 1.1 μm or less, and the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.5 ml / m2 It is preferable that either or both of the following conditions are satisfied: the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.8 μm or less, and the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.2 ml / m or less. 2 It is more preferable that either or both of the following conditions be satisfied: the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.5 μm or less, and the protruding valley spatial volume Vvv4 of the surface of the chamfered portion 29 is 0.1 ml / m or less. 2 Although there are no particular lower limits set for the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the spatial volume Vvv4 of the protruding valleys on the surface of the chamfered portion 29, from the viewpoint of cost-effectiveness, it is preferable that the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.2 μm or more, and that the spatial volume Vvv4 of the protruding valleys on the surface of the chamfered portion 29 is 0.01 ml / m or less. 2 Therefore, for example, it is preferable that the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.2 to 1.1 μm, and the spatial volume Vvv of the protruding valley portion of the surface of the side wall 28 a is 0.2 to 1.1 μm. ４ is 0.01 to 0.5 ml / m 2 It is preferable that the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.2 to 0.8 μm, and the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.01 to 0.2 ml / m 2 It is more preferable that either or both of the following conditions be satisfied: the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.2 to 0.5 μm, and the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0035] From the viewpoint of quality stability, it is desirable that the surface of the chamfered portion 29 is uniformly smooth. Therefore, for example, it is desirable that the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.1 ml / m or less. 2It is preferable that the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.02 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.03 ml / m or less. 2 It is more preferable that the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.005 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.02 ml / m or less. 2 Although there are no particular lower limits set for the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the standard deviation of the protruding valley spatial volume Vvv4 of the surface of the chamfered portion 29, from the viewpoint of cost-effectiveness, it is preferable that the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.001 μm or more, and the standard deviation of the protruding valley spatial volume Vvv4 of the surface of the chamfered portion 29 is 0.001 ml / m or less. 2 Therefore, for example, it is preferable that the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.001 to 0.1 μm, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.001 to 0.1 ml / m 2 It is preferable that the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.001 to 0.02 μm, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.001 to 0.03 ml / m 2 It is more preferable that the standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is 0.001 to 0.005 μm, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion 29 is 0.001 to 0.02 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0036] As described above, the surfaces of the side walls 28a, 28b and the surface of the chamfered portion 29 require the same level of smoothness. Therefore, it is expedient for quality control purposes to subject them to the same polishing process and set the surface roughness of both to the same level. Therefore, the absolute value of the difference between the arithmetic mean roughness Ra4 of the surface of the chamfered portion 29 and the arithmetic mean roughness Ra1 of the surfaces of the side walls 28a, 28b is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. The absolute value of this difference may be 0.

[0037] In addition, the absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a and 28b is 0.4 μm or less, and the absolute value of the difference between the protruding valley spatial volume Vvv4 of the surface of the chamfered portion 29 and the protruding valley spatial volume Vvv1 of the surfaces of the side walls 28a and 28b is 0.4 ml / m 2 It is preferable that the absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a, 28b is 0.3 μm or less, and the absolute value of the difference between the protruding valley spatial volume Vvv4 of the surface of the chamfered portion 29 and the protruding valley spatial volume Vvv1 of the surfaces of the side walls 28a, 28b is 0.3 ml / m or less. 2 It is more preferable that the absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a, 28b is 0.2 μm or less, and the absolute value of the difference between the spatial volume Vvv4 of the protruding valleys of the surface of the chamfered portion 29 and the spatial volume Vvv1 of the protruding valleys of the surfaces of the side walls 28a, 28b is 0.2 ml / m or less. 2 It is even more preferable that one or both of the following conditions be satisfied: The absolute value of the difference between the arithmetic mean height Sa4 of the surface of the chamfered portion 29 and the arithmetic mean height Sa1 of the surfaces of the side walls 28a, 28b may be 0. The absolute value of the difference between the protruding valley spatial volume Vvv4 of the surface of the chamfered portion 29 and the protruding valley spatial volume Vvv1 of the surfaces of the side walls 28a, 28b may be 0.

[0038] 1-2 and 2-2 show schematic structures of protrusions 22 provided on the upper surface 21 of a ceramic substrate 20 in the first and second embodiments, respectively. The shape of the protrusions 22 is not limited, but may be, for example, a cylindrical shape such as a cylinder or a rectangular pillar. The height h of the protrusions 22 is, for example, 5 to 100 μm, and typically 10 to 30 μm. The diameter d of the protrusions 22 is, for example, 0.5 to 5 mm, and typically 0.5 to 3 mm. Here, the diameter d of the protrusions 22 refers to the circle-equivalent diameter when the protrusions 22 are viewed in plan. The portion of the upper surface 21 of the ceramic substrate 20 on which the seal band 25 and the protrusions 22 are not provided is referred to as the reference surface 21b.

[0039] Each of the plurality of protrusions 22 has an upper end surface 21 a. The wafer W in contact with the upper end surface 21 a of the protrusions 22 may slide against the upper end surface 21 a of the protrusions 22 due to thermal expansion or the like. In order to prevent ceramic particles constituting the protrusions 22 from falling off during sliding, it is desirable to make the upper end surface 21 a of the protrusions 22 as smooth as possible. For example, it is preferable that the arithmetic mean roughness Ra3 of the upper end surface 21 a of the plurality of protrusions 22 is smaller than the arithmetic mean roughness Ra1 of the surfaces of the side walls 28 a, 28 b (in other words, the arithmetic mean roughness Ra1 of the surfaces of the side walls 28 a, 28 b is larger than the arithmetic mean roughness Ra3 of the upper end surfaces 21 a of the plurality of protrusions 22). It is also preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is smaller than the arithmetic mean height Sa1 of the surfaces of the side walls 28a, 28b (in other words, the arithmetic mean height Sa1 of the surfaces of the side walls 28a, 28b is larger than the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22).It is also preferable that the protrusion valley spatial volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22 is smaller than the protrusion valley spatial volume Vvv1 of the surfaces of the side walls 28a, 28b (in other words, the protrusion valley spatial volume Vvv1 of the surfaces of the side walls 28a, 28b is larger than the protrusion valley spatial volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22).

[0040] Similarly, it is preferable that the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the plurality of protrusions 22 is smaller than the arithmetic mean roughness Ra4 of the surfaces of the chamfered portions 29 (in other words, the arithmetic mean roughness Ra4 of the surfaces of the chamfered portions 29 is larger than the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the plurality of protrusions 22). It is also preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is smaller than the arithmetic mean height Sa4 of the surfaces of the chamfered portions 29 (in other words, the arithmetic mean height Sa4 of the surfaces of the chamfered portions 29 is larger than the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22). Furthermore, it is preferable that the spatial volume Vvv3 of the protrusion valley portion of the upper end surfaces 21 a of the multiple protrusions 22 is smaller than the arithmetic mean height Sa4 of the surface of the chamfered portion 29 (in other words, the arithmetic mean height Sa4 of the surface of the chamfered portion 29 is larger than the arithmetic mean height Sa3 of the upper end surfaces 21 a of the multiple protrusions 22).

[0041] Specifically, the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22 is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. Although no particular lower limit is set for the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22, from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra3 of the upper end surfaces 21a of the multiple protrusions 22 is preferably 0.05 to 0.4 μm, more preferably 0.05 to 0.2 μm, and even more preferably 0.05 to 0.1 μm.

[0042] Furthermore, the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.1 μm or less, and the protrusion valley space volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.01 ml / m 2 It is preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.05 μm or less, and the protrusion valley spatial volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.005 ml / m or less. 2It is more preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.03 μm or less, and the protrusion valley spatial volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.003 ml / m or less. 2 Although no particular lower limit is set for the arithmetic mean height Sa3 of the upper end surfaces 21 a of the plurality of protrusions 22 and the protrusion valley spatial volume Vvv3 of the upper end surfaces 21 a of the plurality of protrusions 22, from the viewpoint of cost-effectiveness, it is preferable that the arithmetic mean height Sa3 of the upper end surfaces 21 a of the plurality of protrusions 22 is 0.01 μm or more, and the protrusion valley spatial volume Vvv3 of the upper end surfaces 21 a of the plurality of protrusions 22 is 0.001 ml / m or less. 2 Therefore, for example, it is preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.01 to 0.1 μm, and the protrusion valley spatial volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.001 to 0.01 ml / m or more. 2 It is preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.01 to 0.05 μm, and the protrusion valley space volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.001 to 0.005 ml / m 2 It is more preferable that the arithmetic mean height Sa3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.01 to 0.03 μm, and the protrusion valley space volume Vvv3 of the upper end surfaces 21a of the plurality of protrusions 22 is 0.001 to 0.003 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0043] For the same reasons, the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25 is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. While no particular lower limit is set for the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25, from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra5 of the upper end surface 21c of the seal band 25 is preferably 0.05 to 0.4 μm, more preferably 0.05 to 0.2 μm, and even more preferably 0.05 to 0.1 μm.

[0044] The arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.1 μm or less, and the protruding valley space volume Vvv5 of the upper end surface 21c of the seal band 25 is 0.01 ml / m 2 It is preferable that the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.05 μm or less, and the protruding valley space volume Vvv5 of the upper end surface 21c of the seal band 25 is 0.005 ml / m or less. 2 It is more preferable that the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.03 μm or less, and the protruding valley space volume Vvv5 of the upper end surface 21c of the seal band 25 is 0.003 ml / m or less. 2 Although no particular lower limit is set for the arithmetic mean height Sa of the upper end surface 21c of the seal band 25 and the protruding valley spatial volume Vvv of the upper end surface 21c of the seal band 25, from the viewpoint of cost-effectiveness, it is preferable that the arithmetic mean height Sa of the upper end surface 21c of the seal band 25 is 0.01 μm or more, and that the protruding valley spatial volume Vvv of the upper end surface 21c of the seal band 25 is 0.001 ml / m or less. 2 Therefore, for example, it is preferable that the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.01 to 0.1 μm, and the protruding valley space volume Vvv5 of the upper end surface 21c of the seal band 25 is 0.001 to 0.01 ml / m or more. 2It is preferable that the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.01 to 0.05 μm, and the protruding valley space volume Vvv5 of the upper end surface 21c of the seal band 25 is 0.001 to 0.005 ml / m 2 It is more preferable that the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25 is 0.01 to 0.03 μm, and the protruding valley space volume Vvv5 of the upper end surface 21c of the seal band 25 is 0.001 to 0.003 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0045] Although the reference surface 21b of the upper surface 21 of the ceramic substrate 20 is not expected to slide against the wafer W, it may be affected by plasma during wafer processing. Therefore, it is desirable to make the reference surface 21b smooth. Therefore, for example, the arithmetic mean roughness Ra of the reference surface 21b in the ceramic substrate 20 according to the second embodiment is preferably smaller than the arithmetic mean roughness Ra of the upper surface 27 of the outer circumferential portion 20b. Furthermore, the arithmetic mean height Sa of the reference surface 21b in the ceramic substrate 20 according to the second embodiment is preferably smaller than the arithmetic mean height Sa of the upper surface 27 of the outer circumferential portion 20b. The protruding valley spatial volume Vvv of the reference surface 21b in the ceramic substrate 20 according to the second embodiment is preferably smaller than the protruding valley spatial volume Vvv of the upper surface 27 of the outer circumferential portion 20b.

[0046] In both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean roughness Ra6 of the reference surface 21b is preferably 0.4 μm or less, more preferably 0.2 μm or less, and even more preferably 0.1 μm or less. While no particular lower limit is set for the arithmetic mean roughness Ra6 of the reference surface 21b, from the viewpoint of cost-effectiveness, it is preferably 0.05 μm or more. Therefore, the arithmetic mean roughness Ra6 of the reference surface 21b is preferably, for example, 0.05 to 0.4 μm, more preferably 0.05 to 0.2 μm, and even more preferably 0.05 to 0.1 μm.

[0047] In both the ceramic substrate 20 of the first embodiment and the ceramic substrate 20 of the second embodiment, the arithmetic mean height Sa of the reference surface 21b is 0.9 μm or less, and the protruding valley space volume V of the reference surface 21b is 0.2 ml / m 2 It is preferable that either or both of the following conditions are satisfied: the arithmetic mean height Sa6 of the reference surface 21b is 0.8 μm or less, and the protruding valley space volume Vvv6 of the reference surface 21b is 0.15 ml / m 2 It is more preferable that the arithmetic mean height Sa6 of the reference surface 21b is 0.7 μm or less, and the protruding valley space volume Vvv6 of the reference surface 21b is 0.1 ml / m or less. 2 Although no particular lower limit is set for the arithmetic mean height Sa6 of the reference surface 21b and the protruding valley spatial volume Vvv6 of the reference surface 21b, from the viewpoint of cost-effectiveness, it is preferable that the arithmetic mean height Sa6 of the reference surface 21b is 0.05 μm or more, and the protruding valley spatial volume Vvv6 of the reference surface 21b is 0.01 ml / m or less. 2 Therefore, for example, it is preferable that the arithmetic mean height Sa6 of the reference surface 21b is 0.05 to 0.9 μm, and the protruding valley space volume Vvv6 of the reference surface 21b is 0.01 to 0.2 ml / m or more. 2 It is preferable that the arithmetic mean height Sa6 of the reference surface 21b is 0.05 to 0.8 μm, and the protruding valley space volume Vvv6 of the reference surface 21b is 0.01 to 0.15 ml / m 2 It is more preferable that the arithmetic mean height Sa6 of the reference surface 21b is 0.05 to 0.7 μm, and the protruding valley space volume Vvv6 of the reference surface 21b is 0.01 to 0.1 ml / m 2 It is even more preferable that one or both of the above conditions be satisfied.

[0048] The arithmetic mean roughness Ra of the surfaces of the side walls 28a, 28b, the arithmetic mean roughness Ra of the upper surface 27 of the outer circumferential portion 20b, the arithmetic mean roughness Ra of the upper end surfaces 21a of the plurality of protrusions 22, the arithmetic mean roughness Ra of the surface of the chamfered portion 29, the arithmetic mean roughness Ra of the upper end surface 21c of the seal band 25, and the arithmetic mean roughness Ra of the reference surface 21b are each measured in accordance with JIS B0601:2013. The surface roughness for each measurement point is measured at three points, and the average value is taken as the measured value.

[0049] The arithmetic mean height Sa1 of the surfaces of the side walls 28a, 28b, the arithmetic mean height Sa2 of the upper surface 27 of the outer peripheral portion 20b, the arithmetic mean height Sa3 of the upper end surfaces 21a of the multiple protrusions 22, the arithmetic mean height Sa4 of the surface of the chamfered portion 29, the arithmetic mean height Sa5 of the upper end surface 21c of the seal band 25, and the arithmetic mean height Sa6 of the reference surface 21b are each measured in accordance with ISO 25178 and can be measured using, for example, a non-contact roughness meter, Model VK-X3100, manufactured by Keyence Corporation. Surface roughness measurements for each measurement point are performed at three locations, and the average value is taken as the measured value. The standard deviation of each of the arithmetic mean heights Sa1, Sa2, Sa3, Sa4, Sa5, and Sa6 is calculated based on the results of measurements performed at four locations without bias.

[0050] The protrusion valley spatial volume Vvv1 on the surface of the side walls 28a, 28b, the protrusion valley spatial volume Vvv2 on the upper surface 27 of the outer peripheral portion 20b, the protrusion valley spatial volume Vvv3 on the upper end surface 21a of the multiple protrusions 22, the protrusion valley spatial volume Vvv4 on the surface of the chamfered portion 29, the protrusion valley spatial volume Vvv5 on the upper end surface 21c of the seal band 25, and the protrusion valley spatial volume Vvv6 on the reference surface 21b are each measured in accordance with ISO 25178 and can be measured using, for example, a non-contact roughness meter, model VK-X3100, manufactured by Keyence Corporation. Surface roughness measurements for each measurement location are performed at three locations, and the average value is used as the measured value. The standard deviation of each of the protrusion valley spatial volumes Vvv1, Vvv2, Vvv3, Vvv4, Vvv5, and Vvv6 is calculated based on the results of measurements performed at four locations without bias.

[0051] The ceramic substrate 20, including the protrusions 22 and the seal band 25, can be formed of a ceramic material such as alumina or aluminum nitride. In a preferred embodiment, the ceramic substrate 20 contains one or two materials selected from alumina and aluminum nitride. In a more preferred embodiment, the ceramic substrate 20 contains 80 mass % or more of one or two materials selected from alumina and aluminum nitride. In an even more preferred embodiment, the ceramic substrate 20 contains 95 mass % or more of one or two materials selected from alumina and aluminum nitride.

[0052] The electrode 26 is a planar electrode used as an electrostatic electrode and is connected to an external DC power supply via a power supply member (not shown). The electrode 26 is formed of a material containing, for example, W, Mo, WC, or MoC. A low-pass filter may be disposed midway along the power supply member. The power supply member is electrically insulated from the bonding layer 40 and the base plate 30. When a DC voltage is applied to the electrode 26, the wafer W is attracted and fixed to the wafer mounting surface, specifically, the upper end surface 21 c of the seal band 25 and the upper end surface 21 a of the protrusions 22, by electrostatic attraction. When the application of the DC voltage is stopped, the wafer W is released from the wafer mounting surface.

[0053] Instead of or in addition to the electrostatic attraction electrode, a heater electrode (resistance heating element) or an RF electrode for generating plasma may be built in as the electrode 26. In this case, a heater power supply is connected to the heater electrode, and an RF power supply is connected to the RF electrode. The ceramic substrate 20 may have one layer of the electrode 26 built in, or two or more layers of the electrode 26 built in with gaps between them.

[0054] The base plate 30 may be, for example, disk-shaped. The base plate 30 may have an annular flange portion on its lower surface that is used to clamp the semiconductor manufacturing equipment member 10 to a jig in the chamber. The thickness of the base plate 30 may be 10 to 30 mm, typically 15 to 30 mm. The base plate 30 is connected to a radio frequency (RF) power source and can also be used as an RF electrode.

[0055] The base plate 30 may be a circular plate (having the same diameter as or larger than the ceramic substrate 20) with good electrical and thermal conductivity. A refrigerant flow path 32 through which a refrigerant circulates may be formed within the base plate 30. The refrigerant flowing through the refrigerant flow path 32 is preferably a liquid, preferably electrically insulating. Examples of electrically insulating liquids include a fluorine-based inert liquid. The refrigerant flow path 32 may be formed, for example, in a single stroke across the entire base plate 30 in a plan view from one end (inlet) to the other end (outlet). One end and the other end of the refrigerant flow path 32 are connected to a supply port and a recovery port of an external refrigerant device (not shown), respectively. The refrigerant supplied from the supply port of the external refrigerant device to one end of the refrigerant flow path 32 passes through the refrigerant flow path 32, returns from the other end of the refrigerant flow path 32 to the recovery port of the external refrigerant device, has its temperature adjusted, and is then supplied again from the supply port to one end of the refrigerant flow path 32.

[0056] The base plate 30 can be made of, for example, a metal material or a composite material of metal and ceramic. Examples of metal materials include Al, Ti, Mo, and alloys thereof. Examples of composite materials of metal and ceramic include metal matrix composites (MMCs) and ceramic matrix composites (CMCs). Specific examples of such composite materials include a material containing Si, SiC, and Ti (also known as SiSiCTi), a material in which porous SiC is impregnated with Al and / or Si, and a composite material of Al2O3 and TiC. A material in which porous SiC is impregnated with Al is called AlSiC, and a material in which porous SiC is impregnated with Si is called SiSiC. It is preferable to select a material for the base plate 30 that has a thermal expansion coefficient similar to that of the material for the ceramic substrate 20. For example, if the ceramic substrate 20 is made of alumina, the base plate 30 is preferably made of SiSiCTi or AlSiC, which have a thermal expansion coefficient similar to that of alumina.

[0057] As shown in FIGS. 1-1 and 2-1 , the upper surface 31 of the base plate 30 is bonded to the lower surface 23 of the ceramic substrate 20 via a bonding layer 40. The bonding layer 40 bonds the lower surface 23 of the ceramic substrate 20 to the upper surface 31 of the base plate 30. The bonding layer 40 may be composed of, for example, a metal layer formed of solder or a metal brazing material. The bonding layer 40 is formed, for example, by thermal compression bonding (TCB). TCB refers to a known method in which a metal bonding material is sandwiched between two components to be bonded and the two components are pressure-bonded while heated to a temperature below the solidus temperature of the metal bonding material. The bonding layer 40 is not limited to a metal layer. For example, a resin bonding layer may be used instead of the metal layer. The resin bonding layer may be composed of, for example, a cured product of a silicone resin adhesive, an epoxy resin adhesive, an acrylic resin adhesive, or a urethane resin adhesive.

[0058] At least a portion of the sidewalls 28a, 28b of the ceramic substrate 20, the outer periphery of the bonding layer 40, the chamfered portion 29, and the side surface of the base plate 30 can be coated with a coating layer 60. Examples of the coating layer 60 include thermal spray films of alumina or yttria, aerosol deposition films, and ion-assisted deposition films. From the viewpoint of preventing corrosion due to plasma and reducing particle generation, the porosity of the coating layer 60 is preferably 2% or less, more preferably 1% or less, and even more preferably 0.5% or less. Among the coating layers 60, ion-assisted deposition is preferred because it can produce a dense film with low porosity. By coating at least a portion of the sidewalls 28a, 28b of the ceramic substrate 20, the outer periphery of the bonding layer 40, the chamfered portion 29, and the side surface of the base plate 30 with such a dense film, corrosion of these areas due to plasma can be suppressed and particle generation can be reduced. Furthermore, the coating layer is preferably an insulating film.

[0059] In the first and second embodiments, the semiconductor manufacturing equipment component 10 may have multiple holes penetrating the semiconductor manufacturing equipment component 10 in the vertical direction. Examples of such holes include multiple gas holes 50 opening in the upper surface 21 and lift pin holes for inserting lift pins that move the wafer W up and down relative to the upper surface 21. Multiple gas holes 50 can be provided at appropriate positions when the upper surface 21 is viewed from above (see FIGS. 1-3 and 2-3). A thermally conductive gas such as He gas is supplied to the gas holes 50. Typically, the gas holes 50 are provided so as to open to a portion of the upper surface 21 where the seal band 25 and multiple protrusions 22 are not provided (reference surface 21b). When the thermally conductive gas is supplied to the gas holes 50, the thermally conductive gas fills the space on the backside of the wafer W placed on the upper surface 21. A plug 55 having a gas flow path may be embedded in the gas holes 50. A plurality of lift pin holes can be provided at equal intervals along concentric circles on the upper surface 21 when the upper surface 21 is viewed in plan view.

[0060] 2. Method of Using the Semiconductor Manufacturing Equipment Member Next, an example of a method of using the semiconductor manufacturing equipment member 10 will be described. First, with the semiconductor manufacturing equipment member 10 installed in a chamber (not shown), a wafer W is placed on the upper surface 21 of the ceramic substrate 20. Then, the chamber is depressurized using a vacuum pump to adjust the chamber to a predetermined degree of vacuum, and a voltage is applied to the electrodes 26 of the ceramic substrate 20 to generate an electrostatic adsorption force, thereby adsorbing and fixing the wafer W to the wafer mounting surface (specifically, the upper end surfaces 21 c of the seal bands 25 and the upper end surfaces 21 a of the protrusions 22).

[0061] Next, the chamber is filled with a reactive gas atmosphere at a predetermined pressure (for example, several tens to several hundreds of Pa), and in this state, a high-frequency voltage such as an RF voltage is applied between an upper electrode (not shown) provided on the ceiling of the chamber and the base plate 30 of the semiconductor manufacturing equipment member 10 to generate plasma. The surface of the wafer W is processed by the generated plasma.

[0062] 3. Manufacturing Example of a Semiconductor Manufacturing Equipment Component Next, a manufacturing example of a semiconductor manufacturing equipment component 10 will be described with reference to FIG. 4. Here, a manufacturing example of a semiconductor manufacturing equipment component 10 according to the second embodiment shown in FIG. 2-1 will be described. First, a disk-shaped ceramic sintered body 120, which is the base of the ceramic substrate 20, is produced by hot-pressing and firing a ceramic powder compact (FIG. 4A). The compact may be produced by stacking multiple tape compacts, by mold casting, or by compressing ceramic powder. The ceramic sintered body 120 has an electrode 26 built in.

[0063] Next, the upper surface of the ceramic sintered body 120 is polished, and then the plurality of protrusions 22 and the seal band 25 are formed by blasting or laser processing ( FIG. 4B ). This allows the upper end surfaces 21 a of the plurality of protrusions 22 to be smoothed. Lapping can be used as a polishing method, but it is preferable to perform polishing in addition to lapping. Diamond slurry can be used for lapping, and colloidal silica can be used for polishing. Furthermore, the plurality of protrusions 22 and the seal band 25 are formed on the upper surface of the ceramic sintered plate by laser processing or the like. The plurality of protrusions 22 and the seal band 25 may be formed after the ceramic substrate 20 and the base plate 30 are bonded.

[0064] In parallel with this, two MMC disk members 131 and 136 are fabricated ( FIG. 4C ). Then, grooves 132 that will ultimately become the coolant flow paths 32 are formed in the underside of the upper MMC disk member 131 by machining ( FIG. 4D ). Through-holes 133 for introducing the coolant and through-holes 134 for discharging the coolant are drilled in the lower MMC disk member 136. When the ceramic sintered body 120 is made of alumina, the MMC disk members 131 and 136 are preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is roughly the same as that of SiSiCTi or AlSiC.

[0065] The SiSiCTi disk member can be fabricated, for example, as follows: First, silicon carbide, metallic Si, and metallic Ti are mixed to prepare a powder mixture. Next, the resulting powder mixture is uniaxially pressed to prepare a disk-shaped compact, which is then hot-press sintered in an inert atmosphere to obtain the SiSiCTi disk member.

[0066] Next, a metal bonding material 135 is placed between the lower surface of the upper MMC disk member 131 and the upper surface of the lower MMC disk member 136, and a metal bonding material 137 is placed on the upper surface of the upper MMC disk member 131. The ceramic sintered body 120 is then placed on the metal bonding material 137 placed on the upper surface of the upper MMC disk member 131. This results in a laminate 110 in which the lower MMC disk member 136, the metal bonding material 135, the upper MMC disk member 131, the metal bonding material 137, and the ceramic sintered body 120 are stacked in this order from bottom to top ( FIG. 4E ). This laminate 110 is then heated and pressurized (TCB) to obtain a bonded body. The bonded body is composed of the ceramic sintered body 120 bonded to the upper surface of the MMC block 130, which will become the base plate 30, via a metal bonding layer. The MMC block 130 is formed by joining an upper MMC disk member 131 and a lower MMC disk member 136 via a metal joining layer. The MMC block 130 has a coolant flow path 32, a coolant inlet 36, and a coolant outlet 38.

[0067] TCB is performed, for example, as follows. That is, the laminate is pressed and bonded at a temperature below the solidus temperature of the metal bonding material (for example, a temperature equal to or higher than the solidus temperature minus 20°C and lower than the solidus temperature), and then returned to room temperature. As a result, the metal bonding material becomes a metal bonding layer. As the metal bonding material, an Al-Mg based bonding material or an Al-Si-Mg based bonding material can be used. For example, when TCB is performed using an Al-Si-Mg based bonding material, the laminate is pressed while heated in a vacuum atmosphere. It is preferable to use a metal bonding material with a thickness of about 100 μm.

[0068] In the above, the case has been described where the base plate 30 is made of MMC and is joined to the ceramic sintered body 120 via the metal joining material 137. Alternatively, the base plate 30 may be made of metal and joined to the ceramic sintered body 120 using a resin adhesive sheet.

[0069] Furthermore, when the bonding layer 40 is formed using the metal bonding material 137, the coating layer 60 can be formed by thermal spraying on the base plate 30 either before or after bonding with the ceramic substrate 20. When the bonding layer 40 is formed using a resin adhesive sheet, the resin melts, so the coating layer 60 is formed by thermal spraying before bonding with the ceramic substrate 20.

[0070] Next, the outer periphery of the ceramic sintered body 120 is cut to form a step, resulting in a ceramic substrate 20 having a central portion 20a and an outer periphery 20b. Next, the surface of the sidewall 28b of the central portion 20a, preferably the surface of the sidewall 28b of the central portion 20a and the surface of the chamfered portion 29, is smoothed. Polishing using a machining center or wet blasting with a fine grindstone can be used as a smoothing method. This results in a semiconductor manufacturing equipment component 10 (FIG. 4F).

[0071] Although the base plate 30 in FIG. 1-1 is described as a single unit, it may have a structure in which two members are joined by a metal joining layer as shown in FIG. 4F, or a structure in which three or more members are joined by a metal joining layer.

[0072] (1-1. Production of Ceramic Substrate) A disk-shaped ceramic sintered body (300 mm diameter x 4 mm thickness) was produced by hot-pressing and sintering a compact of alumina powder. The top surface and sidewall of the ceramic sintered body were then machined, such as by grinding and polishing, to shape the body. Then, a C-chamfer was formed at the corner where the sidewall and top surface joined by grinding. The surfaces of the sidewall and the C-chamfer of the ceramic sintered body were then smoothed. Smoothing can be performed by grinding with a grindstone, polishing by wet blasting or dry blasting, or polishing with a brush using diamond slurry. These methods may also be combined to gradually increase the grit size of the grindstone. Here, a stepwise smoothing process was also performed, but the grit size of the grindstone was changed so that the arithmetic mean roughness Ra of the sidewall surface of the ceramic substrate reached the value listed in Table 1 according to the test number. As described above, the arithmetic mean roughness Ra was measured in accordance with JIS B0601:2013. Although the arithmetic mean roughness Ra of the C-chamfered portion was not measured, it is assumed to be similar to that of the side wall surface because the smoothing treatment conditions were the same. After the smoothing treatment, the processed surface was cleaned with an organic solvent and pure water.

[0073] (1-2. Evaluation of particle suppression effect) Particles are often caused mainly by ceramic processing residues and fractured layers (microcracks) remaining on the surface of the sidewalls and the surface of the chamfered portion of the ceramic substrate. Such processing residues and fractured layers (microcracks) tend to adhere to adhesive tape. Therefore, the particle suppression effect can be easily evaluated by applying and peeling adhesive tape, without actually placing the ceramic substrate under the influence of plasma. Therefore, cellophane tape was applied to the surface of the sidewalls under the following conditions, and then peeled off. <Conditions for applying and peeling cellophane tape> Type of cellophane tape: Cellotape (registered trademark) No. 405 manufactured by Nichiban Co., Ltd. Area of ​​cellophane tape applied to the sidewall: 100 mm 2 Pressure when laminating cellophane tape to the side wall: 98066 Pa Speed ​​when peeling cellophane tape from the side wall: 1 mm / s Angle when peeling cellophane tape from the side wall: 30°

[0074] The likelihood of particle generation was evaluated by the number of Al2O3 particles adhering to the cellophane tape when peeled off. The number of Al2O3 particles was evaluated by magnifying the adhesive surface of the cellophane tape 100 times with an SEM, then binarizing the white areas to be regarded as Al2O3 particles, and counting the number of Al2O3 particles with a circle equivalent diameter of 1 μm or more. The results are shown in Table 1. It can be seen that the number of adhering Al2O3 particles is significantly reduced when Ra is 0.4 μm or less.

[0075]

[0076] (2-1. Production of Ceramic Substrate) A disk-shaped ceramic sintered body (300 mm diameter x 4 mm thickness) was produced by hot-pressing and sintering a compact of alumina powder. The top surface and sidewall of the ceramic sintered body were then machined, such as by grinding and polishing, to shape the body. Then, a C-chamfer was formed at the corner where the sidewall and top surface joined by grinding. The surface of the sidewall and the surface of the C-chamfer of the ceramic sintered body were then smoothed. Smoothing can be performed by grinding with a grindstone, polishing by wet blasting or dry blasting, or polishing with a brush using diamond slurry. These methods may also be combined to gradually increase the grit size of the grindstone. Here, a stepwise smoothing process was also performed, but the grit size of the grindstone was changed so that the arithmetic mean roughness Ra of the sidewall surface of the ceramic substrate, the arithmetic mean height Sa of the sidewall surface of the ceramic substrate, and the protruding valley space volume Vvv of the sidewall surface were the values ​​listed in Table 2 according to the test number. As mentioned above, the arithmetic mean roughness Ra was measured in accordance with JIS B0601:2013. As mentioned above, the arithmetic mean height Sa and the protruding valley void volume Vvv were measured in accordance with ISO 25178 using a non-contact roughness meter, model VK-X3100, manufactured by Keyence Corporation. Although the arithmetic mean roughness Ra, arithmetic mean height Sa, and protruding valley void volume Vvv of the C-chamfer were not measured, they are presumed to be similar to those of the side wall surface because the smoothing treatment conditions were the same. After the smoothing treatment, the processed surface was cleaned with an organic solvent and pure water.

[0077] (2-2. Evaluation of particle suppression effect) Particles are often caused mainly by ceramic processing residues and fractured layers (microcracks) remaining on the surface of the sidewalls and the surface of the chamfered portion of the ceramic substrate. Such processing residues and fractured layers (microcracks) tend to adhere to adhesive tape. Therefore, the particle suppression effect can be easily evaluated by applying and peeling adhesive tape, without actually placing the ceramic substrate under the influence of plasma. Therefore, cellophane tape was applied to the surface of the sidewalls under the following conditions, and then peeled off. <Conditions for applying and peeling cellophane tape> Type of cellophane tape: Cellotape (registered trademark) No. 405 manufactured by Nichiban Co., Ltd. Area of ​​cellophane tape applied to the sidewall: 100 mm 2 Pressure when laminating cellophane tape to the side wall: 98066 Pa Speed ​​when peeling cellophane tape from the side wall: 1 mm / s Angle when peeling cellophane tape from the side wall: 30°

[0078] The likelihood of particle generation was evaluated by the number of Al2O3 particles adhering to the cellophane tape during peeling. The number of Al2O3 particles was evaluated by magnifying the adhesive surface of the cellophane tape 100 times with an SEM, then binarizing the white areas to identify Al2O3 particles, and counting the number of Al2O3 particles with a circle-equivalent diameter of 1 μm or more. The results are shown in Table 2. The number of adhering Al2O3 particles is more likely to decrease as Ra decreases, but even when Ra is the same, it can be seen that the number of adhering Al2O3 particles significantly varied when Sa, Vvv, and their standard deviations were changed.

[0079]

[0080] (3-1. Production of Ceramic Substrate) A disk-shaped ceramic sintered body (300 mm diameter x 4 mm thickness) was produced by hot-pressing and sintering a compact of alumina powder. The top surface and sidewall of the ceramic sintered body were then machined, such as by grinding and polishing, to shape the body. Then, a C-chamfer was formed at the corner where the sidewall and top surface joined by grinding. The surfaces of the sidewall and the C-chamfer of the ceramic sintered body were then each smoothed. Smoothing can be performed by grinding with a grindstone, polishing by wet blasting or dry blasting, or polishing with a brush using diamond slurry. These methods may also be combined to gradually increase the grit size of the grindstone. Here, a stepwise smoothing process was also performed, but the grit size of the grindstone was changed so that the arithmetic mean height Sa1 of the sidewall surface of the ceramic substrate and the arithmetic mean height Sa4 of the C-chamfer surface were the values ​​listed in Table 3 according to the test number. As described above, the arithmetic mean height Sa was measured using a non-contact roughness meter, Model VK-X3100, manufactured by Keyence Corporation, in accordance with ISO 25178. After the smoothing treatment, the processed surface was washed with an organic solvent and pure water.

[0081] (3-2. Evaluation of particle suppression effect) Particles are often mainly caused by ceramic processing residues and fractured layers (microcracks) remaining on the surface of the sidewalls and the surface of the chamfered portion of the ceramic substrate. Such processing residues and fractured layers (microcracks) tend to adhere to adhesive tape. Therefore, the particle suppression effect can be easily evaluated by applying and peeling adhesive tape, without actually placing the ceramic substrate under the influence of plasma. Therefore, cellophane tape was applied to the surface of the sidewalls under the following conditions, and then peeled off. <Conditions for applying and peeling cellophane tape> Type of cellophane tape: Cellotape (registered trademark) No. 405 manufactured by Nichiban Co., Ltd. Area of ​​cellophane tape applied to the sidewall: 100 mm 2 Pressure when laminating cellophane tape to the side wall: 98066 Pa Speed ​​when peeling cellophane tape from the side wall: 1 mm / s Angle when peeling cellophane tape from the side wall: 30°

[0082] The likelihood of particle generation was evaluated by the number of Al2O3 particles adhering to the cellophane tape during peeling. To evaluate the number of Al2O3 particles, the adhesive surface of the cellophane tape was magnified 100 times using an SEM, and then the white areas were binarized to represent Al2O3 particles. The number of Al2O3 particles with an equivalent circle diameter of 1 μm or more was counted. The results are shown in Table 3. It can be seen that the number of adhering Al2O3 particles is significantly reduced when Sa1 is 1.1 μm or less. It can also be seen that even if Sa1 is the same, the smaller the standard deviation, the fewer the number of adhering Al2O3 particles. Furthermore, it can be seen that a smooth C-chamfered portion is preferable. A smooth C-chamfered portion reduces the number of Al2O3 particles remaining in the C-chamfered portion, and even if Al2O3 particles fall off from the C-chamfered portion, they are less likely to adhere to the sidewall.

[0083]

[0084] DESCRIPTION OF SYMBOLS 10: MEMBER FOR SEMICONDUCTOR MANUFACTURING APPARATUS 20: CERAMIC SUBSTRATE 20a: CENTRAL PORTION 20b: PERIPHERAL PORTION 21: UPPER SURFACE 21a: UPPER END SURFACE 21b: REFERENCE SURFACE 21c: UPPER END SURFACE 22: PROJECTION 23: LOWER SURFACE 25: SEAL BAND 26: ELECTRODE 27: UPPER SURFACE 28a: SIDE WALL 28b: SIDE WALL 29: CHAMFERRED PORTION 30: BASE PLATE 31: UPPER SURFACE 32: REFRIGERATED FLOW FLOW 36: REFRIGERATED FLOW IN PORTION 38: REFRIGERATED FLOW PORTION 40: JOINTING LAYER 50: GAS HOLE 55: PLUG 60: COATING LAYER 110: LAMINATE 120: CERAMIC SINTERED BODY 130: MMC BLOCK 131: DISC MEMBER 132: GROOVE 133: THROUGHPUT HOLE 134 : Through hole 135 : Metal bonding material 136 : Disk member 137 : Metal bonding material W : Wafer FR : Focus ring

Claims

1. A component for semiconductor manufacturing equipment comprising a ceramic substrate having an upper surface with a plurality of protrusions for placing a wafer thereon and a sidewall forming the outer edge of the upper surface, wherein the arithmetic mean roughness Ra1 of the surface of the sidewall is 0.4 μm or less.

2. A member for semiconductor manufacturing equipment according to claim 1, wherein the surface of said sidewall has a patterned uneven shape.

3. A member for semiconductor manufacturing equipment according to claim 2, wherein the patterned uneven shape is formed by laser processing.

4. A semiconductor manufacturing equipment member according to claim 2, wherein the surface of the sidewall has one or more of the following patterned uneven shapes i) to iv): i) a pattern made up of a plurality of stripe-like convex portions; ii) a pattern made up of a plurality of dot-like convex portions; iii) a pattern made up of a plurality of dimples; iv) a pattern made up of a net-like convex portion in which a plurality of linear convex portions intersect.

5. A semiconductor manufacturing equipment member according to claim 1 or 2, wherein the upper surface and the side wall are connected via a chamfered portion, and the arithmetic mean roughness Ra4 of the surface of the chamfered portion is 0.4 μm or less.

6. The arithmetic mean height Sa1 of the surface of the side wall is 1.1 μm or less, and the protruding valley space volume Vvv1 of the surface of the side wall is 0.5 ml / m 2 3. The semiconductor manufacturing equipment member according to claim 1, wherein one or both of the following conditions are satisfied:

7. The arithmetic mean height Sa4 of the surface of the chamfered portion is 1.1 μm or less, and the protruding valley space volume Vvv4 of the surface of the chamfered portion is 0.5 ml / m 2 6. The semiconductor manufacturing equipment member according to claim 5, which satisfies one or both of the following conditions:

8. The standard deviation of the arithmetic mean height Sa1 of the side wall surface is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv1 of the side wall surface is 0.1 ml / m 2 7. The semiconductor manufacturing equipment member according to claim 6, which satisfies one or both of the following conditions:

9. The standard deviation of the arithmetic mean height Sa4 of the surface of the chamfered portion is 0.1 μm or less, and the standard deviation of the protruding valley space volume Vvv4 of the surface of the chamfered portion is 0.1 ml / m 2 8. The semiconductor manufacturing equipment member according to claim 7, which satisfies one or both of the following conditions:

10. A component for semiconductor manufacturing equipment as described in claim 1 or 2, wherein the arithmetic mean roughness Ra1 of the surface of the side wall is smaller when measured in the circumferential direction of the ceramic substrate than when measured in the thickness direction of the ceramic substrate.

11. A semiconductor manufacturing equipment member according to claim 1 or 2, wherein at least a portion of the side wall is covered with a coating layer, and the porosity of the coating layer is 2% or less.

12. A member for semiconductor manufacturing equipment comprising a ceramic substrate having a central upper surface having a plurality of protrusions for placing a wafer thereon, a peripheral upper surface that is on the outer periphery of the central upper surface and is positioned lower than the central upper surface, and a central side wall that forms a step between the central upper surface and the peripheral upper surface, wherein the arithmetic mean roughness Ra1 of the surface of the central side wall is smaller than the arithmetic mean roughness Ra2 of the peripheral upper surface.

13. A member for semiconductor manufacturing equipment according to claim 12, wherein the arithmetic mean roughness Ra1 of the surface of the side wall of the central portion is greater than the arithmetic mean roughness Ra3 of the upper end surfaces of the plurality of protrusions.

14. A member for semiconductor manufacturing equipment according to claim 12 or 13, wherein the arithmetic mean roughness Ra1 of the surface of the central side wall is 0.4 μm or less.

15. A semiconductor manufacturing equipment member according to claim 12 or 13, wherein the central upper surface and the central side wall are connected via a chamfered portion.

16. A member for semiconductor manufacturing equipment according to claim 15, wherein the arithmetic mean roughness Ra4 of the surface of said chamfered portion is smaller than the arithmetic mean roughness Ra2 of the upper surface of said outer periphery.

17. A member for semiconductor manufacturing equipment according to claim 15, wherein the arithmetic mean roughness Ra4 of the surface of said chamfered portion is greater than the arithmetic mean roughness Ra3 of the upper end faces of said plurality of protrusions.

18. A member for semiconductor manufacturing equipment according to claim 15, wherein the arithmetic mean roughness Ra4 of the surface of said chamfered portion is 0.4 μm or less.

19. A member for semiconductor manufacturing equipment according to claim 15, wherein the absolute value of the difference between the arithmetic mean roughness Ra4 of the surface of said chamfered portion and the arithmetic mean roughness Ra1 of the surface of said central side wall is 0.4 μm or less.

20. A member for semiconductor manufacturing equipment according to claim 12, wherein the surface of the side wall of the central portion has a patterned uneven shape.

21. A member for semiconductor manufacturing equipment according to claim 20, wherein the patterned uneven shape is formed by laser processing.

22. A semiconductor manufacturing equipment member according to claim 20, wherein the surface of the side wall of the central portion has one or more of the following patterned uneven shapes i) to iii): i) a pattern made up of a plurality of dot-like protrusions; ii) a pattern made up of a plurality of dimples; or iii) a pattern made up of a network-like protrusion in which a plurality of linear protrusions intersect.

23. A member for semiconductor manufacturing equipment according to any one of claims 20 to 22, wherein the arithmetic mean roughness Ra1 of the surface of the central side wall is 0.4 μm or less.

24. A semiconductor manufacturing equipment member according to claim 12 or 13, wherein at least a portion of the side wall of the central portion is covered with a coating layer, and the porosity of the coating layer is 2% or less.

25. A component for semiconductor manufacturing equipment comprising a ceramic substrate having an upper surface with a plurality of protrusions for placing a wafer thereon and sidewalls forming the outer edge of the upper surface, wherein the arithmetic mean height Sa1 of the surface of the sidewalls is 1.1 μm or less.

26. A semiconductor manufacturing equipment member according to claim 25, wherein the upper surface and the side wall are connected via a chamfered portion, and the arithmetic mean height Sa4 of the surface of the chamfered portion is 0.1 μm or less.

27. A member for semiconductor manufacturing equipment according to claim 25 or 26, wherein the standard deviation of the arithmetic mean height Sa1 of the sidewall surface is 0.1 μm or less.

28. A member for semiconductor manufacturing equipment according to claim 26, wherein the standard deviation of the arithmetic mean height Sa4 of the surface of said chamfered portion is 0.1 μm or less.

29. A semiconductor manufacturing equipment member according to claim 25 or 26, wherein at least a portion of the side wall is covered with a coating layer, and the porosity of the coating layer is 2% or less.

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