Hetero-junction bipolar transistor

Abstract

A first collector layer (103a) is constituted from n-type InAlAs in which the In composition ratio gradually decreases as the distance from the third sub-collector layer (102c) side increases. A second collector layer (103b) is constituted from n-type InAlAs in which the In composition is 0.3-0.557 inclusive. A third collector layer (103c) is constituted from n-type InAlAs in which the In composition ratio gradually increases as the distance from the second collector layer (103b) side increases. A setback layer (104) is constituted from n-type InP and is formed on the third collector layer (103c) in contact therewith.

Description

heterojunction bipolar transistor

[0001] The present invention relates to a heterojunction bipolar transistor.

[0002] Increasing demand for faster and larger capacity communications has led to demand for improved performance in high-frequency semiconductor transistors such as heterojunction bipolar transistors (HBTs). In recent years, active research has been conducted into the use of InP-based HBTs, which offer particularly excellent high-frequency characteristics, in ICs that operate in the millimeter-wave and terahertz bands, or frequencies up to about 1 THz.

[0003] The current gain cut-off frequency (f) is used as an index to evaluate the high frequency characteristics of a transistor. T and the maximum oscillation frequency f max There is. T is expressed by the following formula:

[0004]

[0005] In the above equation, t E is the emitter charging time, t B is the base running time, t C is the collector transit time, t CC is the collector charging time. E Yat CC is expressed by the contact resistance and capacitance of the emitter and collector. T To improve t, it is important to reduce the capacitance by reducing the device area and to reduce the contact resistance by heavily doping the contact layer. B Yat C represents the time required for electrons to pass through the base layer and collector layer, and further f T To improve the efficiency, it is necessary to reduce these travel times.

[0006] Also, f max can be expressed by the following formula:

[0007]

[0008] In the above formula, R B is the base resistance, C BC is the capacitance between the base and collector. Reducing these will reduce f max The base resistance is expressed as the sum of the intrinsic resistance of the base layer directly under the emitter, the access resistance from the base electrode to the region where carriers flow, and the contact resistance with the base electrode. For example, by heavily doping the base layer, the intrinsic resistance can be reduced and f max However, it is not desirable to increase the doping concentration too much because the current gain β decreases with increasing the doping concentration. Therefore, it is necessary to reduce other parameters such as the contact resistance to improve f. max Technology to improve this is required.

[0009] Compound semiconductor devices are typically fabricated by first forming an epitaxial layer structure on a substrate such as InP by an epitaxial growth method such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). In InP-based HBTs, an epitaxial wafer is generally fabricated by stacking desired layer structures such as a subcollector layer, collector layer, base layer, emitter layer, and emitter contact layer.

[0010] A resist pattern is created on such an epitaxial wafer using semiconductor lithography, and the emitter structure, base structure, etc. are fabricated using techniques such as wet etching. By using an etchant with particularly high etching selectivity, the above-described structures can be fabricated relatively easily by etching only the desired semiconductor layers and leaving the necessary layers. Once such an element structure is fabricated, an HBT is fabricated by forming the emitter contact electrode, base contact electrode, and collector contact electrode using techniques such as high-vacuum deposition.

[0011] When used for wireless communication, in addition to high frequency operation, breakdown voltage is also an important parameter. The breakdown voltage of a PN junction depends on the band gap of the semiconductor material and the thickness of the PN junction. Therefore, to improve the breakdown voltage, a wide-gap material can be used for the collector layer and the thickness of the collector layer can be increased. However, as mentioned above, T The collector transit time t C Therefore, if the film thickness is increased too much, T Therefore, it has been conventional to use a material with a larger band gap for the collector layer.

[0012] In a so-called single heterojunction bipolar transistor (SHBT), which uses InGaAs for the base layer and InGaAs for the collector layer, the band gap is small because the collector is InGaAs, making it difficult to ensure a high breakdown voltage. For this reason, a double heterojunction bipolar transistor (DHBT) using an InP collector has been proposed. However, in this DHBT, a barrier to electron transport is formed due to the conduction band offset between InP and InGaAs, which increases the collector charging time. T will deteriorate.

[0013] To solve this problem, there are DHBTs in which materials that form a band lineup called type-II with InP, such as GaAsSb and InGaAsSb, are used for the base layer. These materials eliminate the conduction band barrier, so T A high-voltage InP collector can be applied without causing degradation.

[0014] In this way, in the DHBT in which InP is used as the collector layer, a very high f T , f max It has been reported that these devices have been operated while maintaining a high breakdown voltage (Non-Patent Documents 1 and 2), but to further increase the breakdown voltage, it is necessary to use a material with a larger band gap than InP.

[0015] There is a technique for fabricating an HBT structure using other materials, such as GaAs, GaP, and AlP, as substrates, which have a larger bandgap than InP. However, these materials do not offer high electron mobility or electron velocity compared to InP-based materials, making their adoption extremely difficult from the perspective of high-frequency operation. To use InP-based materials with InP as the substrate, ternary alloy crystal materials such as InGaP and InAlP are considered.

[0016] Although these materials can be grown on InP substrates, they are alloyed with GaP or AlP, which have smaller lattice constants than InP, resulting in pseudo-lattice-matched growth and the application of strong in-plane tensile strain. Such strain introduces cracks and crystal defects due to stress relaxation, limiting the thickness of the material for application. To address this issue, techniques have been proposed for compensating for the strain-induced stress by applying strain in the opposite direction, but there are no P-based materials with lattice constants larger than InGaP or InAlP. Therefore, applying strain compensation to these material systems is difficult, resulting in limitations on the collector layer thickness and the Ga or Al composition required to achieve a wide gap.

[0017] Another example of a material system that pseudomorphically matches InP and has a larger bandgap than InP is InAlAs. InAlAs lattice matches InP at an In composition of approximately 0.53, and in this state, its bandgap is 1.4 eV or greater, larger than the bandgap of InP (1.35 eV). Therefore, applying InAlAs with an In composition of 0.53 to a DHBT can also be expected to achieve a high breakdown voltage. However, since InAlAs has a conduction band energy even greater than InP, it is necessary to devise a way to further reduce the band offset compared to InP.

[0018] Furthermore, by controlling the In composition, InAlAs can be changed to compressive strain at high In composition and tensile strain at low In composition. Therefore, by appropriately designing the In composition, the following technologies are required. First, by eliminating the band offset of the conduction band and without increasing the charging time, it is possible to suppress the introduction of crystal defects due to strain relaxation within the constraints imposed by the critical film thickness, and by applying a collector with a larger band gap than conventional InP, and T Therefore, there is a need for a technology that can increase the breakdown voltage without causing deterioration of the device.

[0019] AM Arabhavi et al., "InP / GaAsSb Double Heterojunction Bipolar Transistor Technology with fMAX = 1.2 THz", IEEE International Electron Devices Meeting , vol. 60, no. 4, pp. 2122-2129, 2022.Y. Shiratori et al., "InGaP / GaAsSb / InGaAsSb / InP Double Heterojunction Bipolar Transistors With Record ft of 813 GHz", IEEE Electron Device Letters, vol. 41, no. 5, pp. 697-700, 2020.

[0020] As mentioned above, there is a demand for a material with a larger band gap than InP to achieve a high breakdown voltage without increasing the collector transit time. InAlAs is a material that satisfies this demand without any limitations on the critical film thickness. However, if InAlAs is simply used, the barrier to electrons due to the conduction band offset is large, and the high frequency characteristics (especially f T ) deteriorates.

[0021] The present invention has been made to solve the above problems, and has as its object to make it possible to form a collector layer from InAlAs without deteriorating the high frequency characteristics.

[0022] A heterojunction bipolar transistor according to the present invention includes a substrate made of InP, a sub-collector layer made of InP formed on the substrate, a first collector layer made of InAlAs whose In composition ratio decreases with increasing distance from the sub-collector layer side and formed on the sub-collector layer, a second collector layer made of InAlAs whose In composition ratio is 0.3 or more and 0.557 or less and formed on the first collector layer, a third collector layer made of InAlAs whose In composition ratio increases with increasing distance from the second collector layer side and formed on the second collector layer, and a set-back layer made of InP formed on the third collector layer, the first collector layer has an In composition of 0.525 or more on the side in contact with the sub-collector layer, and the third collector layer has an In composition of 0.525 or more and an In composition of 0.75 or less on the side in contact with the set-back layer; the third collector layer has an In composition of 0.525 or more and an In composition of 0.75 or less on the side in contact with the set-back layer; the third collector layer has an In composition of 0.525 or more and an In composition of 0.75 or less on the side in contact with the set-back layer;

[0023] As described above, according to the present invention, the first collector layer is made of InAlAs in which the In composition ratio decreases with increasing distance from the subcollector layer side, the second collector layer is made of InAlAs in which the In composition ratio is 0.3 or more and 0.557 or less, the third collector layer is made of InAlAs in which the In composition ratio increases with increasing distance from the second collector layer side, and the set-back layer is made of InP. Therefore, the collector layer can be made of InAlAs without degrading the high frequency characteristics.

[0024] FIG. 1 is a cross-sectional view showing the configuration of a heterojunction bipolar transistor according to a first embodiment of the present invention. FIG. 2 is a characteristic diagram showing the state of the band gap at the Γ point of InAlAs. FIG. 3 is a characteristic diagram showing the energy states of the conduction band edge and the valence band edge at the Γ point of InAlAs. FIG. 4A is a band diagram in a thermal equilibrium state when the collector layer 103 is made of the most common InP. FIG. 4B is a band diagram when the collector layer 103 is made of InAlAs and includes a setback layer 104. FIG. 4C is a band diagram of a heterojunction bipolar transistor according to an embodiment. FIG. 5 is a cross-sectional view showing the configuration of a heterojunction bipolar transistor according to a second embodiment of the present invention. FIG. 6 is a photograph showing the results of measuring the surface state of a fabricated sample with a white light interferometer. FIG. 7 is a graph showing the collector current density (J) of the fabricated HBT when the base current is 0 A (during off operation). C ) is 100 A / cm 2 10 is a characteristic diagram showing the relationship between the collector-emitter voltage and the thickness of the second collector layer when

[0025] Hereinafter, a heterojunction bipolar transistor according to an embodiment of the present invention will be described.

[0026] First Embodiment First, a heterojunction bipolar transistor according to a first embodiment of the present invention will be described with reference to FIG. 1 . This heterojunction bipolar transistor includes a substrate 101, a first sub-collector layer 102a, a second sub-collector layer 102b, and a third sub-collector layer 102c formed on the substrate 101, a collector layer 103 formed on the third sub-collector layer 102c, and a set-back layer 104 formed on the collector layer 103. The collector layer 103 is composed of a first collector layer 103a, a second collector layer 103b, and a third collector layer 103c. The first collector layer 103a, the second collector layer 103b, and the third collector layer 103c are stacked in this order from the first sub-collector layer 102a side.

[0027] The heterojunction bipolar transistor also includes a base layer 105 formed on the setback layer 104, an emitter layer 106 formed on the base layer 105, and an emitter contact layer 107 formed on the emitter layer 106.

[0028] The substrate 101 is made of semi-insulating InP doped with Fe to have high resistance, and the (001) plane of the InP can be used as the main surface. In this example, a buffer layer 121 and an etching stop layer 122 are provided on the substrate 101. The buffer layer 121 can be made of InP. The etching stop layer 122 can be made of InGaAs. The etching stop layer 122 is formed on the substrate 101 side of the first sub-collector layer 102a.

[0029] As described above, this example includes a second sub-collector layer 102b formed on the first sub-collector layer 102a, and a third sub-collector layer 102c formed on the second sub-collector layer 102b. The first sub-collector layer 102a may be made of InP doped with a high concentration of n-type impurities. For example, the first sub-collector layer 102a may have a thickness of 500 nm. The first sub-collector layer 102a may have a thickness of 100 nm or more. The doping concentration in the first sub-collector layer 102a may be 100 nm or more. 19 cm -3 It can be more than that.

[0030] The second sub-collector layer 102b may be made of InGaAs doped with a high concentration of n-type impurities. 19 cm -3or more. Because the band gap of InGaAs is small, the resistance can be set even lower than that of the upper and lower first sub-collector layer 102a and third sub-collector layer 102c made of InP. Therefore, by forming the collector electrode 111 on the first sub-collector layer 102a via the second sub-collector layer 102b, the contact resistance can be further reduced. Furthermore, in the etching process for forming the collector layer into a predetermined device shape, the second sub-collector layer 102b can also be used as an etching stop layer by selective wet etching with InP.

[0031] The third sub-collector layer 102c can be made of n-type InP. The third sub-collector layer 102c has a high impurity concentration and is degenerated so that a barrier is not formed at the conduction band edge due to the band offset between the collector layer 103 and the second sub-collector layer 102b. The sub-collector layer can have a single-layer structure made of n-type InP.

[0032] The first collector layer 103a is made of n-type InAlAs, in which the In composition ratio gradually decreases with increasing distance from the third sub-collector layer 102c. By providing the first collector layer 103a and forming a region with a high In composition, strain compensation is performed for the entire semiconductor stack structure that constitutes the collector, base, and emitter, and the introduction of crystal defects due to strain relaxation can be suppressed.

[0033] The second collector layer 103b is made of n-type InAlAs with an In content of 0.3 to 0.557. The second collector layer 103b is formed on and in contact with the first collector layer 103a. By providing the second collector layer 103b made of InAlAs with a low In content, the band gap is increased, thereby improving the breakdown voltage.

[0034] The third collector layer 103c is composed of n-type InAlAs, in which the In composition ratio gradually increases with increasing distance from the second collector layer 103b. The third collector layer 103c is formed on and in contact with the second collector layer 103b. The third collector layer 103c has a compositionally graded structure toward the second collector layer 103b, which ensures a high breakdown voltage, to eliminate conduction band energy mismatch. By forming a region with a high In composition in the third collector layer 103c, strain compensation is performed for the entire epitaxial structure, and the introduction of crystal defects due to strain relaxation is suppressed.

[0035] The setback layer 104 is made of n-type InP and is formed on and in contact with the third collector layer 103c. The setback layer 104 can have a thickness of, for example, 5 nm or more. The setback layer 104 is introduced for the purpose of arranging the band lineup of the device from the emitter to the subcollector and preventing degradation of the performance of the heterojunction bipolar transistor. By providing the setback layer 104, a large band offset is formed on the valence band side, which makes it possible to suppress the tunneling current of holes from the base layer 105 to the third collector layer 103c. In addition, by providing the setback layer 104, the energy difference in the conduction band between the third collector layer 103c and the base layer 105 is adjusted, the conduction band barrier is reduced, and f t It is possible to prevent deterioration of the

[0036] The first collector layer 103a has an In composition of 0.525 or more on the side in contact with the third sub-collector layer 102c. The first collector layer 103a can have an In composition of the second collector layer 103b side that is the same as the In composition of the second collector layer 103b. The third collector layer 103c has an In composition of 0.525 or more and 0.75 or less on the side in contact with the setback layer 104. The third collector layer 103c can have an In composition of the second collector layer 103b side that is the same as the In composition of the second collector layer 103b.

[0037] The base layer 105 is made of a p-type compound semiconductor. For example, the base layer 105 can be made of a compound semiconductor such as InGaAs, InGaAsSb, or GaAsSb. The doping concentration is 10 19 cm -3 It can be more than that.

[0038] The base layer 105 may have a compositionally graded structure in which the band gap or doping concentration is modulated from the emitter layer 106 side to the third collector layer 103c side. For example, the base layer 105 may have a thickness of 25 nm and be made of InGaAsSb with a graded composition. By providing the base layer 105 with a compositionally graded structure, an internal electric field can be generated, accelerating carriers.

[0039] Furthermore, a highly doped contact layer can be introduced to form an electrode with lower contact resistance with the base electrode 112. This contact layer can be formed by regrowth in the outer region of the base layer 105 around the emitter layer 106. The impurity that makes the base layer 105 p-type can be C, Be, Zn, or the like.

[0040] The emitter layer 106 is composed of a compound semiconductor different from that of the base layer 105. The emitter layer 106 can be composed of an n-type compound semiconductor such as InP, InGaP, InAlAs, or InGaAsP. The emitter layer 106 has a larger band gap than the base layer 105, forming a heterojunction with the base layer 105. This creates a large band offset in the valence band, suppressing back-injection of holes from the base layer 105 and achieving high current gain. The emitter layer 106 can have a compositionally graded structure to adjust the band lineup of the conduction band. Furthermore, the emitter layer 106 may incorporate an As-containing layer, such as InGaAsP, to facilitate the fabrication of fine structures by wet etching during the process.

[0041] The emitter contact layer 107 can be made of a compound semiconductor such as n-type doped InGaAs or InAs. The emitter contact layer 107 has a thickness of 100 nm and a doping concentration of 3×1019 cm -3 The emitter contact layer 107 is set to a doping concentration higher than that of the emitter layer 106 and the collector layer in order to form a low-resistance ohmic contact with the emitter electrode 113. Generally, the impurity concentration of the emitter contact layer 107 is set to 10 19 cm -3 The emitter contact layer 107 may have a multi-layer structure, such as gradually increasing the In composition over the top surface of several nanometers that comes into contact with the emitter electrode 113 if the layer is made of InGaAs, or completely changing the layer to InAs.

[0042] The first collector layer 103a, the second collector layer 103b, the third collector layer 103c, and the setback layer 104 will be described in more detail below.

[0043] Figure 2 shows the results of calculations for the band gap of InAlAs applied to the collector layer. Figure 2 shows the results of calculations for the conduction band edge energy at the Γ point (k = 0, center of the first Brillouin zone) in momentum space (k space), which shows the characteristics of a direct transition type. The horizontal axis plots the In composition of InAlAs, and the vertical axis plots the band gap energy. The dotted line in Figure 2 shows the band gap energy of InP for comparison. The calculation results are for the band gap energy at the Γ point, which is a direct transition.

[0044] InAlAs lattice-matches with InP at an In composition of approximately 0.525 (arrow A). The bandgap in this configuration is approximately 1.43 eV, which is larger than the bandgap of InP (1.35 eV). Therefore, simply replacing the collector layer with InAlAs of the lattice-matched composition improves the breakdown voltage by approximately 6%.

[0045] From this composition, as the In composition decreases, the band gap becomes larger. However, according to reference literature, from an In composition of approximately 0.4 to 0.3, the conduction band edge energy at the Γ point (k = 0, center of the first Brillouin zone) in momentum space (k space) becomes close to the energy of the X point (k ≠ 0, edge point in the {100} direction of the first Brillouin zone) in k space, resulting in a shift from direct transition to indirect transition. If the In composition is reduced beyond this, the band gap increase effect becomes sluggish.

[0046] On the other hand, arrow B indicates the In composition when the band gap is almost the same as that of InAlAs and InP (In composition around 0.557, Eg = 1.35 eV). If the In composition is larger than this, the band gap becomes smaller than that of InP, so care must be taken from the viewpoint of improving the breakdown voltage.

[0047] Figure 3 shows the results of calculations plotting the conduction band and valence band energies of InAlAs versus the In composition of InAlAs. The calculations were performed for the Γ point, which is a direct transition. The dotted lines show the conduction band and valence band energies of InP. With increasing In composition, the conduction band energy of InAlAs decreases, while the valence band energy increases. The difference between these two energies corresponds to the band gap.

[0048] The conduction band energies of InP and InAlAs are nearly equal at an In composition of about 0.75 (arrow C). Therefore, if the In composition is greater than this, when an InAlAs / InP heterojunction is formed, a conduction band barrier with InP is formed, and electron transport from the InAlAs side to the InP side is inhibited.

[0049] Next, the effects of the configuration of first collector layer 103a, second collector layer 103b, and third collector layer 103c according to the first embodiment will be described with reference to the band diagrams of Figures 4A, 4B, and 4C. Figure 4A is a band diagram showing a thermal equilibrium state when collector layer 103 is made of the most common InP. Calculations were performed under the following settings.

[0050] First, the emitter contact layer 107 is made of InGaAs, has a thickness of 100 nm, and has an n-type impurity concentration of 3×10 19 cm -3 The emitter layer 106 was made of InP, had a thickness of 20 nm, and was undoped. The base layer 105 was made of compositionally graded InGaAsSb, had a thickness of 25 nm, and had a p-type impurity concentration of 3.3×10 19 cm -3 From 8.4 x 10 19 cm -3 was changed to.

[0051] The collector layer 103 is made of InP, has a thickness of 130 nm, and has an n-type impurity concentration of 1×10 17 cm -3 It was decided.

[0052] The first sub-collector layer 102a is made of InP, has a thickness of 500 nm, and has an n-type impurity concentration of 2×10 19 cm -3 The second sub-collector layer 102b was made of InGaAs, had a thickness of 30 nm, and had an n-type impurity concentration of 1.5×10 19 cm -3 The third sub-collector layer 102c was made of InP, had a thickness of 50 nm, and had an n-type impurity concentration of 2×10 19 cm -3 It was decided.

[0053] As shown in FIG. 4A, when the collector layer 103 is made of a uniform InP, it functions as a depletion region of the pn junction to ensure a breakdown voltage.

[0054] 4B is a band diagram for the case where the collector layer 103 is made of InAlAs and includes the setback layer 104. The calculation was performed under the following settings: The collector layer 103 is made of InAlAs with an Al composition of 0.525, has a thickness of 120 nm, and has an n-type impurity concentration of 1×10 17 cm -3 The InAlAs with an Al composition of 0.525 is lattice-matched with InP. The setback layer 104 is made of InP, has a thickness of 10 nm, and has an n-type impurity concentration of 1×10 17 cm -3It was decided.

[0055] The layers other than the collector layer 103 and the setback layer 104 were calculated in the same manner as in FIG. 4A.

[0056] Since the conduction band energy of InAlAs is larger than that of InP, it has a higher conduction band energy than many typical materials for the base layer 105, including InGaAsSb, InGaAs, and GaAsSb, which were used in this calculation. If the base layer 105 is structured so that it is in contact with the collector 103, the large conduction band offset acts as a barrier to electron transport, increasing the charging time during device operation and increasing the f t In order to prevent this, the setback layer 104 is introduced.

[0057] However, as shown in Figure 4B, a large conduction band barrier still remains in the collector layer. The conduction band energy difference between InAlAs and InP when lattice-matched is estimated to be about 0.3 eV (about 300 meV), as shown in Figure 4B. This is larger than the thermal energy (about 26 meV) of electrons at room temperature (about 25°C), and it is not easy to overcome this barrier simply by thermionic emission.

[0058] Therefore, simply constructing the collector layer from InAlAs or using the setback layer 104 made of InP will result in a large f t It is not possible to achieve high breakdown voltage without causing deterioration of characteristics such as the above.

[0059] 4C shows a band diagram of the heterojunction bipolar transistor according to the first embodiment. The calculation was performed under the following conditions: First, the setback layer 104 had a thickness of 10 nm and an n-type impurity concentration of 1.0×10 17 cm -3 The first collector layer 103a had a thickness of 20 nm and an n-type impurity concentration of 1.0×10 16 cm -3 The In composition was changed from 0.7 to 0.4 from the third sub-collector layer 102c side.

[0060] The second collector layer 103b has a two-layer structure consisting of a first collector layer 103a side and a third collector layer 103c side. The first collector layer 103a side has a thickness of 50 nm and an n-type impurity concentration of 8.0×10 16 cm -3 The third collector layer 103b side had a thickness of 20 nm and an n-type impurity concentration of 3.0×10 17 cm -3 In both cases, the In composition was set to 0.4. By calculating the second collector layer 103b as a two-layer structure in this way, the band lineup in the second collector layer 103b becomes smooth, as shown in FIG. 4C .

[0061] The third collector layer 103c has a thickness of 30 nm and an n-type impurity concentration of 1.0×10 16 cm -3 The In composition was changed from 0.4 to 0.7 from the second collector layer 103b side.

[0062] 4C, the conduction band barrier can be reduced by using the first collector layer 103a and the third collector layer 103c with graded In composition compared to when the collector layers are made of uniform InAlAs. In this example, the In composition on the setback layer 104 side is increased to 0.7, so the conduction band barrier can be reduced to approximately 76 meV.

[0063] The second collector layer 103b has an In composition reduced to 0.4, and the band gap is approximately 1.7 eV. The band gap of the second collector layer 103b is approximately 0.35 eV larger than the band gap of InP, which is 1.35 eV. The band gap of the second collector layer 103b is also approximately 0.3 eV larger than the band gap of InAlAs, which is lattice-matched to InP, which is 1.47 eV. Therefore, by providing the second collector layer 103b, a higher breakdown voltage can be ensured compared to when the collector layer is composed only of InP.

[0064] The heterojunction bipolar transistor according to the first embodiment has several important points to be considered in order to ensure the breakdown voltage while not impairing the high frequency characteristics.

[0065] First, the In composition of the third collector layer 103c has a profile in which the In composition is high on the side in contact with the setback layer 104 and the In composition smoothly decreases toward the second collector layer 103b. In the example described above, the In composition of the InAlAs on the side in contact with the setback layer 104 is set to around 0.7, thereby reducing the conduction band barrier and preventing the loss of high-frequency characteristics.

[0066] Furthermore, a high In composition region for strain compensation can be formed by setting the In composition of the third collector layer 103c on the side in contact with the setback layer 104 to 0.525 or more. When the In composition of the third collector layer 103c on the side in contact with the setback layer 104 is set to about 0.75, the conduction band offset with the setback layer 104 becomes almost zero, and the withstand voltage can be improved without impairing the RF characteristics.

[0067] Even if the In composition of the side of the third collector layer 103c in contact with the setback layer 104 is increased beyond 0.75, the conduction band offset problem does not occur, but the band gap of the third collector layer 103c becomes smaller, which may cause a decrease in the breakdown voltage.

[0068] Therefore, the In composition of the side of the third collector layer 103c in contact with the setback layer 104 can be set to 0.525 or more and 0.75 or less. However, InAlAs with an In composition of 0.7 has a small band gap (approximately 1 eV), and the conduction band energy in particular is extremely high. Therefore, depending on the position where it is formed and the electric field profile, the effect of increasing the breakdown voltage due to the narrow band gap may not be obtained, and there is also a concern of an increase in leakage current due to the influx of holes from the base layer 105. The setback layer 104 is also effective in preventing this, and it is desirable for the thickness of the setback layer 104 to be 5 nm or more.

[0069] The In composition of the second collector layer 103b is set to be smaller than the In composition of the side of the third collector layer 103c that contacts the setback layer 104. By setting the In composition of the second collector layer 103b to 0.557 or less, the band gap becomes larger than that of InP, thereby improving the breakdown voltage. Furthermore, by setting the In composition of the second collector layer 103b to 0.3 or more, the benefit of the band gap increase effect can be obtained without causing indirect transition, while avoiding the constraints imposed by the critical film thickness. Therefore, it is preferable to set the In composition of the second collector layer 103b to be 0.3 or more and 0.557 or less.

[0070] The In composition of the first collector layer 103a is such that the In composition is high on the side in contact with the third sub-collector layer 102c and gradually increases from the side of the second collector layer 103b. For example, the In composition of the first collector layer 103a on the side in contact with the third sub-collector layer 102c can be approximately 0.7.

[0071] As with the third collector layer 103c, the In composition of the first collector layer 103a can be appropriately set to reduce the conduction band barrier so as not to impair high-frequency characteristics. However, unlike the third collector layer 103c, the conduction band barrier does not pose a problem in the direction of electron travel, so there are no significant restrictions on the In composition on the side in contact with the third sub-collector layer 102c. By setting the In composition of the first collector layer 103a on the side in contact with the third sub-collector layer 102c to 0.525 or more, a high In composition region for strain compensation can be formed.

[0072] Second Embodiment Next, a heterojunction bipolar transistor according to a second embodiment of the present invention will be described with reference to FIG. 5 . This heterojunction bipolar transistor includes a substrate 101, a first subcollector layer 102a, a second subcollector layer 102b, and a third subcollector layer 102c formed on the substrate 101, a collector layer 103 formed on the third subcollector layer 102c, and a setback layer 104 formed on the collector layer 103. The collector layer 103 is composed of a first collector layer 103a, a second collector layer 103b', and a third collector layer 103c. The first collector layer 103a, the second collector layer 103b', and the third collector layer 103c are stacked in this order from the first subcollector layer 102a side.

[0073] The heterojunction bipolar transistor also includes a base layer 105 formed on the setback layer 104, an emitter layer 106 formed on the base layer 105, and an emitter contact layer 107 formed on the emitter layer 106.

[0074] The substrate 101 is made of semi-insulating InP doped with Fe to have high resistance, and the (001) plane of the InP can be used as the main surface. In this example, a buffer layer 121 and an etching stop layer 122 are provided on the substrate 101. The buffer layer 121 can be made of InP. The etching stop layer 122 can be made of InGaAs. The etching stop layer 122 is formed on the substrate 101 side of the first sub-collector layer 102a.

[0075] As described above, this example includes a second sub-collector layer 102b formed on the first sub-collector layer 102a, and a third sub-collector layer 102c formed on the second sub-collector layer 102b. The first sub-collector layer 102a may be made of InP doped with a high concentration of n-type impurities. For example, the first sub-collector layer 102a may have a thickness of 500 nm. The first sub-collector layer 102a may have a thickness of 100 nm or more. The doping concentration in the first sub-collector layer 102a may be 100 nm or more. 19 cm -3It can be more than that.

[0076] The second sub-collector layer 102b may be made of InGaAs doped with a high concentration of n-type impurities. 19 cm -3 The second sub-collector layer 102b can have a thickness of 30 nm. Because the bandgap of InGaAs is small, the resistance can be set even lower than that of the upper and lower first sub-collector layers 102a and third sub-collector layers 102c made of InP. Therefore, by forming the collector electrode 111 on the first sub-collector layer 102a via the second sub-collector layer 102b, the contact resistance can be further reduced. Furthermore, in the etching process for forming the collector layer into a predetermined device shape, the second sub-collector layer 102b can also be used as an etching stop layer by selective wet etching with InP.

[0077] The third sub-collector layer 102c may be made of n-type InP. The doping concentration in the third sub-collector layer 102c is 10 19 cm -3 or more. The third sub-collector layer 102c may have a thickness of 50 nm. The third sub-collector layer 102c has a high impurity concentration and is degenerated so that a barrier is not formed at the conduction band edge due to the band offset between the collector layer 103 and the second sub-collector layer 102b. The sub-collector layer may have a single-layer structure made of n-type InP.

[0078] The first collector layer 103a is made of n-type InAlAs, in which the In composition ratio gradually decreases with increasing distance from the third sub-collector layer 102c. By providing the first collector layer 103a and forming a region with a high In composition, strain compensation is performed for the entire semiconductor stack structure that constitutes the collector, base, and emitter, and the introduction of crystal defects due to strain relaxation can be suppressed.

[0079] The second collector layer 103b' is made of n-type InAlAs with an In composition of 0.4 to 0.557. Furthermore, the second collector layer 103b' has a thickness of 40 nm or less (maximum 40 nm). The second collector layer 103b' is formed on and in contact with the first collector layer 103a. By providing the second collector layer 103b' made of InAlAs with a low In composition, the band gap is increased, thereby improving the breakdown voltage.

[0080] The third collector layer 103c is composed of n-type InAlAs, in which the In composition ratio gradually increases with increasing distance from the second collector layer 103b'. The third collector layer 103c is formed on and in contact with the second collector layer 103b'. The third collector layer 103c has a compositionally graded structure toward the second collector layer 103b', which ensures a high breakdown voltage, to eliminate a mismatch in conduction band energy. By forming a region with a high In composition in the third collector layer 103c, strain compensation is performed for the entire epitaxial structure, and the introduction of crystal defects due to strain relaxation is suppressed.

[0081] The setback layer 104 is made of n-type InP and is formed on and in contact with the third collector layer 103c. The setback layer 104 may have a thickness of, for example, 5 nm or more. The setback layer 104 is introduced to adjust the band lineup of the device from the emitter to the subcollector and prevent degradation of the performance of the heterojunction bipolar transistor. The setback layer 104 forms a large band offset on the valence band side, suppressing hole tunneling current from the base layer 105 to the third collector layer 103c. The setback layer 104 also adjusts the conduction band energy difference between the third collector layer 103c and the base layer 105, reducing the conduction band barrier and preventing degradation of f.

[0082] The first collector layer 103a has an In composition of 0.525 or more on the side in contact with the third sub-collector layer 102c. The first collector layer 103a can have an In composition of the second collector layer 103b' side that is the same as the In composition of the second collector layer 103b'. The third collector layer 103c has an In composition of 0.525 or more and 0.75 or less on the side in contact with the setback layer 104. The third collector layer 103c can have an In composition of the second collector layer 103b' side that is the same as the In composition of the second collector layer 103b'.

[0083] The base layer 105 is made of a p-type compound semiconductor. For example, the base layer 105 can be made of a compound semiconductor such as InGaAs, InGaAsSb, or GaAsSb. The doping concentration is 10 19 cm -3 It can be more than that.

[0084] The base layer 105 may have a compositionally graded structure in which the band gap or doping concentration is modulated from the emitter layer 106 side to the third collector layer 103c side. For example, the base layer 105 may have a thickness of 25 nm and be made of InGaAsSb with a graded composition. By providing the base layer 105 with a compositionally graded structure, an internal electric field can be generated, accelerating carriers.

[0085] Furthermore, a highly doped contact layer can be introduced to form an electrode with lower contact resistance with the base electrode 112. This contact layer can be formed by regrowth in the outer region of the base layer 105 around the emitter layer 106. The impurity that makes the base layer 105 p-type can be C, Be, Zn, or the like.

[0086] The emitter layer 106 is composed of a compound semiconductor different from that of the base layer 105. The emitter layer 106 can be composed of an n-type compound semiconductor such as InP, InGaP, InAlAs, or InGaAsP. The emitter layer 106 has a larger band gap than the base layer 105, forming a heterojunction with the base layer 105. This creates a large band offset in the valence band, suppressing back-injection of holes from the base layer 105 and achieving high current gain. The emitter layer 106 can have a compositionally graded structure to adjust the band lineup of the conduction band. Furthermore, the emitter layer 106 may incorporate an As-containing layer, such as InGaAsP, to facilitate the fabrication of fine structures by wet etching during the process.

[0087] The emitter contact layer 107 can be made of a compound semiconductor such as n-type doped InGaAs or InAs. The emitter contact layer 107 has a thickness of 100 nm and a doping concentration of 3×10 19 cm -3 The emitter contact layer 107 is set to a doping concentration higher than that of the emitter layer 106 and the collector layer in order to form a low-resistance ohmic contact with the emitter electrode 113. Generally, the impurity concentration of the emitter contact layer 107 is set to 10 19 cm -3 The emitter contact layer 107 may have a multi-layer structure, such as gradually increasing the In composition over the top surface of several nanometers that comes into contact with the emitter electrode 113 if the layer is made of InGaAs, or completely changing the layer to InAs.

[0088] Next, the results of actually fabricating the layer structure of the heterojunction bipolar transistor according to the second embodiment will be described.

[0089] On an InP substrate, a buffer layer made of InP, an etch stopper layer made of InGaAs, a first sub-collector layer made of InP, a second sub-collector layer made of InGaAs, a third sub-collector layer made of InP, a first collector layer made of InAlAs, a second collector layer made of InAlAs, a third collector layer made of InAlAs, a setback layer made of InP, a base layer made of compositionally graded InGaAsSb and GaAsSb, an emitter layer made of InGaP, and an emitter contact layer made of InGaAs and InAs were laminated in this order by epitaxial growth.

[0090] The first sub-collector layer is formed to a thickness of 500 nm and has an n-type impurity concentration of 1×10 19 cm -3 The second sub-collector layer was formed to a thickness of 30 nm and had an n-type impurity concentration of 1×10 19 cm -3 The third sub-collector layer was formed to a thickness of 50 nm and had an n-type impurity concentration of 1×10 19 cm -3 That's all.

[0091] The total thickness of the first, second, and third collector layers was 120 nm. With this total thickness, samples were fabricated under four conditions: first collector layer thicknesses of 50 nm, 40 nm, 25 nm, and 20 nm, second collector layer thicknesses of 10 nm, 40 nm, 55 nm, and 70 nm, and third collector layer thicknesses of 60 nm, 40 nm, 40 nm, and 30 nm.

[0092] The first collector layer was formed so that the In composition ratio gradually decreased from 0.6 to 0.4 from the substrate side. The third collector layer was formed so that the In composition ratio gradually increased from 0.4 to 0.6 from the substrate side. By doing so, these layers have lattice constants ranging from tensile to compressive strain when pseudomorphically matched to the InP substrate, so that these layers alone do not generate stress due to large strain. Therefore, the strain and critical film thickness of the collector layer can be controlled by the composition and thickness of the second collector layer.

[0093] The second collector layer had an In composition of 0.4. Under these conditions, the lattice constant of the second collector layer was smaller than that of InP, resulting in in-plane tensile strain in the second collector layer. The critical thickness of InAlAs with an In composition of 0.4 when pseudomorphic to an InP substrate is assumed is 32.9 nm in the Matthews and Blakeslee model. In actual structures, the thickness is affected by the strain of the preceding and succeeding layers, so a thickness within a range of a few nanometers greater than this value can be applied by adjusting these layers. In particular, in HBTs, the emitter contact layer is often formed thickly from InGaAs or InAs with a high In composition, and these layers are subject to strong compressive strain. Therefore, considering the strain of the entire device, a thickness of approximately 40 to 50 nm can be used for a second collector layer with an In composition of 0.4.

[0094] The setback layer is formed to a thickness of 10 nm and has an n-type impurity concentration of 1×10 17 cm -3 It was decided.

[0095] The base layer is formed to a thickness of 30 nm and has a p-type impurity concentration of 1×10 19 cm -3 That's all.

[0096] The emitter layer was formed to a thickness of 15 nm. The emitter contact layer was formed to a thickness of 30 nm, with an InAs layer on an InGaAs layer, and had an n-type impurity concentration of 1×10 19 cm -3 That's all.

[0097] The results of measuring the surface state of the above-mentioned sample using a white light interferometer are shown in Figure 6. Figure 6(a) shows the surface state of a sample with a second collector layer thickness of 10 nm. Figure 6(b) shows the surface state of a sample with a second collector layer thickness of 40 nm. Figure 6(c) shows the surface state of a sample with a second collector layer thickness of 55 nm. Figure 6(d) shows the surface state of a sample with a second collector layer thickness of 70 nm.

[0098] The samples with second collector layer thicknesses of 10 nm and 40 nm exhibited relatively flat surface morphologies. In contrast, the samples with second collector layer thicknesses of 55 nm and 70 nm exhibited numerous linear defects (scratches). This is believed to be due to the fact that the tensile stress increases as the second collector layer becomes thicker, exceeding the critical thickness, resulting in the introduction of linear defects due to stress relaxation. These defects introduce numerous recombination centers, improving the breakdown voltage of the HBT, reducing current gain, and degrading high-frequency characteristics due to reduced electron velocity, thereby reducing the breakdown voltage. Furthermore, the defects degrade reliability and etching characteristics during the process. Therefore, it is preferable to limit the thickness of the second collector layer to a maximum of 40 nm.

[0099] Next, the results of evaluation of the breakdown voltage improvement performance will be described. For this evaluation, HBTs were fabricated by patterning samples with the layer structure described above. In the fabricated HBT devices, the device shape of the emitter portion was a rectangle of 50 nm square in a plan view seen from the normal direction of the substrate. The collector current density (J) of the fabricated HBTs when the base current was 0 A (off operation) was C ) is 100 A / cm 2 The collector-emitter voltage at this point was plotted against the thickness of the second collector layer, and the results are shown in Figure 7. The device was able to operate at higher voltages when the second collector layer was 40-55 nm thick than when it was 10 nm, confirming the improved breakdown voltage.

[0100] In the surface morphology described above, when the thickness of the second collector layer was made thicker than 55 nm, numerous scratch structures were observed, and therefore, even if there was an effect of improving the breakdown voltage of the HBT, there were many problems in terms of long-term reliability, etc. Taking this result into consideration along with the result of the above-mentioned device body pressure measurement, it is preferable to set the thickness of the second collector layer (InAlAs with an In composition of 0.4) to a maximum of 40 nm.

[0101] As described above, according to the embodiment of the present invention, the first collector layer made of InAlAs in which the In composition ratio decreases with increasing distance from the subcollector layer side, the second collector layer made of InAlAs in which the In composition ratio is 0.3 or more and 0.557 or less, the third collector layer made of InAlAs in which the In composition ratio increases with increasing distance from the second collector layer side, and the set-back layer made of InP are provided, so that the collector layer can be made of InAlAs without degrading the high frequency characteristics.

[0102] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0103] [Reference] JW Nicklasa and JW Wilkins, "Accurate ab initio predictions of III-V direct-indirect band gap crossovers", Applied Physics Letters, vol. 97, no. 9, 091902, 2010.

[0104] 101...substrate, 102a...first sub-collector layer, 102b...second sub-collector layer, 102c...third sub-collector layer, 103...collector layer, 103a...first collector layer, 103b...second collector layer, 103c...third collector layer, 104...setback layer, 105...base layer, 106...emitter layer, 107...emitter contact layer, 111...collector electrode, 112...base electrode, 113...emitter electrode, 121...buffer layer, 122...etching stop layer.

Claims

a first collector layer formed on the sub-collector layer and made of InAlAs whose In composition ratio decreases with increasing distance from the sub-collector layer; a second collector layer formed on the first collector layer and made of InAlAs whose In composition ratio is between 0.3 and 0.557; a third collector layer formed on the second collector layer and made of InAlAs whose In composition ratio increases with increasing distance from the second collector layer; a setback layer formed on the third collector layer and made of InP; a base layer formed on the setback layer and made of a compound semiconductor; an emitter layer formed on the base layer and made of a compound semiconductor different from that of the base layer; an emitter contact layer formed on the emitter layer and made of a compound semiconductor; a collector electrode formed on the sub-collector layer around the first collector layer; a base electrode formed on the base layer around the emitter layer; and an emitter electrode formed on the emitter contact layer. the first collector layer has an In composition of 0.525 or more on a side in contact with the sub-collector layer, and the third collector layer has an In composition of 0.525 or more and 0.75 or less on a side in contact with the setback layer.

2. A heterojunction bipolar transistor according to claim 1, further comprising an etching stop layer made of InGaAs formed on the substrate side of said subcollector layer.

3. A heterojunction bipolar transistor according to claim 1, wherein the subcollector layer is a first subcollector layer, and further comprising a second subcollector layer formed on the first subcollector layer and made of InGaAs, and a third subcollector layer formed on the second subcollector layer and made of InP, and the first collector layer is formed on the third subcollector layer.

4. A heterojunction bipolar transistor according to any one of claims 1 to 3, wherein the second collector layer is made of InAlAs with an In composition of 0.4 to 0.557, and has a thickness of 40 nm or less.

Images