Apparatus and method for generating non-sinusoidal high voltage pulse in semiconductor manufacturing facility using plasma

Abstract

The present disclosure relates to an apparatus and a method for generating a non-sinusoidal high voltage pulse in a semiconductor manufacturing facility using plasma. According to an aspect of the present disclosure, provided is a high voltage pulse generating apparatus comprising: a first voltage source having a (+) terminal connected to a first node and a (-) terminal connected to a reference terminal; a first input capacitor connected in parallel to the first voltage source; a second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to a second node; a second input capacitor connected in parallel to the second voltage source; a first switch connected between an output terminal and the first node; a second switch connected between the output terminal and the second node; and an inductor connected between the reference terminal and the output terminal.

Description

Device and method for generating non-sinusoidal high-voltage pulses in semiconductor manufacturing facilities using plasma

[0001] The present disclosure relates to a device and method for generating a non-sinusoidal high-voltage pulse in a semiconductor manufacturing facility using plasma.

[0002]

[0003] The content described below merely provides background information related to the present embodiment and does not constitute prior art.

[0004] To reduce semiconductor production costs, wafer pattern miniaturization and high etch rates are required under identical chamber size conditions. However, conventional pulse output circuits installed in plasma semiconductor equipment provide two-level unipolar output. This two-level unipolar output limits the ability to achieve wafer pattern miniaturization and high etch rates.

[0005] In addition, the existing pulse output circuit has a problem of generating switching loss by performing hard switching operation.

[0006]

[0007] The main purpose of the present disclosure is to provide a device and method for generating a non-sinusoidal high-voltage pulse in a semiconductor manufacturing facility using plasma.

[0008] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

[0009]

[0010] According to one aspect of the present disclosure, a high voltage pulse generator is provided, including: a first voltage source having a (+) terminal connected to a first node and a (-) terminal connected to a reference terminal; a first input capacitor connected in parallel to the first voltage source; a second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to a second node; a second input capacitor connected in parallel to the second voltage source; a first switch connected between an output terminal and the first node; a second switch connected between the output terminal and the second node; and an inductor connected between the reference terminal and the output terminal.

[0011] According to another aspect of the present disclosure, a semiconductor device manufacturing apparatus is provided, comprising a high voltage pulse generator and a chamber, wherein the high voltage pulse generator comprises: a first voltage source having a (+) terminal connected to a first node and a (-) terminal connected to a reference terminal; a first input capacitor connected in parallel to the first voltage source; a second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to a second node; a second input capacitor connected in parallel to the second voltage source; a first switch connected between an output terminal and the first node; a second switch connected between the output terminal and the second node; and an inductor connected between the reference terminal and the output terminal.

[0012] According to another aspect of the present disclosure, a high voltage pulse generator is provided, including: a first voltage source having a (+) terminal connected to a first node and a (-) terminal connected to a reference terminal; a second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to a second node; a plurality of first switches connected in series between an output terminal and the first node; a plurality of second switches connected in series between the output terminal and the second node; a plurality of first capacitors connected in parallel to each of the plurality of first switches; a plurality of second capacitors connected in parallel to each of the plurality of second switches; a plurality of first resistance elements connected in parallel to each of the plurality of first switches; a plurality of second resistance elements connected in parallel to each of the plurality of second switches; and an inductor connected between the reference terminal and the output terminal.

[0013] According to another aspect of the present disclosure, there is provided a first voltage source having a (+) terminal connected to a first node and a (-) terminal connected to a reference terminal; a second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to a second node; a plurality of first switches connected in series between an output terminal and a third node; a plurality of third switches connected in series between the third node and the first node; a plurality of second switches connected in series between the output terminal and a fourth node; a plurality of fourth switches connected in series between the fourth node and the second node; a plurality of first capacitors connected in parallel to each of the plurality of first switches; a plurality of second capacitors connected in parallel to each of the plurality of second switches; a plurality of third capacitors connected in parallel to each of the plurality of third switches; a plurality of fourth capacitors connected in parallel to each of the plurality of fourth switches; a first diode having an anode connected to the reference terminal and a cathode connected to the third node; A high voltage pulse generator is provided, comprising: a second diode having a cathode connected to the reference terminal and an anode connected to the fourth node; and an inductor connected between the reference terminal and the output terminal.

[0014] According to another aspect of the present disclosure, a high voltage pulse generator is provided, comprising: a first voltage source providing a positive voltage higher than a voltage level of a reference terminal to a first node; a second voltage source providing a negative voltage lower than a voltage level of the reference terminal to a second node; a first capacitor bypassed in a first mode and connected between the first node and an output terminal in second to fourth modes; a second capacitor bypassed in a third mode and connected between the second node and the output node in the first, second and fourth modes; and an inductor connected between the reference terminal and the output terminal, wherein in the first mode, the first node and the output terminal are electrically connected, and in the third mode, the second node and the output terminal are electrically connected.

[0015] According to another aspect of the present disclosure, there is provided a first voltage source providing a positive voltage higher than a voltage level of a reference terminal to a first node; a second voltage source providing a negative voltage lower than a voltage level of the reference terminal to a second node; a first capacitor bypassed in a first mode and a fifth mode and connected between a third node and an output terminal in the second to fourth modes; a third capacitor bypassed in the first mode and connected between the first node and the third node in the second to fifth modes; a second capacitor bypassed in the third mode and the fifth mode and connected between the output terminal and the fourth node in the first, second, and fourth modes; a fourth capacitor bypassed in the third mode and connected between the fourth node and the second node in the first, second, fourth, and fifth modes; an inductor connected between the reference terminal and the output terminal; a first diode supplying current from the reference terminal to the third node when the voltage level of the reference terminal is higher than the voltage level of the third node; And when the voltage level of the fourth node is higher than the voltage level of the reference terminal, a second diode is included that supplies current from the fourth node to the reference terminal, and in the first mode, the first node and the output terminal are electrically connected, and in the third mode, the second node and the output terminal are electrically connected.

[0016]

[0017] According to an embodiment of the present disclosure, by providing a bipolar output to the chamber, pattern refinement and high etching rate of the wafer can be achieved under the same chamber size conditions.

[0018] Additionally, by performing soft switching operation on the pulse output circuit, there is an effect of reducing the occurrence of switching loss.

[0019] The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

[0020]

[0021] FIG. 1 is a block diagram showing a high-voltage pulse generator and a capacitive load according to a first embodiment of the present disclosure.

[0022] FIG. 2 is a diagram illustrating an output waveform of a high-voltage pulse generator according to the first embodiment.

[0023] FIGS. 3A to 3D are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator according to the first embodiment.

[0024] Fig. 4 is a block diagram showing a high-voltage pulse generator and a capacitive load according to the second embodiment.

[0025] FIG. 5 is a diagram illustrating an output waveform of a high-voltage pulse generator according to a second embodiment of the present disclosure.

[0026] FIGS. 6A to 6E are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator according to the second embodiment.

[0027] FIG. 7 is a block diagram showing a high-voltage pulse generator (700) and a capacitive load (200) according to a third embodiment of the present disclosure.

[0028] Figure 8 is a drawing showing an example of a pulse generation circuit implemented by connecting multiple high-voltage pulse generation devices in parallel.

[0029] Fig. 9 is a flowchart illustrating a high-voltage pulse generation method according to the present embodiment.

[0030] FIG. 10 is a block diagram illustrating a semiconductor device manufacturing apparatus (1000) according to one embodiment of the present disclosure.

[0031]

[0032] Hereinafter, some embodiments of the present disclosure will be described in detail using exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings. Furthermore, when describing the present disclosure, detailed descriptions of related known structures or functions will be omitted if they are deemed to obscure the gist of the present disclosure.

[0033] In describing components of embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b) may be used. These symbols are only for distinguishing the components from other components, and the nature, order, or sequence of the components are not limited by the symbols. When a part in the specification is said to "include" or "have" a component, this does not mean that other components are excluded, but rather that other components may be included, unless explicitly stated otherwise.

[0034] The detailed description set forth below, together with the accompanying drawings, is intended to explain exemplary embodiments of the present disclosure and is not intended to represent the only embodiments in which the present disclosure may be practiced.

[0035] FIG. 1 is a block diagram illustrating a high voltage pulse generator (100) and a capacitive load (200) according to a first embodiment of the present disclosure. The high voltage pulse generator (100) can generate a high voltage pulse (Vout) having a predetermined waveform set by a user, and the generated high voltage pulse (Vout) can be provided to a capacitive load (200). For example, the capacitive load (200) may be a chamber (CB) as a facility for manufacturing semiconductor devices using plasma.

[0036] In Fig. 1, the components of the high-voltage pulse generator (100) may include a controller (not shown), and the controller (not shown) generates a driving signal so that each switch (SW1, SW2) is switched on or off.

[0037] In the description below, the operation of turning a switch on or off is caused by a controller (not shown) providing a driving signal required to turn the switch on or off to the gate of the switch.

[0038] The output pulse of the high voltage pulse generator (100) is 400 kHz, and the maximum peak-to-peak voltage Vp-p can be output at a voltage level of 12 kV.

[0039] As illustrated in FIG. 1, a high-voltage pulse generator (100) may be implemented including a first voltage source (VS1), a first input capacitor (Ci1), a second voltage source (VS2), a second input capacitor (Ci2), a first switch (SW1), a second switch (SW2), an inductor (L), and a fifth capacitor (C5). In some embodiments, the fifth capacitor (C5) may be omitted and one end of the inductor may be directly connected to a reference terminal (Nref).

[0040] The first voltage source (VS1) has its (+) terminal connected to the first node (N1) and its (-) terminal connected to the reference terminal, and generates a voltage having a magnitude of V1.

[0041] The first input capacitor (Ci1) is connected in parallel to the first voltage source (VS1).

[0042] The second voltage source (VS2) has its (+) terminal connected to the reference terminal (Nref) and its (-) terminal connected to the second node (N2), and generates a voltage having a magnitude of V2.

[0043] The second input capacitor (Ci2) is connected in parallel to the second voltage source (VS2).

[0044] The first switch (SW1) is connected between the output terminal (Nout) and the first node (N1).

[0045] The second switch (SW2) is connected between the output terminal (Nout) and the second node (N2).

[0046] An inductor (L) is connected between the reference terminal (Nref) and the output terminal (Nout).

[0047] The fifth capacitor (C5) is connected in series with the inductor (L). For example, one end of the fifth capacitor (C5) is connected to the reference terminal (Nref), the other end of the fifth capacitor (C5) is connected to one end of the inductor (L), and the other end of the inductor (L) is connected to the output terminal (Nout).

[0048] Meanwhile, a first capacitor (C1) and a first resistor element (R1) connected in parallel to each of both ends of the first switch (SW1) may further be included, and a second capacitor (C2) and a second resistor element (R2) connected in parallel to each of both ends of the second switch (SW2) may further be included. In addition, the first switch (SW1) and the second switch (SW2) may each be implemented as a single element, but may also each be implemented in a form in which a plurality of switch elements are connected in series. In addition, each capacitor and each resistor element may be connected in parallel to each switch element connected in series.

[0049] FIG. 2 is a diagram illustrating an output waveform of a high-voltage pulse generator (100) according to the first embodiment.

[0050] FIGS. 3A to 3D are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator (100) according to the first embodiment.

[0051] Hereinafter, the operation of the high voltage pulse generator (100) according to the first embodiment will be described with reference to FIGS. 2 and 3.

[0052] The high voltage pulse generator (100) operates repeatedly in the order of mode 1 to mode 4.

[0053] When the first switch (SW1) is implemented in a form in which multiple switch elements are connected in series, the capacitors connected in parallel to each of the multiple switch elements are intended to provide dynamic balance so that a high voltage is not applied unevenly to any one of the multiple switch elements during the on / off switching process of the multiple switch elements. In addition, the resistor elements connected in parallel to each of the multiple switch elements are intended to provide static balance so that a high voltage is not applied unevenly to any one of the multiple switch elements during the initial power-on process of the multiple switch elements.

[0054] In addition, when the second switch (SW2) is implemented in a form in which a plurality of switch elements are connected in series, the capacitor connected in parallel to each of the plurality of switch elements is to provide dynamic balance so that a high voltage is not applied biasedly to any one of the plurality of switch elements during the on / off switching process of the plurality of switch elements, and the resistor connected in parallel to each of the plurality of switch elements is to provide static balance so that a high voltage is not applied biasedly to any one of the plurality of switch elements during the initial power supply process of the plurality of switch elements.

[0055] As shown in FIG. 2 and FIG. 3a, when the first gate input signal (Gsw1) of the first switch (SW1) becomes 1 (i.e., the first switch (SW1) is ON) and the second gate input signal (Gsw2) of the second switch (SW2) becomes 0 (i.e., the second switch (SW2) is OFF), the high-voltage pulse generator (100) enters mode 1.

[0056] In mode 1, the output voltage Vout becomes the same voltage as the voltage V1 of the first voltage source (VS1).

[0057] As shown in FIGS. 2 and 3b, when the first gate input signal (Gsw1) changes to 0 and the first switch (SW1) turns OFF in mode 1, the high-voltage pulse generator (100) becomes mode 2. That is, when the first switch (SW1) is ON and the second switch (SW2) is OFF, and the first switch (SW1) is turned OFF, mode 2 occurs.

[0058] In Fig. 3b, the impedances of R1 and R2 are greater than the impedances of C1 and C2, respectively, and the current of the DC power supply of VS1 and VS2 is substantially blocked from the output terminal Nout by C1 and C2, respectively, so the current paths connecting to R1, R2, VS1, and VS2 are omitted.

[0059] During mode 1, the energy stored in the inductor (L) gradually decreases Vout due to LC resonance by the inductor (L) and the composite capacitance in mode 2. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitance of the first capacitor (C1) and the second capacitor (C2) and the parasitic capacitance. The first capacitor (C1) is charged via the parasitic capacitor (Cp) formed between the high voltage pulse generator (100) and the ground terminal, and Vout decreases due to LC resonance in which the second capacitor (C2) is discharged. The decrease in Vout may continue until mode 3.

[0060] As shown in FIGS. 2 and 3c, when the second gate input signal (Gsw2) becomes 1 and the second switch (SW2) is turned ON in mode 2, the high-voltage pulse generator (100) becomes mode 3. That is, when the first switch (SW1) and the second switch (SW2) are turned OFF and the second switch (SW2) is turned ON, mode 3 is entered.

[0061] In mode 3, the output voltage Vout becomes -V2, which is the same value as the voltage of the second voltage source (VS2).

[0062] As shown in FIGS. 2 and 3d, when the second gate input signal (Gsw2) changes to 0 and the second switch (SW2) turns OFF in mode 3, the high-voltage pulse generator (100) becomes mode 4. That is, when the first switch (SW1) is OFF and the second switch (SW2) is ON, and the second switch (SW2) is turned OFF, mode 4 is entered.

[0063] In Fig. 3d, the impedances of R1 and R2 are larger than the impedances of C1 and C2, and the DC power of VS1 and VS2 is substantially blocked from the output terminals by C1 and C2, so the current paths connecting R1, R2, VS1, and VS2 are omitted.

[0064] Meanwhile, Ci1=Ci2=C1=C2 and R1=R2.

[0065] During Mode 3, the (-) energy stored in the inductor (L) gradually increases Vout due to LC resonance by the inductor (L) and the composite capacitance in Mode 4. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitances of the first capacitor (C1) and the second capacitor (C2) and the parasitic capacitance. Vout monotonically increases due to LC resonance that discharges the first capacitor (C1) and charges the second capacitor (C2) via the parasitic capacitor (Cp), and this increase may continue until Mode 1.

[0066] Note that during the periods of mode 2 and mode 4, despite the LC resonance by the composite capacitance and inductor (L), a monotonous decrease in Vout occurs during the period of mode 2, and a monotonous increase in Vout occurs during the period of mode 4.

[0067] The periods of mode 2 and mode 4 are each T as a dead time interval. deadDuring the dead time period, the capacitances (Co) of C1, C2 and chamber (CB) connected in parallel to each switch are all discharged, enabling turn-on and turn-off by zero voltage switching (ZVS).

[0068] Minimum current (i) to satisfy the discharge time in the dead time interval Lpk ) can be calculated using mathematical formula 1.

[0069]

[0070] Here, △V is the voltage difference between the top and bottom of the output waveform (i.e., peak-to-peak voltage), which can be calculated as V1+V2. Also, C PT represents the (+) terminal equivalent capacitance including the capacitance of the first capacitor (C1) between the output terminal (Nout) and the first node (N1) and the parasitic capacitance, and C NT represents the (-) terminal equivalent capacitance including the capacitance of the second capacitor (C2) between the output terminal (Nout) and the second node (N2) and parasitic capacitance, and Co represents a known capacitance value for the corresponding chamber (CB). Here, each equivalent capacitance can be obtained by measurement.

[0071] Therefore, current i Lpk The value Lc of the inductor L for the current to flow can be calculated from mathematical expression 2.

[0072]

[0073] Here, Tsw represents one switching cycle from mode 1 to mode 4, and V L represents the voltage between the two terminals of the inductor.

[0074] The fifth capacitor (C5) is configured to prevent saturation of the inductor (L). If the fifth capacitor (C5) is not present, the average voltage of the inductor (L) may not be 0 when the ON / OFF ratio of each switch (SW1, SW2) is not 5:5. That is, a DC component may exist in the inductor voltage, which may cause saturation of the inductor (L). Here, a case in which the average voltage of the inductor (L) is not 0 may occur when the voltage application time in mode 1 and the voltage application time in mode 3 are different when V1=V2, or when the voltage application time in mode 1 and the voltage application time in mode 3 are the same and V1 and V2 are different. Here, the dead time among one cycle related to switching is excluded from the ON / OFF time. Therefore, the inductor (L) may be saturated due to a non-zero average voltage, and the average voltage, ripple voltage, and resonant current must be considered when selecting the value of C5.

[0075] Average voltage V avg is as shown in mathematical formula 3.

[0076]

[0077] In mathematical expression 3, Intensicty_P means the duty at which V1 is applied when the first switch (SW1) is turned on, and Intensicty_N means the duty at which V2 is applied when the second switch (SW2) is turned on.

[0078] Peak-to-peak ripple voltage △v of the inductor c can be calculated as in mathematical formula 4.

[0079]

[0080] Here, i L is the current flowing in the inductor L and i Lpk , where Cc5 represents the capacitance value of capacitor C5.

[0081] Here, the maximum value of the ripple voltage v c_max and minimum value vc_min is as shown in mathematical formula 5.

[0082]

[0083] Therefore, the maximum resonant current i is obtained by Equation 6 c_max and minimum value i c_min This can be calculated.

[0084]

[0085] As shown in Fig. 2, in mode 4, when the first switch (SW1) is OFF and the second switch (SW2) is OFF, changing the first switch (SW1) to ON results in mode 1.

[0086] In this way, the high voltage pulse generator (100) sequentially turns on / off the first switch (SW1) and the second switch (SW2) to control mode 1 to mode 4 to be sequentially generated.

[0087] FIG. 4 is a block diagram showing a high-voltage pulse generator (400) and a capacitive load (200) according to the second embodiment.

[0088] As illustrated in FIG. 4, a high voltage pulse generator (400) can be implemented by including a first voltage source (VS1), a first input capacitor (Ci1), a second voltage source (VS2), a second input capacitor (Ci2), a first switch (SW1), a second switch (SW2), a third switch (SW3), a fourth switch (SW4), an inductor (L), a fifth capacitor (C5), a first diode (D1), and a second diode (D2).

[0089] The circuit diagram of the high-voltage pulse generator (400) according to the second embodiment is in the form of the circuit diagram of FIG. 1, which further includes a third switch (SW3), a fourth switch (SW4), a first diode (D1), and a second diode (D2).

[0090] In Fig. 4, the other end of the first switch (SW1) is connected to the output terminal (Nout), and the third switch (SW3) is connected between one end of the first switch (SW1) and the first node (N1).

[0091] One end of the second switch (SW2) is connected to the output terminal Nout, and the fourth switch (SW4) is connected between the other end of the second switch (SW2) and the second node.

[0092] The first diode (D1) has its anode connected to the reference terminal (Nref) and its cathode connected to one end of the first switch (SW1).

[0093] The second diode (D2) has its cathode connected to the reference terminal (Nref) and its anode connected to the other terminal of the second switch (SW2).

[0094] A first balance capacitor (Cd1) may be connected in parallel across both ends of a first diode (D1), and a second balance capacitor (Cd2) may be connected in parallel across both ends of a second diode (D2). In addition, the first balance capacitor (Cd1) and the second balance capacitor (Cd2) may each be implemented as a single element, but may also be implemented in a form in which a plurality of diode elements are connected in series. In addition, each capacitor may be connected in parallel to each diode element connected in series.

[0095] The first switch (SW1) may further include a first capacitor (C1) and a first resistor element (R1) connected in parallel at both ends, respectively, the second switch (SW2) may further include a second capacitor (C2) and a second resistor element (R2) connected in parallel at both ends, respectively, the third switch (SW3) may further include a third capacitor (C3) and a third resistor element (R3) connected in parallel at both ends, respectively, and the fourth switch (SW4) may further include a fourth capacitor (C4) and a fourth resistor element (R4) connected in parallel at both ends, respectively. In addition, the first switch (SW1) to the fourth switch (SW4) may each be implemented as a single element, but may also be implemented in a form in which a plurality of switch elements are connected in series. In addition, each capacitor and each resistor element may be connected in parallel to each switch element connected in series.

[0096] FIG. 5 is a diagram illustrating an output waveform of a high-voltage pulse generator (400) according to the second embodiment.

[0097] FIGS. 6A to 6E are drawings for explaining the operating state in each mode in the output waveform of the high-voltage pulse generator (400) according to the second embodiment.

[0098] Hereinafter, the operation of the high voltage pulse generator (400) according to the second embodiment will be described with reference to FIGS. 5 and 6.

[0099] The high voltage pulse generator (400) operates repeatedly in the order of mode 1 to mode 5.

[0100] For reference, the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), and the fourth capacitor (C4) connected in parallel to the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) respectively are intended to provide dynamic balance of the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) so ​​that a high voltage is not applied biasedly to at least one of the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) during the on / off switching process of the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4).

[0101] In addition, the first resistor element (R1), the second resistor element (R2), the third resistor element (R3), and the fourth resistor element (R4) connected in parallel to the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) respectively are intended to provide a static balance of the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) so ​​that a high voltage is not applied biasedly to at least one of the first switch (SW1), the second switch (SW2), the third switch (SW3), and the fourth switch (SW4) during the initial power-on process.

[0102] In addition, the first balance capacitor (Cd1) and the second balance capacitor (Cd2), which are connected in parallel to each end of the first diode (D1) and the second diode (D2), respectively, are intended to provide dynamic balance so that a high voltage is not applied biasedly to either the first diode (D1) or the second diode (D2) during the on / off switching process of the diodes.

[0103] As shown in FIGS. 5 and 6a, when the first gate input signal (Gsw1) of the first switch (SW1) and the third gate input signal (Gsw3) of the third switch (SW3) each become 1 (i.e., the first switch (SW1) and the third switch (SW3) are each turned ON) and the second gate input signal (Gsw2) of the second switch (SW2) and the fourth gate input signal (Gsw4) of the fourth switch (SW4) each become 0 (i.e., the second switch (SW2) and the fourth switch (SW4) are each turned OFF), the high-voltage pulse generator (400) enters mode 1.

[0104] In mode 1, the output voltage Vout becomes the same voltage V1 as the voltage V1 of the first voltage source (VS1).

[0105] As illustrated in FIGS. 5 and 6b, when the first gate input signal (Gsw1) and the third gate input signal (Gsw3) are each changed to 0 in mode 1 and the first switch (SW1) and the third switch (SW3) are each turned OFF, the high-voltage pulse generator (400) becomes mode 2. That is, when the first switch (SW1) and the third switch (SW3) are each turned ON and the second switch (SW2) and the fourth switch (SW4) are each turned OFF, and the first switch (SW1) and the third switch (SW3) are each turned OFF, mode 2 is entered.

[0106] In Fig. 6b, the impedances of R1, R2, R3, and R4 are greater than the impedances of C1, C2, C3, and C4, respectively, and the DC power of VS1 and VS2 is substantially blocked from the output terminals by C1, C2, C3, and C4, so the current paths connecting R1, R2, R3, R4, VS1, and VS2 are omitted and shown.

[0107] During Mode 1, the energy stored in the inductor (L) gradually decreases Vout due to LC resonance by the inductor (L) and the composite capacitance in Mode 2. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitances of the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), and the fourth capacitor (C4) and the parasitic capacitance. Vout decreases due to LC resonance in which the first capacitor (C1) and the third capacitor (C3) are charged and the second capacitor (C2) and the fourth capacitor (C4) are discharged via the parasitic capacitor (Cp), and this decrease may continue until Mode 3.

[0108] As shown in FIGS. 5 and 6c, when in mode 2, the second gate input signal (Gsw2) and the fourth gate input signal (Gsw4) are each 1, and the second switch (SW2) and the fourth switch (SW4) are each turned ON, the high-voltage pulse generator (400) becomes mode 3. That is, when the first switch (SW1) to the fourth switch (SW4) are OFF and the second switch (SW2) and the fourth switch (SW4) are each turned ON, mode 3 is entered.

[0109] In mode 3, the output voltage Vout becomes -V2, which is the same value as the voltage of the second voltage source (VS2).

[0110] As illustrated in FIGS. 5 and 6d, when the second gate input signal (Gsw2) and the fourth gate input signal (Gsw4) are each changed to 0 in mode 3, and the second switch (SW2) and the fourth switch (SW4) are each turned OFF, the high-voltage pulse generator (400) becomes mode 4. That is, when the first switch (SW1) and the third switch (SW3) are OFF and the second switch (SW2) and the fourth switch (SW4) are ON, and the second switch (SW2) and the fourth switch (SW4) are each turned OFF, mode 4 is entered.

[0111] During Mode 3, the (-) energy stored in the inductor (L) gradually increases Vout by the LC resonance by the composite capacitance and the inductor (L) in Mode 4. The composite capacitance may be an equivalent capacitance between the ground and the output terminal (Nout) including the capacitances of the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), and the fourth capacitor (C4) and the parasitic capacitance. The first capacitor (C1) and the third capacitor (C3) are discharged via the parasitic capacitor (Cp) and the Vout monotonically increases by the LC resonance that charges the second capacitor (C2) and the fourth capacitor (C4), and this increase may continue until Mode 1.

[0112] Meanwhile, the parallel-connected capacitors may be Ci1=Ci2=C1=C2=C3=C4, and the parallel-connected resistor elements may be R1=R2=R3=R4. Here, the values ​​of the parallel-connected capacitors and the parallel-connected resistor elements may each have appropriately tuned values ​​to achieve ZVS.

[0113] Here, the L value can be determined by mathematical expression 2 similarly to the first embodiment, and i of mathematical expression 2 in the second embodiment Lpk The value can be determined as in mathematical formula 7.

[0114]

[0115] Here, △V is the voltage difference between the top and bottom of the output waveform, which can be calculated as V1+V2. Also, C PT represents the (+) terminal equivalent capacitance including the capacitance of the first capacitor (C1), the third capacitor (C3) and the parasitic capacitance between the output terminal (Nout) and the first node (N1), and C NTrepresents the (-) terminal equivalent capacitance including the capacitance of the second capacitor (C2), the fourth capacitor (C4) and the parasitic capacitance between the output terminal (Nout) and the second node (N2). Co represents a known capacitance value for the corresponding chamber (CB).

[0116] In this embodiment, each equivalent capacitance can be obtained by measurement.

[0117] Also, the maximum resonant current i c_max and minimum value i c_min The relationship between Lc and Cc5 is as shown in mathematical expression 6.

[0118] As shown in Fig. 5, when the first switch (SW1) to the fourth switch (SW4) are OFF in mode 4, mode 1 is obtained by turning the first switch (SW1) and the third switch (SW3) ON, respectively.

[0119] In this way, the high voltage pulse generator (400) can control the first switch (SW1) to the fourth switch (SW4) to sequentially turn on / off so that modes 1 to 4 are sequentially generated.

[0120] The high voltage pulse generator (400) can also be controlled to switch to mode 5 after mode 3.

[0121] As shown in Fig. 5, in mode 3, when the first switch (SW1) and the third switch (SW3) are OFF and the second switch (SW2) and the fourth switch (SW4) are ON, mode 5 is achieved by changing the first switch (SW1) to ON and the fourth switch (SW4) to OFF.

[0122] As illustrated in FIGS. 5 and 6e, in mode 5, the output terminal Nout is connected to the reference terminal via the first diode (D1) and the first switch (SW1), and to the reference terminal via the second diode (D2) and the second switch (SW2), so that Vout becomes 0 V. At this time, there is a process of consuming energy by LC resonance in the process of Vout switching from -V2 to 0 V, but for the sake of simplicity, the output voltage when switching from mode 3 to mode 5 is illustrated as in FIG. 5.

[0123] As illustrated in Fig. 5, in mode 5, when the first switch (SW1) and the second switch (SW2) are ON and the third switch (SW3) and the fourth switch (SW4) are OFF, mode 1 is obtained by changing the second switch (SW2) to OFF and the third switch (SW3) to ON. Here, too, there is a process of accumulating energy by LC resonance in the process of Vout switching from 0 V to V1, but for simplicity, the output voltage in the case of switching from mode 5 to mode 1 is illustrated as in Fig. 5.

[0124] Fig. 7 is a block diagram showing a high-voltage pulse generator (700) and a capacitive load (200) according to the third embodiment.

[0125] The high-voltage pulse generator (700) according to the third embodiment is a high-voltage pulse generator (400) according to the second embodiment in which the fifth capacitor (C5) is omitted and one end of the inductor (L) is directly connected to the reference terminal (Nref).

[0126] The operating waveform of the high voltage pulse generator (700) according to the third embodiment is substantially the same as the operating waveform of the high voltage pulse generator (400) according to the second embodiment illustrated in FIG. 5.

[0127] In addition, the flow of current on the circuit according to each operation mode of the high voltage pulse generator (700) is substantially the same as the flow of current on the circuit according to each operation mode of the high voltage pulse generator (400) illustrated in FIG. 6.

[0128] However, compared to the second embodiment, in the third embodiment, the output voltage Vout increases rapidly by the inductor (L) in mode 2, and the output voltage Vout decreases rapidly by the inductor (L) in mode 4, so that system stability can be increased.

[0129] In the third embodiment, the value of the inductor (L) may have a similar value to that in the second embodiment.

[0130] The first to fourth switches (SW1, SW2, SW3, SW4) may be power semiconductor devices. A power semiconductor device is a semiconductor device used for converting or controlling power, and can be implemented as a device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).

[0131] Figure 8 is a drawing showing an example of a pulse generation circuit implemented by connecting multiple high-voltage pulse generation devices in parallel.

[0132] As illustrated in Fig. 8, the pulse generation circuit (800) includes a controller (810) and a plurality of high-voltage pulse generation devices (820). Here, the plurality of high-voltage pulse generation devices (820) include a high-voltage pulse generation device (100), a high-voltage pulse generation device (400), and a high-voltage pulse generation device (700).

[0133] Each reference terminal (Nref) of the plurality of high-voltage pulse generators (100, 400, 700) is connected to ground, and each output terminal (Nout) of the plurality of high-voltage pulse generators (100, 400, 700) is connected in parallel to the chamber (200). Accordingly, pulses generated by controlling each of the plurality of high-voltage pulse generators (100, 400, 700) by the controller (810) are output to the chamber (200).

[0134] Fig. 9 is a flowchart illustrating a high-voltage pulse generation method according to the present embodiment.

[0135] Hereinafter, a high-voltage pulse generation method according to the present embodiment will be described with reference to FIGS. 1 to 8.

[0136] The controller (810) controls the on / off of the first switch (SW1) and the second switch (SW2) of the high voltage pulse generator (100), or controls the on / off of the first to fourth switches (SW1, SW2, SW3, SW4) of the high voltage pulse generator (400, 700).

[0137] When operating the high voltage pulse generator (100), the controller (810) turns on the first switch (SW1) and turns off the second switch (SW2) to enter mode 1 (S910).

[0138] After the mode 1 state is performed for a certain period of time, the controller (810) turns off the first switch (SW1) to enter mode 2 (S920).

[0139] After a certain period of time after entering mode 2, the controller (810) turns on the second switch (SW2) to enter mode 3 (S930).

[0140] After a certain period of time after entering mode 3, the controller (810) turns off the second switch (SW2) to enter mode 4 (S940).

[0141] After a certain period of time after entering mode 4, the controller (810) turns on the first switch (SW1) to enter mode 1 (S950).

[0142] In this way, the controller (810) controls the on / off of the first switch (SW1) and the second switch (SW2) to control the high voltage pulse generator (100) to operate in the order of mode 1 to mode 4.

[0143] Meanwhile, when operating the high-voltage pulse generator (400, 700), in steps S910 to S950, the controller (810) additionally controls the on / off of the third switch (SW3) and the fourth switch (SW4) in addition to the on / off control of the first switch (SW1) and the second switch (SW2). In other words, the controller (810) additionally turns on the third switch (SW3) and turns off the fourth switch (SW4) in step S910, additionally turns off the third switch (SW3) in step S920, additionally turns on the fourth switch (SW4) in step S930, additionally turns off the fourth switch (SW4) in step S940, and additionally turns on the third switch (SW3) in step S950.

[0144] In addition, when operating the high voltage pulse generator (400, 700), the controller (810) may control mode 5 to be performed in the next step of mode 3 and control mode 1 to be performed in the single-tone step of mode 5.

[0145] FIG. 10 is a block diagram illustrating a semiconductor device manufacturing apparatus (1000) according to one embodiment of the present disclosure.

[0146] Referring to FIG. 10, a semiconductor device manufacturing device (1000) may include a chamber (200) and a pulse generation circuit (800).

[0147] A ceramic cover (210) is placed in the upper area of ​​the chamber (200), and a plurality of induction coils (220) are placed on the outside of the ceramic cover (210).

[0148] A bottom electrode (230) is placed in the lower region of the chamber (200), and a wafer (W) can be placed on top of the bottom electrode (230).

[0149] The lower electrode (230) may be an electrostatic chuck (ESC) that supports a wafer (W) by absorbing it using electrostatic force. In addition, the chamber (200) may include a gas supply unit (not shown) and a gas exhaust unit (not shown), and the gas supply unit (not shown) may supply a reaction gas into the chamber (200) and exhaust the gas through the gas exhaust unit (not shown) to maintain the chamber (200) in a vacuum state.

[0150] The RF power generator (1010) can generate RF power in the form of a sinusoidal wave (i.e., first power) and provide the generated first power to the induction coil (220). The first power is power for generating plasma and may be referred to as source power. The first power generator (1010) may be a device that generates high-frequency power in the form of a sinusoidal wave of several tens of MHz.

[0151] The semiconductor device manufacturing device (1000) is a semiconductor facility to which the ICP (Inductively Coupled Plasma) method is applied.

[0152] When RF power is supplied to the induction coil (220), an electric field is generated within the chamber (200) by the induction coil (220), and free electrons generated within the chamber (200) are accelerated in concentric circles by the magnetic field. The free electrons within the chamber (200) do not collide with the inner wall of the chamber (200) but continue to collide with neutral particles to form plasma, thereby forming a high-density plasma.

[0153] A high density plasma (HDP) can be formed within the chamber (200) by a magnetic field generated by the induction coil (220), and the ion density of the plasma can be controlled by controlling the intensity of the first power.

[0154] The pulse generation circuit (800) can generate a pulse (i.e., second power) in a non-sinusoidal form. The second power is power for controlling the ion energy of the plasma.

[0155] The pulse generation circuit (800) selects one of a plurality of high-voltage pulse generation devices (100, 400, 700) under the control of the controller (810) to generate a pulse. The controller (810) controls the on or off of each switch in the plurality of high-voltage pulse generation devices (100, 400, 700) so that one suitable for a semiconductor process is selected among the plurality of high-voltage pulse generation devices (100, 400, 700), thereby generating a pulse from a specific high-voltage pulse generation device (100, 400, 700) in the pulse generation circuit (800). The pulse generated from the pulse generation circuit (800) is provided to the lower electrode (230) as second power.

[0156] When a second power is supplied to the lower electrode (230), a voltage can be induced in the wafer (W) placed on the lower electrode (230). Accordingly, the voltage of the wafer (W) can be controlled according to the second power, and accordingly, the ion energy of the plasma generated within the chamber (200) can be controlled.

[0157] A reaction gas can be diffused within the chamber (200) and converted into plasma by a first power applied to the induction coil (220) and a second power applied to the lower electrode (230). The plasma comes into contact with the surface of the wafer (W) and reacts physically or chemically, and through this reaction, wafer processing processes such as plasma annealing, etching, plasma-enhanced chemical vapor deposition, physical vapor deposition, and plasma cleaning can be performed.

[0158] When the semiconductor device manufacturing device (1000) is used in an etching process, the reaction gas is converted into plasma by high-frequency discharge on the upper portion of the lower electrode (230), and the film to be processed on the wafer (W) can be etched into a desired pattern by radicals, electrons, and ions activated by the plasma. According to the present embodiment, by precisely controlling the radicals, electrons, and ions of the plasma, the etching performance such as the etching rate, aspect ratio, critical dimension of the etching pattern, profile of the etching pattern, and selectivity can be improved.

[0159] Meanwhile, the various functions or methods described in the present disclosure may also be implemented as instructions stored on a non-transitory storage medium that can be read and executed by one or more processors. Non-transitory storage media include, for example, all types of storage devices that store data in a form readable by a computer system. For example, non-transitory storage media include storage media such as Erasable Programmable Read Only Memory (EPROM), flash drives, optical drives, magnetic hard drives, and solid-state drives (SSDs).

[0160] It should be understood that the exemplary embodiments described above can be implemented in many different ways. The functions described in one or more examples can be implemented in hardware, software, firmware, or any combination thereof. It should be understood that the functional components described herein are labeled as "units" to further emphasize their implementation independence.

[0161] The above description is merely an example of the technical idea of ​​the present embodiment, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present embodiment. Therefore, the present embodiments are not intended to limit the technical idea of ​​the present embodiment, but rather to explain it, and the scope of the technical idea of ​​the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be interpreted by the claims below, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of rights of the present embodiment.

Claims

1. A first voltage source having a (+) terminal connected to the first node and a (-) terminal connected to the reference terminal; A first input capacitor connected in parallel to the first voltage source; A second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to the second node; A second input capacitor connected in parallel to the second voltage source; A first switch connected between the output terminal and the first node; a second switch connected between the output terminal and the second node; and An inductor connected between the reference terminal and the output terminal A high voltage pulse generator comprising:

2. In paragraph 1, A high voltage pulse generator further comprising a fifth capacitor connected in series with the inductor between the reference terminal and the output terminal.

3. In paragraph 1, In the first mode, the first switch is turned on and the second switch is turned off, In the second mode, the first switch and the second switch are turned off, In the third mode, the first switch is turned off and the second switch is turned on, A high voltage pulse generator, characterized in that in the fourth mode, the first switch and the second switch are turned off.

4. In paragraph 3, A high voltage pulse generator, characterized in that the above modes are repeated in the order of the first mode, the second mode, the third mode, and the fourth mode.

5. In paragraph 1, The other end of the first switch is connected to the output terminal, and one end of the second switch is connected to the output terminal. A third switch connected between the first node and one end of the first switch; A fourth switch connected between the second node and the other end of the second switch; A first diode having an anode connected to the reference terminal and a cathode connected to one end of the first switch; and A high voltage pulse generator further comprising a second diode having a cathode connected to the reference terminal and an anode connected to the other terminal of the second switch.

6. In paragraph 5, In the first mode, the first switch and the third switch are turned on and the second switch and the fourth switch are turned off. In the second mode, the first switch, the second switch, the third switch and the fourth switch are turned off, In the third mode, the first switch and the third switch are turned off and the second switch and the fourth switch are turned on. In the fourth mode, the first switch, the second switch, the third switch and the fourth switch are turned off, A high voltage pulse generator, characterized in that in the fifth mode, the first switch and the second switch are turned on and the third switch and the fourth switch are turned off.

7. In paragraph 6, In a section where a high voltage pulse toggles to the output terminal is generated, the first mode, the second mode, the third mode, and the fourth mode are repeated, A high voltage pulse generator characterized in that the fifth mode is set in a section for fixing the voltage level of the output terminal.

8. In paragraph 5, A high voltage pulse generator further comprising a fifth capacitor connected in series with the inductor between the reference terminal and the output terminal.

9. In paragraph 5, A high-voltage pulse generator, characterized in that each of the first to fourth switches has a resistor element and a capacitor connected in parallel.

10. In paragraph 9, The value Lc of the above inductor is given by the following mathematical formula , is produced by, Here, V L is the voltage between the two terminals of the inductor, Tsw is the switching period, and T dead is the switching dead time during which all of the first to fourth switches are turned off, △V is the peak-to-peak voltage of the output waveform, and C PT represents the equivalent capacitance between the output terminal and the first node, and C NT A high-voltage pulse generator, characterized in that is an equivalent capacitance between the output terminal and the second node, and Co is a capacitance of a chamber connected to the output terminal.

11. In paragraph 5, A high voltage pulse generator, characterized in that a capacitor is connected in parallel to each of the first and second diodes.

12. Including a high voltage pulse generator and chamber, The above high voltage pulse generator, A first voltage source having a (+) terminal connected to the first node and a (-) terminal connected to the reference terminal; A first input capacitor connected in parallel to the first voltage source; A second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to the second node; A second input capacitor connected in parallel to the second voltage source; A first switch connected between the output terminal and the first node; a second switch connected between the output terminal and the second node; and An inductor connected between the reference terminal and the output terminal A semiconductor device manufacturing apparatus characterized by including:

13. A first voltage source having a (+) terminal connected to the first node and a (-) terminal connected to the reference terminal; A second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to the second node; A plurality of first switches connected in series between the output terminal and the first node; A plurality of second switches connected in series between the output terminal and the second node; A plurality of first capacitors connected in parallel to each of the plurality of first switches; A plurality of second capacitors connected in parallel to each of the plurality of second switches; A plurality of first resistance elements connected in parallel to each of the plurality of first switches; a plurality of second resistor elements connected in parallel to each of the plurality of second switches; and An inductor connected between the reference terminal and the output terminal A high voltage pulse generator comprising:

14. In paragraph 13, A high voltage pulse generator further comprising a fifth capacitor connected in series with the inductor between the reference terminal and the output terminal.

15. In paragraph 13, a first input capacitor connected in parallel to the first voltage source; and A high voltage pulse generator further comprising a second input capacitor connected in parallel to the second voltage source.

16. In paragraph 13, In the first mode, the plurality of first switches are turned on and the plurality of second switches are turned off, In the second mode, the plurality of first switches and the plurality of second switches are turned off, In the third mode, the plurality of first switches are turned off and the plurality of second switches are turned on, A high voltage pulse generator, characterized in that in the fourth mode, the plurality of first switches and the plurality of second switches are turned off.

17. In paragraph 16, A high voltage pulse generator, characterized in that the above modes are repeated in the order of the first mode, the second mode, the third mode, and the fourth mode.

18. A first voltage source having a (+) terminal connected to the first node and a (-) terminal connected to the reference terminal; A second voltage source having a (+) terminal connected to the reference terminal and a (-) terminal connected to the second node; A plurality of first switches connected in series between the output terminal and the third node; A plurality of third switches connected in series between the third node and the first node; A plurality of second switches connected in series between the output terminal and the fourth node; A plurality of fourth switches connected in series between the fourth node and the second node; A plurality of first capacitors connected in parallel to each of the plurality of first switches; A plurality of second capacitors connected in parallel to each of the plurality of second switches; A plurality of third capacitors connected in parallel to each of the plurality of third switches; A plurality of fourth capacitors connected in parallel to each of the plurality of fourth switches; A first diode having an anode connected to the reference terminal and a cathode connected to the third node; A second diode having a cathode connected to the reference terminal and an anode connected to the fourth node; and An inductor connected between the reference terminal and the output terminal A high voltage pulse generator comprising:

19. In paragraph 18, A plurality of third resistor elements connected in parallel to each of the plurality of third switches; and A high voltage pulse generator further comprising a plurality of fourth resistor elements connected in parallel to each of the plurality of fourth switches.

20. In paragraph 19, a plurality of first resistor elements connected in parallel to each of the plurality of first switches; and A high voltage pulse generator further comprising a plurality of second resistance elements connected in parallel to each of the plurality of second switches.

21. In paragraph 18, A high voltage pulse generator further comprising a fifth capacitor connected in series with the inductor between the reference terminal and the output terminal.

22. In paragraph 18, a first input capacitor connected in parallel to the first voltage source; and A high voltage pulse generator further comprising a second input capacitor connected in parallel to the second voltage source.

23. In paragraph 18, In the first mode, the plurality of first switches and the plurality of third switches are turned on and the plurality of second switches and the plurality of fourth switches are turned off. In the second mode, the plurality of first switches, the plurality of second switches, the plurality of third switches and the plurality of fourth switches are turned off, In the third mode, the plurality of first switches and the plurality of third switches are turned off and the plurality of second switches and the plurality of fourth switches are turned on. In the fourth mode, the plurality of first switches, the plurality of second switches, the plurality of third switches and the plurality of fourth switches are turned off, A high voltage pulse generator, characterized in that in the fifth mode, the plurality of first switches and the plurality of second switches are turned on and the plurality of third switches and the plurality of fourth switches are turned off.

24. In paragraph 23, In a section where a high voltage pulse toggles to the output terminal is generated, the first mode, the second mode, the third mode, and the fourth mode are repeated, A high voltage pulse generator, characterized in that the fifth mode is set in a section for fixing the voltage level of the output terminal.

25. In paragraph 18, A high voltage pulse generator, characterized in that a capacitor is connected in parallel to each of the first diode and the second diode.

26. A first voltage source providing a positive voltage higher than the voltage level of the reference terminal to the first node; A second voltage source providing a negative voltage lower than the voltage level of the reference terminal to the second node; A first capacitor bypassed in the first mode and connected between the first node and the output terminal in the second to fourth modes; A second capacitor bypassed in the third mode and connected between the second node and the output node in the first, second and fourth modes; and Including an inductor connected between the reference terminal and the output terminal, A high voltage pulse generator, characterized in that in the first mode, the first node and the output terminal are electrically connected, and in the third mode, the second node and the output terminal are electrically connected.

27. In paragraph 26, a first resistor element connected in parallel to the first capacitor; and A high voltage pulse generator further comprising a second resistor element connected in parallel to the second capacitor.

28. In paragraph 27, A high voltage pulse generator further comprising a fifth capacitor connected in series with the inductor between the reference terminal and the output terminal.

29. In paragraph 28, A high voltage pulse generator, characterized in that the above modes are repeated in the order of the first mode, the second mode, the third mode, and the fourth mode.

30. A first voltage source providing a positive voltage higher than the voltage level of the reference terminal to the first node; A second voltage source providing a negative voltage lower than the voltage level of the reference terminal to the second node; A first capacitor bypassed in the first and fifth modes and connected between the third node and the output terminal in the second to fourth modes; A third capacitor bypassed in the first mode and connected between the first node and the third node in the second to fifth modes; A second capacitor bypassed in the third and fifth modes and connected between the output terminal and the fourth node in the first, second and fourth modes; A fourth capacitor bypassed in the third mode and connected between the fourth node and the second node in the first, second, fourth and fifth modes; An inductor connected between the reference terminal and the output terminal; A first diode that supplies current from the reference terminal to the third node when the voltage level of the reference terminal is higher than the voltage level of the third node; and When the voltage level of the fourth node is higher than the voltage level of the reference terminal, a second diode is included that supplies current from the fourth node to the reference terminal, A high voltage pulse generator, characterized in that in the first mode, the first node and the output terminal are electrically connected, and in the third mode, the second node and the output terminal are electrically connected.

31. In paragraph 30, A first resistor element connected in parallel to the first capacitor; A second resistor element connected in parallel to the second capacitor; A third resistor element connected in parallel to the third capacitor; A fourth resistor element connected in parallel to the fourth capacitor; A first balance capacitor connected in parallel to the first diode; a second balance capacitor connected in parallel to the second diode; and A high voltage pulse generator further comprising a fifth capacitor connected in series with the inductor between the reference terminal and the output terminal.

32. In paragraph 30, In a section where a high voltage pulse toggles to the output terminal is generated, the first mode, the second mode, the third mode, and the fourth mode are repeated, A high voltage pulse generator, characterized in that the fifth mode is set in a section for fixing the voltage level of the output terminal.

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