Low-rate noise shaping vector quantizer for audio coding

Abstract

A method of operating a two-stage vector quantizer comprising receiving an input target vector, performing a search for the best matching code vector of an initial codebook and determining an MSE distortion for the initial codebook. If the MSE distortion of the initial codebook is below a first threshold, the initial codebook is selected. If the MSE distortion is above the first threshold, a search is performed for the best matching code vector of an outlier codebook. The method comprises determining an MSE distortion for the outlier codebook, selecting a codebook giving the lowest MSE distortion, and performing a first stage vector quantization on the input target vector using the selected codebook. If the MSE distortion of the selected codebook is above the second threshold, a first stage residual is calculated and a best matching code vector is searched for the residual using a second stage of the two-stage VQ.

Description

LOW-RATE NOISE SHAPING VECTOR QUANTIZER FOR AUDIO CODINGTECHNICAL FIELD

[0001] The present disclosure is related to communication systems and more particularly toa low-rate noise-shaping vector quantizer for audio coding.BACKGROUND

[0002] Vector quantization (VQ) has been widely used in the development of datacompression technologies. VQ is an efficient data compression technique, which constructs a plurality of scalar data columns into a vector and performs overall quantization in the vector space. As a result, the data is compressed while not much information is lost.

[0003] A generic 37-bit dimension of 24 coefficients / vector trained stochastic codebookwould require: 237 *24 = 3*240 = 3.29 *1012 Words (Word16) of ROM storage. A generic 30-bittrained stochastic codebook for 16-coefficent vectors would require: 230*16 = 234= 17.17 *109Words (Word16 assuming 16-bit coefficients) of ROM storage. Designing, searching and storing such a codebook is not practical in most real-world implementations.

[0004] In the 1980s and 1990s, the concepts of Split-VQs and Multistage VQs weredeveloped to reach more reasonable storage and search complexities, while still maintaining substantial vector quantization gains. Coefficient correlation properties are still properly exploited in the training of these VQs.

[0005] An example Split-VQ is the AMRWB ISF-VQ described in the 3rd GenerationPartnership Project, 3GPP, technical standard, TS, 26.190, section "5.2.5 Quantization of the ISP coefficients." There the total number of coefficients are 16, which are split into 9 coefficients (8bits) and 7 coefficients (8 bits) in the first stage, and in the second stage they are further splitinto {3,3,3} coefficients with (6,7,7) bits and a higher stage2 split of {3,4} coefficients with (5,5) bits, in total 8+8+6+7+7+5+5 = 46 bits are used, the total number of ROM table entries then becomes in Matlab syntax: sum((2.^

[0088] ).*

[0097] ) + sum((2.^

[0677] ).*

[0333] ) + sum((2.^

[55] ).*

[0034] )= 5.2 kW (Word16), i.e., a much more realistic Table ROM number.SUMMARY

[0006] According to a first aspect there is provided a method of operating a two-stage vectorquantizer, VQ. The method comprises receiving an input target vector comprising a plurality ofvalues. Furthermore, the method comprises performing a search for the best matching code vector of an initial codebook, CBB, determining an MSE distortion for the initial codebook, and determining whether the MSE distortion of the initial codebook is below or above a first threshold.In addition, if the MSE distortion is below the first threshold, the initial codebook is selected, andif the MSE distortion is above the first threshold, a search is performed for the best matching code vector of an outlier codebook, CBC. The method further comprises determining an MSE distortion for the outlier codebook, selecting a codebook giving the lowest MSE distortion, and performing a first stage vector quantization on the input target vector using the selected codebook to obtain aquantized first stage vector. In addition, it is further determined whether the MSE distortion of theselected codebook is below or above a second threshold, and if the MSE distortion of the selectedcodebook is above the second threshold, a first stage residual is calculated based on the initialcodebook and a best matching code vector is searched for the residual using a second stage of thetwo-stage VQ.

[0007] According to a second aspect there is provided an audio encoder comprising a two-stage vector quantizer, VQ, configured to perform the method according to the first aspect.

[0008] According to a third aspect there is provided a two-stage vector quantizer, VQ,configured to receive an input target vector comprising a plurality of values. Furthermore, thetwo-stage vector quantizer comprises performing a search for the best matching code vector of aninitial codebook, CBB, determining an MSE distortion for the initial codebook, and determining whether the MSE distortion of the initial codebook is below or above a first threshold. In addition,if the MSE distortion is below the first threshold, the initial codebook is selected, and if the MSEdistortion is above the first threshold, a search is performed for the best matching code vector ofan outlier codebook, CBC. The two-stage vector quantizer further comprises determining an MSEdistortion for the outlier codebook, selecting a codebook giving the lowest MSE distortion, and performing a first stage vector quantization on the input target vector using the selected codebookto obtain a quantized first stage vector. In addition, it is further determined whether the MSEdistortion of the selected codebook is below or above a second threshold, and if the MSE distortionof the selected codebook is above the second threshold, a first stage residual is calculated basedon the initial codebook and a best matching code vector is searched for the residual using a secondstage of the two-stage VQ.

[0009] According to a fourth aspect there is provided an audio encoder comprising the two-stage vector quantizer according to the third aspect.

[0010] According to a fifth aspect there is provided a method of operating an encoder, themethod comprising receiving a scale factor target signal, selecting a codebook capable ofincluding an entry modified by vector polarity and vector order reversal, and performing stage1vector quantization on the scale factor target signal using the codebook.

[0011] According to a sixth aspect there is provided a method of operating a decoder, themethod comprising receiving an index, selecting a codebook capable of including an entrymodified by vector polarity and vector order reversal, and generating a quantized scale factorsignal from the index using the codebook.

[0012] According to a seventh aspect there is provided an encoder adapted to perform any ofthe operations according to the fifth aspect.

[0013] According to an eighth aspect there is provided a computer program comprisingprogram code to be executed by processing circuitry of an encoder, whereby execution of the program code causes the encoder to perform any of the operations according to the first or fifth aspect.

[0014] According to a nineth aspect there is provided a computer program product comprisinga non-transitory storage medium including program code to be executed by processing circuitry of an encoder, whereby execution of the program code causes the encoder to perform any of the operations according to the first or fifth aspect.

[0015] According to a tenth aspect there is provided a decoder adapted to perform any of theoperations according to the sixth aspect.

[0016] According to an eleventh aspect there is provided a computer program comprisingprogram code to be executed by processing circuitry of a decoder, whereby execution of the program code causes the decoder to perform any of the operations according to the sixth aspect.

[0017] According to a twelfth aspect there is provided a computer program productcomprising a non-transitory storage medium including program code to be executed by processing circuitry of a decoder, whereby execution of the program code causes the decoder to perform any of the operations according to the sixth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understandingof the disclosure, illustrate certain non-limiting embodiments of inventive concepts. In the drawings:

[0019] FIG. 1 is a schematic diagram illustrating an example of a 5th generation (“5G”)network;

[0020] FIG. 2 is a block diagram illustrating an example of an operating environment of anencoder in accordance with some embodiments;

[0021] FIG. 3 is a block diagram illustrating an example of an audio encoder in accordancewith some embodiments;

[0022] FIG. 4 is a block diagram illustrating an example of an audio decoder in accordancewith some embodiments;

[0023] FIG. 5 is a block diagram illustrating an example of a host in accordance with someembodiments;

[0024] FIG. 6 is a block diagram illustrating an example of an exemplary virtualizationenvironment in which some components of an encoder or decoder or an encoder or decoder may be implemented in accordance with some embodiments;

[0025] FIG. 7 is a block diagram illustrating an example of an encoder side system inaccordance with some embodiments;

[0026] FIG. 8 is a block diagram illustrating an example of a decoder side system inaccordance with some embodiments;

[0027] FIG. 9 is a block diagram illustrating an example of an encoder with low-rate SNS-VQ analysis in accordance with some embodiments;

[0028] FIG. 10 is a block diagram illustrating an example of a decoder with low-rate SNS-VQ decoding and synthesis in accordance with some embodiments;

[0029] FIG. 11 is a flow chart illustrating an example of a procedure for LR SNS Stage1 Bvector reconstruction in accordance with some embodiments;

[0030] FIG. 12 is a flow chart illustrating an example of operations performed by anencoder in accordance with some embodiments; and

[0031] FIG. 13 is a flow chart illustrating an example of operations performed by a decoderin accordance with some embodiments. DETAILED DESCRIPTION

[0032] A lower complexity alternative to the Trained Stochastic (SplitVQ, MSVQ) codebookis codebooks with a given algebraic or lattice structure that is easier to search, but they will have suboptimal Voronoi regions and typically only be efficient for certain input vector distribution(e.g., Gaussian or Laplacian) and further, efficient indexing schemes (to construct the finalCodebook vector from the bit stream) may become costly, and even further the lattice structure are typically not very flexible in terms of vector length. Examples of lattice Quantizers are D8- lattice, RE8-lattice, and PVQ (Pyramid VQ), Spherical PVQ is also used in EVS and IETF-OPUS to encode Gaussian sources.

[0033] There currently exist certain challenge(s). The current solution for the first stage(and subsequent stages) of an MS-VQ typically requires a large storage space. For example, in the case of Enhanced Voice Services (EVS) the FD-CNG VQ in the first stage uses 128 levels (7bits) with 24 coefficients each, resulting in (128x24)=3072 kW (Word 16) of ROM storage, inthe EVS- FD-CNG-VQ (Enhanced Voice Services - Frequency Domain – Comfort NoiseGeneration – Vector Quantization) implementation this corresponds to 6 kBytes, where eachByte is 8 bits.

[0034] The absence of an efficient structure in the first stage makes it very hard to providelow storage space and an accompanying low complex search solution.

[0035] For ETSI- LC3plus (ETSI TS 103634) 10 ms frame duration operation mode, theSpectral Noise Shaping (SNS) VQ is using 38 bits for 16 coefficients resulting in a bits percoefficient rate R of 2.375 bits / coefficient. For shorter frame durations like 1.25 ms, thecorresponding bit rate is resulting in a lot of overhead. For 1.25 ms operations the quantizedSNS parameters (noise-shaping scale factors) are sent 8 times more often than for 10 msoperation The first stage Split-VQ in ETSI- LC3plus 10 ms frame approach results in lowROM, but the Split-VQ is not able to compress the input as efficiently as a full non-split VQ, which can utilize the correlation between the coefficient in different split regions in the VQ.

[0036] Some existing procedures include a kind of amplitude reuse in an initial VQ stagethrough training on absolute value vectors (also called absolute vectors), storing absolute vectorsand then using the stored absolute vectors in combination with transmission of the polarity (sign) for each coefficient to save ROM and search complexity.

[0037] Some existing procedures include a higher stage reuse MSVQ lower stage throughscaling of each vector with a common or individual scaling factor and apply indirect addressingto identify vectors from earlier stages and a scaling factor for each stage or for each CB vector tosave some ROM and still maintain efficiency. Still, these procedures have to save the completefirst stage as a very large ROM table for the subsequent stages.

[0038] The proposed VQ-scheme employs a Variable Bit Rate (VBR) approach that onlyconditionally searches outlier vectors in an alternative first stage and only conditionally appliesand transmits a second stage. The previous SNS-VQ solutions (like LC3plus 10 ms) provide afixed rather high bit rate R=2.375, while the proposed VBR SNS-VQ provides R of 0.625 bits / coefficient about 90% of the time and an R of 1.84 bits / coefficient about 10% of the time, and thus enabling higher quality compression than the legacy SNS-VQ. The saved bits from the proposed VBR SNS-VQ will be spent on better quantization of the actual spectrum of the input audio signal.

[0039] One important part of the bit rate reduction is that the first stage outlier codebook ishandling voiced pitch signals in an efficient way by utilizing the available voicing information at the decoder side. The decoder has a ternary information if the low frequency band, 0…6.4 kHzhas low, medium or high long-term correlation. The first stage outlier CB is using that information (in the encoder and decoder) to apply different SNS-VQ mean vectors for thevarying degrees of voicing. This results in a lower ROM use, and a lower complexity for theoutlier codebook, in comparison to not using the ternary voicing information.

[0040] Voicing based mean prediction of an outlier codebook to save ROM and WMOPShas not been identified in prior art.

[0041] To always analyze both stage1 options (Normal and Outliers) in the worst-caseanalysis path consumes a lot of WMOPS complexity.

[0042] A refined method to save peak WMOPS is proposed by analyzing the highfrequency range properties of each input vector of the input SNS scale factors, in relation to offline prepared parameters characterizing the normal and outlier codebooks, and then pre-select a single VQ option (Normal or Outlier).

[0043] In the prior art there has been no pre-selection of normal vs outlier VQ codebooks,to save PEAK complexity. Thus, one would always run both VQs in the worst-case analysis path.

[0044] The legacy solution stage2 VQ uses Gain-Shape product quantizer based on thealgorithmic Pyramid vector quantization PVQ and enumeration. The issue with PVQ is that it consumes quite a lot of information to position the location of each stacked unit pulse in the pyramid. The PVQ unit pulses are used to describe the shape of the quantized SNS scale factors.

[0045] The proposed solution additionally employs a variation of the PVQ shapequantization concept, by having FESS (Fixed envelope shifted signs) configuration, which istargeted to handle quantization of stage1 residuals with a rather even envelope, requiring manyunit pulses. The FESS unit pulses are not stacked, and their position is analyzed and codedinexpensively as a shift factor of a predetermined sequence of 12 signs.

[0046] Certain embodiments may provide one or more of the following technicaladvantages. In some embodiments, the introduced codebook structure (transformed by reversal and polarity) allows for relatively fast search using little ROM. Also, at the decoder side the useof an indirectly created transformed codebook will reduce the ROM significantly.

[0047] Some of the embodiments contemplated herein will now be described more fullywith reference to the accompanying drawings. Embodiments are provided by way of example to convey the scope of the subject matter to those skilled in the art, in which examples of embodiments of inventive concepts are shown. Inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forthherein. Rather, these embodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the scope of present inventive concepts to those skilled in the art. It should also be noted that these embodiments are not mutually exclusive. Components from one embodiment may be tacitly assumed to be present / used in another embodiment.

[0048] FIG. 1 illustrates an example of a new radio (“NR”) network (e.g., a 5th Generation(“5G”) network) including a 5G core (“5GC”) network 130, network nodes 120a-b (e.g., 5G base station (“gNB”)), multiple communication devices 110 (also referred to as user equipment (“UE”)).

[0049] FIG. 2 illustrates an example of an operating environment in which the variousembodiments of the present disclosure may be implemented. Turning to FIG. 2, in the exampleoperating environment 200, the encoder 202 receives data, such as an audio file, to be encoded from an entity through network 204, such as a host 206, and / or from storage 208. The encoder 202 in various embodiments is a parametric stereo encoder. In some embodiments, the host 206 may communicate directly to the encoder 202. The encoder 202 encodes the audio file as described herein and either stores the encoded audio file in storage 208 or transmits the encoded audio file to a decoder 212 via network 210. The decoder 212 in various embodiments is a parametric stereo decoder. The decoder 212 decodes the audio file and transmits the decoded audio file to an audio player 214 for playback. The audio player 214 may be or be comprised in a user equipment, a terminal, a mobile phone, and the like. In other embodiments, the host 206 may transmit encoded audio files to the decoder 212 via network 210.

[0050] FIG. 3 shows an audio encoder 202 in accordance with some embodiments wherethe audio encoder 202 is implemented as a stand-alone device. As used herein, an audio encoder refers to a device capable, configured, arranged and / or operable to encode objects and communicate with network nodes, encoders, and / or decoders. Examples of an audio encoder include, but are not limited to, a smart phone, mobile phone, cell phone, voice over IP (VoIP) phone, wireless local loop phone, desktop computer, personal digital assistant (PDA), wireless cameras, gaming console or device, storage device, playback appliance, wearable terminal device, wireless endpoint, mobile station, tablet, laptop, laptop-embedded equipment (LEE), laptop-mounted equipment (LME), smart device, wireless customer-premise equipment (CPE), vehicle-mounted or vehicle embedded / integrated wireless device, etc.

[0051] An audio encoder may support device-to-device (D2D) communication, for exampleby implementing a 3GPP standard for sidelink communication, Dedicated Short-Range Communication (DSRC), vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), or vehicle-to-everything (V2X). In other examples, an encoder may not necessarily have a user in the senseof a human user who owns and / or operates the relevant device.

[0052] The audio encoder 202 includes processing circuitry 302 that is operatively coupledvia a bus 304 to an input / output interface 306, a power source 308, a memory 310, a communication interface 312, and / or any other component, or any combination thereof. Certaindecoders may utilize all or a subset of the components shown in FIG. 3. The level of integrationbetween the components may vary from one decoder to another decoder. Further, certain decoders may contain multiple instances of a component, such as multiple processors, memories, transceivers, transmitters, receivers, etc.

[0053] The processing circuitry 302 is configured to process instructions and data and maybe configured to implement any sequential state machine operative to execute instructions stored as machine-readable computer programs in the memory 310. The processing circuitry 302 may be implemented as one or more hardware-implemented state machines (e.g., in discrete logic, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc.); programmable logic together with appropriate firmware; one or more stored computer programs, general-purpose processors, such as a microprocessor or digital signal processor (DSP), together with appropriate software; or any combination of the above. For example, the processing circuitry 302 may include multiple central processing units (CPUs).

[0054] In the example, the input / output interface 306 may be configured to provide aninterface or interfaces to an input device, output device, or one or more input and / or output devices. Examples of an output device include a speaker, a sound card, a video card, a display, a monitor, a printer, an actuator, an emitter, a smartcard, another output device, or any combination thereof. An input device may allow a user to capture information into the audio encoder 202. Examples of an input device include a touch-sensitive or presence-sensitive display, a camera (e.g., a digital camera, a digital video camera, a web camera, etc.), a microphone, a sensor, a mouse, a trackball, a directional pad, a trackpad, a scroll wheel, a smartcard, and the like. The presence-sensitive display may include a capacitive or resistive touch sensor to sense input from a user. A sensor may be, for instance, an accelerometer, a gyroscope, a tilt sensor, a force sensor, a magnetometer, an optical sensor, a proximity sensor, a biometric sensor, etc., or any combination thereof. An output device may use the same type of interface port as an input device. For example, a Universal Serial Bus (USB) port may be used to provide an input device and an output device.

[0055] In some embodiments, the power source 308 is structured as a battery or batterypack. Other types of power sources, such as an external power source (e.g., an electricity outlet), photovoltaic device, or power cell, may be used. The power source 308 may further include power circuitry for delivering power from the power source 208 itself, and / or an external powersource, to the various parts of the audio encoder 212 via input circuitry or an interface such as an electrical power cable. Delivering power may be, for example, for charging of the power source208. Power circuitry may perform any formatting, converting, or other modification to thepower from the power source 308 to make the power suitable for the respective components of the audio encoder 202 to which power is supplied.

[0056] The memory 310 may be or be configured to include memory such as random accessmemory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read- only memory (EEPROM), magnetic disks, optical disks, hard disks, removable cartridges, flash drives, and so forth. In one example, the memory 310 includes one or more application programs 314, such as an operating system, web browser application, a widget, gadget engine, or other application, and corresponding data 316. The memory 310 may store, for use by the audio encoder 202, any of a variety of various operating systems or combinations of operating systems.

[0057] The memory 310 may be configured to include a number of physical drive units,such as redundant array of independent disks (RAID), flash memory, USB flash drive, external hard disk drive, thumb drive, pen drive, key drive, high-density digital versatile disc (HD-DVD)optical disc drive, internal hard disk drive, Blu-Ray optical disc drive, holographic digital datastorage (HDDS) optical disc drive, external mini-dual in-line memory module (DIMM), synchronous dynamic random access memory (SDRAM), external micro-DIMM SDRAM, smartcard memory such as tamper resistant module in the form of a universal integrated circuit card (UICC) including one or more subscriber identity modules (SIMs), such as a USIM and / or ISIM, other memory, or any combination thereof. The UICC may for example be an embedded UICC (eUICC), integrated UICC (iUICC) or a removable UICC commonly known as ‘SIM card.’ The memory 310 may allow the audio encoder 202 to access instructions, application programs and the like, stored on transitory or non-transitory memory media, to off-load data, or to upload data. An article of manufacture, such as one utilizing a communication system may be tangibly embodied as or in the memory 310, which may be or comprise a device-readable storage medium.

[0058] The processing circuitry 302 may be configured to communicate with an accessnetwork or other network using the communication interface 312. The communication interface 312 may comprise one or more communication subsystems and may include or be communicatively coupled to an antenna 322. The communication interface 312 may include one or more transceivers used to communicate, such as by communicating with one or more remotetransceivers of another device capable of wireless communication (e.g., a UE or a network node in an access network). Each transceiver may include a transmitter 318 and / or a receiver 320 appropriate to provide network communications (e.g., optical, electrical, frequency allocations, and so forth). Moreover, the transmitter 318 and receiver 320 may be coupled to one or more antennas (e.g., antenna 322) and may share circuit components, software or firmware, or alternatively be implemented separately.

[0059] In the illustrated embodiment, communication functions of the communicationinterface 312 may include cellular communication, Wi-Fi communication, LPWAN communication, data communication, voice communication, multimedia communication, short- range communications such as Bluetooth, near-field communication, location-based communication such as the use of the global positioning system (GPS) to determine a location, another like communication function, or any combination thereof. Communications may be implemented in according to one or more communication protocols and / or standards, such as IEEE 802.11, Code Division Multiplexing Access (CDMA), Wideband Code Division Multiple Access (WCDMA), GSM, LTE, New Radio (NR), UMTS, WiMax, Ethernet, transmission control protocol / internet protocol (TCP / IP), synchronous optical networking (SONET), Asynchronous Transfer Mode (ATM), QUIC, Hypertext Transfer Protocol (HTTP), and so forth.

[0060] Regardless of the type of sensor, an audio encoder may provide an output of encodeddata, through its communication interface 312, via a wireless connection to a network node.

[0061] An audio encoder when in the form of an Internet of Things (IoT) device, may be adevice for use in one or more application domains, these domains comprising, but not limited to, city wearable technology, extended industrial application and healthcare. Non-limiting examples of such an IoT device are a device which is or which is embedded in: a connected refrigerator or freezer, a TV, a connected lighting device, an electricity meter, a robot vacuum cleaner, a voice controlled smart speaker, a home security camera, a thermostat, an electrical door lock, a connected doorbell, an autonomous vehicle, a surveillance system, a weather monitoring device, a vehicle parking monitoring device, an electric vehicle charging station, a smart watch, a fitnesstracker, a head-mounted display for Augmented Reality (AR) or Virtual Reality (VR), awearable for tactile augmentation or sensory enhancement. A decoder in the form of an IoT device comprises circuitry and / or software in dependence of the intended application of the IoT device in addition to other components as described in relation to the audio encoder 202 shownin FIG. 3.

[0062] FIG. 4 shows an audio decoder 212 (e.g., a parametric stereo encoder) in accordancewith some embodiments where the audio decoder 212 is implemented as a stand-alone device.As used herein, an audio decoder refers to a device capable, configured, arranged and / or operable to decode objects and communicate with network nodes, encoders, and / or decoders. Examples of an audio decoder include, but are not limited to, a smart phone, mobile phone, cell phone, voice over IP (VoIP) phone, wireless local loop phone, desktop computer, personal digital assistant (PDA), wireless cameras, gaming console or device, storage device, playback appliance, wearable terminal device, wireless endpoint, mobile station, tablet, laptop, laptop- embedded equipment (LEE), laptop-mounted equipment (LME), smart device, wirelesscustomer-premise equipment (CPE), vehicle-mounted or vehicle embedded / integrated wirelessdevice, etc.

[0063] An audio decoder may support device-to-device (D2D) communication, for exampleby implementing a 3GPP standard for sidelink communication, Dedicated Short-Range Communication (DSRC), vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), or vehicle- to-everything (V2X). In other examples, a decoder may not necessarily have a user in the sense of a human user who owns and / or operates the relevant device.

[0064] The audio decoder 212 includes processing circuitry 402 that is operatively coupledvia a bus 404 to an input / output interface 406, a power source 408, a memory 410, a communication interface 412, and / or any other component, or any combination thereof. Certaindecoders may utilize all or a subset of the components shown in FIG. 4. The level of integrationbetween the components may vary from one decoder to another decoder. Further, certain decoders may contain multiple instances of a component, such as multiple processors, memories, transceivers, transmitters, receivers, etc.

[0065] The processing circuitry 402 is configured to process instructions and data and maybe configured to implement any sequential state machine operative to execute instructions stored as machine-readable computer programs in the memory 410. The processing circuitry 302 may be implemented as one or more hardware-implemented state machines (e.g., in discrete logic, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc.); programmable logic together with appropriate firmware; one or more stored computer programs, general-purpose processors, such as a microprocessor or digital signal processor (DSP), together with appropriate software; or any combination of the above. For example, the processing circuitry 402 may include multiple central processing units (CPUs).

[0066] In the example, the input / output interface 406 may be configured to provide aninterface or interfaces to an input device, output device, or one or more input and / or output devices. Examples of an output device include a speaker, a sound card, a video card, a display, a monitor, a printer, an actuator, an emitter, a smartcard, another output device, or anycombination thereof. An input device may allow a user to capture information into the audio decoder 212. Examples of an input device include a touch-sensitive or presence-sensitive display, a camera (e.g., a digital camera, a digital video camera, a web camera, etc.), a microphone, a sensor, a mouse, a trackball, a directional pad, a trackpad, a scroll wheel, a smartcard, and the like. The presence-sensitive display may include a capacitive or resistive touch sensor to sense input from a user. A sensor may be, for instance, an accelerometer, a gyroscope, a tilt sensor, a force sensor, a magnetometer, an optical sensor, a proximity sensor, a biometric sensor, etc., or any combination thereof. An output device may use the same type of interface port as an input device. For example, a Universal Serial Bus (USB) port may be used to provide an input device and an output device.

[0067] In some embodiments, the power source 408 is structured as a battery or batterypack. Other types of power sources, such as an external power source (e.g., an electricity outlet), photovoltaic device, or power cell, may be used. The power source 408 may further include power circuitry for delivering power from the power source 408 itself, and / or an external power source, to the various parts of the audio decoder 212 via input circuitry or an interface such as an electrical power cable. Delivering power may be, for example, for charging of the power source 408. Power circuitry may perform any formatting, converting, or other modification to the power from the power source 408 to make the power suitable for the respective components of the audio decoder 212 to which power is supplied.

[0068] The memory 410 may be or be configured to include memory such as random accessmemory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read- only memory (EEPROM), magnetic disks, optical disks, hard disks, removable cartridges, flash drives, and so forth. In one example, the memory 410 includes one or more application programs 414, such as an operating system, web browser application, a widget, gadget engine, or other application, and corresponding data 416. The memory 410 may store, for use by the audio decoder 212, any of a variety of various operating systems or combinations of operating systems.

[0069] The memory 410 may be configured to include a number of physical drive units,such as redundant array of independent disks (RAID), flash memory, USB flash drive, external hard disk drive, thumb drive, pen drive, key drive, high-density digital versatile disc (HD-DVD) optical disc drive, internal hard disk drive, Blu-Ray optical disc drive, holographic digital data storage (HDDS) optical disc drive, external mini-dual in-line memory module (DIMM), synchronous dynamic random access memory (SDRAM), external micro-DIMM SDRAM,smartcard memory such as tamper resistant module in the form of a universal integrated circuit card (UICC) including one or more subscriber identity modules (SIMs), such as a USIM and / or ISIM, other memory, or any combination thereof. The UICC may for example be an embedded UICC (eUICC), integrated UICC (iUICC) or a removable UICC commonly known as ‘SIM card.’ The memory 310 may allow the audio decoder 212 to access instructions, application programs and the like, stored on transitory or non-transitory memory media, to off-load data, or to upload data. An article of manufacture, such as one utilizing a communication system may be tangibly embodied as or in the memory 410, which may be or comprise a device-readable storage medium.

[0070] The processing circuitry 402 may be configured to communicate with an accessnetwork or other network using the communication interface 412. The communication interface 412 may comprise one or more communication subsystems and may include or be communicatively coupled to an antenna 422. The communication interface 412 may include one or more transceivers used to communicate, such as by communicating with one or more remote transceivers of another device capable of wireless communication (e.g., a UE or a network node in an access network). Each transceiver may include a transmitter 318 and / or a receiver 320 appropriate to provide network communications (e.g., optical, electrical, frequency allocations, and so forth). Moreover, the transmitter 418 and receiver 420 may be coupled to one or more antennas (e.g., antenna 422) and may share circuit components, software or firmware, or alternatively be implemented separately.

[0071] In the illustrated embodiment, communication functions of the communicationinterface 412 may include cellular communication, Wi-Fi communication, LPWAN communication, data communication, voice communication, multimedia communication, short- range communications such as Bluetooth, near-field communication, location-based communication such as the use of the global positioning system (GPS) to determine a location, another like communication function, or any combination thereof. Communications may be implemented in according to one or more communication protocols and / or standards, such as IEEE 802.11, Code Division Multiplexing Access (CDMA), Wideband Code Division Multiple Access (WCDMA), GSM, LTE, New Radio (NR), UMTS, WiMax, Ethernet, transmission control protocol / internet protocol (TCP / IP), synchronous optical networking (SONET), Asynchronous Transfer Mode (ATM), QUIC, Hypertext Transfer Protocol (HTTP), and so forth.

[0072] Regardless of the type of sensor, an audio decoder may provide an output of decodeddata, through its communication interface 412, via a wireless connection to a network node.

[0073] An audio decoder when in the form of an Internet of Things (IoT) device, may be adevice for use in one or more application domains, these domains comprising, but not limited to, city wearable technology, extended industrial application and healthcare. Non-limiting examples of such an IoT device are a device which is or which is embedded in: a connected refrigerator or freezer, a TV, a connected lighting device, an electricity meter, a robot vacuum cleaner, a voice controlled smart speaker, a home security camera, a thermostat, an electrical door lock, a connected doorbell, an autonomous vehicle, a surveillance system, a weather monitoring device, a vehicle parking monitoring device, an electric vehicle charging station, a smart watch, a fitness tracker, a head-mounted display for Augmented Reality (AR) or Virtual Reality (VR), a wearable for tactile augmentation or sensory enhancement. A decoder in the form of an IoT device comprises circuitry and / or software in dependence of the intended application of the IoT device in addition to other components as described in relation to the audio decoder 212 shownin FIG. 4.

[0074] FIG. 5 is a block diagram of a host 206 in accordance with various aspects describedherein. As used herein, the host 206 may be or comprise various combinations hardware and / or software, including a standalone server, a blade server, a cloud-implemented server, a distributed server, a virtual machine, container, or processing resources in a server farm. The host 206 may provide one or more services to one or more UEs.

[0075] The host 206 includes processing circuitry 502 that is operatively coupled via a bus504 to an input / output interface 506, a network interface 508, a power source 510, and a memory 512. Other components may be included in other embodiments. Features of these components may be substantially similar to those described with respect to the devices of previous figures, such as FIGS.3-4, such that the descriptions thereof are generally applicable to the corresponding components of host 206.

[0076] The memory 512 may include one or more computer programs including one ormore host application programs 514 and data 516, which may include user data, e.g., data generated by a encoder or decoder for the host 206 or data generated by the host 206 for a UE. Embodiments of the host 206 may utilize only a subset or all of the components shown. The host application programs 514 may be implemented in a container-based architecture and may provide support for video codecs (e.g., Versatile Video Coding (VVC), High Efficiency Video Coding (HEVC), Advanced Video Coding (AVC), MPEG, VP9) and audio codecs (e.g., FLAC, Advanced Audio Coding (AAC), MPEG, G.711, EVS), including transcoding for multiple different classes, types, or implementations of UEs (e.g., handsets, desktop computers, wearable display systems, heads-up display systems). The host application programs 514 may alsoprovide for user authentication and licensing checks and may periodically report health, routes, and content availability to a central node, such as a device in or on the edge of a core network. Accordingly, the host 206 may select and / or indicate a different host for over-the-top services for a UE. The host application programs 514 may support various protocols, such as the HTTP Live Streaming (HLS) protocol, Real-Time Messaging Protocol (RTMP), Real-Time Streaming Protocol (RTSP), Dynamic Adaptive Streaming over HTTP (MPEG-DASH), etc.

[0077] FIG. 6 is a block diagram illustrating a virtualization environment 600 in whichfunctions implemented by some embodiments of the audio encoder 202 or components of the audio encoder 202 or by some embodiments of the audio decoder 212 or components of the audio decoder 212 may be virtualized. In the present context, virtualizing means creating virtual versions of apparatuses or devices which may include virtualizing hardware platforms, storage devices and networking resources. As used herein, virtualization can be applied to any device described herein, or components thereof, and relates to an implementation in which at least a portion of the functionality is implemented as one or more virtual components. Some or all of the functions described herein may be implemented as virtual components executed by one or more virtual machines (VMs) implemented in one or more virtual environments 500 hosted by one or more of hardware nodes, such as a hardware computing device that operates as a decoder, encoder, network node, UE, core network node, or host. Further, in embodiments in which the virtual node does not require radio connectivity (e.g., a core network node or host), then the node may be entirely virtualized.

[0078] Applications 602 (which may alternatively be called software instances, virtualappliances, network functions, virtual nodes, virtual network functions, etc.) are run in the virtualization environment 600 to implement some of the features, functions, and / or benefits of some of the embodiments disclosed herein.

[0079] Hardware 604 includes processing circuitry, memory that stores software and / orinstructions executable by hardware processing circuitry, and / or other hardware devices as described herein, such as a network interface, input / output interface, and so forth. Software may be executed by the processing circuitry to instantiate one or more virtualization layers 600 (also referred to as hypervisors or virtual machine monitors (VMMs)), provide VMs 608A and 608B (one or more of which may be generally referred to as VMs 608), and / or perform any of the functions, features and / or benefits described in relation with some embodiments described herein. The virtualization layer 600 may present a virtual operating platform that appears like networking hardware to the VMs 608.

[0080] The VMs 608 comprise virtual processing, virtual memory, virtual networking orinterface and virtual storage, and may be run by a corresponding virtualization layer 600.Different embodiments of the instance of a virtual appliance 602 may be implemented on one ormore of VMs 608, and the implementations may be made in different ways. Virtualization of the hardware is in some contexts referred to as network function virtualization (NFV). NFV may be used to consolidate many network equipment types onto industry standard high volume server hardware, physical switches, and physical storage, which can be located in data centers, and customer premise equipment.

[0081] In the context of NFV, a VM 608 may be a software implementation of a physicalmachine that runs programs as if they were executing on a physical, non-virtualized machine. Each of the VMs 608, and that part of hardware 604 that executes that VM, be it hardware dedicated to that VM and / or hardware shared by that VM with others of the VMs, forms separate virtual network elements. Still in the context of NFV, a virtual network function is responsible for handling specific network functions that run in one or more VMs 608 on top of the hardware 604 and corresponds to the application 602.

[0082] Hardware 604 may be implemented in a standalone network node with generic orspecific components. Hardware 604 may implement some functions via virtualization. Alternatively, hardware 604 may be part of a larger cluster of hardware (e.g., such as in a data center or CPE) where many hardware nodes work together and are managed via management and orchestration 610, which, among others, oversees lifecycle management of applications 602. In some embodiments, hardware 604 is coupled to one or more radio units that each include one or more transmitters and one or more receivers that may be coupled to one or more antennas.Radio units may communicate directly with other hardware nodes via one or more appropriatenetwork interfaces and may be used in combination with the virtual components to provide a virtual node with radio capabilities, such as a radio access node or a base station. In some embodiments, some signaling can be provided with the use of a control system 612 which may alternatively be used for communication between hardware nodes and radio units.

[0083] Various embodiments herein describe an indirect lookup structure for the first stagestorage and search, where 170 entries stored in a Word (16 bit per word) table is used to lookupdimension 8 sub-vectors from two existing Split-VQ codebook of a total size of 2x32x8 values (512 values).

[0084] The entries in the existing sub codebooks are modified by vector polarity and vectororder reversal to enable a very efficient storage of the 170 entries.

[0085] If the complete codebook was stored in ROM of 170*16 = 2720 Words. This is nowachieved in (512+170) = 682 words by using vector modifications and indirect retrieval of sub-codebooks. The ROM saving is 74 %, at the cost of a slightly higher search complexity on the encoder side.

[0086] In some embodiments, a codebook structure is proposed where a conditional mean issubtracted before vector quantization based on the available voicing / pitch information.

[0087] In additional or alternative embodiments, a second stage algorithmic codebook witha small number of envelopes and shifted pulse trains, is applied in an efficient manner in thetransformed DCT-II domain.

[0088] A complexity saving Open Loop pre-selection of a normal versus outlier first stagecodebooks is made.

[0089] The system being improved is the first stage of a Variable rate multistage VQ. In thisdescription we focus on improving the Table ROM and Worst case WMOPS properties of the16-dimensional ETSI LC3plus SNS (Spectral Noise Shaping) scale factor quantization.

[0090] The ROM usage consumption for the decoder is also improved by using indirectlookup and vector reversal and polarity reversal of two smaller reference codebooks.

[0091] FIG. 7 illustrates an example of an encoder side system overview of an SNS modulein the encoder.

[0092] FIG. 8 illustrates an example of a decoder side system overview of an SNS modulein the decoder.

[0093] FIG. 9 illustrates an example of an encoder including low-rate SNS-VQ analysis.The proposed Vector Quantization scheme may be employed as a part of the SNS module in anaudio coder, with an incoming audio input signal ‘Input signal”, that may employ the processingblocks of LC3plus (ETSI TS 103634 V1.5.1) LD-MDCT(Low Delay Modified DCT), SNS,TNS(Temporal Noise Shaping), ‘SpecQuant’(Spectral quantization), ‘Noise Level’ coding, andArithmetic & Residual coding. The depicted encoder in Fig. 9. also provides a “BW Detect”(audio bandwidth detector) and an Attack detector. In addition, on top of these encodingparameters, a few voicing parameters is also provided to the bitstream multiplexor, and theparameters are pitchrx, ltpfrx and pitch lag. In a low voicing frame, no lag parameter is sent bythe encoder and both pitchrx, and ltpfrx are transmitted or conveyed as zeroed to the BitstreamMultiplex block. In a medium voicing frame, the lag parameter is sent by the encoder and theparameter pitchrx is set to 1, and parameter ltpfrx is set to 0 and forwarded to the BitstreamMultiplex block. In a high voicing frame, the lag parameter is sent by the encoder and theparameter pitchrx is set to 1, and ltpfrx is set to 1 and forwarded to the Bitstream Multiplex block.The pitchrx and pitch lag parameters are normally used by the LC3plus (ETSI TS 103634V1.5.1) decoder side packet loss concealment unit. The ltpfrx and pitch lag parameters arenormally used by the LC3plus (ETSI TS 103634 V1.5.1) decoder side postfilter unit. For thelow-rate SNS-VQ, the ternary information (‘low’,’medium’,’high’)-voicing is extracted from thetwo binary parameters { pitchrx ltpfrx } and used by the LR SNS-VQ on both the encoder anddecoder side to efficiently quantize harmonic outliers when employing stage1 CBC.

[0094] FIG. 10 is a high-level block diagram illustrating an example of an audio decoderwith low-rate SNS-VQ decoding and synthesis. The audio decoder block operates in line withthe LC3plus (ETSI TS 103634 V1.5.1) processing blocks (‘Arithmetic / Range Decode &Residual’, ‘Noise-filling’, Global Gain’ application, ‘TNS Dec.’, ‘SNS Dec’, ’Inv. LD-MDCT’, and ‘LTPF’(long term postfilter). The Bitstream Demultiplex block provides SNS-bits [b0-b8,b9, b10-b29] to the proposed low-rate ‘SNS Dec’ block, and furthermore, the two binaryparameters { pitchrx ltpfrx } are provided by the demultiplexor to the low-rate ‘SNS-Dec’ blockto convey the ternary voicing information (‘low’,’medium’,’high’)-voicing, for further use in Stage1 CBC decoding. The FIG.10 processing blocks are used by the proposed LC3plus-basedaudio decoder incorporating a low-rate and variable rate SNS-VQ, to provide the decoded‘Output signal’ as decoded audio samples.

[0095] FIG. 11 illustrates an example of an LR SNS Stage1 B vector reconstructionprocedure (decoder and encoder).

[0096] The proposed Low-Rate (LR) Vector Quantizer (VQ) for quantizing the M=16 scfspectral noise-shaping coefficients into quantized vector scfQ is employing two VQ stages. Thefirst stage has three length M codebooks of size (2, 170, 170). The second stage has threeconfigurations, where two are similar in architecture to the LC3plus 28bit PVQ based second stage, and the third configuration is a new quantization structure FESS, employing three FixedEnvelopes with Shifted Signs (FESS) combinations, in the DCT-16 transformed domain.

[0097] The proposed Low-Rate (LR) VQ is variable bit rate and can produce total bit ratesof 9, 10, 29, 30 bits. Stage1A-only is signaled with 9 bits. Stage1B-only is signaled with 10 bits.Stage1C-only is also signaled with 10 bits. Additionally, Stage1B can be followed by a 2ndAlgorithmic VQ stage, and then that combination will consume 29 bits for Stage1B+Stage2 (in‘LR_split_LF’ configuration) and 30 bits for Stage1B+Stage2 (in ‘LR_full’ or ‘LR_FESS’configurations).

[0098] In comparison, the two stage SNS-VQ used in the regular 10 ms operation ofLC3plus has a fixed rate of 38 bits for the SNS scale factors scf. The legacy 10 ms 38 bit VQhas a first stage using a Split-VQ with 32 Low frequency (LF) vectors of length 8 and 32 HighFrequency (HF) vectors, requiring 5+5 = 10 bits for transmission, and a total stage1 ROMstorage of 512 Words (1 kB). The second stage of the legacy 38-bit SNS-VQ is an algorithmicPVQ-based shape and gain quantizer and adds a total of 28 bits, and the 2ndstage is using 4 different PVQ based shapes with a varying number of gain levels. The regular 10 ms SNS-VQ has a stage1 complexity of about 0.4 WMOPS, and a stage2 complexity of about 0.8 WMOPS. When applying the 10 ms VQ to a 1.25 ms frame duration the complexity would increase by a factor of 8, and thus stage1 would use 3.2 WMOPS and stage2 would use 6.4 WMOPS.

[0099] At the encoder side the quantized SNS scale factors scfQ are interpolated andapplied to the spectral coefficients of the LC3plus MDCT operation, to provide a noise-shapedsignal (a whitened signal) for the subsequent MDCT coefficient quantization (the coefficientquantization is denoted TCX in LC3plus). At the decoder side the received and de-quantizedSNS scale factors scfQ are also interpolated and applied to the received spectral coefficientsprior to the LC3plus’s decoders IMDCT operation, to noise shape the synthesized signal afterIMDCT. Essentially the LC3plus SNS (Spectral Noise Shaping) concept is a method tointroduce larger quantization steps in loud signal regions than in weak signal regions, and with the use of an efficient VQ, the information for the noise-shaping is compressed efficiently.

[0100] FIG. 7 illustrates an example of an encoder side system overview of an SNS modulein the encoder. At the encoder side, the incoming SNS scale factors scf are presented to the‘Stage1 VQ’ block. Stage1 includes three different 16-dimensional codebooks CBA, CBB andCBC. The ‘Stage1 selector’ first evaluates the MSE (Mean Squared Error) versus the incomingtarget scf vector for codebooks CB A and CBB versus a first threshold of 1.5dB SD (SpectralDistortion), and establishes if the Stage1 harmonic outlier codebook, CBC , is required or not. Ifthe minimum of the CBAand CBBdistortion is low enough, the outlier codebook CBCis not searched to save encoder average complexity. The output of ‘stage1 selector’ includes the beststage1 index indst1 and the related MSE msest1. The stage1 selector additionally always providesthe CBB Stage1 vector for use with Stage2.

[0101] If the minimum overall resulting Stage1 distortion (CBA, CBB and potentially CBC)is higher than a second threshold of 1.75 dB SD, the DCT-II domain the ‘Stage2’ analysis blockis activated (at the potential cost of transmitting 19-20 additional bits). Stage 2 may thus beactivated if the Stage1 codebook using 9 or 10 bits does not provide sufficient spectral matchingin terms of MSE for noise-shaping. Within ‘Stage2’, the remaining target signal after stage 1B isquantized in the DCT-II transform domain via a ‘Shape search’ and a Stage2 ‘Adjustment gainand submode quantization’ block. The selected stage2 shape and gain results in a MSE distortionvalue of msest2 and the stage2 constribution are represented by an integer submode vector ylrshape,and a Stage2 adjustment gain index (gain index i). After Stage2 has been analyzed, the ‘finalstages setup selector’ analyses the resulting combined stage1B and stage2 distortion msest2versus the so far achieved msest1 to make sure that stage2 actually reduces the MSE. The ‘finalstages setup selector’ also provides the resulting total bit consumption in bits in the variablescf_bits to the bitstream multiplexor, where scf_bits is one of 9, 10, 29 or 30. The output of theencoder side SNS module are the quantized scf’s (scfQ(n)) and stage1 and stage2 indexesrepresenting those quantized SNS scf’s within scf_bits bits.

[0102] FIG. 8 illustrates an example of a decoder including low-rate SNS-VQ synthesis.

[0103] At the decoder side, the Bitstream Demultiplexor provides the received bits b0 to b8(as indSt1), and the bits are further analyzed by the ‘Stages Configuration determination block’.

[0104] In some examples, if it is determined that stage1A is in use, then indA is set basedon b0-b8 and lrsns_bits is set to 9 (i.e., 9 bits), and stage2inuse is set to false (0).

[0105] In additional or alternative examples, if it is determined from b0-b8 that stage1B orStage1C is multiplexed in the bitstream then an additional conditional stop-bit (b9) is read.

[0106] In additional or alternative examples, the ten bits b0-b9 are then analyzed in the VQ‘Stages Configuration determination’ block, which can now deduce the existence or non-existence of a second stage from the so far received 10-bit code space (b0 through b9). A b9stop bit value of 1 normally means that only 10 bits are to be received, however if the indexvalue in bits b0 through b8 is in the range 340 to 509, then a total of 30 bits will be read, thus there is a conditional dependency on b0-b8 that determines the effect of the b9 stop bit value.

[0107] In additional or alternative examples, if there is no second stage then stage2inuse isset to ‘false’ (0). And stage1 indB or stage1 indC is set based on the information in b0-b9 andfurther lrsns_bits is set to 10 (i.e., 10 bits).

[0108] In additional or alternative examples, if there is a second stage then the stage2inuseflag is set to ‘true’ (1). And Stage1 indB set based on the information b0-b9.

[0109] In additional or alternative examples, if the content of b0-b9 indicates the stage2”LR splitLF” configuration, a further 19 additional bits b10-b28 are read, and inverselyquantized to obtain the stage2 shape and gain information, and further lrsns_bits is set to 29(i.e., 29 bits). In additional or alternative examples, if the content of b0-b9 indicates the stage2”LR_full or LR_FESS” configurations, a further 20 additional bits b10-b29 are read, andinversely quantized to obtain the stage2 shape and gain information, lrsns_bits is set to 30(i.e.,30 bits). Based on the determined LR SNS-VQ setup (Stage1(A,B,C) or Stage1B+Stage2) thequantized noise-shaping scale factors scfQ(n) are prepared, interpolated and used to shape thequantized MDCT spectrum prior to the IMDCT of the decoder, and thus providing the desired noise-shaping effect.

[0110] In FIG. 8, the output variable GidxG,lrshape from block ‘LR Stage 2 submode and gaindemultiplexing’ corresponds to the decoded adjustment gain based on submode lrshape, and thegain index idxG. The ‘Shape config and enumeration and normalization’ block decodes theincoming bits for configurations ”LR splitLF”(PVQ-based), ”LR_full”(PVQ -based) or“LR_FESS”(Fixed Envelope Shifted Signs based) into a unit energy normalized vector that ispresented to the ‘inverse Transform(IDCT)’ block and then scaled by the decoded adjustmentgain in block ‘Adjustment gain Application’. In case stage2inuse is true (‘yes’), the scaledStage2 contribution is added to the Stage1 contribution to provide the decoded quantized scale factor signal vector scfQ(n).

[0111] The first stage is a ^ = 16 dimensional VQ, employing three different off-linetrained stochastic codebooks (A, B, C). Each codebook vector has dimension ^ and the numberof codebook vectors ^^ are 2, 170 and 170, respectively, for ^ ∈ {^, ^, ^}. The MSE distortionfor a vector j in one of the three codebooks is defined as follows:(^^ ^^ ^)

[0112] It should be noted that as the vector length of ^^^ is always M, the MSE above doesnot apply any length normalization. The best index in the MSE sense for each first stagecodebook is found according to:^^^^ = argmin^^^^^^^^[ ^ …. ^^^^] ^,^(^^ ^^ ^)

[0113] Codebook ^^^ consists of two SNS vectors where one ^^^,^ is the all zero vectorcorresponding to essentially disabling the noise-shaping effect, and a second vector ^^^,^which corresponds to an inversed and dynamically compressed absolute hearing threshold curve. The stored representation of both vectors is prequantized in steps of 1 / 2048 to enable high precisioninteroperability between floating- and fixed-point implementations.

[0114] The best vector of ^^^,^ and ^^^,^ is denoted ^^^,^^^^ and the related meansquared error is thus ^^^^^^^,^^^^. Eventually if ^^^is selected it is jointly multiplexed as apart of the initial stage one 9-bit index ^^^^^^^^^, where value 510 corresponds to vector ^^^,^and value 511 corresponds to vector ^^^,^.

[0115] In the current implementation, ^^^ is made up of these two vectors M=16dimensional vectors:CBA[2]16]= { / * idx0 --> flat spectrum: * / 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, / * : idx1 * / +1.187e+00, +1.014e+00, +7.773e-01, +4.023e-01, +7.812e-03, -2.637e-01, -2.734e-01, -2.617e-01, -7.519e-02, +1.879e-01, +4.526e-01, +5.517 e-01, +2.222e-01, -3.711e-01, -1.253e+00, -2.304 e+00 };

[0116] The set of vectors of the second codebook ^^^ consists of ^^ order permutations(by conditional reversal) and polarity switch of the reference (regular) SNS stage1 codebookvectors in ^^^^ and ^^^^, quantized into steps of 1 / 2048, and these two reference codebooksare denoted as ^^^^^^^ and ^^^^^^^. ^^^^^^^ and ^^^^^^^. are containing 32 vectors oflength 8 each. Each 16 dimensional vector in ^^^ may be compactly represented by a 14-bitlookup index ^^^^^^^ , ^^^ ∈ [0 … ^^-1], stored within a 16-bit integer and thus only ^^ ∗2 = 340 bytes are required to store the whole configuration of ^^^ (when the tables^^^^^^^ and ^^^^^^^ are already available). When stored in the equivalent fully expandedformat, the ^^^ requires 5.44 kB. A 12-bit lookup is also possibly using the cardinality of theSNSBidx to indicate the two highest bits (“b13”, ”b12”). ^^^^^^^b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0bit position multiplexe LF- HF- LF- HF- d rever rever index in ^^^^^^^index in ^^^^ sign sign^^^information sal seal Table 1 Information explicitly stored within each SNSBidx 14b index value.

[0117] Each SNS vector ^^^^^^^^^^ of length M = 16 may be created by parsing anexplicit 14-bit ^^^^^^^ as follows:

[0118] The bits in section b9-b5 is used to extract the initial vector ^^^^^^^^^ of length^ / 2 from reference codebook ^^^^^^^, and the bits in section b4-b0 is used to extract theinitial vector ^^^^^^^^^ of length ^ / 2 from ^^^^^^^. If b13 is set then the ^ / 2 elements in^^^^^^ are reversed (the vector read in reverse order, i.e., from end to start) and additionally ifb11 is set, the polarity of the elements in ^^^^^^ is reversed (i.e., polarity of each of theelements is switched). If b12 is set, then the ^ / 2 elements in ^^^^^^^^^ are reversed andadditionally if b10 is set the polarity of the elements in ^^^^^^^^^ is reversed. The resultingmodified vectors ^^^^^^^^^and ^^^^^^^^^are then concatenated into an M=16 element long ^^^^^^^^^^vector.

[0119] In FIG. 11 the procedure for extracting and reconstructing an initial 16-dimensionalCBB vector based on the sub-parameters (LF-rev, HF-rev, LF-sign, HF-sign, indLF, indHF)within a 14-bit index is depicted. Each sub-parameter may be extracted from the bit positions b0to b13 according to the leftmost table in FIG. 11. Then, the indLF sub-parameter is used toextract an 8-dimensional vector tmpLF from LFCBQ11(at index indLF). If the LF-rev bitposition (b13) indicates a conditional reversal, the tmpLF vector is reversed (a.k.a. flipped) sothat tmpLF0 switches location with tmpLF7, tmpLF1 switches location with tmpLF6 , tmpLF2switches location with tmpLF5 and tmpLF3, switches location with tmpLF4 . If the LF-sign bitposition (b11) indicates a conditional vector polarity switch, then the eight elements of tmpLFare negated.

[0120] Similarly for the high frequency part, indHF sub-parameter is used to extract an 8-dimensional vector tmpHF from HFCBQ11(at index indHF). If the HF-rev bit position (b12)indicates a conditional reversal, the tmpHF vector is reversed (a.k.a. flipped) so that tmpHF0switches location with tmpHF7, tmpHF1 switches location with tmpHF6 , tmpHF2 switcheslocation with tmpHF5 and tmpHF3, switches location with tmpHF4 . If the HF-sign bit position(b10) indicates a conditional vector polarity switch, then the eight elements of tmpHF arenegated. Finally, the initial CBB vector is reconstructed by concatenating tmpLF and tmpHFinto a 16-dimensional vector.

[0121] To save encoding complexity, the reversal information is stored in the order of theset of SNSB_idx’s , making a low complexity segmented (grouped) search loop feasible.

[0122] The search of codebook ^^^ is on a high level performed by iterating through thesequence of ^^^^^^^^^formatted indexes, creating each 16 element vector ^^^^^^^^^^and minimizing the MSE across all indexes according to (^^ ^^ ^), with ^^^^^^^^^^ , ^^^ ∈[0 … ^^ − 1] as ^^^. The order of the ^^ formatted lookup indexes have been optimizedoffline to reduce the ^^^indirect lookup search complexity, by grouping the lookup indextransformations into a list of elements with 88 initial indexes with {b13, b12} ={0, 0}, followedby 42 indexes with {b13, b12} ={0,1}, followed by 24 indexes with {b13, b12} ={1, 0} andfinally followed by 16 indexes with {b13, b12} ={1,1}. This ordering of ^^^ vectors enablesan efficent search in four segments, where the LF and / or HF part of target signal is conditionallyreversed instead of reversing each partial codebook vector for every index. The final winningindex from the ^^^MSE search is denoted ^^^^. SNSBidx^^^^^^^value“b13” “b12” b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0bit position range [0...87] 0 0[88…129] 1 Segment 0 (rev) LF- HF- multiplexed[130..153] 1index in ^^^^ index in ^^^^ sign si^^^ ^^^0 gn information (rev) [154..169] 11 (rev) (rev) Table 2 Information for indirect lookup, where the b13 and b12 reversal information is available.

[0123] The efficient ^^^ search is performed by searching segmentally group wise in asequential manner, and instead of conditional reversing of each of the 170 candidates code bookvectors LF and HF parts, the target signals HF and / or LF part are conditionally reversed beforestarting the MSE minimization for a group. The overhead in complexity for conditionally reversing the target signal in segments is very limited in comparison to the cost of conditionally reversing each of the 170 ^^^entry.INT32 L_mse_best = INT_MAX; / *a huge positive number * / INT16 seg_cnt_cum[4+1] = { 0, 88, 130, 154, 170 } ;INT16 tmp_buf[M]; INT16 best_ind = -1;for (i = 0; i < (M); i++) {tmp_buf[i] = round(2048.0 *scf[i]) } for (seg = 0; seg < 4; seg++){ memcpy(scfLF_Q11, tmp_buf, M * sizeof(*scfLF_Q11)); / * M * / / *seg==0: fwd, fwd * / / *seg==1: fwd, rev * / / *seg==2: rev, fwd * / / *seg==3: rev, rev * / if ((seg & 0x0002) != 0) { / * {r,*} * / / * flip LF * / for (i = 0; i < (M / 2); i++) { scfLF_Q11[i] = tmp_buf[(M / 2 - 1) - i];} } if ((seg & 0x0001) != 0) { / * {*,r} * / / * flip HF * / for (i = 0; i < (M / 2); i++){ scfLF_Q11[M / 2 + i] = tmp_buf[(M - 1) - i];} } for (i = seg_cnt_cum[seg]; i < seg_cnt_cum[seg + 1]; i++) {idx_12b = idx12b_cb[i]; / * indirect addressing lookup of 12b parts of a 14 bit indexpointing to LF and HF ref CBs + individual polarity swaps * / signbitLF = (0x0800 & idx_12b); / * b11 logical * / signbitHF = (0x0400 & idx_12b); / * b10 logical * / idx_LF = (0x03e0 & idx_12b) >> 5; / * b9...b5 * / idx_HF = (0x001f & idx_12b); / * b4...b0, the lowest 5 bits * / lf_cb = &(LFCBQ11[idx_LF * M / 2]); / * ptr init * / hf_cb = &(HFCBQ11[idx_HF * M / 2]); / * ptr init * / L_mse = 0; / * accumulate energies on the positive side* / for (j = 0; j < (M / 2); j++) {err = (scfLF_Q11[j] - lf_cb[j]); / * a "+"sign, LF err in Q11 * / if (signbitLF != 0) { / * negate LF* / err = (scfLF_Q11[j] + lf_cb[j]); / * "-""-" --> "+" LF err in Q11 * / } L_mse += (err * err); / * accumulate * / err = (scfHF_Q11[j] - hf_cb[j]); / * a "+"sign, HF err in Q11 * / if (signbitHF != 0) { / * negate HF * / err = (scfHF_Q11[j] + hf_cb[j]); / * -- --> "+", LF err in Q11 ,single BASOP * / } L_mse += (err * err); / *simulate L_mac0 * / / * now total error * / } if ( L_mse <= L_mse_best) {best_ind = i; / * update winner * / } L_mse_best = MIN(L_mse, L_mse_best); }* i * / } / * segment / group seg * / / * best_ind is now the best vector in CB_B * / / * L_mse_best is the Mean Square Error for the vector corresponding to best_ind * / Table 3 Pseudo c-code for the optimized segment optimized CBB search loop, including conditional target reversal for each segment.

[0124] Due to the reuse of combined ^^^^^^^ and ^^^^^^^ vectors, a low levelunintentional DC component may be added to the initially selected codebook vector^^^^^^^^^^^ with index ^^^^ ∈ [0 … ^^-1] . The DC component is removed using a DCremoval function with a predetermined precision of 1 / 2048 as follows: ∑ ^^^^^^^^^^^ ^^^ (^)^^^^ = ^^^^^^ 16 (^^ ^^ ^)(^^ ^^ ^)

[0125] Additionally, the MSE obtained from the ^^^^^^^^^^ search is updated to excludeany error contribution from ^^^^^^.(^^ ^^ ^)where the absolute value is needed to avoid negative energy values due to rounding errors in the DC calculation.

[0126] The final index ^^^,^^^^ ^^^ℎ ^^^^ ∈ [0 … ^^-1] is later conditionally multiplexedinto the 9-bit ^^^^^^^^^ as a value in the range [0 … ^^-1] or in the range [2 ∙ ^^ … 3 ∙ ^^-1].

[0127] The stage1 codebook C search is only performed if the minimum of stage1A andstage1B distortion is larger than 1.5 dB in spectral distortion (SD), (corresponding to a SNSdomain MSE of 3,97 ). i.e., Stage 1 C codebook search is skipped if3,97 , ^ℎ^^^ ∝.is 0,875. If codebook Csearch was not performed and the index ^^^^for stage1C was not calculated, then we set^^^^ ^^ 0 and ^^^^^^^,^^^^ ^^ 2 ∙ 3.97.

[0128] The set of vectors of the third codebook ^^^ consists of ^^vectors trained with afocus on instrumental music outliers in relation to the two previous codebooks ^^^and ^^^. The C codebook further utilizes the correlation with the earlier transmitted pitch information, ^^^^ℎ^^and ^^^^^^such that one out of three possible ^^^mean vectors is initially selected and applied based on the available pitch related information.

[0129] The flag ^^^^ℎ^^ is set to 1 if the normalized correlation of the input 12.8 kHz timedomain signal is higher than 0.5, otherwise the flag is set to zero. The flag ^^^^^^is set to 1 if the normalized correation of the 12.8 kHz time domain signal is higher than 0.8, otherwise the flag is set to zero. When the flag ^^^^ℎ^^is set and ^^^^^^is not set, a pitch activation bit is sent and a zeroed ltpf bit is sent and additionally a pitch lag is always transmitted to aid the decoder in concealing lost frames in frame loss conditions. When both ^^^^ℎ^^and ^^^^^^are set, the pitch activation bit is transmitted and the LTPF activation bit is transmitted the decoder side, and a long term postfilter is activated on the decoder side to artificially increase the peak to valley ratios between harmonic peaks in the spectrum.(^^ ^^ ^)Vector pitchrxltpfrxVector values quantized into a S16Q11 domain name value value ^^^^^^^^0 0 0 { 2293, 2602, 1960, 1161, 880, 417, 34, -169,-368, -541, -604, -318, -287, -958, -2341, -3760 } / 2048 ^^^^^^^^1 1 0 { -3680, -3482, -2787, -1918, -1130, -747, 883, 2199,2742, 2742, 2885, 3181, 3022, 1835, -1015, -4730 } / 2048 ^^^^^^^^2 1 1 { -4600, -4353, -3484, -2397, -1413, -933, 1103, 2749,3428, 3428, 3606, 3976, 3777, 2293, -1268, -5912 } / 2048 Table 4 Pitch / Voicing information dependent SNS mean vectors used for CBC

[0130] A new SNS residual target ^^^^^^^ is prepared as:^^^^^^^(^) = ^^^(^) − ^^^^^,^^^(n) , for n = 0 … M-1(^^ ^^ ^)

[0131] The residual vectors for the ^^^ codebook are stored in a S8Q7 format in ^^^^^^,where each SNS coefficient is represented byte with possible integer values ranging from -128 to +127, resulting in a maximum ROM table size for ^^^of 2.7 kB. In the synthesis of the vector for a given ^^^codebok index ^^^^an additional predetermined scaling factor^^^^^^^4 with an integer value of 86 and a fractional value of 86 / 16 == 5.375 brings the storedbyte values to the target SNS residual domain with a precision of 1 / 2048 steps.(^^ ^^ ^)

[0132] The target for the ^^^ MSE search loop the residual signal vector ^^^^^^^ isnormalized into vector ^^^^^^^^ by the factor ^^^^^^^^^^15 (with an integer value of 6096 anda fractional value of 6096 / 2048 == 0.18603515625) to enable an efficient search in the S8Q7 domain. ^^^^^7(^) = ^^^^^^^^^^15 ∙ ^^^^^11(^) , for n = 0 … M-1(^^ ^^ ^)

[0133] The inner loop MSE distortion calculation for codebook ^^^ is performed in adownscaled mean residual domain:(^^ ^^ ^^)

[0134] The best index is selected according to:^^^^ = argmin^^[ ^ …. ^^^^]^^^^^^ ^^^^,^(^^ ^^ ^^)

[0135] Finally, the final ^^^ vector is generated in 1 / 2048.0 precision as:(^^ ^^ ^^)And the outer MSE error is calculated according to:(^^ ^^ ^^)

[0136] The final index ^^^,^^^^ ^^^ℎ ^^^^ ∈ [0 … ^^-1] is later conditionally multiplexedinto the 9-bit ^^^^^^^^^ as a value in the range [0 … ^^-1] or in the range [^^ … (2 ∙ ^^)-1].

[0137] The best low-rate SNS stage1 codebook is represented by the index st1CBidx andselected as follows:(^^ ^^ ^^)where the VQ bit rate compensation weight ∝ is 0,875 and st1CBidx =0 corresponds to ^^^,st1CBidx = 1 corresponds to ^^^ and st1CBidx = 2 corresponds to ^^^ being selected as thebest stage1 only codebook. The weight ∝ is used to compensate for ^^^ using less bits fortransmission (9 bits) than the other two stage1 codebooks, {^^^ ^^^} which are using 10 bits.

[0138] For complexity reduced encoders it is not affordable to run both ^^^ and ^^^ fullMSE analysis as they will cost dual MSE searches of 170 vectors each.

[0139] So optionally ^^^ is open loop preselected by analyzing the variation in the highfrequency bands of the input SNS scf M=16 sized vector.

[0140] The selection is made based on the variation variable ^^^^^^^^, defined as:^^^^^^^^ = |scf[M − 1] − scf[M − 2]| + |scf[M − 2] − scf[M − 3]| )(^^ ^^^^^)

[0141] The high frequency region variation analysis of the input signal and a limitingconstant ^^^^^ = 1,5 is then used to skip analysis of ^^^.^^^^^^1^^^^^^^^^^^^ = ^1 , ^^ ^^^^^^^^ > ^^^^^0 , ^^ℎ^^^^^^(^^ ^^^^^)

[0142] This setting of the ^^^^^ limit creates a larger likelihood (97%) of getting correctdetermination of ^^^ but will reduce the chance of perfectly hitting the outlier coding using^^^ to 84 %, but this is acceptable as the outliers are rather rare events.

[0143] An alternative setting of the ^^^^^ limit to 0,8 creates likelihood (79%) of gettingcorrect determination of ^^^, and will increase the chance of perfectly hitting the outliercoding using ^^^ to 93 %, this approach would keep the LR SNS bit rate increase limited due toOpen Loop selection down as Codebook C is always limited to 10 bits (0.625 bits / coeff).

[0144] In the case ^^^^^^1^^^^^^^^^^^^ is set the open loop decision is complementedby a safety net analysis a limited set of ^^^vectors which are a priori defined to be close to theopen loop decision border. The indexes for the set of B vectors (vector close to the three-dimensional B vs. C decision border) and their distance values to the decision border in terms ofthe parameter ^^^^^^^^ is shown in table 5a below: Border CBB index scfHFvar ( in the range for the CBBindex [0 … 169])146 4,27117 4,2159 2,05135 1,6435 1,6378 1,4847 1,4734 1,4310 1,42Table 5a List of the indexes for the nine-safety net CBB analysis vector. The top five are the CB_B entrieswith very high variation in the HF region and the remaining 4 are the ones which nearly have the same HFvariation as the set of CBC vectors.

[0145] If ^^^ was initially chosen (^^^^St1BAnalysisPre = 1) by the Open Loopdecision, then the MSE of the 9 additional neighboring ^^^vectors (in the table above) are evaluated as a soft safety net feature, to reduce the risk of open loop misclassifications, and the minimum MSE ^^^^_^^^of the nine vectors is calculated, and the idxB for the best ^^^vector in the MSE sense in the set of 9 is maintained for future.

[0146] If the ^^^^_^^^ is lower (better) than the ^^^^_^^^ of the winning ^^^candidate, then ^^^^^^1^^^^^^^^^^^^^^ is set to 0, and thus enabling ^^^ and potentiallyalso stage2 after further MSE analysis. Otherwise if the ^^^^_^^^is higher (worse) than the^^^^_^^^ , then ^^^^^^1^^^^^^^^^^^^^^ is set to 1, and ^^^ or the small ^^^will be usedand stage2 analysis is not made (stage2use will be set 0).

[0147] If ^^^ was initially chosen (^^^^St1BAnalysisPre = 0), then(^^^^St1BAnalysisFinal) is also set to zero and ^^^^_^^^ is set to a very high value, and thusonly ^^^ and ^^^ are evaluated as candidates for the stage1. The second VQ stage may beactivated based on the achieved MSE’s ^^^^_^^^ or ^^^^_^^^ so far, i.e., stage2 use willbe one of 0 or 1.

[0148] The LR SNS-VQ first stage residual signal is calculated as:^1^^^^^(^) = ^^^(^) − ^^^(^), ^^^ ^ = [0 … M − 1].(^^ ^^ ^^)

[0149] For the low-rate SNS-VQ stage2, only ^^^ is allowed as a preceeding first VQstage. It should be noted that both ^^^ and ^^^ are vectors without any DC component, with theresult that no DC component remains in residual ^1^^^^^.

[0150] The low-rate Stage2 is only activated and searched if the SD so far is higher than1.75 dB in Spectral Distortion, which corresponds to a SNS domain MSE value of 5.41.

[0151] The LR SNS-VQ second stage target signal in the transformed domain is denotedt2SNSLR(^) = DCT-II(^1SNSLR).(^^ ^^ ^^)

[0152] There are five different 16-dimensional unit energy normalized shape vectorcandidates evaluated, where the normalization is always performed over 16 coefficients. The pulse configurations for two sets (A and B) of scale factors for each candidate shape index (lrshape) are given in Table 5b. Shape Puls Pulse Indexes in t2 for Ie index ShapeSNSLR ndexes t2SNSLR forc configuration, nam onfiguration, (lrshape )e scale factor set A scale factor set B Set A Set B, PVQ(NB, KB) 0'LR_splitLF' {1, 2, 3, 4, 5} {6, 7, 8, 9, 10, 11, 12, PVQ(5, 6) PVQ(8, 2)13} 1'LR_full’ { 1, 2, 3, 4, 5, 6, 7, 8, 9, Empty set PVQ(15, 5) Empty10, 11, 12, 13, 14, 15} 2‘LR_fix-0’3 ‘LR_fixt-I’{ 1, 2, 3, 4, 5, 6, 7, 8, 9,Empty set FESS(‘LR_fix-II’10, 116, 12) Empty41, 12, 13, 14, 15}Table 5b: LR SNS-VQ second stage shape candidate pulse configurations

[0153] The two first shape configurations (^^^ℎ^^^ ∈ { 0,1}) use stacked unit pulses,according to the Pyramid VQ principles. The final three shapes use FESS pulse configurations.i.e., (^^^ℎ^^^ ∈ { 2,3,4}) use non-stacked unit pulses and thus requires a lower bit rate than aPVQ pulse configuration with the same pulse density.

[0154] The first low-rate shape is focused on minimizing the distortion for lowerfrequencies and is denoted ‘LR_split_LF’ (^^^ℎ^^^ = 0), and uses two PVQ pulseconfigurations over a total of 13 (5+8) SNS residual values. The first set, setA, is used toquantize 5 SNS residual values with 6 unit pulses using a ^^^(^^ = 5, ^^ = 6), starting from^2^^^^^(1) , and ending with ^2^^^^^(5). The second set, setB, is used to quantize 8 SNSresidual values with two (2) unit pulses using a ^^^(^^ = 8, ^^ = 2), starting from^2^^^^^(6) ,and ending with t2SNSLR(13). Residual coefficients ^2^^^^^(0) , ^2^^^^^(14) and^2^^^^^(15) are not encoded for the ‘LR_split_LF’ shape. The ‘LR_split_LF’ shape can berepresented by N0 = N0,A ∗ N0,^ combinations. Where N0,A = NMPVQ^^^^(5,6)^ = 1970 , andN0,B == 128. Correspondingly the bit consumption for ‘LR_split_LF’ isB0 = B0,A + B0,^, where B0,A = log2(N0,A) = 10,944 ^^^^, and B0,B = log2^N0,B^ = 7,0 ^^^^.Thus B0 = 17,994 bits, these ‘LR_split_LF’ bits are later multiplexed over a total of 18 wholebits.

[0155] The second low-rate shape uses an evenly spread distortion minimization over thefull bandwidth (all coefficients) and is denoted ‘LR_full’ (^^^ℎ^^^ = 1), and uses A single PVQpulse configuration over a total of 15 SNS residual values, the first and only set, setA, is used toquantize 15 SNS residual values with 5 unit pulses using a ^^^(^^ = 15, ^^ = 5), startingfrom ^2^^^^^(1) , and ending with ^2^^^^^(15). The DC residual coefficient ^2^^^^^(0) isnot encoded for the ‘LR_full’ shape. The ‘LR_full’ shape can be represented by N1 = N1,Acombinations. Where N1,A = NMPVQ^^^^(15,5)^ = 207006. Correspondingly the bitconsumption for ‘LR_full’ is B1 = B1,A where B1,A = log2^N1,A^ = 17.6593 bits. Theremaining coding space up to a whole of 18 bits is ^1,^,^^^^^^^^ =− ^1,^ = 55138 . Thisremaining coding space ^1,^,^^^^^^^^ = ^^^2^^1,^,^^^^^^^^^ = 15.75 ^^^^ is used to allow formultiplexing of the three FESS shapes ^^^ℎ^^^ ∈ { 2,3,4}, as three separate multiplexingsections after the initial N1,A‘LR full’ entry.

[0156] The remaining low-rate shapes employ a FESS “Fixed Envelope Shifted Signs”enumeration concept, the FESS shapes are here also denoted ‘LR_fix’, with a sub-index 0, I, II.Each of these three fixed shapes have a different potential SNS envelope specified across residual coefficients 1-15, and do not allow stacked pulses. The three available fixed envelopes are:lrshape fixIdx EnvelopeEnvelope integer vector ^^^^,^^^^^Description values for residual coefficients 1 name through 15 20 ^^^^^^^ − 0 FESSenv [0][0 …14] =Completely flat { 1,1,1,1,1, 1,1,1,1,1, 1,1,1,1,1 } envelope, integer levels 31 ^^^^^^^ − ^ FESSenv [1][0 …14] =LF to HF decaying { 24,23,22,21,20, 19,18,17,16,15, envelope, integer 14,13,12,11,10} levels 42 ^^^^^^^ − ^^ FESSenv [2][0 …14] =Mild centered bell {5,5,6,6,7, 7,8,8,8,7, 7,6,6,5,5} envelope, integer levels Table 6 envelopes used for fixed shapes ^^^^^^^ ∈ { ^, ^, ^}

[0157] Consecutive segments of the envelopes above of length ^^ = 12, are normalizedinto unit energy vectors, using the 12 table values FESS_inv_sqrt_en below:lrshape fixIdx Envelope Envelope normlization value for shifts 0Description ...3 name 20 ^^^^^^^ − 0 FESS_inv_sqrt_en [0][0 …3] =Completely {1 / √12 , 1 / √12 , 1 / √12 , 1 / √12 }flat envelope 31 ^^^^^^^ − ^ FESS_inv_sqrt_en [1][0 …3] =LF to HF {1 / √4250 , 1 / √3818 , 1 / √3410 , 1 / √3026decaying } envelope, 42 ^^^^^^^ − ^^ FESS_inv_sqrt_en [2][0 …3] =Mild centered {1 / √546 , 1 / √557 , 1 / √557 , 1 / √546 }bell envelope Table 7 envelope energy normalization values used for fixed shapes ^^^^^^^ ∈ { ^, ^, ^}

[0158] For each of the fixed shapes twelve consecutive signs with a starting point of shiftare encoded consuming 12 bits, followed by one of 4 different shift factors for the shift valueconsuming 2 bits. The total number of combinations N^..^ = (3 ∙ 2^ ∙ 2^^) = 49152 areinformation required for the encoding of the three fixed FESS shapes is thus ^^^^^^=^^^2(^^….^ ) = 15,58 ^^^^ < 15,75. A shift factor ^ℎ^^^ of 0 makes the 12 consecutive signsstart at position 1 (out of 0 ... 15), a shift factor of 1 makes the 12 consecutive signs start beinganalyzed and synthesized at position 2 (out of 0 ..15), a shift factor of 2 makes the 12consecutive signs start being analyzed and synthesized at position 3 (out of 0 ..15) and a shiftfactor of 3 makes the 12 consecutive signs start being analyzed and synthesized at position 4(out of 0 ..15). The fixed Envelope 0 values will be multiplexed in the first section^0 … ^^^^^^ ^^ − 1 ^, Envelope 1 values will be multiplexed in the second sectionand Envelope 2 values are multiplexed in the third and last− 1^ .SNS- residual 01 2 3 4 5 6 7 8 9 10 11 12 13 14 15(DC) index Example t2SNSLR residual0 -24.3 21.7 -21.1 -20.8 20.8 17.7 -15.7 15.6 16.3 -15.4 -14.5 -12.9 -12.2 10.5 10.9signal to quantize fixIdx=1 n / a 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10(env-I) shift=2 n / a x x x x x x x x x x x xSign n / a n / a n / a - - + + - + + - - - - + n / avalues Final fixed0 0.0 0.0 -22 -21 +20 +19 -18 +17 +16 -15 -14 -13 -12 +11 0vector Sign S10= S11= S0=1 S1=1 S2=0 S3=0 S4=1 S5=0 S6=0 S7=1 S8=1 S9=1bits 1 0Table 8 Example of a resulting non-unit energy normalized fixed shape for an example input residual signaland shift index of 2.

[0159] For the full and fixed shapes (shapes one through four) a combined 18-bit bit spaceis used to index the chosen shape mode among the= ^^,^ + ^^….^ = 256158combinations, with a combined multiplexed bit consumption of= ^^^2(^^…^) = 17.97bits.

[0160] For the two PVQ pulse configurations (^^^ℎ^^^ ∈ { 0,1}) the same pyramid VQshape search principle is used as in as LC3plus ETSI TS 103634 V1.5.1, section 5.3.7.3.3.5,however the DC coefficient is always set to zero for the low-rate SNS-VQ, and does not need any coding information after the DCT-II transform and thus reducing the maximum stage2 dimensionality to M-1=15.

[0161] For the FESS configurations the three available envelopes and four possible shiftsper envelope are evaluated using the same energy normalized correlation concept as for PVQ,however the ^ − ^ non-energy normalized shape candidate ^ vector coefficents are allowed tohave integer values in the range -24 to 24.

[0162] All twelve combinations (4 shifts and 3 FESS-envelopes) are evaluated in the firstall positive hyperoctant using maximization of the energy normalized correlation ^^^^^^^^^^^(where ^ and ^^^^,^^^^^ starts right after the always zeroed DC coefficient), and thensubsequently the Ns =12 signs are set based on the sign of the target signal ^. To limit search complexity, only the best shape among the twelve available FESS envelope and shift configurations is forwarded to the final joint stage2 shape and gain evaluation loop, for determination of the final gain adjusted stage2 FESS vector.(^^ ^^ ^^)

[0163] The FESS shape determination loop for the best envelope and best shift factor isdescribed by the following pseudo code: Step 1 / * variable initialization * / float norm_corr[3][4]; int16_t bestFixIdx=-1; int16_t bestShiftIdx=-1; float best_corr = -1; Int16_t Ns = 12; 2 / * FESS shape search , maximizing (LR Eq 17) * / x = &(^2^^^^^(1)); / * point past the first always zero DC coeff * / for (env = 0; env < 3; env++ ){ y= &(FESS_env[env][0]); for (shift = 0;shift < 4;shift++ ){ norm_corr[env][shift]=0.0; for (n = 0; n < Ns; n++){ norm_corr[env][shift] += fabs(x[n+shift])*y[n+shift];} / * energy normalize the correlation * / norm_corr[env][shift] *= FESS_inv_sqrt_en[env][shift]; if(norm_corr[env][shift]> best_corr){ bestFixIdx = env; bestShiftIdx = shift; best_corr = norm_corr[env][shift]; } } } / * Final FESS shape vector synthesis ,incl. adding the Ns signs as polarity information * / float FESSvec[M]; for (n = 0; n < M; n++){ FESSvec[n]=0.0; } Y =&(^^^^_^^^[1]); / * Y points to second element in FESSvec * / for (n = 0; n < Ns; n++){ y[n+bestShiftIdx] = FESS_env[bestFixIdx][n+bestShiftIdx]; if( x[n] < 0 ) { y[n+bestShiftIdx] = -y[n+bestShiftIdx]; / *negate* / } / * normalize the integer vector coeff to unit energy for the whole vector * / y[n+bestShiftIdx] *= FESS_inv_sqrt_en[bestFixidx][bestShiftIdx]; }FESSvec[i] , with ^ ∈ [0 ... ^ − 1] is now the vector with thebest FESS envelope shape, with unit energy and with a zeroed DC coefficient, The decoder can resynthesize the FESSvec from a received and demultiplexed bestFixIdx and a demultiplexed andreceived bestShiftIdx, and the received and demultiplexed 12 (Ns) signs.Table 1 FESS shape search pseudo C-style codeIn Table 9 the steps needed to establish the best FESS fixed envelope index, bestFixIdxand the best FESS shift index, bestShiftIdx are shown. The C-style pseudo code in Table9 maximizes the normalized correlation in Equation 17.

[0164] The resulting FESSvec from the shape search above is subsequently closed looptested with an eight level, three-bit gain against the two other shape vectors from the otherpossible ‘LR_SplitLF’ and ‘LR_full’ stage2 configurations.

[0165] There are essentially five different adjustment gain candidate sets, one setcorresponding to each overall shape candidate lrshape. To reduce the ROM and WMOPScomplexity the ‘LR_fix’ envelope shapes may share the same set of adjustment gains. Theadjustment gain configuration for each of the low-rate shapes are given in Table 5c.Gain set index Adjustment Gain set Start End (same as Corresponding Number of values adjustment adjustment shape index Shape name gain levels (Gi , lrshape ) gain index gain index = lrshape ) 〖Gminindj 〖Gmaxindj〗 0‘LR_splitLF’ 4 (2 bits) {+1.8125, +2.500 ,+3.3125 , +4.3125} 0 3{+1.4375, +1.8125 ,+2.125 , +2.500 ,1 ‘LR_full’ 8 (3 bits) +2.9375 , +3.500 , 0 7+4.0625 , +4.9375}; 2‘LR_fix-0’ 8(3 bits){+1.375, +1.750, +2.000, +2.3125, 3‘LR_fix-I’ 8(3 bits)+2.625, +3.0625,0 7+3.5625, +4.4375 }4 ‘LR_fix-II’ 8(3 bits)Table 5c: LR SNS-VQ Second Stage Adjustment Gain sets

[0166] Even if stage2 has been applied to reduce the distortion there is still a possibility(quite low) that stage1 ^^^ , ^^^ or ^^^ results in an overall lower distortion. A final Stage1versus Stage2 (including Stage1B) MSE evaluation is made before enumerating the stage2parameters for transmission as follows:(^^ ^^ ^^)

[0167] The method of MPVQ enumeration of stage2 shapes is the same as legacy TS103634 LC3plus 5.3.7.3.3.8 MPVQ enumeration method but with different constants and only applied if stage2 is selected for use (stage2use ==1). The following MPVQ enumeration callsare made for a selected shape lrshape. With YLR[0] being ^1^^^^^(1). i.e. YLR is the integershape vector corresponding to elements 1 through M-1 in the target signal t2SNSLR. Shape index ShapeScale factor set A enumeration Scale factor set B enumeration(lrshape) name 0‘LR_splitLF’ [MPVQIdxA , LS_indA] = MPVQenum(5, 6, yLR)[MPVQIdxB, LSIndB] = MPVQenum(8, 2, yLR[ 5...12] ) 1'LR_full' [MPVQIdxA, LS_indA] = MPVQenum(15, 5, yLR) n / aTable10 Low-rate Scale factor VQ second stage MPVQ shape enumeration of integer vector YLR, intoMPVQ shape indexes{MPVQIdxA, MPVQIdxB}, and leading signs indexes{LSIndA, LSIndB} for each possibleMSE selected MPVQ shape lrshape.

[0168] Enumeration and multiplexing of FESS envelope index, shift index value and signbit values: ^^^^^^^^ℎ^^^^^^^^ = ^^^^^ℎ^^^^^^ ∙ 2(^^^^) + ^1 ∙ 2^^ + … + ^10 ∙ 2^ + ^11 ∙ 2^(^^ ^^ ^^)with s1 being the second sign in the FESS sign sequence and s11 is the last NS’th sign in theFESS sign sequence. A set sign bit indicates a negative coefficient, and a zeroed sign bitindicates a positive coefficient in the transformed residual. ^^^^^^^ = bestFixIdx ∙ 2(^^^^^^) + ^^^^^^^^ℎ^^^^^^^^(^^ ^^ ^^)^^^^^^^^^^^^ = FESSIdx + LRFullOffsetIdx(^^ ^^ ^^)^ ^ ^103503 , i.e. the offset forsignaling the MPVQIdxA of ‘LR_full’ configuration in the range ^0… ^.

[0169] Additionally, the FESS s0 sign bit is multiplexed as the ‘aux’ bit of the initial b0-b9bits. The detailed multiplexing off FESS configuration in combination bit stage1 and gain information is shown further below.

[0170] If stage1 (A,B,C) is selected (stage2use = 0), for transmission then the variable bitrate LR SNS-VQ information is multiplexed this way:st1CBIdx Transmitted valueTransmitted value for Total LR b0-b8, value range stop -bit b9, valueSNS-VQ bitrange consumption 0510+^^^^, [510 …Not available, stop bit 9 bits 511], not transmitted for CB_A 10+^^^^, [0 … 169] 1, [0,1] 10 bits2 170+^^^^, [170 … 339] 1, [0,1] 10 bitsTable 11 Low-rate SNS Stage 1 only multiplexing (^^^^^^^^^ = ^)

[0171] If only stage1 information would have been allowed for the VQ 8,42(log2(2+2*170)) fractional bits would have been required, however here the remaining codingspace up to 10 bits is employed to indicate and convey the potential stage2 operation and also the selected stage2 configuration.

[0172] If the low-rate SNS stage2 + stage1B is selected (stage2use = 1) for transmission,then the variable rate LR SNS-VQ information is multiplexed this way:st1CBIdx st2ShapeIdx ‘aux’Transmitted Transmitted Stag Stage Total LR bit value value for e2 2 SNS bit value b0-b8, value “stop” -bit gain shape consumptio range b9, value bits bits n range 21,2,3,4, 1 340+^^^^, 1, [0,1] 3 18=(10- ‘LR_full’ / ’LR_fix [340 … ⌈^1…4⌉ 1+3+18) ’ 509], = =30 bits ⌈17,97⌉20, “LR_splitLF” 0 0+^^^^, 0, [0,1] 2 ⌈^0⌉(10- [0 … 169] = 1+2+18) ⌈17,944 =29 bits 20, “LR_splitLF” 1 170+^^^^, 0, [0,1] 2 ⌈^0⌉(10- [170 … 339]= 1+2+18) ⌈17,944 =29 bits 21,2,3,4, 0 340+^^^^, 0, [0,1] 3 18=(10- “LR_full” / [340 … 509]⌈^1…4⌉ 1+3+18) ”LR_fix” = =30 bits ⌈17,97⌉Table 12 Low-rate SNS combined Stage1B and stage2 multiplexing

[0173] The slightly irregular multiplexing within the first 9 to 10 bits of the low-rate SNSquantization modes is used to efficiently convey the necessary fractional VQ information without adding the complexity of employing an arithmetic or range encoder and decoder with its overhead for short codewords. The result is a variable bit rate VQ scheme that will signal one bitrate out of the set {9, 10, 29 and 30} bits. In the majority of encoded audio frames, the 9- or 10-bit modes will be sufficient while the 29- and 30-bits modes will be used when the first stageonly result in terms of MSE is deemed insufficient to produce enough noise-shaping control.

[0174] The ‘aux’(auxiliary) bit value is set differently by each possibly stage2configuration, for the ‘LR_full’ mode, the ‘aux’ bit which can at the receiver side be derivedfrom received bits b0 to b9 is used to transmit the leading sign bit LSindA of the MPVQ(N=15,K=5) configuration. For the ‘LR_splitLF’ mode the ‘aux’ bit is used to transmit the leading signbit LSindA of the MPVQ(N=5, K=6) configuration, and finally for the three “LR_fix” modesthe ‘aux’ bit is used to transmit the first sign of the Ns =12 signs. i.e., the value of sign bit s0.

[0175] The remaining unused fractional bits space for the stage2 shape bits may be used bythe decoder to identify bit error conditions as they are known a priori to not have been sent by the encoder.

[0176] Detailed Multiplexing of the “LR_splitLF” mode is shown in the two tables 13 and14 below: Transmitted Transmitted b10- b12-b21 b22-b28 value value for b11 (10 bits) (7 bits) b0-b8, value “stop” -bit b9, Stage2 Stage2 section Stage2 section B shape bits range gain A shape bits MPVQ(8,2) bits. MPVQ(5,6) incl.leading sign value excl. leading range sign 0+^^^^, 0, 2 MPVQIdxA,b22 is LSIndB, [0,1][0 … 169] [0…3]^0 ...^^,^ b23-b2^− 1^ 9 is MPVQIdxB, [0 …26[Table 13 Multiplexing of ‘LR_splitLF’ for a MPVQ(N=5, K=6) leading sign value of 0 (LSIndA=0).Transmitted Transmitted b10- b12-b21 b22-b28 value value for b11 (10 bits) (7 bits) b0-b8, value “stop” -bit b9, Stage2 Stage2 section Stage2 section B shape bits range gain A shape bits MPVQ(8,2) bits. MPVQ(5,6) incl. leading sign value excl. leading range sign 170+^^^^,0, 2 [0...3] MPVQIdxA, b22 is LSIndB, [0,1][170 … 339] ^0 ...^^,^ b23-b29 is MPVQIdxB, [0^− 1^… 26[Table 14 Multiplexing of ‘LR_split_LF’ for a MPVQ(N=5, K=6) leading sign value of 1 (LSIndA=1).Transmitted Transmitted b10- b13-b29 value value for b12 (17 bits) b0-b8, value “stop” -bit b9, Stage2 Stage2 section A shape bits range (here a set gain MPVQ(15,5) “stop” bit still bits. excl. leading sign leads to value continued range encoding, due to the specific b0-b8 value) 340+^^^^, 1 3,MPVQIdxA, ^0 ...^^,^^− 1^[340...509] [0…7]Table 15 Multiplexing of ‘LR_full’ for a MPVQ(N=5, K=6) leading sign value of 1 (LSIndA=1).Transmitted Transmitted b10- b13-b29 value value for b12 (17 bits) b0-b8, value “stop” -bit b9, Stage2 Stage2 section A shape bits range gain MPVQ(15,5) bits. excl. leading sign value range 340+^^^^,0 3, MPVQIdxA, ^0 ...^^,^^− 1^[340 … 509][0…7]Table 16 Multiplexing of ‘LR_full’ for a MPVQ(N=5, K=6) leading sign value of 0 (LSIndA=0).

[0177] Detailed Multiplexing of the “LR_full” mode is shown in the two tables 15 and 16above.

[0178] Detailed Multiplexing of the three ‘LR_fix’ FESS configurations is shown in the twotables 17 and 18 below:Section and Transmit Trans b10-b12 b13-b29 bestFixIdx ted value mitted (3 bits) (17 bits) Value, b0-b8, value Stage2 Stage2 ’description” value for gain bits. range “stop” value for ‘LR_fix’ sections it is the *FESS -bit range information excluding sign s0, b9, , value range 340+ MPVQIdxA, ‘LR_full’ ^^^^, 13, [0..7] ^0 ...^^,^ − 1^ ,selected n / a [340 … ^ 509], , [0 … 103503 [ 0,3 [0...7] FESSFinalIdx ,( ‘LR_Fix’, Env N ^1,A + 0 …N1,A + 2(2+Ns−1)^ 0) 2 2 , [103503 … 103503+8192[ 1,3 [0...7] FESSFinalIdx ,( ‘LR_Fix’, Env 340+ 1) ^^^^, N N ^1,A + 2(2+Ns−1)…1,A + 2(1+2+Ns−1)^ 1 2 2 [340 … , [103503+8192 …103503+2*8192[ 2, 509],3 [0...7] FESSFinalIdx ,( ‘LR_Fix’, Env 2) N ^1,A + 2(1+2+Ns−1)N …1,A + 3 ∙ 2(2+Ns−1)^ 2 2 , [103503+2*8192 …103503+3*8192[ ‘Unused’, 340+ n / a N ^1,A ( )2+ 3 ∙ 2 2+Ns−1 … 217 ^may be used for ^^^^, 1 [103503+3*8192 … 217[ bit error [340 … detection 509],Table 17 Multiplexing of ‘LR_fix’ for af first sign value s0 of 1 ( .Section and Transmit Trans b10-b12 b13-b29 bestFixIdx ted value mitted (3 bits) (17 bits) Value, b0-b8, value Stage2 Stage2 ’description” value for gain bits. range “stop” value for ‘LR_fix’ sections it is the *FESS -bit range information excluding sign s0, b9, , value range 340+ MPVQIdxA, ‘LR_full’ ^^^^, 03, [0..7] ^0 ...^^,^^− 1^ ,selected [340 … 509], , [0 … 103503 [ 0,3 [0...7] FESSFinalIdx ,( ‘LR_Fix’, Env N ^1,A + 0 …N1,A + 2(2+Ns−1)^ 0) 2 2 , [103503 … 103503+8192[ 1,3 [0...7] FESSFinalIdx ,( ‘LR_Fix’, Env 340+ 1) ^^^^, N ^1,A + 2(2+Ns−1)N …1,A + 2(1+2+Ns−1)^ 0 2 2 [340 … , [103503+8192 …103503+2*8192[ 2, 509],3 [0...7] FESSFinalIdx ,( ‘LR_Fix’, Env 2) N ^1,A + 2(1+2+Ns−1)N …1,A + 3 ∙ 2(2+Ns−1)^ 2 2 , [103503+2*8192 …103503+3*8192[ ‘Unused’, 340+ n / a N ^1,A2+ 3 ∙ 2(2+Ns−1) … 217 ^may be used for ^^^^, 0 [103503+3*8192 … 217[ bit error [340 … detection 509],Table 18 Multiplexing of ‘LR_fix’ for a first sign value s0 of 0 ( s0=0).

[0179] The decoder can determine if only ^^^ is active from bits b0 to b8.then it can find out from the additional bit b9 if only ^^^or only ^^^is in use, or if ^^^is in use with stage2, see b0..b9 tables above.

[0180] For stage2 the demultiplexer on the decoder side first will use the first 10 bits (b0-b9) to determine the shape configurations (‘LR_splitLF’) or the combined (‘LR_full’ / LR_fix’).

[0181] If the 10 bits indicate ‘LR_splitLF’, 19 additional bits will be read and parsedaccording to the tables above.

[0182] If the 10 bits indicate ‘LR_full / LR_fix’, 20 additional bits will be read and parsedaccording to the tables above (3 gain bits and 17-bit combined index). The combined 17 bitindex has four sections, see Table 18 above, which are used to determine which of lr_shapes 1..4are active.

[0183] Essentially,if b13..b29 in the combined 17 bit index is less than 103503 then lrshape is 1.if 103503 >= (17bit index) < (103503+8192) then lrshape is 2.If 103503+8192 >= (17bit index) < (103503+2*8192) then lrshape is 3.If 103503+2*8192 >= (17bit index) < (103503+3*8192) then lrshape is 4.

[0184] The stage2 lrshape information is then used to deduce the gain values, and how touse the 'aux’ bit from the 10 first bit b0..b9, (see tables above).

[0185] A standalone decoder will benefit significantly ROM-wise from the algorithmicindirect lookup ^^^ structure as for every decoded audio frame only a single idxB isdemultiplexed and decoded. The complexity increase of using an indirect lookup withconditional partial vector reversal and conditional partial polarity vector switch approach, is essentially negligible for ^^^, and the ROM saving is thus substantial without really adding WMOPS / cycle complexity.

[0186] The full Word8 (byte, 8bit) LR SNS ^^^ is required at the decoder side, thus adding170*16 bytes =2.7KB ROM compared to the legacy SNS-VQ. Still the efficiency of the full ^^^saves transmission bits compared to a less efficient Split-VQ.

[0187] The DCT-II transformation for the proposed LR SNS-VQ is the same as for theDCT-II of the legacy LC3plus TS 103634 v1.5.1 SNS-VQ.

[0188] The IDCT-II transformation for the proposed LR SNS-VQ is the same as for theIDCT-II of the legacy LC3plus TS 103634 v1.5.1 SNS-VQ.

[0189] The PVQ projection and MPVQ enumeration method for the proposed LR SNS-VQis the same, but with different N and K constants.

[0190] The IDCT-II transformation for the proposed LR SNS-VQ is the same.

[0191] The MPVQ de-enumeration method for the proposed LR SNS-VQ is the same, butwith different N and K constants.

[0192] With respect to Table 19 Codebook B related Tables, it shows a compact (in theROM sense) implementation for storage of ^^^related information. Codebooks st1SCF0_7_base5_32x8_Q11[8x32] and st1SCF0_7_base5_32x8_Q11[8x32] correspond to thesmall (in a storage sense) reference codebooks ^^^^^^^ and ^^^^^^^. The referencecodebooks have a vector length of 8 and contain 32 vectors each, the coefficients are quantized in with a precision of 1 / 2048 (Q11) and the total size for each reference codebook is 8x32x2 bytes = 512 bytes. The integer vector lrsns_st1B_merged170orderSort12bitIdx contains the 170 indexes that define the conditional lookup of polarity and reversal of the^^^^^^^ and ^^^^^^^ reference codebooks, where each 12-bit index inlrsns_st1B_merged170orderSort12bitIdx has the bit structure according to Table 2 for bits b11 down to b0. Bits b13 and b12 are not part of the stored index, instead b13 and b12 are stored in terms of the order within the 170 indexes, (see the value range column in Table 2). Informationfor indirect lookup, where the b13 and b12 reversal information is available as the cardinal(order value) of the set of SNSBidx’s , i.e., “b13” and “b12” information is easily derived from the actual CBB index value in the range [0..169]. The total size of the lookup integer vectors is 2x170 bytes = 340 bytes. The total required stored size for representing Codebook B thus becomes 1364 bytes. Codebook B const LC3_INT16 lrsns_st1B_merged170orderSort12bitIdx

[0170] = { / * actually 14 bit index can also be saved * / 15, 19, 119, 162, 177, 185, 227, 296, 297, 353, 357, 369, 370, 372, 377, 416, 418, 420, 515, 529, 561, 569, 603, 625, 627, 673, 680, 754, 756, 777, 786, 801, 809, 834, 837, 848, 849, 850, 852, 864, 865, 866, 872, 904, 908, 913, 914, 924, 928, 978, 996, 1041, 1082, 1088, 1089, 1090, 1139, 1651, 1751, 1982, 1999, 2066, 2120, 2194, 2247, 2391, 2495, 2579, 2626, 2632, 2649, 2959, 3071, 3107, 3223, 3331, 3395, 3415, 3548, 3641, 3675, 3703, 3820, 3825, 3849, 3853, 3865, 3916, 45, 107, 110, 151, 168, 169, 247, 305, 313, 323, 357, 361, 777, 785, 841, 1096, 1123, 1347, 1427, 1498, 1555, 1617, 1643, 1646, 1651, 1774, 2051, 2087, 2265, 2296, 2371, 2971, 3022, 3241, 3287, 3319, 3331, 3543, 3601, 3683, 3689, 3697, 122, 259, 274, 387, 401, 496, 657, 707, 739, 850, 857, 928, 929, 932, 996, 1123, 1270, 1303, 1609, 2151, 2193, 2371, 2632, 2633, 55, 119, 291, 299, 343, 681, 1001, 1307, 1427, 1609, 1646, 1683, 2157, 2222, 3331, 4060}; / * LF+HF tables already available in exiting 10ms BASOP * / const LC3_INT16 st1SCF0_7_base5_32x8_Q11[8 * 32] = { 4634 / * 2.2627 * / , 1666 / * 0.8135* / , -1086, -2778, -3276, -2951, -2343, -1547, 6032, 4939 / * 2.412 * / , 1967, -908, -2517, -3186, -3066, -2287, -4477, -4038, -3660, -3929, -3674, -2780, -1445, -98, 1421, 1957, 1178, -235, -1323, -1950, -2200, -1553, -2657, -1516, -707, -642, -825, -762, -160, 199, 1873, 3570, 3910, 3162, 2239, 1326, 74, -608, -5149, -5922, -4105, -1538, 904, 2462, 2719, 2500, -1889, 1295, 2227, 1246, 269, -607, -424, 276, 1619, 1287, 805, 983, 917, 430, 13, -176, 2965, 5579, 4733, 1915, -563, - 1847, -1927, -1298, 1625, 29, -1163, -1341, -982, -356, 139, 604, 5579, 6061, 3788, 1154, 287, 737, 1412, 1310, -1087, -436, 12, 870, 969, 1759, 2439, 2040, 3456, 4989, 4772, 3645, 2958, 3113, 3015, 2002, -6045, -3264, -225, 796, 1050, 1286, 1685, 1794, 209, 1208, 1268, 2595, 4955, 4612, 1078, -812, 5494, 2718, 267, -693, -754, -393, -317, -480, 9886, 6389, 2857, 513, -806, - 1318, -1316, -1481, 180, -1167, -2345, -3420, -3779, -3204, -2289, -1094, 2849, 4058, 2279, -451, -1587, - 1217, 280, 1676, 788, -329, -1105, -1084, 390, 5244, 5773, 1345, 3957, 6165, 6278, 5122, 3954, 1172, -1662, -2409, 359, -1537, -2129, -2326, -2134, -31, 4240, 7024, -2433, 751, 2682, 3447, 2562, 1930, 1692, 901, 5188, 4327, 2586, 1560, 1069, 243, -926, -1434, 8190, 8354, 5781, 3535, 1325, -678, -1811, -2308, 1040, 3253, 3541, 2062, 772, 976, 2227, 2227, 6489, 6673, 4961, 3675, 3117, 2400, 1002, -128, 3879, 2562, 1209, 1246, 1798, 2292, 2086, 1271, 1943, 4367, 5578, 5673, 5208, 4138, 1700, -56, -3851, -2589, 638, 3762, 4621, 4195, 4496, 4150, 505, 1957, 3114, 4048, 3974, 4575, 4072, 2606 }; const LC3_INT16 st1SCF8_15_base5_32x8_Q11[8 * 32] = { 475, -2066, -4387, -4865, -4568, -4456, -4691, -5187, -2652, -3685, -3865, -3707, -3611, - 3756, -3696, -3557, 285, -529, -1333, -2188, -3316, -4480, -5402, -6101, -648, -978, -1129, -993, -488, - 293, 140, 181, 1801, 611, -1875, -4519, -5614, -5860, -5915, -6045, -608, -1997, -2782, -2015, -1337, - 2027, -3307, -4930, 698, 551, 115, 102, -195, -1557, -4767, -7724, -2892, -3042, -2429, -1280, 315, 1180, 1628, 1222, -469, -683, -1657, -3350, -3860, -3369, -2878, -3004, -2194, -2903, -3172, -2976, -2113, - 1414, -878, -1014, -1210, -146, 708, 616, -2291, -4999, -4564, -3881, -1738, -1194, 184, 1731, 2183, 1511, 525, -1008, 2336, 1974, 781, -989, -3720, -5740, -6623, -7084, -771, 87, 1058, 516, -443, -1094, -1312, -1781, 1362, 2249, 2833, 2751, 1685, 442, -829, -2192, -1692, -1375, -468, 1063, 2800, 4465, 5194, 4508, 2888, 1545, -2674, -3832, -2540, -2595, -4171, -5933, 740, -45, -1187, -1801, -1742, - 1596, -1500, -1819, 896, 626, -15, -1015, -1652, -2507, -3485, -4598, 1327, 1397, 519, 151, 644, 481, 296, -140, 2292, 2529, 1207, -2810, -4856, -4112, -3414, -3945, 291, -227, -579, -14, 586, 94, -1234, -4640, 1032, 1694, 2293, 2415, 2212, 1429, -1869, -7325, -1026, -667, 58, 537, 738, 1302, 1964, 2678, 7679, 3120, -937, -1636, -792, -770, -1347, -2625, -2361, -2269, -1152, -452, -716, - 1543, -2025, -2638, 2106, 2248, 1574, 422, -702, -1546, -2134, -3079, 264, 1412, 2301, 2682, 2775, 2915, 2370, 832, 2745, 2847, 2140, 1302, -563, -3173, -5002, -6194, 4380, 8698, 5934, 1910, -600, - 1660, -1616, -1916, 1157, 3260, 4911, 6220, 5456, 2853, 827, -1344, -865, 668, 2850, 4570, 5349, 5459, 4917, 3603 };Table 2 Codebook B related tablesCodebook C / * Word8 storage of ST1 codebook to save ROM in BASOP * / const LC3_INT8 lrsns_st1C_Both_Word8[170 * 16] = { -88, -78, -57, -39, -27, -15, -6, 3, 11, 17, 20, 23, 32, 47, 69, 88, -86, -40, -7, 4, 1, 5, 10, 10, 0, -5, -5, 4, 9, 23, 38, 39, -71, -69, -65, -49, -29, -5, 16, 30, 21, -8, -3, 15, 27, 40, 63, 87, -71, -36, -10, -5, 2, 17, 15, 18, 24, 24, 13, 7, 11, 2, -6, -7, -70, -23, 13, 12, 0, 7, 19, 14, 1, -1, 6, 3, -2, 1, 9, 13, -68, -79, -67, -42, -26, -17, 8, 29, 38, 34, 32, 33, 32, 36, 36, 21, -62, -66, -56, -41, -33, -13, 11, 17, 16, 17, 28, 39, 40, 41, 40, 23, -61, -62, -51, -31, -26, -25, -23, -15, -3, 12, 24, 30, 33, 43, 68, 85, -60, -63, -47, -28, -17, -9, 13, 30, 36, 31, 25, 24, 27, 28, 17, -6, -57, -47, -25, -11, -17, -12, -1, -7, -4, -1, -7, 1, 23, 44, 58, 60, -54, -59, -61, -50, -22, -1, 25, 37, 37, 31, 21, 13, 21, 31, 27, 4, -53, -36, -14, 3, 13, 12, 14, 19, 26, 31, 30, 22, 3, -12, -21, -36, -53, -52, -39, -24, -12, 2, 23, 34, 32, 27, 16, 8, 11, 21, 14, -9, -45, -46, -31, -16, -8, -5, 6, 21, 31, 32, 26, 22, 18, 11, 1, -17, -40, -11, 7, 11, 4, 13, 5, -13, -28, -20, -10, 0, 8, 19, 23, 32, -40, -32, -18, -2, 6, 12, 8, 1, 2, 4, 9, 15, 20, 13, 3, -1, -40, -9, 11, 7, 6, 6, 0, -13, -13, -1, 7, 12, 8, 4, 6, 9, -39, 5, 19, 12, 13, 9, 4, 3, -2, -6, -4, 2, 3, -2, -6, -13, -38, -13, 1, 1, 4, 17, 16, 12, 8, 0, -9, -23, -20, 0, 18, 24, -38, -25, -13, -12, -24, -17, -6, 4, 10, 6, -17, -13, 6, 35, 51, 53, -38, -34, -30, -24, -9, 7, 17, 18, 14, 9, 11, 14, 18, 18, 12, -3, -38, -36, -19, 2, 20, 28, 28, 33, 31, 16, 6, 4, -4, -12, -23, -36, -38, -46, -38, -22, -17, -22, -11, 18, 35, 34, 27, 25, 24, 22, 12, -3, -37, 3, 34, 16, -8, -30, -54, -45, -23, -9, -3, 14, 12, 15, 42, 72, -35, -55, -53, -38, -30, -20, -5, 6, 13, 16, 21, 25, 29, 41, 48, 36, -35, -45, -50, -47, -48, -41, -31, -16, -1, 9, 20, 21, 29, 51, 81, 104, -35, -46, -46, -35, -24, -11, 9, 27, 34, 33, 27, 25, 21, 17, 9, -6, -34, -24, -20, -13, -11, -7, 2, 2, -13, -4, 23, 31, 21, 16, 16, 16, -33, -54, -66, -58, -43, -23, -16, -10, 1, 18, 23, 18, 28, 51, 74, 89, -31, 16, 51, 48, 30, 18, 12, 2, -7, -17, -23, -26, -29, -26, -17, -1, -31, -20, -18, -20, -13, -8, 1, 13, 20, 2, -13, -8, 12, 27, 31, 25, -30, -33, -40, -36, -30, -11, 3, 10, 14, 15, 24, 29, 31, 27, 20, 8, -30, -45, -40, -20, -14, -21, -31, -23, -10, 1, 12, 15, 22, 39, 64, 83, -29, -15, 0, 4, 8, 16, 17, 11, 5, 4, 2, 1, 11, 7, -13, -29, -29, -29, -20, -3, 15, 27, 27, 18, 17, 29, 31, 19, -3, -19, -35, -44, -28, -21, -26, -26, 2, 22, 30, 37, 34, 18, 8, 2, 0, -9, -18, -25, -28, -19, -11, -7, -1, 8, 13, 17, 21, 25, 30, 23, 5, -9, -26, -42, -27, -9, 3, 2, 3, 11, -7, -14, 9, 25, 14, -6, -4, -1, 0, 2, -27, -27, -25, -17, -18, -10, -8, -16, -18, 1, 16, 20, 29, 35, 38, 27, -26, -44, -8, 8, -12, -5, -6, -9, 1, 13, 17, 15, 35, 42, 6, -29, -24, -22, -16, -13, -12, 0, 10, 15, 19, 8, 5, 13, 26, 18, -5, -21, -24, -42, -47, -33, -31, -32, -19, 2, 13, 13, 9, 4, 16, 35, 58, 80, -24, -16, -7, -4, -7, -6, -8, -9, -3, 5, 11, 15, 23, 22, 12, -2, -23, -13, 1, 1, -19, -17, 7, 21, 29, 29, 20, 12, 0, -9, -15, -26, -23, -39, -40, -26, -19, -13, -4, -10, -21, -20, 0, 18, 26, 39, 57, 73, -22, -26, -25, -25, -28, -21, -3, 23, 35, 38, 31, 20, 10, 5, 2, -13, -21, 3, 27, 20, -9, -8, 4, 3, -3, -10, -18, -16, -4, 8, 11, 13, -21, -13, -5, 1, 15, 22, 23, 27, 31, 25, 13, -1, -18, -28, -33, -40, -20, -15, 0, 10, 9, 13, 12, 0, -15, -8, 7, 9, 4, 0, -2, -6,-20, -15, -9, -6, -2, -14, -40, -5, 34, 49, 45, 29, -7, -16, -7, -18, -19, 13, 24, 22, 27, 17, 2, -1, -8, -17, -26, -16, 0, 1, -4, -15, -18, -14, -7, 6, 19, 21, 20, 22, 20, 16, 17, 14, -5, -27, -39, -44, -17, 30, 76, 76, 57, 44, 11, -23, -43, -54, -57, -58, -53, -33, 5, 40, -17, -19, -22, -34, -39, -15, 12, 23, 21, 17, 18, 22, 20, 13, 6, -7, -17, -12, -8, 6, 19, 4, -15, 0, 21, 32, 30, 8, -9, -15, -20, -24, -16, 33, 77, 82, 55, 23, -2, -11, -20, -39, -58, -65, -58, -33, 0, 32, -16, -21, -26, -21, -7, 7, 10, 8, 11, 16, 22, 20, 12, 3, -4, -16, -15, 8, 29, 23, 11, -9, -29, -23, -14, -5, -2, -2, 4, 10, 9, 3, -14, -17, -19, -22, -11, 2, 15, 27, 33, 27, 20, 14, 3, -10, -20, -27, -13, -2, 6, 3, -7, -7, 4, 26, 31, 19, 13, 12, -4, -23, -29, -32, -13, -6, 6, 18, 21, 18, 12, 7, 5, 5, 5, -1, -7, -15, -23, -33, -12, -7, 0, 3, 5, 0, -5, 4, 18, 24, 25, 16, 1, -13, -25, -34, -12, -3, 0, -4, -3, 10, 9, -3, -5, -6, -6, -3, 14, 20, 5, -14, -12, -11, -15, -14, -7, 2, 12, 6, -10, -21, -4, 11, 22, 22, 15, 4, -11, -12, -13, -5, 11, 16, 11, 6, 5, 15, 22, 20, 3, -12, -23, -33, -11, -10, -8, -11, -3, 13, 19, 18, 11, -1, -12, -8, 6, 7, 0, -12, -11, -17, -20, -20, -16, -9, -2, 7, 24, 32, 32, 26, 14, 0, -14, -27, -10, -11, -11, -20, -26, -25, -7, 7, 20, 29, 19, 6, 5, 15, 9, 0, -10, -5, -7, -9, -4, 9, 10, 0, -17, -28, -21, -7, 12, 28, 29, 22, -8, -20, -30, -25, -28, -26, -18, -9, 7, 15, 24, 26, 30, 33, 24, 5, -8, -17, -19, -17, -16, -7, -7, -7, 3, 4, 4, 6, 21, 28, 22, 10, -8, 35, 62, 60, 43, 21, 6, -4, -21, -34, -37, -42, -43, -32, -12, 6, -8, -6, -3, -1, 1, 0, -5, -5, 2, 11, 23, 21, 8, -2, -11, -24, -7, -21, -21, -13, 1, 18, 28, 30, 30, 34, 33, 18, 0, -21, -52, -57, -6, -31, -40, -39, -36, -27, -20, -22, -19, -4, 10, 12, 19, 38, 69, 95, -6, -38, -48, -42, -37, -27, -13, 2, 7, 9, 17, 23, 33, 45, 46, 28, -6, -18, -39, -58, -59, -34, -15, -6, 0, 4, 15, 22, 24, 38, 59, 71, -4, 6, 6, 11, 15, 9, 1, -7, 2, 11, 16, 10, -5, -14, -26, -31, -4, 2, 7, -6, -59, -49, -4, -1, 1, 15, 9, -19, -19, 11, 52, 64, -2, 31, 53, 43, 20, 8, -2, -17, -24, -21, -22, -25, -22, -14, -8, 1, 1, -3, -3, 4, 6, 9, -4, -31, -39, -17, -5, -1, 6, 16, 27, 34, 1, 10, 15, 12, -5, -20, -21, -10, 12, 27, 23, 10, -4, -12, -17, -23, 3, 13, 23, 25, 20, 14, 3, 7, 11, -4, -31, -43, -35, -21, -1, 19, 3, -3, -9, -16, -19, -7, 1, 7, 11, -2, -5, 5, 23, 20, 2, -10, 4, -22, -27, -23, -23, -11, 7, 14, 15, 15, 6, -3, -9, -6, 19, 44, 5, -5, -9, -8, -9, -7, 0, 17, 29, 22, 12, 12, 6, -8, -23, -32, 6, -31, -58, -64, -41, -12, -1, 3, 2, 0, 3, 6, 21, 37, 55, 74, 7, 12, 10, 1, 2, 6, 2, -5, -7, -3, -2, 0, 1, 1, -6, -19, 9, 1, 2, 12, 15, 11, -11, -33, -17, 13, 20, 9, 0, -7, -11, -13, 10, 21, 26, 24, 18, 4, -5, -13, -14, -6, 4, 7, -7, -19, -25, -25, 11, 1, -4, -7, -17, -28, -18, 4, 19, 27, 21, 12, 6, 2, -8, -20, 11, 4, -17, -36, -48, -39, -18, 0, 3, 1, 3, 6, 15, 27, 39, 49, 11, 3, -12, -26, -20, -2, 11, 16, 14, 9, 18, 19, 6, -7, -15, -25, 12, 0, -12, -7, -5, -15, -21, -14, -5, 4, 13, 22, 22, 13, 3, -8, 14, 17, 19, 17, 17, 16, 1, -9, -8, -5, -13, -11, -6, -7, -14, -27, 14, 33, 52, 50, 32, 12, -1, -6, -8, -14, -23, -30, -36, -35, -26, -13, 16, 11, 10, 15, 21, 13, 13, 10, 8, 4, 6, 6, -6, -25, -50, -52, 17, 9, 9, 23, 23, 10, 5, 16, 20, 13, 2, -18, -35, -39, -30, -23, 17, 31, 47, 49, 42, 32, 22, 8, -7, -21, -31, -30, -43, -53, -42, -21, 19, 37, 50, 42, 28, 24, 15, -8, -22, -22, -19, -28, -39, -39, -26, -12,, 39, 47, 31, 10, 0, 1, 1, -6, -15, -21, -23, -26, -25, -18, -13,, 12, 0, -7, -3, 1, -2, -12, -19, -19, -11, -1, 9, 14, 12, 5,, 33, 47, 55, 47, 23, -6, -18, -23, -24, -14, -9, -22, -34, -42, -33,, 13, -1, -20, -24, -13, -6, -6, -11, -16, -21, -24, -15, 9, 45, 71,, 15, 8, 4, 5, 6, 3, 4, -2, -17, -20, -8, 12, 9, -12, -28,, 10, 9, 20, 18, -4, -6, 1, 5, 9, 16, 18, -1, -22, -47, -48,, 22, 27, 42, 41, 33, 21, 0, -17, -27, -28, -37, -39, -32, -19, -8,, 4, -28, -27, -16, -5, 9, 28, 28, 0, -52, -61, -12, 18, 35, 56,, -6, -26, -22, -18, -18, -20, -28, -23, -3, 9, 3, 1, 17, 44, 66,, 21, 12, 10, 6, -5, 3, 8, 4, -1, 8, 11, -2, -16, -40, -43,, 11, -4, -9, -8, -10, -21, -37, -44, -26, 0, 8, 17, 29, 36, 35,, 11, 3, 7, 13, 14, 9, 2, -7, -13, -17, -12, -10, -10, -7, -8,, 24, 17, 12, 20, 7, -11, -10, -15, -16, -16, -5, 3, -4, -11, -21,, 26, 17, 6, -5, -16, -12, 2, -1, -9, -16, -7, 3, 3, -2, -15,, 15, -10, -29, -30, -17, 4, 16, 33, 29, 15, 6, -5, -18, -18, -18,, 12, 4, 16, 23, 12, 6, -1, -6, -7, 2, 8, -2, -19, -38, -37,, 16, -1, -15, -25, -15, -12, -9, 18, 29, 23, 12, -1, -13, -16, -20,, 28, 25, 33, 32, 6, -13, -20, -8, 4, 7, 0, -14, -25, -43, -40,, 25, 19, 17, 20, 8, -12, -34, -34, -19, -14, -6, 2, 4, 3, -9,, 28, 22, 14, 17, 16, 15, 8, -5, -19, -13, -4, -7, -20, -40, -41,, 1, -20, -4, -6, -32, -37, -28, -18, -11, -7, -3, 8, 21, 44, 63,, 42, 57, 45, 22, 6, 8, 2, -10, -27, -43, -50, -45, -33, -13, 9,, 25, 20, 24, 23, 6, 3, -2, -10, -8, 4, 8, -8, -27, -47, -45,, 40, 44, 29, 12, 0, -10, -18, -24, -20, -18, -23, -25, -19, -5, 4,, 45, 56, 51, 33, 16, 10, 6, -8, -21, -25, -42, -55, -52, -33, -16,, 53, 63, 61, 58, 44, 12, -26, -62, -68, -60, -61, -47, -18, 9, 9,, 28, 22, 17, 16, 16, 9, 0, -6, -12, -26, -31, -21, -13, -13, -19,, 23, 10, -15, -33, -24, -17, -15, -7, 0, -5, -10, -4, 5, 23, 35,, 23, 12, 0, -16, -22, -17, 0, 17, 19, 14, 7, -5, -16, -24, -27,, 32, -23, -51, -12, 33, 23, 0, -10, 1, -12, -29, -13, 9, 17, 0,, 69, 78, 62, 30, -9, -40, -49, -49, -44, -48, -51, -37, -10, 19, 44,, 21, 8, 11, 18, 8, 9, 8, 7, 3, 2, 1, -13, -28, -46, -44,, 27, 11, 6, 14, 5, -6, -1, -9, -26, -37, -18, 3, 5, 0, -11,, 31, 20, 13, 12, 6, -8, -12, -16, -16, -22, -18, -9, -6, -5, -10,, 33, 25, 21, 22, 18, 7, -4, -24, -33, -33, -20, -9, -8, -14, -22,, 52, 61, 57, 40, 27, 9, -12, -27, -37, -46, -50, -48, -40, -23, -2,, 31, 20, 18, 14, -8, -5, 4, 8, 4, -1, -2, -14, -28, -42, -38,, 29, 17, 19, 15, -9, -20, -18, -7, 1, 10, 9, -5, -15, -33, -33,, 33, 23, 18, 20, 2, -13, -6, -6, -9, -16, -13, -12, -18, -21, -21,, 58, 71, 51, 33, 19, -13, -42, -56, -58, -65, -67, -53, -17, 32, 65,, 31, 15, 10, 4, -16, -7, 5, 7, 8, 12, 8, -7, -26, -44, -40,, 40, 28, 23, 23, 6, -13, -20, -26, -18, -2, 3, -2, -13, -34, -36,, 23, -11, -15, 2, 3, 6, 5, 3, 4, 11, 11, -2, -17, -33, -32,, 54, 61, 49, 24, -1, -8, -3, -8, -21, -32, -43, -46, -39, -21, -9,, 30, 9, -8, -2, 0, -10, -12, -14, -12, -12, -2, 4, 2, -3, -14,, 35, 23, 15, 12, -8, -33, -27, -16, -12, -14, -4, 5, 0, -6, -13,, 31, 19, 12, 4, -5, 1, -1, -10, -14, -1, 5, -3, -15, -33, -34,, 28, 8, 8, 18, 13, 7, -3, -10, -8, -3, -3, -13, -23, -33, -31,, 40, 9, -22, -17, 6, 18, 19, 6, -11, -14, -5, 5, -9, -35, -35,, 47, 53, 51, 27, -3, -46, -65, -46, -33, -32, -29, -28, -17, 17, 56,, 43, 27, 25, 24, 2, -2, -1, -17, -19, -1, 6, -11, -33, -50, -40,48, 50, 47, 34, 9, -7, -10, -9, -10, -12, -17, -28, -33, -30, -19, -12, 48, 51, 51, 41, 25, 7, -18, -39, -47, -47, -44, -36, -21, -2, 14, 17, 48, 23, -3, 10, 21, -2, -9, -6, -4, -2, 8, 15, 0, -23, -40, -36, 50, 25, 2, -3, 4, 16, 13, -4, -21, -30, -30, -29, -20, -2, 13, 17, 59, 44, 18, 13, 23, 18, 8, -7, -28, -26, -8, -3, -10, -24, -42, -35, 61, 47, 30, 22, 25, 21, 8, -2, -16, -25, -14, -5, -15, -39, -56, -43, 62, 46, 31, 37, 38, 16, -13, -33, -25, -7, -1, -3, -20, -39, -51, -38, 63, 47, 23, 9, 5, -2, -13, -12, -8, -7, -14, -20, -26, -25, -15, -6, 63, 42, 20, 9, 7, 0, -10, -18, -21, -22, -24, -24, -22, -16, 0, 17, 64, 54, 43, 22, -17, -38, -42, -38, -37, -23, -17, -20, -15, -2, 22, 42, 64, 51, 36, 34, 35, 21, 6, -9, -34, -41, -20, -7, -18, -35, -48, -36, 66, 66, 65, 55, 35, 8, -9, -18, -29, -35, -39, -45, -47, -39, -24, -9, 67, 38, -11, -47, -53, -27, -14, -19, -21, -21, 0, 6, 9, 19, 31, 45, 70, 60, 50, 45, 32, 3, -17, -33, -34, -24, -10, -9, -22, -36, -44, -30, 75, 57, 34, 30, 34, 20, -7, -29, -42, -36, -21, -15, -19, -28, -32, -20, 76, 61, 27, -11, -30, -32, -29, -24, -24, -22, -18, -21, -16, 1, 22, 42, 96, 77, 40, 5, -17, -27, -30, -28, -25, -24, -22, -23, -23, -16, 1, 16, 99, 86, 61, 28, -5, -26, -39, -35, -34, -20, -5, -15, -34, -40, -22, 2, 127, 101, 43, -12, -35, -34, -40, -42, -40, -40, -41, -40, -31, -6, 28, 61 };Table 3 Codebook C related tables

[0193] With respect to Table 20, lrsns_st1C_Both_Word8[170 x 16] corresponds to animplementation of a compact storage of the residual CB (Cres,idx_C) (n) codebook, seeEquation 8. The composition of a CBC vector with index idxC employing CB (Cres,idx_C) isshown in Equation 12. The total required stored size for representing Codebook C thus becomes3x16 (for the conditional mean vector) + 170x16 (for the residual codebook CB (Cres,idx_C)) =2768 bytes.

[0194] FIG. 11 illustrates in detail how the initial CBB vector may be reconstructed in theencoder from a stored 14-bit codebook composition index, outlining the reuse and required modifications of the shorter vector entries in the two smaller codebooks LFCBQ11 andHFCBQ11. In addition, FIG. 11 illustrates in detail how the initial CBB vector is reconstructed inthe decoder from a received index idxB (which in turn points to a stored 14-bit CBB compositionindex), outlining the reuse and required modifications of the shorter vector entries in the two smaller codebooks LFCBQ11 and HFCBQ11.

[0195] Operations of an encoder (implemented using the structure of FIG. 3) will now bediscussed with reference to the flow chart of FIG. 12 according to some embodiments ofinventive concepts. For example, modules may be stored in memory 310 of FIG. 3, and thesemodules may provide instructions so that when the instructions of a module are executed byrespective encoder processing circuitry 312, encoder 202 performs respective operations of theflow chart.

[0196] FIG. 12 illustrates examples of operations performed by an encoder: receive a scalefactor target signal (1210), select a codebook capable of including an entry modified by vector polarity and vector order reversal (1220), perform stage1 vector quantization on the scale factor target signal using the codebook (1230), and determine to skip stage2 vector quantization based on a result of the stage1 vector quantization (1240).

[0197] Operations of a decoder (implemented using the structure of FIG. 4) will now bediscussed with reference to the flow chart of FIG. 13 according to some embodiments ofinventive concepts. For example, modules may be stored in memory 410 of FIG. 4, and thesemodules may provide instructions so that when the instructions of a module are executed byrespective decoder processing circuitry 412, decoder 212 performs respective operations of theflow chart.

[0198] FIG. 13 illustrates examples of operations performed by a decoder: receive an index(1310), select a codebook capable of including an entry modified by vector polarity and vector order reversal (1320), and generate a quantized scale factor signal from the index using the codebook (1330).

[0199] Various operations from the flow charts of FIGS. 12-13 may be optional withrespect to some embodiments of communication devices and related methods.

[0200] Although the computing devices described herein may include the illustratedcombination of hardware components, other embodiments may comprise computing devices with different combinations of components. It is to be understood that these computing devices may comprise any suitable combination of hardware and / or software needed to perform the tasks, features, functions and methods disclosed herein. Determining, calculating, obtaining or similar operations described herein may be performed by processing circuitry, which may process information by, for example, converting the obtained information into other information, comparing the obtained information or converted information to information stored in the network node, and / or performing one or more operations based on the obtained information or converted information, and as a result of said processing making a determination. Moreover, while components are depicted as single boxes located within a larger box, or nested within multiple boxes, in practice, computing devices may comprise multiple different physical components that make up a single illustrated component, and functionality may be partitioned between separate components. For example, a communication interface may be configured to include any of the components described herein, and / or the functionality of the components may be partitioned between the processing circuitry and the communication interface. In another example, non-computationally intensive functions of any of such components may beimplemented in software or firmware and computationally intensive functions may be implemented in hardware.

[0201] In certain embodiments, some or all of the functionality described herein may beprovided by processing circuitry executing instructions stored on in memory, which in certain embodiments may be a computer program product in the form of a non-transitory computer-readable storage medium. In alternative embodiments, some or all of the functionalities may beprovided by the processing circuitry without executing instructions stored on a separate or discrete device-readable storage medium, such as in a hard-wired manner. In any of those particular embodiments, whether executing instructions stored on a non-transitory computer- readable storage medium or not, the processing circuitry can be configured to perform the described functionality. The benefits provided by such functionality are not limited to theprocessing circuitry alone or to other components of the computing device but are enjoyed bythe computing device as a whole, and / or by end users and a wireless network generally.

[0202] Explanations are provided below for various abbreviations / acronyms used in thepresent disclosure. Abbreviation ExplanationCB Code BookDCT Discrete Cosine TransformDSP Digital Signal ProcessorIMDCT Inverse MDCTLBG Linde-Buzo-Gray (Vector Quantizer training method)MDCT Modulated DCTMPVQ Modular PVQ (improved PVQ enumeration and indexing scheme)MSE Mean Square ErrorMS-LVQ Multi-Scale Lattice VQMS-S-VQ Multi-Stage Split Vector QuantizerMSVQ Multi-Stage Vector QuantizerPVQ Pyramid VQSD Spectral DistortionSNR Signal to Noise RatioSNS Spectral Noise ShapingSplit-VQ Split Vector QuantizerSSNR Segmental Signal to Noise Ratio VQ Vector QuantizerVQ-1 Inverse Vector QuantizerWC Worst CaseWMOPS Weighted Million Operations per secondWMSE Weighed MSEWord16 Signed 16-bit (two byte) integer, e.g. as used in the ITU-T G.191 BasicOperators, a.k.a. int16_t Word32 Signed 32-bit (two byte) integer, e.g. as used in the ITU-T G.191 BasicOperators, a.k.a int32_t Word8 Signed 8-bit (one byte) integer, e.g. as used in the ITU-T G.191 BasicOperators , a.k.a. int18_t EMBODIMENTS1. A method of operating an encoder (202), the method comprising:receiving (1210) a scale factor target signal; selecting (1220) a codebook capable of including an entry modified by vector polarity and vector order reversal; and performing (1230) stage1 vector quantization on the scale factor target signal using the codebook.2. The method of Embodiment 1, the operations further comprising:determining (1240) to skip stage2 vector quantization based on a result of performing the stage1 vector quantization.3. A method of operating a decoder (212), the method comprising:receiving (1310) an index; selecting (1320) a codebook capable of including an entry modified by vector polarity and vector order reversal; and generating (1320) a quantized scale factor signal from the index using the codebook.4. An encoder (202) adapted to perform any of the operations of Embodiments 1-2.5. A computer program comprising program code to be executed by processing circuitry(302) of an encoder (202), whereby execution of the program code causes the encoder toperform any of the operations of Embodiments 1-2.6. A computer program product comprising a non-transitory storage medium (310) includingprogram code to be executed by processing circuitry (302) of an encoder (202), wherebyexecution of the program code causes the encoder to perform any of the operations ofEmbodiments 1-2.7. A decoder (212) adapted to perform any of the operations of Embodiment 4.8. A computer program comprising program code to be executed by processing circuitry(402) of a decoder (212), whereby execution of the program code causes the decoder to perform any of the operations of Embodiment 4.9. A computer program product comprising a non-transitory storage medium (410) includingprogram code to be executed by processing circuitry (402) of a decoder (212), whereby execution of the program code causes the decoder to perform any of the operations of Embodiment 4.

Claims

CLAIMS 1. A method of operating a two-stage vector quantizer, VQ, the method comprising:receiving an input target vector comprising a plurality of values;performing a search for the best matching code vector of an initial codebook, CBB;determining an MSE distortion for the initial codebook, CBB;determining whether the MSE distortion of the initial codebook, CBB, is below or above a firstthreshold; if the MSE distortion is below the first threshold, selecting the initial codebook, CBB;if the MSE distortion is above the first threshold, performing a search for the bestmatching code vector of an outlier codebook, CBC;determining an MSE distortion for the outlier codebook, CBC;selecting a codebook giving the lowest MSE distortion; performing a first stage vector quantization on the input target vector using the selectedcodebook to obtain a quantized first stage vector;determining whether the MSE distortion of the selected codebook is below or above a secondthreshold; andif the MSE distortion of the selected codebook is above the second threshold, calculating a firststage residual based on the initial codebook, CBB, and searching best matching code vector forthe residual using a second stage of the two-stage VQ.

2. The method of claim 1, the operations further comprising:if the MSE distortion of the selected codebook is below the second threshold, determining toskip the second stage search.

3. The method of claim 1 or 2, the operations further comprising:removing a DC component from the selected code vector of the initial codebook, CBB, beforedetermining the MSE distortion for the initial codebook.

4. The method of any of preceding claims, wherein performing the search of the outliercodebook, CBC, comprises applying different mean vectors for the varying degrees of voicing.

5. The method of any of preceding claims, wherein performing the search on the secondstage comprises evaluating five different shape vector candidates.

6. The method of any of preceding claims, wherein the second stage has three differentconfigurations, where two configurations use stacked unit pulses, and a third configuration uses three fixed shapes with non-stacked unit pulses.

7. The method of any of preceding claims, wherein the first stage residual is calculated bysubtracting the quantized first stage vector from the input target vector.

8. The method of any of preceding claims, the operations further comprising:evaluating whether the MSE distortion is smaller after the first stage vector quantization orafter the second stage vector quantization, andselecting the vector quantization stage that results in the lowest MSE distortion.

9. The method of any of preceding claims, wherein the input target vector values representscale factors.

10. The method of claim 9, wherein the quantized scale factors are output from the VQ andprovided for further processing where they are interpolated and applied to the spectralcoefficients of the modified discrete cosine transform, MDCT, operation to provide a noiseshaped signal for a subsequent MDCT coefficient quantization.

11. An audio encoder comprising a two-stage vector quantizer, VQ, configured to perform themethod according to at least one of the claims 1 to 8.

12. The audio encoder of claim 11, wherein the input target vector comprises scale factors andthe audio encoder is further configured to interpolate quantized scale factors and apply them tothe spectral coefficients of the modified discrete cosine transform, MDCT, operation to providea noise shaped signal for a subsequent MDCT coefficient quantization.

13. A two-stage vector quantizer, VQ, configured to:receiving an input target vector comprising a plurality of values;performing a search for the best matching code vector of an initial codebook, CBB;determining an MSE distortion for the initial codebook;determining whether the MSE distortion of the initial codebook is below or above a firstthreshold;if the MSE distortion is below the first threshold, selecting the initial codebook; if the MSE distortion is above the first threshold, performing a search for the best matching code vector of an outlier codebook, CBC;determining an MSE distortion for the outlier codebook; selecting a codebook giving the lowest MSE distortion;performing a first stage vector quantization on the input target vector using the selectedcodebook to obtain a quantized first stage vector;determining whether the MSE distortion of the selected codebook is below or above a secondthreshold; andif the MSE distortion of the selected codebook is above the second threshold, calculating a firststage residual based on the initial codebook, CBB, and searching best matching code vector forthe residual using a second stage of the two-stage VQ.

14. The two-stage vector quantizer of claim 13, wherein the two-stage VQ comprises a firststage split VQ and a second stage pyramid vector quantizer, PVQ.

15. The two-stage vector quantizer of claim 14, wherein the first stage split VQ employs atleast two different off-line trained stochastic codebooks.

16. The two-stage vector quantizer of any of claims 14 to 15, wherein the first stage split VQemploys two initial codebooks, CBAand CBB, and an outlier codebook, CBC, that isconditionally searched if the MSE distortion of both initial codebooks exceeds the firstthreshold.

17. The two-stage vector quantizer of any of claims 13 to 16, wherein the initial codebookCBB entries in sub codebooks are modified by vector polarity switch and vector order reversal.

18. The two-stage vector quantizer of any of claims 13 to 17, wherein the outlier codebook,CBC, is associated with a plurality of mean vectors, and a target vector for outlier codebook is formed by subtracting a selected mean vector from the input target vector.

19. The two-stage vector quantizer of claim 18, wherein one of the plurality of CBC meanvectors is selected based on voicing information.

20. The two-stage vector quantizer of claim 19, wherein the voicing information comprisestwo pitch flags, ^^^^ℎ^^ and ^^^^^^, where the flag ^^^^ℎ^^ is set to 1 if the normalizedcorrelation of the input time domain signal is higher than a third threshold, otherwise the flag is set to zero, and the flag ^^^^^^is set to 1 if the normalized correation of the time domain signalis higher than a fourth threshold, otherwise the flag is set to zero.

21. The two-stage vector quantizer of any of claims 13 to 20, wherein the second stage hasthree configurations, where two configurations employ PVQ, and a third configuration employs fixed envelopes with shifted signs, FESS.

22. The two-stage vector quantizer of claim 21, wherein the third configuration comprisesthree fixed shapes with non-stacked unit pulses.

23. The two-stage vector quantizer of claim 22, wherein each of the three fixed shapes isrepresented by one of a flat envelope, a decaying envelope and a mild centered bell envelope.

24. The two-stage vector quantizer of claim 22 or 23, wherein each of the three fixed shapes isassociated with four shift factors.

25. The two-stage vector quantizer of claim 24, wherein twelve consecutive signs with astarting point indicated by the shift factor are encoded for each of the fixed shapes followed byone of four different shift factors.

26. An audio encoder comprising the two-stage vector quantizer of any of claims 13 to 25.

27. A method of operating an encoder (202), the method comprising:receiving (1210) a scale factor target signal; selecting (1220) a codebook capable of including an entry modified by vector polarity and vector order reversal; and performing (1230) stage1 vector quantization on the scale factor target signal using the codebook.

28. The method of claim 27, the operations further comprising:determining (1240) to skip stage2 vector quantization based on a result of performing the stage1 vector quantization.

29. A method of operating a decoder (212), the method comprising:receiving (1310) an index; selecting (1320) a codebook capable of including an entry modified by vector polarity and vector order reversal; and generating (1320) a quantized scale factor signal from the index using the codebook.

30. An encoder (202) adapted to perform any of the operations of claims 27-28.

31. A computer program comprising program code to be executed by processing circuitry(302) of an encoder (202), whereby execution of the program code causes the encoder toperform any of the operations of claims 1-10 and 27-28.

32. A computer program product comprising a non-transitory storage medium (310) includingprogram code to be executed by processing circuitry (302) of an encoder (202), whereby execution of the program code causes the encoder to perform any of the operations of claims 1- 10 and 27-28.

33. A decoder (212) adapted to perform any of the operations of claim 29.

34. A computer program comprising program code to be executed by processing circuitry(402) of a decoder (212), whereby execution of the program code causes the decoder to perform any of the operations of claim 29.

35. A computer program product comprising a non-transitory storage medium (410) includingprogram code to be executed by processing circuitry (402) of a decoder (212), whereby execution of the program code causes the decoder to perform any of the operations of claim 29.

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