Envelope tracking system for radio frequency power amplifier and wireless communication apparatus comprising the same

Abstract

An envelope tracking system for a power amplifier (PA) is provided, which is configured to track the envelope component of a radio frequency (RF) signal over a wide bandwidth. The system comprises an auxiliary DC-to-DC converter, a main DC-to- DC converter, a fast switcher (in the form of a properly configured DC-to-DC converter) and a linear amplifier (LA). The auxiliary and main DC-to-DC converters are powered by a battery and generate output signals based on corresponding control signals. Each of the LA and the third DC-to-DC converter is fed with the output signal of the auxiliary DC-to-DC converter. The LA generates an output signal based on a modulation signal derived from the envelope component of the RF signal. The fast switcher generates an output signal based on a control signal, the modulation signal and a first error signal being a replica of the LA output signal. The main DC-to-DC converter further uses a second error signal to generate the second output signal, which is a replica of a combination of the output signal from the fast switcher and the LA output signal. The output signals from the main DC-to-DC converter, the fast switcher and the LA are combined into a PA supply at an output port of the ET system. The LA further uses a feedback signal to generate the LA output signal, which is defined based on the PA supply. There is a low-pass filter at the output of each of the DC-to-DC converters and the fast switcher, and each of the LA and the fast switcher is connected to the output port via a common or different AC coupling capacitor.

Description

[0001] ENVELOPE TRACKING SYSTEM FOR RADIO FREQUENCY POWER AMPLIFIER AND WIRELESS COMMUNICATION APPARATUS COMPRISING THE SAME

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of radio frequency (RF) power amplifiers (PAs). In particular, the present disclosure relates to an envelope tracking (ET) system for RF PAs, as well as to a wireless communication apparatus comprising one or more such ET systems.

[0004] BACKGROUND

[0005] In RF applications, ET is a power management technology in which a supply voltage being fed to an RF PA is adjusted or, in other words, modulated based on the envelope of an RF signal to amplified. Such technology may, for example, improve the efficiency level of RF PAs to help reduce power consumption and thermal dissipation in wireless communication devices (e.g., mobile phones).

[0006] Traditional ET systems for RF PAs often use a combination of an alternating current (AC)-coupled feedback (FB) amplifier and a direct current (DC)-to-DC converter. The DC-to-DC converter supplies current for generation of an average supply voltage for the RF PA, while the FB amplifier stabilizes the supply voltage by compensating for triangular error currents from the DC-to-DC converter. In this configuration, the DC-to-DC converter is also used as a current source for the envelope component of the RF signal to be amplified. The supply voltage changes more slowly compared to the envelope component of the RF signal. Therefore, if there is only one DC-to-DC converter in the ET system, it can be run either at a low speed with high efficiency (which is “good” for the supply voltage generation, but insufficient for properly tracking the envelope component of the RF signal) or at a high speed with moderate efficiency (which allows the envelope component of the RF signal to be properly tracked, but worsens the supply voltage generation). For this reason, this approach based on a single DC- to-DC converter faces limitations, especially with increasing modulation BWs. Furthermore, current errors and switching harmonics from the DC-DC converter can degrade the PA performance, leading to excessive power consumption and spectral impurities.

[0007] Therefore, there is a need for an improved ET system that can handle wider BWs, while maintaining amplification efficiency and minimizing power consumption.

[0008] SUMMARY

[0009] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure.

[0010] It is an objective of the present disclosure to provide a technical solution that provides efficient (in terms of power consumption, distortions, and applicability to wide BWs) envelope tracking for RF PAs.

[0011] The objective above is achieved by the features of the independent claims in the appended claims. Further embodiments and examples are apparent from the dependent claims, the detailed description, and the accompanying drawings.

[0012] According to a first aspect, an ET system for an RF PA is provided, which comprises a first DC-to-DC converter, a second DC-to-DC converter, a third DC-to-DC converter, and a linear amplifier (LA). The first DC-to-DC converter is powered by a battery and configured to receive a first control signal. The first control signal sets an operation mode of the first DC-to-DC converter. The first DC-to-DC converter is further configured to generate a first output signal based on the first control signal. The second DC-to-DC converter is powered by the battery and configured to receive a second control signal and a modulation signal. The second control signal sets an operation mode of the second DC-to-DC converter. The modulation signal is based on an envelope component of an RF signal. The second DC-to-DC converter is further configured to generate a second output signal based on the second control signal and the modulation signal. The LA is configured to receive the modulation signal and the first output signal. The first output signal is used as a supply signal for the LA. The LA is further configured to generate an LA output signal based on the modulation signal. The third DC-to-DC converter is configured to receive a third control signal, the first output signal, the modulation signal and a first error signal. The third control signal sets an operation mode of the third DC-to-DC converter, and the first error signal is a replica of the LA output signal. The first output signal is again used as a supply signal for the third DC-to-DC converter. The third DC-to-DC converter is further configured to generate a third output signal based on the third control signal, the modulation signal and the first error signal. The second DC-to-DC converter is further configured to receive a second error signal and generate the second output signal based on the second control signal, the modulation signal and the second error signal. The second error signal is a replica of a combination of the third output signal and the LA output signal. Furthermore, the ET system further comprises an output port configured to combine the second output signal, the third output signal and the LA output signal into a PA supply for the RF PA. The LA is further configured to receive a feedback signal and generate the LA output signal based on the modulation signal and the feedback signal. The feedback signal is defined based on the PA supply. The ET system further comprises a low-pass filter at an output of each of the first DC-to-DC converter, the second DC-to-DC converter and the third DC-to-DC converter. Each of the LA and the third DC-to-DC converter is connected to the output port via at least one common or different AC coupling capacitor.

[0013] In the ET system so configured, the PA supply may “follow” the envelope component of the RF signal over a wide BW, thereby contributing to a reduction in the RF PA power consumption.

[0014] Furthermore, the purposes of the error signals used in the ET system are as follows:

[0015] - the purpose of the first error signal (i.e. , the replica of the LA output signal) is to minimize the residual errors of the modulation signal which are generated by the third DC-to-DC converter (this may reduce the power contribution provided by the LA to a minimum and the power contribution provided by third DC-to-DC to a maximum); and

[0016] - the purpose of the second error signal (i.e., the replica of the combination of the third output signal and the LA output signal) is to minimize the residual errors of the modulation signal which are generated by the second DC-to-DC converter (this may reduce the power contribution provided by the combination of the LA and the third DC-to-DC converter to a minimum and the power contribution provided by the second DC-to-DC to a maximum).

[0017] It should be also noted that the first to third control signals may be used to properly set the gain contribution, BW and delay of the output signals generated by the first to third DC-to-DC converters, respectively.

[0018] In one exemplary embodiment of the first aspect, the first DC-to-DC converter comprises a three-level boost-buck converter or a resonant boost-buck converter. Using either of these converter types as the first DC-DC converter may reduce unwanted spurious-tone generation due to the fine granularity of the first output signal and soft switching, as well as improve efficiency due to zero- voltage switching (ZVS) and lower harmonic content to filtered by the low-pass filter at the output of the first DC- DC converter.

[0019] In one exemplary embodiment of the first aspect, the second DC-to-DC converter comprises a three-level interleaved boostbuck converter or a resonant interleaved boost-buck converter. Similarly, using either of these converter types as the second DC-DC converter may reduce unwanted spurious-tone generation due to the fine granularity of the second output signal and soft switching, as well as improve efficiency due to ZVS and lower harmonic content to be filtered by the low-pass filter at the output of the second DC-DC converter.

[0020] In one exemplary embodiment of the first aspect, the LA comprises a feedback (FB) LA and a feedforward (FF) LA connected in parallel with the FB LA. By using the FF LA, it is possible to allow the FB LA to operate with a lower gain, resulting in a higher BW.

[0021] In one exemplary embodiment of the first aspect, the third DC-to-DC converter comprises at least one M-ary interleaved converter, where M is a number of cores in each of the at least one M-ary interleaved converter. Each core in each of the at least one M-ary interleaved converter is based on at least one three-level interleaved buck converter or at least one resonant interleaved buck converter. By using either of these converter types as the third DC-to-DC converter, it is possible to provide high-efficient BP envelope generation due to ZVS, less harmonics, and high-efficient partial error current compensation. Moreover, these converter types may reduce the LA output signal, thereby reducing the RF PA power consumption even more.

[0022] In one exemplary embodiment of the first aspect, the resonant interleaved buck converter comprises at least one piezoelectric resonator-based power converter. The piezoelectric resonator-based power converter(s) may provide high-Q and high-density energy storage and less losses, thereby increasing the performance of the ET system.

[0023] In one exemplary embodiment of the first aspect, each of the second DC-to-DC converter, the third DC-to-DC converter and the LA is configured to receive the modulation signal with a delay defined such that the second output signal, the third output signal and the LA output signal come coherently to the output port. When these three signals appear coherently at the output port, the PA supply may be generated and provided to the RF PA more efficiently.

[0024] In one exemplary embodiment of the first aspect, the modulation signal is identical to the envelope component of the RF signal. In an alternative exemplary embodiment of the first aspect, if the RF PA comprises a transistor having a knee voltage, the modulation signal corresponds to the envelope component of the RF signal which is offset by the knee voltage. Thus, different variants of the modulation signal are possible, which may make the ET system according to the first aspect more flexible in use.

[0025] In one exemplary embodiment of the first aspect, the system further comprises a current mirror coupled to an output of the LA and configured to generate the first error signal. By using the current mirror, the first error signal may be generated more efficiently.

[0026] In one exemplary embodiment of the first aspect, the system further comprises a current mirror coupled to outputs of the LA and the third DC-DC converter and configured to generate the second error signal. By using the current mirror, the second error signal may be generated more efficiently.

[0027] According to a second aspect, a wireless communication apparatus is provided, which comprises a battery, a baseband processor (BBP), an RF PA, and the ET system according to the first aspect. The BBP is configured to generate an RF signal and obtain a modulation signal based on an envelope component of the RF signal, as well as to provide the modulation signal to the ET system. The RF PA is configured to amplify the RF signal. The ET system is coupled to the battery. The RF PA is further configured to be fed with the PA supply from the ET system. The wireless communication apparatus so configured may be efficiently used in wireless communication technologies that involve using RF signals for high-rate data transfer. To achieve higher data rates, it is required to employ one or more RF PAs to increase the output power of the RF signal(s). However, the increased output power of RF signal(s) can lead to increased power consumption and thermal dissipation in the wireless communication apparatus, thus compromising overall performance and user experience. At the same time, the use of the ET system according to the first aspect in the wireless communication device according to the second aspect may mitigate or even eliminate these drawbacks. Other features and advantages of the present disclosure will be apparent upon reading the following detailed description and reviewing the accompanying drawings.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present disclosure is explained below with reference to the accompanying drawings in which:

[0030] FIG. 1 shows a block diagram of a wireless communication apparatus comprising a radio frequency (RF) power amplifier (PA) according to one exemplary embodiment;

[0031] FIG. 2 shows a block diagram of an envelope tracking (ET) system included in the apparatus of FIG. 1 according to a first exemplary embodiment;

[0032] FIG. 3 shows different signals generated in the ET system according to the first exemplary embodiment;

[0033] FIG. 4 shows a block diagram of an ET system included in the apparatus of FIG. 1 according to a second exemplary embodiment;

[0034] FIG. 5 shows a block diagram of a fast switcher which may be used in the ET system of FIG. 2 or FIG. 3 according to a first exemplary embodiment; and

[0035] FIG. 6 shows a block diagram of a fast switcher which may be used in the ET system of FIG. 2 or FIG. 3 according to a second exemplary embodiment.

[0036] DETAILED DESCRIPTION

[0037] Various embodiments of the present disclosure are further described in more detail with reference to the accompanying drawings. However, the present disclosure may be embodied in many other forms and should not be construed as limited to any certain structure or function discussed in the following description. In contrast, these embodiments are provided to make the description of the present disclosure detailed and complete.

[0038] According to the detailed description, it will be apparent to the ones skilled in the art that the scope of the present disclosure encompasses any embodiment thereof, which is disclosed herein, irrespective of whether this embodiment is implemented independently or in concert with any other embodiment of the present disclosure. For example, the system and apparatus disclosed herein may be implemented in practice by using any numbers of the embodiments provided herein. Furthermore, it should be understood that any embodiment of the present disclosure may be implemented using one or more of the features presented in the appended claims.

[0039] The word “exemplary” is used herein in the meaning of “used as an illustration”. Unless otherwise stated, any embodiment described herein as “exemplary” should not be construed as preferable or having an advantage over other embodiments.

[0040] Although the numerative terminology, such as “first”, “second”, etc., may be used herein to describe various embodiments, elements or features, it should be understood that these embodiments, elements or features should not be limited by this numerative terminology. This numerative terminology is used herein only to distinguish one embodiment, element or feature from another embodiment, element or feature. For example, a first DC-to-DC converter discussed below could be called a second DC-to-DC converter, and vice versa, without departing from the teachings of the present disclosure.

[0041] As used in the embodiments disclosed herein, a radio frequency (RF) signal may refer to any signal that occurs in different frequency bands of the radio spectrum (e.g., in the so-called centimeter-wave (cm-wave) and millimeter-wave (mm-wave) bands). Such RF signals may be used, for example, in wireless communications, such as point-to-point communications, intersatellite links, and point-to-multipoint communications, etc.

[0042] According to the embodiments disclosed herein, a wireless communication apparatus may refer to a (mobile) user device or user equipment (UE), such as a wireless customer premises equipment (CPE) (e.g., a wireless router, switch, etc.), a mobile station, a mobile terminal, a subscriber unit, a mobile phone, a cellular phone, a smart phone, a cordless phone, a personal digital assistant (PDA), a wireless communication device, a laptop computer, a desktop computer, a tablet computer, a singleboard computer (SBC) (e.g., a Raspberry Pi device), a gaming device, a netbook, a smartbook, an ultrabook, a medical device or medical equipment, a biometric sensor, a wearable device (e.g., a smart watch, smart glasses, a smart wrist band, etc.), an entertainment device (e.g., an audio player, a video player, etc.), a vehicular component or sensor (e.g., a driver-assistance system), a smart meter / sensor, an unmanned vehicle (e.g., an industrial robot, a quadcopter, etc.) and its component (e.g., a self-driving car computer), industrial manufacturing equipment, a global positioning system (GPS) device, an Intemet-of- Things (loT) device, an Industrial loT (IIoT) device, a machine-type communication (MTC) device, a group of Massive loT (MIoT) or Massive MTC (mMTC) devices / sensors, or any other suitable device that uses the radio waves for operation. In some embodiments, the UE may refer to at least two collocated and inter-connected UEs thus defined.

[0043] As is known, a UE may be equipped with a power amplifier (PA) to amplify RF signals for transmission via one or more antennas. Furthermore, it may be required to manage RF signal amplification to maintain a desired transmission range and to conserve UE battery life. A desired transmit power level may depend, for example, on a wireless environment and / or a UE distance from a base station. All of this makes the power consumption of the PA an important factor to consider when amplifying an RF signal.

[0044] One technique for reducing the power consumption of the PA is envelope tracking (ET), which involves controlling a supply voltage of the PA based on the envelope of an RF signal (which is also referred to herein as the envelope component of the RF signal). In other words, the supply voltage of the PA is modulated with the envelope of the RF signal. More specifically, the ET technique implies that the PA amplifies the RF signal based on a time-dependent ET voltage (which is also referred to herein as the PA supply) generated in accordance with time-dependent amplitudes of the RF signal. In other words, the timedependent ET voltage corresponds to a time-dependent voltage envelope that tracks (e.g., rises and falls) a time-dependent power envelope of the RF signal. The better the time-dependent ET voltage envelope tracks the time-dependent power envelope, the more the PA can achieve high efficiency at high linearity.

[0045] However, the time-dependent ET voltage (or PA supply) may be highly susceptible to distortions caused, for example, by the operation of DC-to-DC converters typically used in ET systems, particularly when the time-dependent ET voltage should track the time-dependent power envelope of a higher modulation bandwidth (BW) (e.g., more than 200 MHz) RF signal. As a result, the time-dependent voltage envelope may become misaligned with the time- variant power envelope of the RF signal, thus causing unwanted distortions (e.g., amplitude clipping) in the RF signal.

[0046] The exemplary embodiments disclosed herein relate to an ET system for an RF PA that is configured to properly track the envelope component of an RF signal even over a wide BW. The ET system comprises an auxiliary DC-to-DC converter, a main DC-to-DC converter, a fast switcher (in the form of a properly configured DC-to-DC converter) and a linear amplifier (LA). Each of the auxiliary and main DC-to-DC converters is powered by a battery and configured to generate an output signal based on a corresponding control signal. Each of the LA and the fast switcher is fed with the output signal of the auxiliary DC-to-DC converter. The LA is configured to generate an LA output signal based on a modulation signal. The modulation signal itself is based on the envelope component of the RF signal. The fast switcher is configured to generate an output signal based on a corresponding control signal, the modulation signal and a first error signal being a replica of the LA output signal. The main DC-to-DC converter further uses a second error signal to generate the second output signal, with the second error signal being a replica of a combination of the output signal from the fast switcher and the LA output signal. The output signals from the main DC-to-DC converter, the fast switcher and the LA are combined into a PA supply at an output port of the ET system. The LA is further configured to use a feedback signal to generate the LA output signal, with the feedback signal being defined based on the PA supply. There is a low-pass filter at the output of each of the DC-to-DC converters and the fast switcher, and each of the LA and the fast switcher is connected to the output port via at least one (common or different) AC coupling capacitor.

[0047] FIG. 1 shows a block diagram of a wireless communication apparatus 100 according to one exemplary embodiment. The apparatus 100 may be implemented as (part of) any of the above-indicated UEs. The apparatus 100 comprises a battery 102, a baseband processor (BBP) 104, an RF PA 106, and an ET system 108.

[0048] The BBP 104 is configured to generate a desired RF signal and obtain a modulation signal "Mod " based on the envelope component of the RF signal. As should be known to those skilled in the art, the basic envelope information may be derived from the so-called I and Q signal components using the following calculation: where a is the scaling factor, and Vmlnis the parameter dependent on the PA transistor technology, i.e., the parameter which describes the minimal supply voltage for which a RF transistor can provide enough RF gain in a pre-distorted lineup.

[0049] The I and Q signal components may be used to represent a (sinusoidal) RF signal of a desired amplitude, frequency, and phase. For example, the I signal component may be used to represent an in-phase component of the RF signal and the Q signal component may be used to represent a quadrature component of the RF signal. The composite of the I and Q signal components may be an equivalent representation of the RF signal. In the context of the present disclosure, the BBP 104 is assumed to combine the functions of baseband signal processing and envelope detection and shaping. For instance, the BBP 104 may include a digital signal processor, a microprocessor, a programmable core, or any combination thereof. Moreover, in some implementations, two or more BBPs 104 may be included in the apparatus 100.

[0050] As for the modulation signal “Mod”, it may be either identical to the envelope component or represent its processed version. For example, if the RF PA 106 is based on a transistor, the modulation signal “Mod" may correspond to the envelope component offset, e.g., by a knee voltage of the transistor, so that when the offset envelope component reaches levels below a minimum allowable limit Vc of the transistor the PA supply is kept Vc to maintain gain. Any other transistor parameters may be also taken into account when processing the envelope component, such as a PA transistor gain versus the supply voltage, PA transistor memory effects, load conditions of the PA 106, a latency of any of the PA 106, the second DC-to-DC converter 202 and the third DC-to-DC converter 204, etc.

[0051] The ET system 108 is coupled to the battery 102 and the BBP 104. The ET system 108 is configured to generate a PA supply (voltage) for the RF PA 106 based on a battery voltage from the battery 102 and adjust or modulate the PA supply based on the modulation signal “Mod" received from the BBP 104 such that the PA supply “rises” and “falls” in accordance with the envelope component and, at the same time, corresponds to the minimum allowable limit for the RF PA 106 (which is defined by the PA gain drop at the min and max achievable pre-distortion based gain boost in the BBP 104). Preferred embodiments of the ET system 108 will be described below in detail with reference to FIGs. 2 and 3.

[0052] The RF PA 106 is configured to amplify the RF signal, while being fed with the PA supply from the ET system 108. As is known, the PA supply and the RF signal should be aligned in time. Even small time deviations will adversely affect the RF PA output signal (i.e., the amplified RF signal), leading, for example, to amplitude clipping. The RF PA 106 may be any electronic device that amplifies RF signals using solid-state components like transistors. It should be also noted that the BBP 104 and the ET system 108 may be used to supply only one RF PA 106. Optionally, the apparatus 100 may also comprise a driver 110 coupled between the BBP 104 and the RF PA 106. The driver 110 is a pre-amplifier that may be used to pre-amplify the RF signal before providing it to the RF PA 106. It should be noted that the apparatus 100 may comprise other intermediate functional blocks, such as digital-to-analogue converters, baseband to RF up-conversion circuitry, etc., which are well-known in the art and therefore not described herein.

[0053] FIG. 2 shows a block diagram of the ET system 108 included in the apparatus 100 according to a first exemplary embodiment. In the first exemplary embodiment, the ET system 108 comprises a first (auxiliary) DC-to-DC converter 200, a second (main) DC-to-DC converter 202, a third DC-to-DC converter 204 (also referred to herein as the fast switcher), and a linear amplifier (LA) 206. The functions of each of these elements of the ET system 108 will be described below in more detail.

[0054] The first DC-to-DC converter 200 is powered by the battery 102 and receives a first control signal “Ctrll” . The first control signal “Ctrll” sets the operation mode of the first DC-to-DC converter 200. The operation mode may refer to at least one of the following operational parameters: a gain, a bandwidth, and a delay. The first control signal “Ctrll” may be generated by the BBP 104 or any other control module which may be included in the apparatus 100. By using the first control signal “Ctrll”, the first DC-to-DC converter 200 generates a first output signal “Outl” which are further used as a supply signal by each of the third DC-to-DC converter 204, the LA 206 and the driver 110 (if it is used in the apparatus 100). Preferably, the first DC- to-DC converter 200 is implemented as a multi-level (e.g., three-level) boost-buck converter or a resonant boost-buck converter.

[0055] The second DC-to-DC converter 202 is powered by the battery 102 and receives a second control signal “Ctrl2” and the modulation signal " od" from the BBP 104. Similarly, the second control signal “Ctrl2” sets the operation mode of the second DC-to-DC converter 202, which may relate to any of the above-mentioned operational parameters. The second control signal “Ctrl2” may be again generated by the BBP 104 and any other control module included in the apparatus 100. By using these input signals, the second DC-to-DC converter 202 generates a second output signal “Out2”. Preferably, the second DC-to-DC converter 202 is implemented as a multi-level (e.g., three-level) interleaved boost-buck converter or a resonant interleaved boost-buck converter.

[0056] The LA 206 is fed with the first output signal “Outl” from the first DC-to-DC converter 200. The LA 206 further receives the modulation signal " od" from the BBP 104 and, in response, generates an LA output signal “LAouf’. Preferably, the LA 206 is implemented as a parallel connection of a feedback (FB) LA 208 and a feedforward (FF) LA 210, each of which is assumed to receive both “Outl” and “Mod”, as can be seen in FIG. 2.

[0057] The third DC-to-DC converter 204 is also fed with the first output signal “Outl” from the first DC-to-DC converter 200. The third DC-to-DC converter 204 further receives a third control signal “Ctrl3”, the modulation signal “Mod" from the BBP 104, and a first error signal “Errl”. Similarly, the third control signal “Ctrl3” sets the operation mode of the third DC-to-DC converter 204, which may relate to any of the above-mentioned operational parameters. The third control signal “Ctrl3” may be again generated by the BBP 104 and any other control module included in the apparatus 100. The first error signal “Errl” is a replica of the LA output signal “LAouf ’, which may be generated by implementing a current mirror to the output stage of the LA 206. Instead of the current mirror, any other circuits suitable for copying the output signal of the LA 206 can be used. By using these input signals, the third DC-to-DC converter generates a third output signal “Out3”. Preferably, the third DC-to- DC converter 204 is implemented as a multi-level (e.g., three-level) interleaved buck converter or a resonant interleaved buck converter; in the latter case, it may comprise one or more piezoelectric resonator-based power converters.

[0058] As can be seen in FIG. 2, the second DC-to-DC converter 202 further receives a second error signal “Err2” that is a replica of a combination of the third output signal “Out3” and the LA output signal “LAout”, and uses it, together with the other input signals (i.e., “Ctrl2” and “Mod") to generate the second output signal “Out2”. The signal “Err2” may be presented as the sum of the replicas of the output signals “LAout” and “Out3”, and this sum may be obtained by implementing a current mirror to the output stage of the LA 206 and the third DC-DC converter 204. Instead of the current mirror, any other circuits suitable for copying the sum of the output signals of the LA 206 and the third DC-to-DC converter 204 can be used. The ET system 108 further comprises an output port 212 at which the second output signal “Out2”, the third output signal “Out3” and the LA output signal “LAout” are combined into a PA supply for the RF PA 106. Preferably, the BBP 104 delays the modulation signal " od" for each of the second DC-to-DC converter 202, the third DC-to-DC converter 204 and the LA 206 such that their output signals (i.e., “Out2”, “Out3” and “LAouf”) are coherently received at the output port 212. It should be noted that such delays may be the same or different - for example, the third DC-to-DC converter 204 and the LA 206 may receive the modulation signal “Mod” with the same delay, while the second DC-to-DC converter 202 may receive the modulation signal “Mod" with a different delay.

[0059] As also follows from FIG. 2, the LA 206 (e.g., the FB LA 208 if the LA 206 is implemented as the above-indicated parallel connection of the FB LA 208 and the FF LA 210) further receives a feedback signal “FB” that is generated from the PA supply. In particular, the feedback signal “FB” is determined by a FB circuit 214 based on the PA supply. In general, the feedback signal “FB” should be defined so as to properly generate the LA output signal “LAouF. The feedback signal “FB” is a representation of the PA supply without “sinking” power from the PA supply to the LA 206 (or the FB LA 208). In this sense, the feedback signal “FB” is voltage sensing feedback.

[0060] The ET system 108 further comprises low-pass filters (LPFs) 216, 218 and 220 at the outputs of the first DC-to-DC converter 200, the second DC-to-DC converter 202 and the third DC-to-DC converter 204, respectively. Such LPF s are needed to separate the elements of the ET system 108 from each other.

[0061] In the ET system 108 according to the first exemplary embodiment, each of the LA 206 and the third DC-to-DC converter 204 is connected to the output port 212 via a common AC coupling capacitor 222. The purpose of the AC coupling capacitor 222 is explained below with reference to FIG. 3.

[0062] FIG. 3 shows different signals generated in the ET system 108 according to the first exemplary embodiment. More specifically, a signal 300 (solid line) corresponds to a required PA supply, a signal 302 (dashed line) corresponds to the square root of the mean (average) value of the PA supply generated by the second DC-to-DC converter 202of the ET system 108, a signal 304 (dash-dotted line) corresponds to the envelope component signal of the PA supply generated, and a signal 306 (dotted line) corresponds to the AC coupled response of the signal 304. The signal 304 is smaller than the signal 300 (i.e., the PA supply), for which reason the LA 206 and the third DC-to-DC converter 204 which generate the signal 204 may be supplied from a lower voltage (i.e., the first output signal “Outl” which is generated by the first DC-to-DC converter 200). The signal 306 is generated jointly by the LA 206 and the third DC-to-DC converter 204, and the AC coupling capacitor 222 is used to add the signal 306 to the signal 302 generated by the second DC-to-DC converter 202.

[0063] FIG. 4 shows a block diagram of the ET system 108 included in the apparatus 100 according to a second exemplary embodiment. In the second exemplary embodiment, the ET system 108 comprises a first (auxiliary) DC-to-DC converter 400, a second (main) DC-to-DC converter 402, a third DC-to-DC converter 404 (also referred to herein as the fast switcher), and an LA 406, which may be implemented in the same or similar manner as the first DC-to-DC converter 200, the second DC-to-DC converter 202, the third DC-to-DC converter 204, and the LA 206, respectively. For example, the LA 406 may be implemented as a similar parallel connection of an FB LA 408 and an FF LA 410.

[0064] The functions of the elements of the ET system 108 according to the second exemplary embodiment are also the same as or similar to those according to the first exemplary embodiment. The first DC-to-DC converter 400 is powered by the battery 102 and receives the first control signal “Ctrll” to generate the first output signal “Outl”. The second DC-to-DC converter 402 is powered by the battery 102 and receives the second control signal “Ctrl2”, the modulation signal “Mod" from the BBP 104 and the second error signal “Err2” to generate the second output signal “Out2”. The LA 406 receives the modulation signal “Mod" from the BBP 104, the first output signal “Outl” (used as a supply signal) from the first DC-to-DC converter 400 and the feedback signal “FB” (via a feedback circuit 414) and, in response, generates the LA output signal “LAout”. The third DC- to-DC converter 404 receives the third control signal “CtrlS”, the first output signal “Outl” (used as a supply signal) from the first DC-to-DC converter 400, the modulation signal "Mod' from the BBP 104 and the first error signal “Errl” and, in response, generates the third output signal “Out3”. The second output signal “0ut2”, the third output signal “Out3” and the LA output signal “LAout” are similarly combined at an output port 412 into a PA supply for the RF PA 106.

[0065] Like in the first exemplary embodiment, in the second exemplary embodiment the ET system 108 further comprises low-pass filters (LPFs) 416, 418 and 420 at the outputs of the first DC-to-DC converter 400, the second DC-to-DC converter 402 and the third DC-to-DC converter 404, respectively.

[0066] At the same time, the ET system 108 according to the second exemplary embodiment is characterized in that each of the LA 406 and the third DC-to-DC converter 404 is connected to the output port 412 via a different AC coupling capacitor. More specifically, the LA 406 is connected to the output port 412 via an AC coupling capacitor 422, while the third DC-to-DC converter 404 - via an AC coupling capacitor 424. The AC coupling capacitors 422 and 424 are used for the same as the capacitor 222.

[0067] FIG. 5 shows a block diagram of a fast switcher 500 which may be used in the ET system 108 according to a first exemplary embodiment. In other words, the fast switcher 500 may be used as the third DC-to-DC converter 204 or 404. The fast switcher 500 may comprise one or more M-ary interleaved converters to increase the converter speed or BW, where M is the number of cores in each M-ary interleaved converter. Although the fast switcher 500 is shown to comprise two cores 502 and 504, this should not be construed as any limitation of the present disclosure (in other embodiments, the number of cores may be more than two). The core 502 comprises cells 506-1 - 506-n, and the core 504 comprises cells 508-1 - 508-n. To derive the max effective switcher frequency, the total number of the cells per core is multiplied with the max switch frequency of each core. The cores 502 and 504 are separated from each other through an inductor at the output of each core. Furthermore, each of the cores 502 and 504 is implemented based on interleaved three-level buck converters. Three- level buck converter cores may have up to two (maximum four) switching cells forming interleaving switching, i.e., these cell outputs are hard-connected together and then fed to the inductor to form a corresponding core.

[0068] FIG. 6 shows a block diagram of a fast switcher 600 which may be used in the ET system 108 according to a second exemplary embodiment. Like the fast switcher 500, the fast switcher 600 may be used as the third DC-to-DC converter 204 or 404. Furthermore, the fast switcher 600 may also comprise one or more M-ary interleaved converters to increase the converter speed or BW, where M is the number of cores in each M-ary interleaved converter. The fast switcher 600 comprises two cores 602 and 604; again, the number of the cores (i.e., two) is taken for illustrative purposes only and should not be construed as any limitation of the present disclosure. The core 602 comprises cells 606-1 - 606-n, and the core 604 comprises cells 608-1 - 608- n. Similarly, the cores 602 and 604 are separated from each other through an inductor at the output of each core. Unlike the cores 502 and 504, the cores 602 and 604 are based on resonant interleaved buck converters (e.g., interleaved piezo-resonant buck converter). Such piezo-resonant buck cores may have up to four (maximum 8) switching cells forming interleaving switching, i.e., these cell outputs are hard-connected together and then fed to the inductor to form a corresponding core.

[0069] Let us now give two non-restrictive numerical examples regarding the fast switchers 500 and 600.

[0070] Example 1 :

[0071] The fast switcher 500 is assumed to comprise 12 cores each having two interleaved three-level buck converter cells. In this example, the fast switcher will generate an equivalent switcher frequency of 12 ■ 2 ■ fsw3L, where fsw3L is the maximum switch frequency of one three-level buck converter.

[0072] Example 2: The fast switcher 600 is assumed to comprise 12 cores each having four interleaved piezo-resonant buck converter cells. In this example, the fast switcher 600 will generate an equivalent switcher frequency of 12 ■ 4 ■ fswpr, where fswpr is the maximum switch frequency of one piezo-resonant buck converter.

[0073] Although the exemplary embodiments of the present disclosure are described herein, it should be noted that any various changes and modifications could be made in the embodiments of the present disclosure, without departing from the scope of legal protection which is defined by the appended claims. In the appended claims, the word “comprising” does not exclude other elements or operations, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS1. An envelope tracking, ET, system for a radio frequency, RF, power amplifier, PA, comprising: a first direct current- to-direct current, DC-to-DC, converter powered by a battery and configured to: receive a first control signal setting an operation mode of the first DC-to-DC converter; and generate a first output signal based on the first control signal; a second DC-to-DC converter powered by the battery and configured to: receive a second control signal and a modulation signal, the second control signal setting an operation mode of the second DC-to-DC converter, the modulation signal being based on an envelope component of an RF signal; and generate a second output signal based on the second control signal and the modulation signal; a linear amplifier, LA, configured to: receive the modulation signal and the first output signal, the first output signal being a supply signal for the LA; and generate an LA output signal based on the modulation signal; and a third DC-to-DC converter configured to: receive a third control signal, the first output signal, the modulation signal and a first error signal, the first output signal being a supply signal for the third DC-to-DC converter, the third control signal setting an operation mode of the third DC-to-DC converter, the first error signal being a replica of the LA output signal; and generate a third output signal based on the third control signal, the modulation signal and the first error signal; wherein the second DC-to-DC converter is further configured to receive a second error signal and generate the second output signal based on the second control signal, the modulation signal and the second error signal, the second error signal being a replica of a combination of the third output signal and the LA output signal; wherein the ET system further comprises an output port configured to combine the second output signal, the third output signal and the LA output signal into a PA supply for the RF PA; wherein the LA is further configured to receive a feedback signal and generate the LA output signal based on the modulation signal and the feedback signal, the feedback signal being defined based on the PA supply; wherein the ET system further comprises a low-pass filter at an output of each of the first DC-to-DC converter, the second DC-to-DC converter and the third DC-to-DC converter; and wherein each of the LA and the third DC-to-DC converter is connected to the output port via at least one common or different alternating-current, AC, coupling capacitor.

2. The system of claim 1, wherein the first DC-to-DC converter comprises a three-level boost-buck converter or a resonant boost-buck converter.

3. The system of claim 1 or 2, wherein the second DC-to-DC converter comprises a three-level interleaved boost-buck converter or a resonant interleaved boost-buck converter.

4. The system of any one of claims 1 to 3, wherein the LA comprises a feedback, FB, LA and a feedforward LA connected in parallel with the FB LA.

5. The system of any one of claims 1 to 4, wherein the third DC-to-DC converter comprises at least one M-ary interleaved converter, where M is a number of cores in each of the at least one M-ary interleaved converter, andwherein each core in each of the at least one M-ary interleaved converter is based on at least one three-level interleaved buck converter or at least one resonant interleaved buck converter.

6. The system of claim 5, wherein each of the at least one resonant interleaved buck converter comprises at least one piezoelectric resonator-based power converter.

7. The system of any one of claims 1 to 6, wherein each of the second DC-to-DC converter, the third DC-to-DC converter and the LA is configured to receive the modulation signal with a delay defined such that the second output signal, the third output signal and the LA output signal come coherently to the output port.

8. The system of any one of claims 1 to 7, wherein the modulation signal is identical to the envelope component of the RF signal.

9. The system of any one of claims 1 to 7, wherein the RF PA comprises a transistor having a knee voltage, and wherein the modulation signal corresponds to the envelope component of the RF signal which is offset by the knee voltage.

10. The system of any one of claims 1 to 9, further comprising a current mirror coupled to an output of the LA and configured to generate the first error signal.

11. The system of any one of claims 1 to 10, further comprising a current mirror coupled to outputs of the LA and the third DC-DC converter and configured to generate the second error signal.

12. A wireless communication apparatus comprising: a battery; a baseband processor, BBP, configured to generate a radio frequency, RF, signal and obtain a modulation signal based on an envelope component of the RF signal; an RF power amplifier, PA, configured to amplify the RF signal; and the ET system according to any one of claims 1 to 11, the ET system being coupled to the battery; wherein the BBP is further configured to provide the modulation signal to the ET system; and wherein the RF PA is further configured to be fed with the PA supply from the ET system.

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