Display panel

Abstract

A display panel (100), comprising: an array substrate (10), a liquid crystal layer (20), and an opposite substrate (30) which are arranged in sequence; the opposite substrate (30) comprises a black matrix layer (32), and the black matrix layer (32) is provided with an opening (m1); the array substrate (10) comprises a second common electrode (12) and a pixel electrode (13), the pixel electrode (13) comprises a pixel portion (px), a first connection portion (p1), and a second connection portion (p2); the second connection portion (p2) is connected to a thin film transistor (tft); the pixel portion (px) comprises a first trunk electrode (z1) and a first branch electrode (h1) connected to the first trunk electrode (z1); the first connection portion (p1) is connected to the second connection portion (p2) and the first branch electrode (h1). In a plan view of the display panel (100), the black matrix layer (32) covers the first connection portion (p1) and the second connection portion (p2), and the second common electrode (12) and the pixel portion (px) are within a region in which the opening (m1) is located, an included angle formed between the extension direction of the first connection portion (p1) and the extension direction (F3) of the first branch electrode (h1) being greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connection portion (p1) being consistent with the extension direction (F3) of the first branch electrode (h1).

Description

Display panel

[0001] This application claims priority to Chinese Patent Application No. 202411115391.1, filed on August 14, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0003] In the architecture of the vertical alignment technology, in the TSS (Transparent Storage capacity and Shielding-layer) pixel architecture of the liquid crystal display panel, a transparent electrode layer is newly added to replace the DBS (Data line BM less), the transparent electrode layer overlaps the data line, the data line can be shielded by controlling the electric field, and a large transparent storage capacitor is formed between the transparent electrode layer and the pixel electrode, which can greatly improve the light transmittance and the storage capacity. However, a connection corner gj (as shown in FIG. 1) of approximately 90 degrees is formed between the pixel electrode pix located in the opening area and the via portion gk, the connection corner gj is adjacent to the opening area, and the transparent electrode layer tm passes through, when the panel is lit, due to the influence of the boundary electric field generated by the transparent electrode layer tm and the corner gj, the liquid crystal at the connection corner gj is inverted to chaos, thereby forming a dark line in the opening area, as shown in FIG. 2. SUMMARY

[0004] The embodiments of the present application provide a display panel, which can reduce the risk of dark lines in the opening area.

[0005] The embodiments of the present application provide a display panel, which comprises an array substrate, a liquid crystal layer and an opposite substrate arranged in sequence, the opposite substrate comprises a first substrate, a black matrix layer and a first common electrode, the black matrix layer is arranged on the side of the first substrate close to the liquid crystal layer, the first common electrode is arranged on the side of the black matrix layer close to the liquid crystal layer, and the black matrix layer is provided with an opening.

[0006] The array substrate comprises a second substrate, a second common electrode and a pixel electrode, the second common electrode is arranged on the side of the second substrate close to the liquid crystal layer, and the pixel electrode is arranged on the side of the second common electrode close to the liquid crystal layer and is different from the second common electrode in layer.

[0007] The pixel electrode comprises a pixel part, a first connecting part and a second connecting part, the second connecting part is connected to a thin film transistor, the pixel part comprises a first main trunk electrode and a first branch electrode connected to the first main trunk electrode; the first connecting part connects the second connecting part and the first branch electrode;

[0008] In a plan view of the display panel, the black matrix layer covers the first connecting part and the second connecting part, and the second common electrode and the pixel part are in the region of the opening, wherein an included angle formed by an extension direction of the first connecting part and an extension direction of the first branch electrode is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connecting part is consistent with the extension direction of the first branch electrode. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a schematic diagram of a display panel of the related art;

[0010] FIG. 2 is a schematic diagram of simulated light transmission effect when the distance between a corner and a transparent electrode layer of the display panel of the related art is close to 0;

[0011] FIG. 3 is a schematic diagram of a cross-sectional structure of a display panel according to an embodiment of the present application;

[0012] FIG. 4 is a schematic diagram of a plan view of a display panel according to an embodiment of the present application;

[0013] FIG. 5 is an enlarged schematic diagram of portion A in FIG. 4;

[0014] FIG. 6 is an enlarged schematic diagram of portion B in FIG. 5;

[0015] FIG. 7 is a schematic diagram of an array substrate in FIG. 6;

[0016] FIG. 8 is an enlarged schematic diagram of portion C in FIG. 7;

[0017] FIG. 9 is a schematic diagram of a display panel according to one or more embodiments of the present application;

[0018] FIG. 10 is a schematic diagram of simulated light transmission effect when the shortest distance L1 is increased;

[0019] FIG. 11 is a schematic diagram of a display panel according to one or more embodiments of the present application;

[0020] FIG. 12 is a schematic diagram of a display panel according to one or more embodiments of the present application. Embodiments of the present application

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application. In addition, it should be understood that the specific implementation described herein is only used to illustrate and explain the present application, and is not used to limit the present application. In the present application, the embodiments can be combined with each other but will not be described one by one, and the positional words such as "upper" and "lower" are generally used to refer to the upper and lower of the device in the actual use or working state, and the specific is the direction of the drawing surface in the drawings; and "inner" and "outer" are used in relation to the outline of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose a numerical requirement or establish an order.

[0022] It should be noted that the technical problem described in the background art is that the inventors found that dark lines appear in the opening area when the liquid crystal panel using the TSS pixel architecture adopts the vertical alignment technology. Subsequently, the inventors found that the boundary electric field formed by the transparent electrode layer tm and the corner gj affects the deflection of the liquid crystal in the corner gj region, causing the liquid crystal in this region to be inverted randomly, thereby causing dark lines to appear in the opening area.

[0023] And the display panel of the present application improves the inversion of liquid crystal by improving the corner gj, thereby improving the dark lines.

[0024] The display panel provided by the embodiments of the present application comprises an array substrate, a liquid crystal layer and an opposite substrate arranged in sequence, the opposite substrate comprises a first substrate, a black matrix layer and a first common electrode, the black matrix layer is arranged on the side of the first substrate close to the liquid crystal layer, the first common electrode is arranged on the side of the black matrix layer close to the liquid crystal layer, and the black matrix layer is provided with an opening.

[0025] The array substrate comprises a second substrate, a second common electrode and a pixel electrode, the second common electrode is arranged on the side of the second substrate close to the liquid crystal layer, and the pixel electrode is arranged on the side of the second common electrode close to the liquid crystal layer and is different from the second common electrode in layer.

[0026] The pixel electrode comprises a pixel part, a first connecting part and a second connecting part, the second connecting part is connected to a thin film transistor, the pixel part comprises a first trunk electrode and a first branch electrode connected to the first trunk electrode, and the first connecting part connects the second connecting part and the first branch electrode.

[0027] In a plan view of the display panel, the black matrix layer covers the first connecting part and the second connecting part, and the second common electrode and the pixel part are in the region of the opening, wherein an included angle formed by an extension direction of the first connecting part and an extension direction of the first branch electrode is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connecting part is consistent with the extension direction of the first branch electrode.

[0028] Optionally, in some embodiments of the present application, the extension direction of the first connecting part is consistent with the extension direction of the first branch electrode, the second connecting part includes a via subpart and an extension subpart connecting the via subpart, the via subpart connects the thin film transistor, and the extension subpart connects the first connecting part.

[0029] In a plan view of the display panel, the first trunk electrode extends along a first direction; in the first direction, a shortest distance from an intersection line of the extension subpart and the first connecting part to the second common electrode is greater than or equal to 1.3 microns.

[0030] Optionally, in some embodiments of the present application, in a plan view of the display panel, the extension subpart extends along a second direction perpendicular to the first direction; in the first direction, a shortest distance from an intersection line of the extension subpart and the first connecting part to the second common electrode is greater than or equal to 1.5 microns.

[0031] Optionally, in some embodiments of the present application, the extension direction of the first connecting part is consistent with the extension direction of the first branch electrode, the second connecting part includes a via subpart, a first extension subpart and a second extension subpart, the via subpart connects the thin film transistor, the second extension subpart connects the first connecting part, and the first extension subpart connects the via subpart and the second extension subpart.

[0032] In a plan view of the display panel, the second extension subpart and the first connecting part are cross-connected, and the first trunk electrode extends along a first direction; in the first direction, a shortest distance from an intersection line of the second extension subpart and the first connecting part to the second common electrode is greater than or equal to 1.3 microns.

[0033] Optionally, in some embodiments of the present application, in a plan view of the display panel, the first extension subpart extends along a second direction perpendicular to the first direction, and the second extension subpart is cross-connected with the first extension subpart; in the first direction, a shortest distance from an intersection line of the second extension subpart and the first connecting part to the second common electrode is greater than or equal to 1.5 microns.

[0034] Optionally, in some embodiments of the present application, the number of the first connecting portions is at least two, one first connecting portion corresponds to one first branch electrode, and a slit is formed between two adjacent first branch electrodes.

[0035] In a second direction perpendicular to the first direction, the distance between two adjacent first connecting portions is equal to the width of the slit.

[0036] Optionally, in some embodiments of the present application, the number of the first connecting portions is at least two, one first connecting portion corresponds to one first branch electrode, and a slit is formed between two adjacent first branch electrodes.

[0037] In a second direction perpendicular to the first direction, the distance between two adjacent first connecting portions is greater than twice the width of the slit.

[0038] Optionally, in some embodiments of the present application, the display panel further comprises a data line, in a plan view of the display panel, the data line extends along the first direction; in a second direction perpendicular to the first direction, the distance from the intersection of the first connecting portion and the second connecting portion to the data line is greater than 1 micrometer.

[0039] Optionally, in some embodiments of the present application, the first connecting portion and the second connecting portion are connected to form a corner, in a plan view of the display panel, the side of the corner close to the data line is rounded.

[0040] Optionally, in some embodiments of the present application, the number of the first connecting portions is at least two, one first connecting portion corresponds to one first branch electrode, and a slit is formed between two adjacent first branch electrodes.

[0041] In a second direction perpendicular to the first direction, the shortest distance from the first connecting portion to the first trunk electrode is greater than twice the width of the slit.

[0042] Optionally, in some embodiments of the present application, the width of the first connecting portion is equal to the width of the first branch electrode.

[0043] Optionally, in some embodiments of the present application, the black matrix layer comprises a plurality of light shielding strips, the light shielding strips are arranged at intervals along the first direction, the light shielding strips extend along a second direction perpendicular to the first direction, and the openings are formed between two adjacent light shielding strips.

[0044] The second common electrode and the first common electrode are configured to be connected to the same voltage. The second common electrode includes a first portion and a second portion. In a plan view of the display panel, the first portion is arranged in the region of the opening and overlaps the pixel portion. The first portion also covers a portion of the data line located in the opening. The second portion is connected to opposite sides of the first portion. The second portion covers a portion of the data line located in the region of the light shielding strip.

[0045] The display panel of the embodiment of the present application includes an array substrate and an opposite substrate. In a plan view of the display panel, the black matrix layer covers the first connection portion and the second connection portion, and the second common electrode and the pixel portion are located in the region of the opening. The extension direction of the first connection portion forms an angle with the extension direction of the first branch electrode that is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connection portion is consistent with the extension direction of the first branch electrode.

[0046] The angle formed by the extension direction of the first connection portion and the extension direction of the first branch electrode is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connection portion is consistent with the extension direction of the first branch electrode. Under the influence of the boundary electric field based on the second common electrode and the pixel electrode, the direction of the liquid crystal in the region near the first connection portion can be improved, and the dark lines in the opening region can be improved.

[0047] The embodiment of the present application provides a display panel, which is described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0048] The display panel 100 of the present application adopts a vertical alignment (VA) technology driving architecture.

[0049] In FIG. 3, the embodiment of the present application provides a display panel 100, which includes an array substrate 10, a liquid crystal layer 20, and an opposite substrate 30 arranged in sequence.

[0050] The opposite substrate 30 includes a first substrate 31, a black matrix layer 32, and a first common electrode 33. The black matrix layer 32 is arranged on the side of the first substrate 31 close to the liquid crystal layer 20. The first common electrode 33 is arranged on the side of the black matrix layer 32 close to the liquid crystal layer 20.

[0051] The array substrate 10 comprises a second substrate 11, a second common electrode 12 and a pixel electrode 13. The second common electrode 12 is arranged on the side of the second substrate 11 close to the liquid crystal layer 20. The pixel electrode 13 is arranged on the side of the second common electrode 12 close to the liquid crystal layer 20.

[0052] It should be noted that the first common electrode 33 of the opposite substrate 30 and the pixel electrode 13 of the array substrate 10 form a vertical electric field after being connected to different voltages, so as to drive the liquid crystal of the liquid crystal layer 20 to deflect, thereby realizing picture display.

[0053] In addition, the second common electrode 12 and the first common electrode 33 are arranged to be connected to the same common voltage, so that a boundary electric field affecting the deflection of the liquid crystal is formed between the second common electrode 12 and the pixel electrode 13.

[0054] Secondly, in the area avoiding the pixel electrode 13, the second common electrode 12 and the first common electrode 33 will not form an electric field between them due to being connected to the same common voltage, so that the liquid crystal in this area does not deflect, and therefore the second common electrode 12 can be used to cover the data line data, thereby achieving the effect of shielding the data line data, so as to save the part of the black matrix layer 32 corresponding to the data line data.

[0055] Optionally, the array substrate 10 further comprises a scan line, a data line data and a thin film transistor tft, which are arranged on the side of the second substrate 11 close to the liquid crystal layer 20. The scan line is connected to the gate electrode of the thin film transistor tft, the data line data is connected to the input electrode of the thin film transistor tft, and the output electrode of the thin film transistor tft is connected to the pixel electrode 13.

[0056] Optionally, the scan line is arranged in the same layer as the gate electrode of the thin film transistor tft, but is not limited thereto. The data line data and the source / drain electrode of the thin film transistor tft are arranged in the same layer, but are not limited thereto.

[0057] Among them, the thin film transistor tft can be top-gate type, bottom-gate type or double-gate type, and FIG. 3 takes the top-gate type as an example, but is not limited thereto. Since the structure of the thin film transistor tft is prior art, it will not be described here.

[0058] In some embodiments, the array substrate 10 further comprises a color filter layer cf and a planarization layer tp, the color filter layer cf is formed above the thin film transistor tft. The second common electrode 12 is arranged on the side of the color filter layer cf close to the liquid crystal layer 20. The planarization layer tp covers the second common electrode 12. The pixel electrode 13 is arranged on the side of the planarization layer tp close to the liquid crystal layer 20.

[0059] Optionally, the color filter layer cf includes red color resist, green color resist and blue color resist, one color resist corresponding to one pixel electrode 13. The data line data is arranged between two adjacent color resist.

[0060] It should be noted that, in addition to the color filter layer cf formed on the array substrate 10, the color filter layer cf can also be formed on the opposite substrate 30.

[0061] In FIG. 4, the first direction F1 can be a direction parallel to one side of the display panel 100 in a plan view, and can be, for example, a longitudinal direction of the display panel 100. The second direction F2 can be a direction parallel to the other side of the display panel 100 in a plan view, and can be a transverse direction of the display panel 100.

[0062] Optionally, in combination with FIGS. 5 to 7, in some embodiments, in the opposite substrate 30, the first common electrode 33 can be arranged in a full surface or in a patterned manner.

[0063] The black matrix layer 32 is provided with an opening m1. The black matrix layer 32 includes a plurality of light shielding strips 321, the light shielding strips 321 are arranged in an interval along the first direction F1, the light shielding strips 321 are arranged in extension along the second direction F2 perpendicular to the first direction F1, and the opening m1 is formed between the adjacent two light shielding strips 321. That is, the opening m1 is also arranged in an interval along the first direction F1 and arranged in extension along the second direction F2.

[0064] In some embodiments, in the array substrate 10, a plurality of data lines data extend along the first direction F1 and are arranged in an interval along the second direction F2. A plurality of pixel electrodes 13 are arranged in a matrix along the first direction F1 and the second direction F2. Among them, the pixel electrode 13 has 4 domains, but is not limited to this, such as 2 domains or 8 domains. In the following, the architecture of 4 domains will be described, but is not limited to this.

[0065] In some embodiments, the pixel electrode 13 includes a pixel part px, a first connecting part p1 and a second connecting part p2. The second connecting part p2 is connected to the thin film transistor tft. The pixel part px includes a first trunk electrode z1 and a first branch electrode h1 connected to the first trunk electrode z1. The first connecting part p1 connects the second connecting part p2 and the first branch electrode h1.

[0066] Among them, the pixel part px further includes a second trunk electrode z2, a first edge electrode b1, a second edge electrode b2, a second branch electrode h2, a third branch electrode h3 and a fourth branch electrode h4. The first trunk electrode z1 and the second trunk electrode z2 are cross-connected to form a first region q1, a second region q2, a third region q3 and a fourth region q4.

[0067] The first branch electrodes h1 are arranged in the first region q1 in a spaced manner, and part of the first branch electrodes h1 are connected to the first trunk electrode z1, and the other part of the first branch electrodes h1 are connected to the second trunk electrode z2. The second branch electrodes h2 are arranged in the second region q2 in a spaced manner, and part of the second branch electrodes h2 are connected to the first trunk electrode z1, and the other part of the second branch electrodes h2 are connected to the second trunk electrode z2. The third branch electrodes h3 are arranged in the third region q3 in a spaced manner, and part of the third branch electrodes h3 are connected to the first trunk electrode z1, and the other part of the third branch electrodes h3 are connected to the second trunk electrode z2. The fourth branch electrodes h4 are arranged in the fourth region q4 in a spaced manner, and part of the fourth branch electrodes h4 are connected to the first trunk electrode z1, and the other part of the fourth branch electrodes h4 are connected to the second trunk electrode z2. The first side electrode b1 is connected to one side of the second trunk electrode z2, and the second side electrode b2 is connected to the other side of the second trunk electrode z2. The first branch electrodes h1 and the second branch electrodes h2 are connected to the first side electrode b1, and the third branch electrodes h3 and the fourth branch electrodes h4 are connected to the second side electrode b2.

[0068] Optionally, the first trunk electrode z1 extends along the first direction F1, and the second trunk electrode z2 extends along the second direction F2, that is, the first trunk electrode z1 and the second trunk electrode z2 are perpendicular to each other, but are not limited thereto, for example, the first trunk electrode z1 and the second trunk electrode z2 are not perpendicular to each other.

[0069] The first side electrode b1 and the second side electrode b2 extend along the first direction F1, but are not limited thereto, for example, they can extend along other directions as long as they are connected to the second trunk electrode z2.

[0070] The first branch electrodes h1 and the third branch electrodes h3 extend along the third direction F3, and the second branch electrodes h2 and the fourth branch electrodes h4 extend along the fourth direction F4. But are not limited thereto, for example, the first branch electrodes h1 and the third branch electrodes h3 extend in different directions, and the second branch electrodes h2 and the fourth branch electrodes h4 extend in different directions.

[0071] Optionally, in some embodiments, the first direction F1, the second direction F2, the third direction F3 and the fourth direction F4 intersect with each other.

[0072] Optionally, the third direction F3 is perpendicular to the fourth direction F4, but is not limited thereto, for example, they can be non-perpendicular to each other. The angle between the third direction F3 and the first direction F1 is an acute angle, for example, the angle between them can be 15 degrees, 30 degrees, 45 degrees, 60 degrees or 75 degrees, etc. The angle between the fourth direction F4 and the second direction F2 is an acute angle, for example, the angle between them can be 15 degrees, 30 degrees, 45 degrees, 60 degrees or 75 degrees, etc.

[0073] Optionally, the third direction F3 and the fourth direction F4 each forms an angle of 45 degrees with the first direction F1, and the third direction F3 and the fourth direction F4 each forms an angle of 45 degrees with the second direction F2.

[0074] In some embodiments, the second common electrode 12 is arranged along the first direction F1 and extends along the second direction F2. The second common electrode 12 overlaps the pixel portion px to form a storage capacitor.

[0075] Optionally, the array substrate 10 further comprises a common electrode line 14 arranged in the same layer as the pixel electrode 13, the common electrode line 14 being connected to the second common electrode 12. The common electrode line 14 is arranged between two adjacent rows of pixel electrodes 13. The common electrode line 14 partially covers a portion of the data line data.

[0076] Optionally, the second common electrode 12 and the first common electrode 33 are arranged to be connected to the same voltage, and the second common electrode 12 comprises a first portion 121 and a second portion 122.

[0077] In a plan view of the display panel 100, the first portion 121 is arranged in the region of the opening m1 and overlaps the pixel portion px, and the first portion 121 further covers the portion of the data line data located in the opening m1. The second portion 122 is connected to the opposite side of the first portion 121, and the second portion 122 covers the portion of the data line located in the region of the light shielding strip 321.

[0078] The first portion 121 overlaps the pixel portion px to form a storage capacitor. The first portion 121 and the second portion 122 cover the data line data to shield the data line data, thereby saving the portion of the black matrix layer 32 corresponding to the data line data.

[0079] In some embodiments of the present application, the first portion 121 can also not be arranged in its entirety, for example, a hollow portion can be arranged in the middle region of the first portion 121 corresponding to the pixel portion px to improve light transmittance.

[0080] Optionally, the common electrode line 14, the first common electrode 33, the second common electrode 12 and the pixel electrode 13 can each be made of transparent conductive material such as indium tin oxide, indium zinc oxide, etc.

[0081] In some embodiments of the present application, referring to FIGS. 5-8, in a plan view of the display panel 100, the black matrix layer 32 covers the first connecting portion p1 and the second connecting portion p2, and the second common electrode 12 and the pixel portion px are in the region of the opening m1, wherein the extension direction of the first connecting portion p1 and the extension direction of the first branch electrode h1 form an included angle greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connecting portion p1 is consistent with the extension direction F3 of the first branch electrode h1.

[0082] It should be noted that in the second direction F2, the junction line of the first connecting portion p1 and the first branch electrode h1 is flush with the contour line of the adjacent first branch electrode h1.

[0083] It should be understood that the extension direction of the first connecting portion p1 is consistent with the extension direction F3 of the first branch electrode h1 (as shown in FIG. 8), or the included angle a formed by the extension direction of the first connecting portion p1 and the extension direction of the first branch electrode h1 is greater than or equal to 120 degrees and less than 180 degrees (as shown in FIG. 9), under the influence of the boundary electric field based on the second common electrode and the pixel electrode, the reverse direction of the liquid crystal in the region near the first connecting portion can be improved, and in turn the dark lines in the opening region can be improved.

[0084] It should be noted that the position of FIG. 9 on the display panel 100 is consistent with the position of FIG. 8 or FIG. 11 on the display panel 100, the difference between the embodiment corresponding to FIG. 8 and the embodiment corresponding to FIG. 9 or FIG. 11 is only that the structures of the first connecting portion p1 and the second connecting portion p2 are different, which will not be described here. Hereinafter, the case where the extension direction of the first connecting portion p1 is consistent with the extension direction of the first branch electrode h1 will be described, but it is not limited thereto.

[0085] Optionally, in some embodiments of the present application, the extension direction of the first connecting portion p1 is consistent with the extension direction of the first branch electrode h1. The second connecting portion p2 includes a via sub-portion p21 and an extension sub-portion p22 connecting the via sub-portion p21, the via sub-portion p21 connects the thin film transistor tft, and the extension sub-portion p22 connects the first connecting portion p1.

[0086] In a plan view of the display panel 100, the first trunk electrode z1 extends along the first direction F1. In the first direction F1, the shortest distance L1 from the junction line jjx of the extension sub-portion p22 and the first connecting portion p1 to the second common electrode 12 is greater than or equal to 1.3 microns.

[0087] It needs to be understood that the extension sub-p22 and the first connecting part p1 intersect to form a corner gy1, and in the first direction F1, the corner gy1 is away from the second common electrode 12 to reduce the influence of the boundary electric field to reduce the dark lines, and the corner gy1 is away from the opening m1 area, and even if there are still dark lines, the dark lines are reduced due to the distance from the opening m1 area. The risk of appearing in the opening m1 area.

[0088] Among them, in one pixel area, the greater the shortest distance L1, the farther the corner gy1 from the second common electrode 12, and the better the effect of improving the dark lines. Optionally, the shortest distance L1 can be 1.3 microns, 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns, 2 microns, 3 microns, 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, 9 microns or 10 microns, etc.

[0089] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, the extension sub-p22 extends along the second direction F2 perpendicular to the first direction F1. In the first direction F1, the shortest distance L1 from the intersection line jjx of the extension sub-p22 and the first connecting part p1 to the second common electrode 12 is greater than or equal to 1.5 microns.

[0090] It can be understood that the extension sub-p22 extends along the second direction F2, so that the extension direction of the intersection line jjx and the second common electrode 12 is parallel, so as to achieve the effect that the shortest distance L1 is a constant value, thereby saving space arrangement; on the other hand, referring to FIG. 10, parts a and b of FIG. 10 show the light transmission effect diagram simulated based on the background technology by adjusting only the shortest distance L1; part a of FIG. 10 shows the simulated light transmission effect diagram when the shortest distance L1 is equal to 2.5 microns, and part b of FIG. 10 shows the simulated light transmission effect diagram when the shortest distance L1 is 6 microns. Part c of FIG. 10 is the simulated light transmission effect diagram when the shortest distance L1 of an embodiment of the present application is equal to 1.5 microns. As can be seen from FIG. 10, there are no dark lines near the short side of the opening in parts a, b and c. Therefore, the shortest distance L1 greater than or equal to 1.5 microns can eliminate the dark lines.

[0091] Optionally, in some embodiments of the present application, the width of the first connecting part p1 is equal to the width of the first branch electrode h1, so that the pre-tilt angle of the liquid crystal located on the first connecting part p1 and the liquid crystal located on the first branch electrode h1 tends to be consistent.

[0092] Optionally, in some embodiments of the present application, the number of the first connecting part p1 is at least two, and hereinafter the first connecting part p1 is taken as an example with two, but not limited thereto, such as 3.

[0093] The first connecting part p1 corresponds to connecting the first branch electrode h1, and a slit xf is formed between two adjacent first branch electrodes h1.

[0094] In the second direction F2 perpendicular to the first direction F1, the distance L2 between two adjacent first connecting parts p1 is equal to the width of the slit xf.

[0095] It can be understood that using multiple first connecting parts p1 to connect the second connecting part p2 and the pixel part px can improve the reliability of the connection and reduce the impedance. In addition, the adjacent arrangement of two first connecting parts p1 can reduce the requirement for layout space.

[0096] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, the data line data extends along the first direction F1. In the second direction F2 perpendicular to the first direction F1, the distance L3 from the junction of the first connecting part p1 and the second connecting part p2 to the data line data is greater than 1 micrometer.

[0097] It can be understood that the first connecting part p1 and the second connecting part p2 cross-connect to form the corner gy1. In FIG. 8, the first connecting part p1 and the extension sub-pixel part p22 cross-connect to form the corner gy1. The distance L3 from the corner gy1 to the data line data is greater than 1 micrometer to reduce the risk of crosstalk.

[0098] Optionally, the distance L3 from the corner gy1 to the data line data can be 1.1 micrometers, 1.2 micrometers, 1.3 micrometers, 1.4 micrometers, 1.5 micrometers, 1.6 micrometers, 1.7 micrometers, 1.8 micrometers, 1.9 micrometers, 2 micrometers, 2.1 micrometers, 2.2 micrometers, 2.3 micrometers, 2.4 micrometers, or 2.5 micrometers, etc.

[0099] Optionally, in some embodiments of the present application, the first connecting part p1 and the second connecting part p2 connect to form the corner gy1. In the plan view of the display panel 100, the side of the corner gy1 close to the data line data is a rounded corner.

[0100] It can be understood that setting the side of the corner gy1 close to the data line data as a rounded corner can further reduce the risk of crosstalk.

[0101] Optionally, in some embodiments of the present application, in the second direction F2 perpendicular to the first direction F1, the shortest distance L4 from the first connecting part p1 to the first trunk electrode z1 is greater than twice the width of the slit xf.

[0102] It can be understood that the area where the first trunk electrode z1 is located will form a dark line, and the first connecting portion p1 being away from the first trunk electrode z1 can reduce the risk of the area where the first connecting portion p1 is located forming a dark line. Therefore, the shortest distance L4 being greater than twice the width of the slit xf can better reduce the risk of forming a dark line.

[0103] FIG. 11 shows the first connecting portion p1 of the display panel 100 and the structure connected thereto according to one or more embodiments disclosed, and corresponds to the area shown in FIG. 8. In FIG. 11, parts different from the above-described embodiments will be described to avoid redundant description.

[0104] Referring to FIG. 11, in some embodiments of the present application, in a second direction F2 perpendicular to the first direction F1, the distance L2 between two adjacent first connecting portions p1 is greater than twice the width of the slit xf.

[0105] It can be understood that the greater the distance L2, the smaller the area between the two first connecting portions p1 is affected by the boundary electric field, which can further reduce the risk of dark lines.

[0106] FIG. 12 shows the first connecting portion p1 of the display panel 100 and the structure connected thereto according to one or more embodiments disclosed, and corresponds to the area shown in FIG. 8. In FIG. 12, parts different from the above-described embodiments will be described to avoid redundant description.

[0107] Referring to FIG. 12, in some embodiments of the present application, the extension direction of the first connecting portion p1 is consistent with the extension direction of the first branch electrode h1. The second connecting portion p2 includes a via sub-portion p21, a first extension sub-portion p31, and a second extension sub-portion p32. The via sub-portion p21 is connected to the thin film transistor tft. The second extension sub-portion p32 is connected to the first connecting portion p1, and the first extension sub-portion p31 is connected to the via sub-portion p21 and the second extension sub-portion p32.

[0108] In the plan view of the display panel 100, the second extension sub-portion p32 and the first connecting portion p1 are cross-connected, and the first trunk electrode z1 extends along the first direction F1. In the first direction F1, the shortest distance L1 from the junction line jjx of the second extension sub-portion p32 and the first connecting portion p1 to the second common electrode 12 is greater than or equal to 1.3 microns.

[0109] It should be understood that the second extension sub-portion p32 and the first connecting portion p1 are cross-connected to form a corner gy1, and in the first direction F1, the corner gy1 is away from the second common electrode 12 to reduce the influence of the boundary electric field, thereby reducing the dark line. At the same time, the corner gy1 is away from the opening m1 area, so that even if there is still a dark line, the dark line is away from the opening m1 area to reduce the risk of appearing in the opening m1 area.

[0110] In one pixel region, the greater the shortest distance L1, the farther the corner gy1 is from the second common electrode 12, and the better the effect of improving the dark lines is. Optionally, the shortest distance L1 can be 1.3 microns, 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns, 2 microns, 3 microns, 4 microns, 5 microns, 6 microns, 7 microns, 8 microns, 9 microns, or 10 microns, etc.

[0111] In addition, the first extension sub-pieces p31 and the second extension sub-pieces p32 are cross-connected to achieve the effect of saving space in the second direction F2.

[0112] Optionally, in some embodiments of the present application, in the plan view of the display panel 100, the first extension sub-pieces p31 extend along the second direction F2 perpendicular to the first direction F1, and the second extension sub-pieces p32 are cross-connected with the first extension sub-pieces p31. In the first direction F1, the shortest distance from the intersection line jjx of the second extension sub-pieces p32 and the first connection piece p1 to the second common electrode 12 is greater than or equal to 1.5 microns.

[0113] It can be understood that the extension direction of the intersection line jjx of the second extension sub-pieces p32 and the first connection piece p1 and the second common electrode 12 is parallel, to achieve the effect that the shortest distance L1 is a constant value, thereby saving space arrangement; and the shortest distance L1 is greater than or equal to 1.5 microns, so that the effect of improving the dark lines is better, and even the dark lines are eliminated.

[0114] Optionally, in some embodiments, the angle between the extension direction of the second extension sub-pieces p32 and the extension direction of the first connection piece p1 is greater than or equal to 120 degrees and less than 180 degrees. For example, it can be 120 degrees, 135 degrees, 150 degrees, or 175 degrees, etc.

[0115] It should be understood that the greater the angle between the extension direction of the second extension sub-pieces p32 and the extension direction of the first connection piece p1, the better the effect of improving the dark lines in the opening m1 region.

[0116] Optionally, in some embodiments, in the first direction F1, the length of the second extension sub-pieces p32 is less than the length of the first connection piece p1. It can be understood that in the first direction F1, the smaller the distance of the second extension sub-pieces p32, the farther the corner gy1 is from the second common electrode 12, and the better the effect of improving the dark lines is.

[0117] Optionally, in some embodiments, in the first direction F1, the length of the second extension sub-pieces p32 is less than half the length of the first connection piece p1.

[0118] The display panel 100 provided by the embodiment of the present application comprises an array substrate 10 and an opposite substrate 30. In the plan view of the display panel 100, the black matrix layer 32 covers the first connecting part p1 and the second connecting part p2, and the second common electrode 12 and the pixel part px are in the region of the opening m1. The included angle formed by the extension direction of the first connecting part p1 and the extension direction of the first branch electrode h1 is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connecting part p1 is consistent with the extension direction of the first branch electrode h1.

[0119] In the above, the included angle formed by the extension direction of the first connecting part p1 and the extension direction of the first branch electrode h1 is set to be greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connecting part p1 is set to be consistent with the extension direction of the first branch electrode h1. Under the influence of the boundary electric field based on the second common electrode and the pixel electrode, the reverse direction of the liquid crystal in the region near the first connecting part can be improved, and in turn the dark lines in the opening region can be improved.

[0120] The display panel provided by the embodiment of the present application is described in detail above. The principle and implementation mode of the present application are described by applying specific examples in this paper. The above embodiment is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A display panel, comprising an array substrate, a liquid crystal layer and a counter substrate arranged in sequence, wherein the counter substrate comprises a first substrate, a black matrix layer and a first common electrode, the black matrix layer is arranged on a side of the first substrate close to the liquid crystal layer, the first common electrode is arranged on a side of the black matrix layer close to the liquid crystal layer, and the black matrix layer is provided with an opening; the array substrate comprises a second substrate and a pixel electrode, the pixel electrode is arranged on a side of the second substrate close to the liquid crystal layer; the pixel electrode comprises a pixel part, a first connecting part and a second connecting part, the second connecting part is connected to a thin film transistor, the pixel part comprises a first trunk electrode and a first branch electrode connected to the first trunk electrode, and the first connecting part connects the second connecting part and the first branch electrode; in a plan view of the display panel, the black matrix layer covers the first connecting part and the second connecting part, and the pixel part is in a region of the opening, wherein an included angle formed by an extension direction of the first connecting part and an extension direction of the first branch electrode is greater than or equal to 120 degrees and less than 180 degrees, or the extension direction of the first connecting part is consistent with the extension direction of the first branch electrode. the array substrate further comprises a second common electrode, the second common electrode is arranged on a side of the second substrate close to the liquid crystal layer, the pixel electrode is arranged on a side of the second common electrode close to the liquid crystal layer and is different from the second common electrode in layer, and the second common electrode is in the region of the opening; the extension direction of the first connecting part is consistent with the extension direction of the first branch electrode, the second connecting part comprises a via sub-part and an extension sub-part connected to the via sub-part, the via sub-part is connected to the thin film transistor, and the extension sub-part is connected to the first connecting part; in the plan view of the display panel, the first trunk electrode extends along a first direction; in the first direction, a shortest distance from an intersection line of the extension sub-part and the first connecting part to the second common electrode is greater than or equal to 1.3 microns. in the plan view of the display panel, the extension sub-part extends along a second direction perpendicular to the first direction; in the first direction, a shortest distance from an intersection line of the extension sub-part and the first connecting part to the second common electrode is greater than or equal to 1.5 microns. the array substrate further comprises a second common electrode, the second common electrode is arranged on a side of the second substrate close to the liquid crystal layer, the pixel electrode is arranged on a side of the second common electrode close to the liquid crystal layer and is different from the second common electrode in layer, and the second common electrode is in the region of the opening; the extension direction of the first connecting part is consistent with the extension direction of the first branch electrode, the second connecting part comprises a via sub-part, a first extension sub-part and a second extension sub-part, the via sub-part is connected to the thin film transistor, the second extension sub-part is connected to the first connecting part, and the first extension sub-part connects the via sub-part and the second extension sub-part; ​ 2. The display panel of claim 1, wherein, ​ ​ 3. The display panel of claim 2, wherein, ​ 4. The display panel of claim 1, wherein, ​ In a plan view of the display panel, the second extension sub-section and the first connection section are cross-connected, and the first trunk electrode extends along a first direction; in the first direction, a shortest distance from an intersection line of the second extension sub-section and the first connection section to the second common electrode is greater than or equal to 1.3 microns.

5. The display panel of claim 4, wherein, In a plan view of the display panel, the first extension sub-section extends along a second direction perpendicular to the first direction, and the second extension sub-section is cross-connected with the first extension sub-section; in the first direction, a shortest distance from an intersection line of the second extension sub-section and the first connection section to the second common electrode is greater than or equal to 1.5 microns.

6. The display panel according to any one of claims 2-5, wherein, The number of the first connection sections is at least two, and one first connection section corresponds to connecting one first branch electrode, and a slit is formed between adjacent two first branch electrodes; In a second direction perpendicular to the first direction, a distance between adjacent two first connection sections is equal to a width of the slit.

7. The display panel of any of claims 2-5, wherein, The number of the first connection sections is at least two, and one first connection section corresponds to connecting one first branch electrode, and a slit is formed between adjacent two first branch electrodes; In a second direction perpendicular to the first direction, a distance between adjacent two first connection sections is greater than twice the width of the slit.

8. The display panel of any one of claims 2-5, wherein, The display panel further comprises a data line, in a plan view of the display panel, the data line extends along the first direction; in a second direction perpendicular to the first direction, a distance from an intersection of the first connection section and the second connection section to the data line is greater than 1 micron.

9. The display panel of claim 8, wherein, The first connection section and the second connection section are connected to form a corner, and in a plan view of the display panel, a side of the corner close to the data line is a rounded corner.

10. The display panel of any one of claims 2-5, wherein, The number of the first connection sections is at least two, and one first connection section corresponds to connecting one first branch electrode, and a slit is formed between adjacent two first branch electrodes; In a second direction perpendicular to the first direction, a shortest distance from the first connection section to the first trunk electrode is greater than twice the width of the slit.

11. The display panel of any one of claims 2-5, wherein, The black matrix layer comprises a plurality of light-shielding strips, the light-shielding strips are arranged at intervals along the first direction, the light-shielding strips are arranged to extend along a second direction perpendicular to the first direction, and the openings are formed between adjacent two light-shielding strips; The second common electrode and the first common electrode are set to be connected to the same voltage, the second common electrode comprises a first part and a second part, in a plan view of the display panel, the first part is arranged in the entire area of the opening and overlaps the pixel section, the first part also covers a part of the data line located in the opening, the second part is connected to the opposite side of the first part, and the second part covers a part of the data line located in the light-shielding strip area.

12. The display panel of any one of claims 2-5, wherein, The second common electrode and the first common electrode are set to be connected to the same common voltage.

13. The display panel of claim 8, wherein, In a thickness direction of the display panel, the second common electrode covers the data line.

14. The display panel of claim 13, wherein, The array substrate further comprises a common electrode line arranged in the same layer as the pixel electrode, the common electrode line is connected to the second common electrode, the common electrode line is arranged between two adjacent rows of the pixel electrode, and a local part of the common electrode line locally covers a local part of the data line.

15. The display panel of any one of claims 2-5, wherein, The pixel part further comprises a second trunk electrode, a first side electrode, a second side electrode, a second branch electrode, a third branch electrode, and a fourth branch electrode, the first trunk electrode and the second trunk electrode are cross-connected to form a first area, a second area, a third area, and a fourth area; A plurality of first branch electrodes are arranged at intervals in the first area, part of the first branch electrodes are connected to the first trunk electrode, and another part of the first branch electrodes are connected to the second trunk electrode, a plurality of second branch electrodes are arranged at intervals in the second area, part of the second branch electrodes are connected to the first trunk electrode, and another part of the second branch electrodes are connected to the second trunk electrode, a plurality of third branch electrodes are arranged at intervals in the third area, part of the third branch electrodes are connected to the first trunk electrode, and another part of the third branch electrodes are connected to the second trunk electrode, a plurality of fourth branch electrodes are arranged at intervals in the fourth area, part of the fourth branch electrodes are connected to the first trunk electrode, and another part of the fourth branch electrodes are connected to the second trunk electrode, the first side electrode is connected to one side of the second trunk electrode, the second side electrode is connected to the other side of the second trunk electrode, the first branch electrode and the second branch electrode are connected to the first side electrode, and the third branch electrode and the fourth branch electrode are connected to the second side electrode.

16. The display panel of any one of claims 2-5, wherein, The width of the first connecting part is equal to the width of the first branch electrode.

17. A display panel, comprising an array substrate, a liquid crystal layer, and a counter substrate arranged in sequence, wherein, The counter substrate comprises a first substrate, a black matrix layer, and a first common electrode, the black matrix layer is arranged on one side of the first substrate close to the liquid crystal layer, the first common electrode is arranged on one side of the black matrix layer close to the liquid crystal layer, and the black matrix layer is provided with an opening; The array substrate comprises a second substrate, a pixel electrode, a color filter layer, and a planar layer, the color filter layer is arranged on one side of the second substrate close to the liquid crystal layer, the planar layer is arranged on one side of the color filter layer close to the liquid crystal layer, and the pixel electrode is arranged on one side of the planar layer close to the liquid crystal layer; The pixel electrode comprises a pixel part, a first connecting part, and a second connecting part, the second connecting part is connected to a thin film transistor, the pixel part comprises a first trunk electrode and a first branch electrode connected to the first trunk electrode, the first connecting part connects the second connecting part and the first branch electrode, and the second connecting part is connected to the first branch electrode. In a plan view of the display panel, the black matrix layer covers the first connecting part and the second connecting part, and the pixel part is in the region of the opening, wherein the first connecting part is in the same direction as the first branch electrode, and the second connecting part comprises a via subpart and an extension subpart connecting the via subpart, the via subpart is connected to the thin film transistor, and the extension subpart is connected to the first connecting part.

18. The display panel of claim 17, wherein, The array substrate further comprises a second common electrode, the second common electrode is arranged on the side of the second substrate close to the liquid crystal layer, the pixel electrode is arranged on the side of the second common electrode close to the liquid crystal layer and is different from the second common electrode in layer, and the second common electrode is in the region of the opening; the first connecting part is in the same direction as the first branch electrode, and the second connecting part comprises a via subpart and an extension subpart connecting the via subpart, the via subpart is connected to the thin film transistor, and the extension subpart is connected to the first connecting part. In a plan view of the display panel, the first main electrode extends along a first direction; in the first direction, the shortest distance from the intersection line of the extension subpart and the first connecting part to the second common electrode is greater than or equal to 1.3 microns.

19. The display panel of claim 18, wherein, In a plan view of the display panel, the extension subpart extends along a second direction perpendicular to the first direction; in the first direction, the shortest distance from the intersection line of the extension subpart and the first connecting part to the second common electrode is greater than or equal to 1.5 microns.

20. The display panel of claim 17, wherein, The array substrate further comprises a second common electrode, the second common electrode is arranged on the side of the second substrate close to the liquid crystal layer, the pixel electrode is arranged on the side of the second common electrode close to the liquid crystal layer and is different from the second common electrode in layer, and the second common electrode is in the region of the opening; the first connecting part is in the same direction as the first branch electrode, and the second connecting part comprises a via subpart, a first extension subpart and a second extension subpart, the via subpart is connected to the thin film transistor, the second extension subpart is connected to the first connecting part, and the first extension subpart connects the via subpart and the second extension subpart. In a plan view of the display panel, the second extension subpart and the first connecting part are cross-connected, the first main electrode extends along a first direction; in the first direction, the shortest distance from the intersection line of the second extension subpart and the first connecting part to the second common electrode is greater than or equal to 1.3 microns.

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