Driving circuit, controller and vehicle

Abstract

The present application relates to the technical field of electronic circuits. Disclosed are a driving circuit, a controller and a vehicle. The driving circuit comprises: a current sampling module, a latch module, and a first control module, wherein the current sampling module is connected to the latch module; the latch module is connected to the first control module; the first control module is connected to a driving module; the current sampling module is configured to collect the current value of an input current of a driving object of the driving module, and output a first overcurrent notification signal by means of the current sampling module when it is determined that the input current is an overcurrent; the latch module is configured to output a second overcurrent notification signal to the first control module when the first overcurrent notification signal is received, and the second overcurrent notification signal is a latch signal for the first overcurrent notification signal; and the first control module is configured to control, when the second overcurrent notification signal is received, the driving module to stop enabling.

Description

Drive circuit, controller and vehicle

[0001] This application claims priority to Chinese Patent Application No. 2024112016752, filed on August 28, 2024, entitled "Drive Circuit, Controller and Vehicle", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic circuit technology, and more specifically, to a drive circuit, controller, and vehicle. Background Technology

[0003] In electronic devices, driver chips are core components and are widely used in power management, motor control, LED lighting and many other fields.

[0004] For example, driver chips can be used in motor controllers. A motor controller also includes power transistors, a control board, and a current sampling module. Power transistors are used to form at least three-phase bridge arms, and the current sampling module is used to sample the input current of the three-phase bridge arms.

[0005] Overcurrent in the input current of power transistors in a motor controller can lead to performance degradation and damage to the power transistors driven by the driver chip, and may even cause more serious safety problems such as explosions and burnout of the motor controller. Therefore, how to protect power transistors under overcurrent conditions has become an urgent technical problem to be solved. Summary of the Invention

[0006] One objective of this application is to provide a new technical solution for a drive circuit.

[0007] According to a first aspect of this application, a driving circuit is provided, comprising:

[0008] A current sampling module is used to collect the input current of the driven object of the drive module, and outputs a first overcurrent notification signal when it is determined that the input current is overcurrent;

[0009] A latching module, connected to the current sampling module, is used to receive the first overcurrent notification signal; and

[0010] A first control module is connected to the latch module and is used to receive a second overcurrent notification signal output by the latch module. The second overcurrent notification signal is a latch signal for the first overcurrent notification signal. The first control module is also connected to the drive module. When the first control module receives the second overcurrent notification signal, it controls the drive module to stop enabling.

[0011] Optionally, the driving circuit further includes:

[0012] The second control module is wherein the first output terminal of the current sampling module is connected to the first input terminal of the second control module.

[0013] The first output terminal of the second control module is connected to the second input terminal of the first control module; the first output terminal of the current sampling module is connected to the first input terminal of the latch module; the output terminal of the latch module is connected to the first input terminal of the first control module.

[0014] The second control module is used to output a third overcurrent notification signal to the first control module upon receiving the first overcurrent notification signal;

[0015] The first control module is configured to control the drive module to stop enabling when it receives at least one of the third overcurrent notification signal and the second overcurrent notification signal.

[0016] Optionally, the latching module outputs the second overcurrent notification signal to the first control module at a first moment;

[0017] The second control module outputs the third overcurrent notification signal to the first control module at a second time; the second time is later than the first time.

[0018] The first control module is used to control the drive module to stop enabling when it receives the second overcurrent notification signal;

[0019] The first control module is used to control the drive module to stop enabling again upon receiving the third overcurrent notification signal.

[0020] Optionally, the second output terminal of the current sampling module is connected to the second input terminal of the second control module, and the current sampling module is further used to convert the input current into a voltage signal and transmit the voltage signal to the second control module through the second output terminal of the current sampling module;

[0021] The second control module is configured to output the third overcurrent notification signal to the first control module if it is determined, at least based on the voltage signal, that the input current is overcurrent.

[0022] Optionally, the second output terminal of the second control module is connected to the second input terminal of the latch module;

[0023] The current sampling module is also used to output a first no-overcurrent notification signal through the first output terminal of the current sampling module when it is determined that the input current is not overcurrent.

[0024] Upon receiving the first no-overcurrent notification signal, the second control module outputs a reset signal to the latch module and a second no-overcurrent notification signal to the first control module.

[0025] The latching module is used to output a third no-overcurrent notification signal to the first control module when it receives the reset signal and the first no-overcurrent notification signal;

[0026] The first control module is used to enable the drive module upon receiving the third no-overcurrent notification signal and the second no-overcurrent notification signal.

[0027] Optionally, the second output terminal of the second control module is connected to the second input terminal of the latch module;

[0028] The current sampling module is also used to output a first no-overcurrent notification signal through the first output terminal of the current sampling module when it is determined that the input current is not overcurrent.

[0029] The second control module is used to output a reset signal to the latch module and a second no-overcurrent notification signal to the first control module when it is determined from the voltage signal that the input current is not overcurrent.

[0030] The latching module is used to output a third no-overcurrent notification signal to the first control module when it receives the reset signal and the first no-overcurrent notification signal;

[0031] The first control module is used to enable the drive module upon receiving the third no-overcurrent notification signal and the second no-overcurrent notification signal.

[0032] Optionally, the first control module includes:

[0033] First power source;

[0034] The first pull-up resistor is connected to the second end of the first power supply.

[0035] The AND gate circuit has its first input terminal connected to the first output terminal of the second control module and the first terminal of the first pull-up resistor, its second input terminal connected to the output terminal of the latch module, and its output terminal connected to the enable terminal of the drive module.

[0036] Optionally, the latching module includes:

[0037] First NAND gate circuit;

[0038] A unidirectional conduction unit, wherein the first end of the unidirectional conduction unit is connected to the first output end of the current sampling module, the second end of the unidirectional conduction unit is connected to the first input end of the first NAND gate circuit, and the conduction direction of the unidirectional conduction unit is the direction from the second end of the unidirectional conduction unit to the first end of the unidirectional conduction unit.

[0039] The second NAND gate circuit has its second input terminal connected to the output terminal of the first NAND gate circuit, and its output terminal connected to the first input terminal of the second NAND gate circuit; the second input terminal of the second NAND gate circuit is connected to the second output terminal of the second control module, and its output terminal is connected to the first input terminal of the first control module.

[0040] Second power source;

[0041] The second pull-up resistor has its first end connected to the second power supply and its second end connected to the first input terminal and the ground terminal of the first NAND gate circuit, respectively.

[0042] Third pull-up resistor;

[0043] The third power supply is connected to the output of the second NAND gate circuit through the third pull-up resistor.

[0044] Optionally, the driving circuit further includes a filter capacitor;

[0045] The second pull-up resistor is grounded through the filter capacitor.

[0046] Optionally, the unidirectional conduction unit is a diode;

[0047] The anode of the diode is connected to the first input terminal of the first NAND gate circuit, and the cathode of the diode is connected to the first output terminal of the current sampling module.

[0048] Optionally, the second control module includes:

[0049] A first core is connected to both the first output terminal and the second output terminal of the current sampling module.

[0050] The second core is connected to both the first output terminal and the second output terminal of the current sampling module, and is also connected to the first input terminal of the first control module; the first core and the second core are communicatively connected.

[0051] The first core is configured to send an overcurrent feedback indication signal to the second core when it receives the first overcurrent notification signal and / or determines that the drive current is overcurrent based on the voltage signal;

[0052] When the second kernel receives the return check indication signal, it determines whether the first overcurrent notification signal has been received, and determines whether the drive current is overcurrent based on the voltage signal. If the second kernel receives the first overcurrent notification signal and determines that the drive current is overcurrent based on the voltage signal, it sends the third overcurrent notification signal to the first control module.

[0053] Optionally, the third output terminal of the second control module is connected to the drive signal input terminal of the drive module.

[0054] When the second control module outputs the third overcurrent notification signal, it stops outputting drive signals to the drive module.

[0055] According to a second aspect of this application, a controller is provided, comprising:

[0056] Driver chip;

[0057] A control chip, which is connected to the driver chip;

[0058] A latch, which is connected to the control chip;

[0059] A current sensor, which is connected to the latch;

[0060] The current sensor collects the current value of the input current of the driven object of the driving chip, and when it is determined that the input current is overcurrent, it outputs a first overcurrent notification signal through the first output terminal of the current sensor.

[0061] Upon receiving the first overcurrent notification signal, the latch outputs a second overcurrent notification signal to the control chip. The second overcurrent notification signal is a latch signal for the first overcurrent notification signal.

[0062] Upon receiving the second overcurrent notification signal, the control chip controls the driver chip to stop being enabled.

[0063] According to a third aspect of this application, a vehicle is provided, including a drive circuit as described in any one of the first aspects;

[0064] Alternatively, it may include the controller described in the second aspect.

[0065] This application provides a driving circuit, including: a current sampling module, a latching module, and a first control module, wherein: the current sampling module is connected to the latching module; the latching module is connected to the first control module; and the first control module is connected to the driving module; wherein, the current sampling module is used to collect the current value of the input current of the driven object of the driving module, and outputs a first overcurrent notification signal through the current sampling module when it is determined that the input current is overcurrent; the latching module is used to output a second overcurrent notification signal to the first control module when it receives the first overcurrent notification signal, the second overcurrent notification signal being a latched signal for the first overcurrent notification signal; and the first control module is used to control the driving module to stop enabling when it receives the second overcurrent notification signal. The driving circuit provided by this application can realize the deactivation of the driving module when the input current of the driven object of the driving module is overcurrent, thus realizing the protection of the driven object of the driving module under overcurrent conditions. For example, when the driven object is a power device as a power module, the protection of the input current of the power device under overcurrent conditions can be realized. Furthermore, on the one hand, in the driving circuit provided by this application, the current sampled by the current sampling module is the input current of the driven object of the driving module, which is the actual current. This ensures that the driving circuit provided by this application does not have problems such as false alarms or false triggers. On the other hand, in the absence of a latching function for the first overcurrent notification signal by the current sampling module, the latching module can achieve the latching of the first overcurrent notification signal. This can avoid the problem of overheating and tube bursting in the driven object of the driving module, such as power transistors, caused by the continuous enabling and disabling of the driving module.

[0066] Other features and advantages of this application will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0067] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present application and, together with their description, serve to explain the principles of the present application.

[0068] Figure 1 is a schematic diagram of a driving circuit provided in this application;

[0069] Figure 2 is a schematic diagram of a driving circuit provided by the user.

[0070] Figure 3 is a schematic diagram of a drive circuit provided by the user.

[0071] Reference numerals: 100 - Driver module; 101 - Current sampling module; 101a - First output terminal of the current sampling module; 101b - Second output terminal of the current sampling module; 102 - First control module; 102a - First input terminal of the first control module; 102b - Second input terminal of the first control module; 102c - Output terminal of the first control module; 1021 - First power supply; 1022 - First pull-up resistor; 1022a - First terminal of the first pull-up resistor; 1022b - Second terminal of the first pull-up resistor; 1023 - AND gate circuit; 1023a - First input terminal of the AND gate circuit; 1023b - Second input terminal of the AND gate circuit; 1023c - Output terminal of the AND gate circuit; 103 - Latch module; 103a - First input terminal of the latch module; 103b - Output terminal of the latch module; 103c - Second input terminal of the latch module; 103d - Ground terminal; 1031 - Unidirectional conduction unit; 1031a - First terminal of unidirectional conduction unit; 1031b - Second terminal of unidirectional conduction unit; 1032 - Second power supply; 1033 - Second pull-up resistor; 1033a - First terminal of second pull-up resistor; 1033b - Second terminal of second pull-up resistor; 1034 - First NAND gate circuit; 1034a - First input terminal of first NAND gate circuit; 1034b - Second input terminal of first NAND gate circuit; 1034c - Output terminal of first NAND gate circuit; 1035 - Third pull-up resistor; 1036 - Third power supply; 1037 - Second NAND gate circuit; 1037a - First input terminal of second NAND gate circuit; 1037b - Second input terminal of second NAND gate circuit; 1037c - Output terminal of second NAND gate circuit; 1038 - Filter capacitor; 104 - Second control module; 104a - First input terminal of the second control module; 104b - First output terminal of the second control module; 104c - Second input terminal of the second control module; 104d - Second output terminal of the second control module; 104e - Third output terminal of the second control module; 200 - Drive module; 200a - Enable terminal of the drive module; 200b - Drive signal input terminal of the drive module. Specific Implementation

[0072] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0073] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.

[0074] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0075] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0076] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0077] In motor controller technology, once an overcurrent occurs in a power transistor, the transistor's overcurrent withstand time is relatively short. Therefore, the driver chip needs to be quickly deactivated to rapidly shut down the power transistor. However, the driver chip is typically controlled by the control chip within the motor controller. The processing time of the control chip (DSP) after receiving the overcurrent signal from the current sampling module far exceeds the overcurrent withstand time of the power transistor. Therefore, an additional path is needed to quickly deactivate the driver chip.

[0078] In related technologies, some solutions can control the driver chip to quickly stop enabling; however, new technical problems arise. Specifically, the current sampling module that samples the input current of the power transistor lacks a latching function. Thus, when the power transistor experiences overcurrent, the output signal of the current sampling module frequently switches between indicating overcurrent and no overcurrent. Consequently, the driver chip also frequently switches between enabling and disabling, leading to frequent switching of the power transistor between on and off. This frequent switching can cause the power transistor to explode, ultimately burning out the motor controller.

[0079] To address the aforementioned problems, this application provides a driving circuit 100, as shown in Figure 1, comprising: a current sampling module 101, a latching module 103, and a first control module 102, wherein:

[0080] The first output terminal 101a of the current sampling module 101 is connected to the first input terminal 103a of the latch module 103;

[0081] The output terminal 103b of the latch module 103 is connected to the first input terminal 102a of the first control module 102;

[0082] The output terminal 102c of the first control module 102 is connected to the enable terminal 200a of the drive module 200;

[0083] The current sampling module 101 is used to collect the current value of the input current of the driven object of the drive module 200. When it is determined that the input current is overcurrent, the first overcurrent notification signal is output through the first output terminal 101a of the current sampling module 101.

[0084] The latch module 103 is used to output a second overcurrent notification signal to the first control module 102 when it receives the first overcurrent notification signal. The second overcurrent notification signal is a latch signal for the first overcurrent notification signal.

[0085] The first control module 102 is used to control the drive module 200 to stop enabling when it receives the second overcurrent notification signal.

[0086] In this embodiment, the current sampling module 101 is used to collect the current value of the input current of the drive object of the drive module 200. In one example, the drive module 200 is specifically a drive chip that serves as the drive object. The drive object can be a power module, which includes power transistors, such as IGBTs. Specifically, the power module can be a three-phase full-bridge inverter circuit. The current on the DC bus passes through the three-phase full-bridge inverter circuit to form a three-phase current. This three-phase current is input to the three-phase windings of the motor, which generate a three-phase magnetic field that drives the motor. Based on this, the input terminal of the current sampling module 101 is connected to the DC bus current output terminal to collect the current value on the DC bus. When the drive circuit provided in this application determines that there is an overcurrent on the DC bus, it controls the drive chip to stop enabling, thereby stopping the drive of the three-phase full-bridge inverter circuit and preventing the overcurrent current on the DC bus from entering the three-phase full-bridge inverter circuit, thus avoiding damage to the three-phase full-bridge inverter circuit.

[0087] After acquiring the input current value, the current sampling module 101 compares the acquired current value with a pre-stored preset current value. The preset current value is the maximum current value when the input current is not excessive. If the acquired current value is less than or equal to the preset current value, it is determined that the input current is not excessive. Conversely, if the acquired current value is greater than the preset current value, it is determined that the input current is excessive. In the case of excessive input current, a first overcurrent notification signal is output through the first output terminal 101a of the current sampling module 101. Based on this, the latch module 103 receives the first overcurrent notification signal.

[0088] Upon receiving the first overcurrent notification signal, the latch module 103 determines that the input current is overcurrent. At this point, it latches the first overcurrent notification signal to obtain a second overcurrent notification signal. Then, it outputs the second overcurrent notification signal to the first control module 102.

[0089] After receiving the second overcurrent notification signal, the first control module 102 controls the drive module 200 to stop being enabled.

[0090] Based on the above, the driving circuit provided in this application can disable the driving module 200 when the input current of the driven object is overcurrent. This protects the driven object of the driving module from overcurrent. For example, when the driven object is a power device in a power module, it can protect the input current of the power transistor from overcurrent. Furthermore, in the driving circuit 100 provided in this application, the current sampled by the current sampling module 101 is the input current of the driven object, i.e., the actual current. This eliminates false alarms and false triggers in the driving circuit provided in this application. On the other hand, even if the current sampling module 101 does not have a latching function for the first overcurrent notification signal, the latching module 103 can latch the first overcurrent notification signal. This avoids damage to the driven object caused by the continuous enabling and disabling of the driving module 200, such as the problem of power transistor overheating and bursting.

[0091] This application provides a driving circuit, including a current sampling module, a latching module, and a first control module. The first output terminal 101a of the current sampling module 101 is connected to the first input terminal 103a of the latching module 103; the output terminal 103b of the latching module 103 is connected to the first input terminal 102a of the first control module 102; and the output terminal 102c of the first control module 102 is connected to the enable terminal 200a of the driving module 200. The current sampling module is used to collect the current value of the input current of the driven object. When an overcurrent is detected in the input current, a first overcurrent notification signal is output through the first output terminal 101a of the current sampling module 101. The latching module, upon receiving the first overcurrent notification signal, outputs a second overcurrent notification signal to the first control module. The second overcurrent notification signal is a latched signal corresponding to the first overcurrent notification signal. The first control module, upon receiving the second overcurrent notification signal, controls the driving module to de-enable. The driving circuit provided in this application can de-enable the driving module when the input current of the driven object is overcurrent. This enables protection of the driven object of the drive module under overcurrent conditions. For example, when the driven object is a power device in a power module, protection can be achieved for the input current of the power transistor under overcurrent conditions. Furthermore, in the drive circuit provided in this application, the current sampled by the current sampling module is the input current of the driven object, i.e., the actual current. This eliminates problems such as false alarms and false triggers in the drive circuit provided in this application. On the other hand, even if the current sampling module lacks a latching function for the first overcurrent notification signal, the latching module can latch the first overcurrent notification signal. This avoids damage to the driven object caused by the drive module's continuous enabling and disabling, such as the problem of power transistor overheating and causing it to explode.

[0092] In one embodiment of this application, based on the embodiment shown in FIG1 above, as shown in FIG2, the driving circuit provided by this application further includes:

[0093] The second control module 104, wherein:

[0094] The first output terminal 101a of the current sampling module 101 is connected to the first input terminal 104a of the second control module 104;

[0095] The first output terminal 104b of the second control module 104 is connected to the second input terminal 102b of the first control module 102.

[0096] The second control module 104 is used to output a third overcurrent notification signal to the first control module 102 when it receives the first overcurrent notification signal;

[0097] The first control module 102 is used to control the drive module 200 to stop enabling when it receives at least one of the third overcurrent notification signal and the second overcurrent notification signal.

[0098] In this embodiment, after acquiring the input current value, the current sampling module 101 compares the acquired current value with a pre-stored preset current value. The preset current value is the maximum current value when the input current is not excessive. If the acquired current value is less than or equal to the preset current value, it is determined that the input current is not excessive. Conversely, if the acquired current value is greater than the preset current value, it is determined that the input current is excessive. If an overcurrent is determined, a first overcurrent notification signal is output through the first output terminal 101a of the current sampling module 101. Based on this, both the first control module 101 and the latching module 103 receive the first overcurrent notification signal.

[0099] Upon receiving the first overcurrent notification signal, the latch module 103 determines that the input current is overcurrent. At this point, it latches the first overcurrent notification signal to obtain a second overcurrent notification signal. Then, it outputs the second overcurrent notification signal to the first control module 102.

[0100] After receiving the second overcurrent notification signal, the first control module 102 controls the drive module 200 to stop being enabled.

[0101] Furthermore, upon receiving the first overcurrent notification signal, the second control module 104 determines that the input current is overcurrent. At this time, the second control module 104 outputs a third overcurrent notification signal to the first control module 102.

[0102] Upon receiving the third overcurrent notification signal, the first control module 102 again controls the drive module 200 to stop enabling.

[0103] Based on the above, the driving circuit provided in this application can disable the driving module 200 when the input current of the driven object is overcurrent. This protects the driven object of the driving module from overcurrent. Furthermore, in the driving circuit 100 provided in this application, the current sampled by the current sampling module 101 is the input current of the driven object, i.e., the actual current, which eliminates false alarms and false triggers. On the other hand, even if the current sampling module 101 does not have a latching function for the first overcurrent notification signal, the latching module 103 can latch the first overcurrent notification signal, preventing damage to the driven object caused by the continuous enabling and disabling of the driving module 200, such as overheating of power transistors leading to transistor failure. Moreover, by adding a latching module, the driving module can be disabled more quickly than the second control module 104 when the input current is overcurrent, preventing transistor failure caused by excessive input current in the driven object of the driving module 200. On the other hand, the second control module merges the two signals output by the first control module and the latch module and inputs them to an enable pin of the drive module to achieve dual control of the drive module.

[0104] In one embodiment of this application, the latch module 103 outputs a second overcurrent notification signal to the first control module 102 at a first moment;

[0105] The second control module 104 outputs a third overcurrent notification signal to the first control module 102 at a second time, which is later than the first time.

[0106] The first control module 102 is used to control the drive module 200 to stop enabling when it receives the second overcurrent notification signal;

[0107] The first control module 102 is used to control the drive module 200 to stop enabling again when a third overcurrent notification signal is received.

[0108] For a detailed description of this embodiment, please refer to the previous embodiment. Furthermore, in this embodiment, the time elapsed between the moment the current sampling module 101 acquires the input current and the first moment is less than the overcurrent duration that the driven object of the driving module can tolerate. Thus, when the latching module 103 receives the first overcurrent notification signal and outputs a second overcurrent notification signal to the first control module 102 at the first moment, it can ensure that the driven object is not damaged by prolonged overcurrent input current, such as preventing problems like transistor failure caused by prolonged overcurrent in power components within the driven object.

[0109] In one example, the time elapsed between the moment the current sampling module 101 acquires the input current and the first moment can be, for example, 1.61. When the driven object includes an IGBT power device, the overcurrent duration that the driven object can tolerate can be, for example, 3.

[0110] In one embodiment of this application, as shown in FIG2, the second output terminal 101b of the current sampling module 101 is connected to the second input terminal 104c of the second control module 104. The current sampling module 101 is also used to convert the input current into a voltage signal and transmit the voltage signal to the second control module 104 through the second output terminal 101b of the current sampling module 101.

[0111] The second control module 104 is used to output a third overcurrent notification signal to the first control module 102 when it is determined, at least based on the voltage signal, that the input current is overcurrent.

[0112] In this embodiment, the current sampling module 101 also has the function of converting the input current into a proportional voltage signal. After the current sampling module 101 converts the input current into a proportional voltage signal, it transmits the signal to the second control module 104 via its own second output terminal 101b and the second input terminal 104c of the second control module 104.

[0113] When the second control module 104 receives a voltage signal, it detects the voltage value of the signal and compares it with a pre-stored preset voltage value. The preset voltage value is the maximum voltage value of the voltage signal converted by the current sampling module 101 when the input current is not overcurrent. If the detected voltage value is less than or equal to the preset voltage value, it is determined that the input current is not overcurrent. In this case, the second control module 104 does not output a third overcurrent notification signal to the first control module 102.

[0114] Conversely, if the detected voltage value is greater than the preset voltage value, an input current overcurrent is determined. At this time, the second control module 104 outputs a third overcurrent notification signal to the first control module 102. That is, in this embodiment, whether the detected voltage value is greater than the preset voltage value is used to determine whether the input current is overcurrent. This is because the voltage signal detected by the first control signal is an analog quantity, which is less susceptible to interference. However, the signal output by the current sampling module 101 through its first output terminal 101a is a digital quantity, such as the first overcurrent notification signal, which is more susceptible to interference. Therefore, the input current overcurrent determination by the second control module 104 based on the voltage signal is more accurate.

[0115] In this embodiment, the problems of false alarms and false triggers caused by interference in the driving circuit provided in this application can be avoided.

[0116] In one embodiment of this application, as shown in FIG2, the second output terminal 104d of the second control module 104 is connected to the second input terminal 103c of the latch module 103;

[0117] The current sampling module 101 is also used to output a first no-overcurrent notification signal through the first output terminal 101a of the current sampling module 101 when it is determined that the input current is not overcurrent.

[0118] The second control module 104 is used to output a reset signal to the latch module 103 and a second no-overcurrent notification signal to the first control module 102 when it receives the first no-overcurrent notification signal.

[0119] The latch module 103 is used to output a third no-overcurrent notification signal to the first control module 102 when it receives a reset signal and a first no-overcurrent notification signal;

[0120] The first control module 102 is used to enable the drive module 200 when it receives the third no-overcurrent notification signal and the second no-overcurrent notification signal.

[0121] In this embodiment, the current sampling module 101 determines that there are two scenarios where the input current is not overcurrent. Scenario one is that the input current itself is not overcurrent, and scenario two is that after the input current overcurrents, the input current returns to normal after clearing the obstruction.

[0122] If the current sampling module 101 determines that the input current is not overcurrent, it outputs a first no-overcurrent notification signal through its first output terminal 101a. At this time, both the second control module 104 and the latching module 103 receive the first no-overcurrent notification signal.

[0123] Upon receiving the first no-overcurrent notification signal, the second control module 104 outputs a reset signal to the latch module 103 and a second no-overcurrent notification signal to the first control module 102. Based on this, the latch module 103 receives the reset signal, and the first control module 102 receives the second no-overcurrent notification signal.

[0124] Upon receiving a reset signal and a first no-overcurrent notification signal, latch module 103 exits the latching state. Simultaneously, latch module 103 outputs a third no-overcurrent notification signal to first control module 102. Based on this, first control module 102 receives the third no-overcurrent notification signal.

[0125] Upon receiving the second no-overcurrent notification signal and the third no-overcurrent notification signal, the first control module 102 determines that the input current is not overcurrent. At this time, the control drive module 200 is enabled.

[0126] In this embodiment, the driving circuit provided by this application can also control the driving module 200 to be enabled when the input current is not overcurrent, or when it is overcurrent but is not overcurrent after clearing the obstruction.

[0127] In one embodiment of this application, the second output terminal 104d of the second control module 104 is connected to the second input terminal 103c of the latch module 103;

[0128] The current sampling module 101 is also used to output a first no-overcurrent notification signal through the first output terminal 101a of the current sampling module 101 when it is determined that the input current is not overcurrent.

[0129] The second control module 104 is used to output a reset signal to the latch module 103 and a second no-overcurrent notification signal to the first control module 102 when it is determined from the voltage signal that the input current is not overcurrent.

[0130] The latch module 103 is used to output a third no-overcurrent notification signal to the first control module 102 when it receives a reset signal and a first no-overcurrent notification signal;

[0131] The first control module 102 is used to enable the drive module 200 when it receives the third no-overcurrent notification signal and the second no-overcurrent notification signal.

[0132] Compared to the previous embodiment where the second control module 104 outputs a reset signal to the latch module 103 and a second no-overcurrent notification signal to the first control module 102 upon receiving a first no-overcurrent notification signal, in this embodiment, the second control module 104 outputs a reset signal to the latch module 103 and a second no-overcurrent notification signal to the first control module 102 only after determining that the input current is not overcurrent based on the voltage signal. This allows the second control module 104 to more accurately determine whether the input current is overcurrent based on the voltage signal. Based on this, it can more accurately output a reset signal to the latch module 103 and a second no-overcurrent notification signal to the first control module 102.

[0133] In one embodiment of this application, as shown in FIG3, the first control module 102 includes: an AND gate circuit 1023, a first pull-up resistor 1022, and a first power supply 1021, wherein:

[0134] The first input terminal 1023a of the AND gate circuit 1023 is connected to the first output terminal 104b of the second control module 104 and the first terminal 1022a of the first pull-up resistor 1022, respectively. The second input terminal 1023b of the AND gate circuit 1023 is connected to the output terminal 103b of the latch module 103. The output terminal 1023c of the AND gate circuit 1023 is connected to the enable terminal 200a of the drive module 200.

[0135] The first power supply 1021 is connected to the second terminal 1022b of the first pull-up resistor 1022.

[0136] In this embodiment, the first power supply 1021 is a power supply that can provide a 5V voltage signal. Furthermore, this embodiment uses an AND gate circuit 1023 to implement the first control module, which can merge the two signals output from the second control module 104 and the latch module 103 and input them to an enable pin of the drive module 200, thus achieving dual control of the drive module 200. The first control module 102 has a simple structure and is easy to implement.

[0137] In one embodiment of this application, the latch module 103 includes: a first NAND gate circuit 1034, a second NAND gate circuit 1037, a second pull-up resistor 1033, a second power supply 1032, a third pull-up resistor 1035 and a third power supply 1036, and a unidirectional conduction unit 1031, wherein:

[0138] The first terminal 1031a of the unidirectional conduction unit 1031 is connected to the first output terminal 101a of the current sampling module 101, and the second terminal 1031b of the unidirectional conduction unit 1031 is connected to the first input terminal 1034a of the first NAND gate circuit 1034. The conduction direction of the unidirectional conduction unit 1031 is the direction in which the second terminal 1031b of the unidirectional conduction unit 1031 points to the first terminal 1031a of the unidirectional conduction unit 1031.

[0139] The second input terminal 1034b of the first NAND gate circuit 1034 is connected to the output terminal 1037c of the second NAND gate circuit 1037, and the output terminal 1034c of the first NAND gate circuit 1034 is connected to the first input terminal 1037a of the second NAND gate circuit 1037.

[0140] The first end 1033a of the second pull-up resistor 1033 is connected to the output end of the second power supply 1032, and the second end 1033b of the second pull-up resistor 1033 is connected to the first input end 1034a and the ground end 103d of the first NAND gate circuit 1034, respectively.

[0141] The second input terminal 1037b of the second NAND gate circuit 1037 is connected to the second output terminal 104d of the second control module 104, and the output terminal 1037c of the second NAND gate circuit 1037 is connected to the first input terminal 102a of the first control module 102.

[0142] The output terminal of the third power supply 1036 is connected to the output terminal 1037c of the second NAND gate circuit 1037 through the third pull-up resistor 1035.

[0143] In this embodiment, the second power supply 1032 and the third power supply 1036 are a single power supply that can provide a 5V voltage signal. This embodiment also provides a structure for a latch module 103, which is simple and easy to implement.

[0144] In one embodiment of this application, as shown in FIG3, the driving circuit provided in this application further includes a filter capacitor 1038, wherein:

[0145] The second pull-up resistor 1033 is grounded through the filter capacitor 1038.

[0146] In this embodiment, interference signals can be filtered out by the filter capacitor 1038, which allows the latch module 103 to receive accurate signals output by the current sampling module.

[0147] In one embodiment of this application, as shown in FIG3, the unidirectional conduction unit 1031 is a diode, wherein:

[0148] The anode of the diode is connected to the first input terminal 1034a of the first NAND gate circuit 1034, and the cathode of the diode is connected to the first output terminal 101a of the current sampling module 101.

[0149] In this embodiment, the unidirectional conduction unit 1031 is implemented using a diode, which is a simple and easy-to-implement method.

[0150] In one embodiment of this application, the second control module 104 in the driving circuit provided by this application includes a first core and a second core, wherein:

[0151] The first core is connected to both the first output terminal 101a and the second output terminal 101b of the current sampling module 101, and the first core is communicatively connected to the second core.

[0152] The first core is used to send an overcurrent feedback indication signal to the second core when it receives a first overcurrent notification signal and / or determines that the drive current is overcurrent based on the voltage signal.

[0153] The second core is connected to both the first output terminal 101a and the second output terminal 101b of the current sampling module 101, and the second core is connected to the first input terminal 102a of the first control module 102.

[0154] Upon receiving a return check indication signal, the second kernel determines whether a first overcurrent notification signal has been received, and determines whether the drive current is overcurrent based on the voltage signal. If the first overcurrent notification signal is received and the drive current is determined to be overcurrent based on the voltage signal, the second kernel sends a third overcurrent notification signal to the first control module 102.

[0155] In this embodiment, the first control module is implemented using a dual-core architecture consisting of a first core and a second core. If the first core determines that the input current is overcurrent, it sends a feedback instruction to the second core. Upon receiving the feedback instruction, the second core re-detects whether the input current is overcurrent. This reduces the likelihood of processing errors by the first control module.

[0156] In one embodiment of this application, as shown in FIG2, the third output terminal 104e of the second control module 104 is connected to the drive signal input terminal 200b of the drive module 200, wherein:

[0157] The second control module 104 is used to stop outputting drive signals to the drive module 200 when a third overcurrent notification signal is output.

[0158] In this embodiment, when the second control module 104 outputs a third overcurrent notification signal, it indicates that the input current is overcurrent. At this time, the second control module 104 stops outputting drive signals to the drive module 200, thereby protecting the devices in the drive module 200. The devices in the drive module 200 are typically power devices, and the drive signal is typically a PWM signal.

[0159] Taking the driving circuit shown in Figure 3 as an example, the working principle of the driving circuit provided in this application will be explained below.

[0160] When the current sampling module 101 determines that the input current is not overcurrent, its first output terminal 101a outputs a high-level signal, which serves as a first no-overcurrent notification signal. Simultaneously, the current sampling module 101 converts the input current into a voltage signal and inputs it to the second control module 104. Based on this, the second control module 104 receives the high-level signal (serving as the first no-overcurrent notification signal) at its first input terminal 104a, and receives the voltage signal at its second input terminal 104c. The second control module 104 determines that the input current is not overcurrent based on the voltage signal. At this time, the second control module 104 outputs a high-level reset signal to the second input terminal 1037b of the second NAND gate circuit 1037, and inputs a high-level second no-overcurrent notification signal to the first input terminal 1023a of the AND gate circuit 1023. Since the first output terminal 101a of the current sampling module 101 is a high-level signal, and due to the presence of the diode in the unidirectional conduction unit 1031, the first input terminal 1034a of the first NAND gate circuit 1034 is also a high-level signal. The second input terminal 1037b of the second NAND gate circuit 1037 is also a high-level signal. The output terminal 1037c of the second NAND gate circuit 1037 is pulled up by a 5V third power supply 1036, so the second input terminal 1034b of the first NAND gate circuit 1034 is also a high-level signal. The two high-level signals input to the first NAND gate circuit 1034 are output as low-level signals after passing through the first NAND gate circuit 1034. Therefore, the first input terminal 1037a of the second NAND gate circuit 1037 is a low-level signal. After a high-level signal and a low-level signal are input to the second NAND gate 1037, the second NAND gate 1037 outputs a high-level signal. This further strengthens the feedback between the first NAND gate 1034 and the second NAND gate 1037, ensuring that the latch module 103 inputs a high-level signal to the second input terminal of the AND gate 1023, resulting in a third no-overcurrent notification signal. Simultaneously, the first output terminal 104b of the second control module 104 outputs a high-level second no-overcurrent notification signal. Since both input terminals of the AND gate 1023 are high-level signals, it outputs a high-level signal to the driver module 200. When the enable signal of the driver module 200 is high, the driver module 200 is allowed to operate normally.

[0161] Correspondingly, when the current sampling module 101 determines that the input current is overcurrent, its first output terminal 101a outputs a low-level first overcurrent notification signal. Simultaneously, the current sampling module 101 converts the input current into a voltage signal and inputs it to the second control module 104. Based on this, the first input terminal 104a of the second control module 104 receives the low-level signal as the first overcurrent notification signal, and the second input terminal 104c of the second control module 104 receives the voltage signal. The second control module 104 determines that the input current is overcurrent based on the voltage signal. At this time, the high-level signal input to the first input terminal 1034a of the first NAND gate circuit 1034 becomes a low-level first overcurrent notification signal. The high-level signal and the low-level signal are output as a high-level signal after passing through the first NAND gate circuit 1034. At this time, two high-level signals are input to the second NAND gate circuit 1037, and these two high-level signals become low-level after passing through the second NAND gate circuit 1037. When the output of the second NAND gate 1037 is low, the pull-up of the external 5V third power supply 1036 ceases to function, and the output to the second input terminal 1023b of the AND gate 1023 becomes a low-level signal, which serves as the second overcurrent notification signal. After the operation of the AND gate 1023, a low-level signal is output. At this time, the enable pin of the drive module 200 becomes a low-level signal, and the drive module 200 ceases to operate. Simultaneously, after receiving the low-level signal serving as the first overcurrent notification signal, the first core of the second control module 104 instructs the second core to perform a recheck to determine whether the input current is overcurrent. If the second core determines that there is an overcurrent, the second control module 104 outputs a low-level third overcurrent notification signal. At this time, the first input terminal 1023a of the AND gate 1023 receives the low-level third overcurrent notification signal, thus the enable pin of the drive module 200 remains at a low level, and the drive module 200 ceases to operate.

[0162] After the input current recovers from overcurrent to non-overcurrent, the first overcurrent notification signal output by the current sampling module 101 switches to the first non-overcurrent notification signal. At this time, the first input terminal 1034a of the first NAND gate circuit 1034 returns to a high-level signal. However, the output signal of the second NAND gate circuit 1037 is still a low-level signal, and the second input terminal 1034b fed back to the first NAND gate circuit 1034 is a low-level signal. At this time, the first NAND gate circuit 1034 outputs a high-level signal, so the first input terminal 1037a of the second NAND gate circuit 1037 is a high-level signal. The high-level reset signal output by the second control module 104 changes from a high-level signal to a low-level signal, the second non-overcurrent notification signal, and the drive circuit 100 provided in this application starts the reset mode, and the output of the second NAND gate circuit 1037 becomes a high-level signal.

[0163] It should be noted that Figure 3 illustrates an example where the voltage values ​​of the first power supply 1021, the second power supply 1032, and the third power supply 1036 are 5V. However, the voltage values ​​of the first power supply 1021, the second power supply 1032, and the third power supply 1036 are not limited to 5V; for example, they could be any of 3.3V, 5V, and 12V. Furthermore, the voltage values ​​of the first power supply 1021, the second power supply 1032, and the third power supply 1036 can be different.

[0164] Furthermore, the low-level and high-level signals in the above examples are relative; that is, the high-voltage and low-level signals do not involve specific voltage ranges, as long as the voltage value of the high-level signal is higher than the voltage value of the low-level signal. For example, the high-level signal, which serves as the first overcurrent notification signal, corresponds to a voltage value greater than 50% of the voltage value of the second power supply 1032. Correspondingly, the first overcurrent notification signal of the low-level signal corresponds to a voltage value less than 50% of the voltage value of the second power supply 1032. Similarly, the reset signal of the high-level signal corresponds to a voltage value greater than 50% of the voltage value of the third power supply 1036. The second overcurrent notification signal of the high-level signal corresponds to a voltage value greater than 50% of the voltage value of the first power supply 1021. The second overcurrent notification signal of the low-level signal corresponds to a voltage value less than 50% of the voltage value of the third power supply 1036. The third overcurrent notification signal of the high-level signal corresponds to a voltage value greater than 50% of the voltage value of the third power supply 1036. The third overcurrent notification signal of the low-level signal corresponds to a voltage value less than 50% of the voltage value of the first power supply 1021.

[0165] This application also provides an electronic device that includes the driving circuit provided in any of the above embodiments.

[0166] This application also provides a motor controller, including: a current sensor, a control chip, a driver chip, and a latch, wherein:

[0167] The first output terminal of the current sensor is connected to the first input terminal of the latch;

[0168] The output of the latch is connected to the first input of the control chip;

[0169] The output terminal of the control chip is connected to the enable terminal of the driver chip;

[0170] Among them, the current sensor collects the current value of the input current of the driven object of the driving chip, and when it is determined that the input current is overcurrent, the first overcurrent notification signal is output through the first output terminal of the current sensor.

[0171] Upon receiving the first overcurrent notification signal, the latch outputs a second overcurrent notification signal to the control chip. The second overcurrent notification signal is a latch signal for the first overcurrent notification signal.

[0172] Upon receiving the second overcurrent notification signal, the control chip controls the driver chip to stop being enabled.

[0173] It should be noted that the specific implementation of the current sensor in this embodiment is the same as the specific implementation of the current sampling module in any of the above driving circuit embodiments, the specific implementation of the control chip in this embodiment is the same as the specific implementation of the first control module in any of the above driving circuit embodiments, the specific implementation of the latch in this embodiment is the same as the specific implementation of the latch module in any of the above driving circuit embodiments, and the specific implementation of the driving chip in this embodiment is the same as the specific implementation of the driving module in any of the above driving circuit embodiments. These details will not be repeated here.

[0174] In one example, the controller can specifically be a motor controller. Based on this, the driver chip is specifically the driver chip within the motor controller, and the driven object is the power module within the motor controller. The power module includes power transistors, which can be IGBTs.

[0175] This application also provides a vehicle that includes the controller provided in the controller embodiments described above. Alternatively, the vehicle includes a drive circuit as provided in any of the drive circuit embodiments described above.

[0176] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this application is defined by the appended claims.

Claims

1. A driving circuit (100), wherein, include: A current sampling module (101) is used to collect the input current of the driven object of the drive module (200), and outputs a first overcurrent notification signal when it is determined that the input current is overcurrent; A latch module (103) is connected to the current sampling module (101), and the latch module (103) is used to receive the first overcurrent notification signal; and A first control module (102) is connected to the latch module (103) and is used to receive a second overcurrent notification signal output by the latch module. The second overcurrent notification signal is a latch signal for the first overcurrent notification signal. The first control module is also connected to the drive module (200). When the first control module (102) receives the second overcurrent notification signal, it controls the drive module (200) to stop enabling.

2. The driving circuit according to claim 1, wherein, The driving circuit also includes: The second control module (104) is connected to the first input terminal (104a) of the current sampling module (101). The first output terminal (104b) of the second control module (104) is connected to the second input terminal (102b) of the first control module (102); the first output terminal (101a) of the current sampling module (101) is connected to the first input terminal (103a) of the latch module (103); the output terminal (103b) of the latch module (103) is connected to the first input terminal (102a) of the first control module (102). The second control module (104) is used to output a third overcurrent notification signal to the first control module (102) when the first overcurrent notification signal is received; The first control module (102) is used to control the drive module (200) to stop enabling when it receives at least one of the third overcurrent notification signal and the second overcurrent notification signal.

3. The driving circuit according to claim 2, wherein, The latch module (103) outputs the second overcurrent notification signal to the first control module (102) at the first moment; The second control module (104) outputs the third overcurrent notification signal to the first control module (102) at a second time; the second time is later than the first time. The first control module (102) is used to control the drive module (200) to stop enabling when the second overcurrent notification signal is received; The first control module (102) is used to control the drive module (200) to stop enabling again when the third overcurrent notification signal is received.

4. The driving circuit according to claim 2, wherein, The second output terminal (101b) of the current sampling module (101) is connected to the second input terminal (104c) of the second control module (104). The current sampling module (101) is also used to convert the input current into a voltage signal and transmit the voltage signal to the second control module (104) through the second output terminal (101b) of the current sampling module (101). The second control module (104) is used to output the third overcurrent notification signal to the first control module (102) when it is determined that the input current is overcurrent based at least on the voltage signal.

5. The driving circuit according to claim 2, wherein, The second output terminal (104d) of the second control module (104) is connected to the second input terminal (103c) of the latch module (103); The current sampling module (101) is also used to output a first no-overcurrent notification signal through the first output terminal (101a) of the current sampling module (101) when it is determined that the input current is not overcurrent; Upon receiving the first no-overcurrent notification signal, the second control module (104) outputs a reset signal to the latch module (103) and outputs a second no-overcurrent notification signal to the first control module (102); The latch module (103) is used to output a third no-overcurrent notification signal to the first control module (102) when it receives the reset signal and the first no-overcurrent notification signal; The first control module (102) is used to enable the drive module (200) when it receives the third no overcurrent notification signal and the second no overcurrent notification signal.

6. The driving circuit according to claim 4, wherein, The second output terminal (104d) of the second control module (104) is connected to the second input terminal (103c) of the latch module (103); The current sampling module (101) is also used to output a first no-overcurrent notification signal through the first output terminal (101a) of the current sampling module (101) when it is determined that the input current is not overcurrent; The second control module (104) is used to output a reset signal to the latch module (103) and output a second no-overcurrent notification signal to the first control module (102) when it is determined from the voltage signal that the input current is not overcurrent. The latch module (103) is used to output a third no-overcurrent notification signal to the first control module (102) when it receives the reset signal and the first no-overcurrent notification signal; The first control module (102) is used to enable the drive module (200) when it receives the third no overcurrent notification signal and the second no overcurrent notification signal.

7. The driving circuit according to claim 2, wherein, The first control module (102) includes: First power supply (1021); The first pull-up resistor (1022) is connected to the second terminal (1022b) of the first power supply (1021); The AND gate circuit (1023) has its first input terminal (1023a) connected to the first output terminal (104b) of the second control module (104) and the first terminal (1022a) of the first pull-up resistor (1022), respectively. The second input terminal (1023b) of the AND gate circuit (1023) is connected to the output terminal (103b) of the latch module (103), and the output terminal (1023c) of the AND gate circuit (1023) is connected to the enable terminal (200a) of the drive module (200).

8. The driving circuit according to claim 2, wherein, The latch module (103) includes: First NAND gate (1034); A unidirectional conduction unit (1031) is provided, wherein the first end (1031a) of the unidirectional conduction unit (1031) is connected to the first output end (101a) of the current sampling module (101), and the second end (1031b) of the unidirectional conduction unit (1031) is connected to the first input end (1034a) of the first NAND gate circuit (1034). The conduction direction of the unidirectional conduction unit (1031) is the direction in which the second end (1031b) of the unidirectional conduction unit (1031) points to the first end (1031a) of the unidirectional conduction unit (1031). The second NAND gate (1037) has its second input terminal (1034b) of the first NAND gate (1034) connected to its output terminal (1037c), and its output terminal (1034c) connected to its first input terminal (1037a). The second input terminal (1037b) of the second NAND gate (1037) is connected to the second output terminal (104d) of the second control module (104), and its output terminal (1037c) is connected to the first input terminal (102a) of the first control module (102). Second power supply (1032); The second pull-up resistor (1033) has its first end (1033a) connected to the second power supply (1032), and its second end (1033b) connected to the first input terminal (1034a) and the ground terminal (103d) of the first NAND gate circuit (1034), respectively. Third pull-up resistor (1035); The third power supply (1036) is connected to the output terminal (1037c) of the second NAND gate circuit (1037) through the third pull-up resistor (1035).

9. The driving circuit according to claim 8, wherein, The driving circuit also includes a filter capacitor (1038); The second pull-up resistor (1033) is grounded through the filter capacitor (1038).

10. The driving circuit according to claim 8, wherein, The unidirectional conduction unit (1031) is a diode; The anode of the diode is connected to the first input terminal (1034a) of the first NAND gate circuit (1034), and the cathode of the diode is connected to the first output terminal (101a) of the current sampling module (101).

11. The driving circuit according to claim 4, wherein, The second control module (104) includes: The first core is connected to both the first output terminal (101a) and the second output terminal (101b) of the current sampling module (101); The second core is connected to both the first output terminal (101a) and the second output terminal (101b) of the current sampling module (101), and is also connected to the first input terminal (102a) of the first control module (102); the first core and the second core are communicatively connected. The first core is configured to send an overcurrent feedback indication signal to the second core when it receives the first overcurrent notification signal and / or determines that the drive current is overcurrent based on the voltage signal; When the second kernel receives the return check indication signal, it determines whether the first overcurrent notification signal has been received, and determines whether the drive current is overcurrent based on the voltage signal. When the second kernel receives the first overcurrent notification signal and determines that the drive current is overcurrent based on the voltage signal, the second kernel sends the third overcurrent notification signal to the first control module (102).

12. The driving circuit according to claim 2, wherein, The third output terminal (104e) of the second control module (104) is connected (200b) to the drive signal input terminal of the drive module (200). When the second control module (104) outputs the third overcurrent notification signal, it stops outputting drive signals to the drive module (200).

13. A controller, wherein, include: Driver chip; A control chip, which is connected to the driver chip; A latch, which is connected to the control chip; A current sensor, which is connected to the latch; The current sensor collects the current value of the input current of the driven object of the driving chip, and outputs a first overcurrent notification signal through the current sensor when it is determined that the input current is overcurrent. Upon receiving the first overcurrent notification signal, the latch outputs a second overcurrent notification signal to the control chip. The second overcurrent notification signal is a latch signal for the first overcurrent notification signal. Upon receiving the second overcurrent notification signal, the control chip controls the driver chip to stop being enabled.

14. A vehicle, wherein, Includes the drive circuit as described in any one of claims 1-12; Alternatively, it may include the controller as described in claim 13.

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