Method for etching group iii nitride semiconductor

Abstract

This method for etching a group III nitride semiconductor comprises: a first step of preparing a group III nitride semiconductor having a carrier concentration of 1E +19 / cm 3 or more; and a second step of etching at least a section of the group III nitride semiconductor by applying a voltage between the group III nitride semiconductor and a counter electrode in a state of immersion in an electrolyte.

Description

Etching method for group III nitride semiconductor

[0001] The present disclosure relates to a method for etching Group III nitride semiconductors.

[0002] Conventionally, photoelectrochemical etching has been used as a wet etching method for chemically stable group III nitride semiconductors. A technique for etching group III nitride semiconductors using photoelectrochemical etching is disclosed in, for example, Patent Document 1.

[0003] Japanese Patent Application Laid-Open No. 2007-227450

[0004] Patent Document 1 proposes a method for selectively etching a Group III nitride semiconductor by irradiating the Group III nitride semiconductor with light having a band gap energy lower than that of an etch stop layer and higher than that of a layer to be etched.

[0005] However, the photoelectrochemical etching method of Patent Document 1 requires the use of an optical system including a light source that emits ultraviolet light and a bandpass filter that selectively transmits only light in the vicinity of a specific wavelength range, which makes the etching apparatus complex and increases costs.

[0006] In view of the above circumstances, an object of the present disclosure is to provide a method for etching a Group III nitride semiconductor that can be realized using a simple etching apparatus.

[0007] In order to achieve the above object, the method for etching a Group III nitride semiconductor according to the present disclosure provides a method for etching a Group III nitride semiconductor with a concentration of 1E+19 / cm ３ The method includes a first step of preparing a Group III nitride semiconductor having the above carrier concentration, and a second step of applying a voltage between the Group III nitride semiconductor and a counter electrode while the semiconductor is immersed in an electrolyte solution, thereby etching at least a portion of the Group III nitride semiconductor.

[0008] According to one aspect of the present disclosure, it is possible to provide a method for etching a Group III nitride semiconductor that can be realized using a simple etching apparatus.

[0009] Graph showing the carrier concentration dependence of the etching rate in the electrochemical etching of group III nitride semiconductors Flowchart showing the etching method of group III nitride semiconductors according to an embodiment of the present disclosure Schematic diagram showing a configuration example of an apparatus for manufacturing a group III nitride semiconductor Flowchart showing the process of manufacturing a group III nitride semiconductor Schematic configuration diagram schematically showing an electrochemical etching apparatus for group III nitride semiconductors Diagram schematically showing a cross-section of a group III nitride semiconductor after etching Cross-sectional SEM image of a group III nitride semiconductor after etching by a scanning electron microscope according to an embodiment Graph showing the change in current density during the etching of a group III nitride semiconductor according to an embodiment Schematic cross-sectional view conceptually showing a group III nitride semiconductor device according to an embodiment of the present disclosure Schematic cross-sectional view conceptually showing an example in which a wafer of the group III nitride semiconductor device of FIG. 8A is thinned using the etching method according to an embodiment Schematic cross-sectional view conceptually showing a group III nitride semiconductor stacked device according to an embodiment of the present disclosure Schematic cross-sectional view conceptually showing an example in which a substrate of the group III nitride semiconductor stacked device of FIG. 9A is etched using the etching method according to an embodiment Schematic cross-sectional view conceptually showing the configuration of an N-polarity GaN-HEMT Diagram conceptually showing one step of the manufacturing process of an N-polarity GaN-HEMT to which the etching method according to an embodiment is applied Diagram conceptually showing one step of the manufacturing process of an N-polarity GaN-HEMT to which the etching method according to an embodiment is applied Diagram conceptually showing one step of the manufacturing process of an N-polarity GaN-HEMT to which the etching method according to an embodiment is applied

[0010] (Findings underlying the present disclosure) The inventors of the present application have obtained novel findings regarding the relationship between the etching rate and the carrier concentration of the etching target in the electrochemical etching of group III nitride semiconductors. This will be described with reference to FIG. 1. FIG. 1 is a graph showing the carrier concentration dependence of the etching rate in the electrochemical etching of group III nitride semiconductors.

[0011] It is generally known that the etching rate of electrochemical etching varies depending on the electrical conductivity of the material being etched. The present inventors have investigated the relationship between the etching rate and the carrier concentration of the material being etched in electrochemical etching of a Group III nitride semiconductor. Figure 1 shows the relationship between the etching rate and the carrier concentration of the material being etched when the carrier concentration is 1E+15 / cm ３ GaN substrate A less than about 2E+18 / cm ３ GaN substrate B of about 1E+19 / cm ３ GaN substrate C of about 5E+19 / cm ３ GaN substrate D of about 1E+20 / cm ３ The etching rates were measured when electrochemical etching was performed using a GaN substrate E of 10 and a GaN substrate E of 10. In this specification, E represents a power of 10. For example, 1E+19 is 10 １９ means.

[0012] As shown in FIG. 1, the carrier concentration is 1E+15 / cm ３ The etching rate of GaN substrate A is almost zero and is 2E+18 / cm ３ In the case of GaN substrate B, the etching rate is 200 μm / h, but this is due to etching into a porous structure, and electrochemical etching does not progress substantially. On the other hand, the carrier concentration is about 1E+19 / cm ３ The etching rate clearly increases with a threshold value of 1E+19 / cm ３ The GaN substrate C had an etching rate of more than 600 μm / h. Furthermore, the carrier concentration was 5E+19 / cm ３ It was found that the etching rates of GaN substrates D and E increased significantly, reaching 3,000 μm / h or more. Note that Figure 1 shows the results when the applied voltage was 13 V. Even when the applied voltage was increased to 33 V for GaN substrate B, delamination occurred, and good electrochemical etching did not proceed.

[0013] In this specification, the carrier concentration at which the etching rate clearly begins to increase in electrochemical etching of a Group III nitride semiconductor is referred to as the "etching threshold." The inventors of the present application have found that the carrier concentration at which the etching rate clearly begins to increase in electrochemical etching of a Group III nitride semiconductor is 1E+19 / cm ３ Based on this novel finding, the inventors of the present invention have arrived at the invention disclosed below.

[0014] According to the first aspect of the present disclosure, 1E+19 / cm ３ and a second step of applying a voltage between the Group III nitride semiconductor and a counter electrode while the Group III nitride semiconductor is immersed in an electrolyte solution, thereby etching at least a portion of the Group III nitride semiconductor.

[0015] According to this aspect, it is possible to provide a method for etching a Group III nitride semiconductor that can be realized using a simple etching apparatus.

[0016] According to a second aspect of the present disclosure, the carrier concentration is 5E+19 / cm ３ As described above, there is provided a method for etching a Group III nitride semiconductor according to the first aspect.

[0017] According to a third aspect of the present disclosure, there is provided the method for etching a Group III nitride semiconductor according to the first or second aspect, wherein the first step comprises supplying a nitrogen-containing gas and a Group III element oxide gas into a chamber, and growing a Group III nitride crystal in the chamber to fabricate a Group III nitride semiconductor.

[0018] According to a fourth aspect of the present disclosure, there is provided the method for etching a Group III nitride semiconductor according to the third aspect, wherein the first step further comprises adjusting the supply amount of the Group III element oxide gas relative to the amount of the nitrogen-containing gas supplied into the chamber.

[0019] According to a fifth aspect of the present disclosure, there is provided the method for etching a Group III nitride semiconductor according to any one of the first to fourth aspects, wherein the second step has an etching rate of 1 mm / h or more.

[0020] According to a sixth aspect of the present disclosure, there is provided the method for etching a Group III nitride semiconductor according to any one of the first to fifth aspects, wherein the Group III nitride semiconductor is gallium nitride, and an impurity contained in the Group III nitride semiconductor that has the highest concentration is any one of oxygen, Ge, and Sn.

[0021] According to a seventh aspect of the present disclosure, there is provided the method for etching a Group III nitride semiconductor according to the sixth aspect, wherein the impurity having the highest concentration is oxygen.

[0022] According to an eighth aspect of the present disclosure, there is provided the method for etching a Group III nitride semiconductor according to any one of the first to seventh aspects, wherein the Group III nitride semiconductor comprises a semiconductor film, a semiconductor crystal layer, a semiconductor wafer, or a semiconductor substrate, each of which contains a nitride of a Group III element.

[0023] Any of the above-described various embodiments may be combined appropriately to achieve the effects of each of them.

[0024] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, more detailed explanation than necessary may be omitted. For example, detailed explanation of well-known matters or redundant explanation of substantially the same configuration may be omitted. This is to avoid unnecessary redundancy in the following explanation and to facilitate understanding by those skilled in the art.

[0025] A method for etching a Group III nitride semiconductor according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 10B3. The accompanying drawings and the following description are provided to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the subject matter described in the claims. In addition, in each drawing, each element is exaggerated for ease of explanation. Note that substantially identical components in the drawings are assigned the same reference numerals.

[0026] First Embodiment (Method of Etching a Group III Nitride Semiconductor) A method of etching a Group III nitride semiconductor according to a first embodiment of the present disclosure will be described with reference to Fig. 2. Fig. 2 is a flowchart showing the method of etching a Group III nitride semiconductor according to an embodiment of the present disclosure.

[0027] 2 , the method for etching a Group III nitride semiconductor according to the embodiment of the present disclosure can include the steps of: preparing a Group III nitride semiconductor having a carrier concentration equal to or higher than an etching threshold (S01); and etching a desired portion of the prepared Group III nitride semiconductor by electrochemical etching (S02). Each step will be described in detail below.

[0028] (Step S01 of Preparing a Group III Nitride Semiconductor) A Group III nitride semiconductor according to an embodiment of the present disclosure can constitute a semiconductor film, a semiconductor crystal layer, a semiconductor wafer, or a semiconductor substrate containing a nitride of a Group III element. Furthermore, in an embodiment of the present disclosure, Step S01 of Preparing a Group III Nitride Semiconductor can include growing a Group III nitride crystal to fabricate the Group III nitride semiconductor. Step S01 will be described below with reference to FIGS. 3 and 4 . FIG. 3 is a schematic diagram showing an example configuration of an apparatus 150 for fabricating a Group III nitride semiconductor, and FIG. 4 is a flowchart showing a process 200 for fabricating a Group III nitride semiconductor.

[0029] <Outline of Group III Nitride Semiconductor Fabrication Apparatus> An outline of an apparatus 150 for fabricating a Group III nitride semiconductor will be described with reference to Fig. 3. Note that in Fig. 3, the size, ratio, etc. of each component may differ from the actual size, ratio, etc.

[0030] In an apparatus 150 for producing a Group III nitride semiconductor according to this embodiment, a source material reaction chamber 101 is disposed within a source material chamber 100, and a source material boat 104 carrying a starting Group III element source 105 is disposed within the source material reaction chamber 101. A reactive gas supply pipe 103 is connected to the source material reaction chamber 101, supplying a reactive gas that reacts with the starting Group III element source 105, and the source material reaction chamber 101 also has a Group III oxide gas outlet 107. Here, a reducing gas is used as the reactive gas when the starting Group III source is an oxide, and an oxidizing gas is used when the starting Group III source is a metal. The source material chamber 100 is further provided with a first carrier gas supply port 102.

[0031] The Group III oxide gas generated in the raw material reaction chamber 101 is discharged into the raw material chamber 100 through the Group III oxide gas outlet 107, and flows together with the carrier gas from the carrier gas outlet 108 through the connecting pipe 109 to the growth chamber 111.

[0032] The growth chamber 111 includes a Group III oxide gas and carrier gas supply port 118, an oxidizable gas supply port 113, a nitrogen-containing gas supply port 112, a second carrier gas supply port 114, and an exhaust port 119. A substrate susceptor 117 on which a support substrate 116 is placed is provided within the growth chamber 111, and a Group III nitride semiconductor can be produced by growing a Group III nitride crystal on the support substrate 116.

[0033] <Group III Nitride Semiconductor Fabrication Process> A Group III nitride semiconductor fabrication process 200 according to this embodiment will be described in detail with reference to FIGS. 3 and 4 . In process 200, a Group III nitride crystal is grown by oxide vapor phase epitaxy (OVPE) using a Group III element oxide gas as a raw material to fabricate a Group III nitride semiconductor. In this embodiment, for example, the Group III nitride semiconductor is a gallium nitride semiconductor and is composed of gallium nitride crystal. In the following description, the Group III nitride semiconductor will be referred to as a "GaN semiconductor." The GaN semiconductor formation process will be described using, as an example, metallic Ga as the starting Group III element source 105.

[0034] 4 can include a reactive gas supply step (S201), a Group III element oxide gas generation step (S202), a Group III element oxide gas supply step (S203), a nitrogen-containing gas supply step (S204), a Group III nitride crystal generation step (S205), and a residual gas exhaust step (S206). Each step will be described below.

[0035] (1) In the reactive gas supply step S 201 , a reactive gas is supplied to the source reaction chamber 101 through the reactive gas supply pipe 103 .

[0036] Methods for generating a group III oxide gas are roughly classified into a method for reducing the starting Ga source 105 and a method for oxidizing the starting Ga source 105. For example, in the reduction method, an oxide (e.g., Ga ２ O ３ ), a reducing gas (e.g., H ２ Gas, CO gas, CH ４ Gas, C ２ H ６ Gas, H ２ S gas, SO ２ On the other hand, in the oxidation method, a non-oxide (e.g., liquid Ga) is used as the starting Ga source 105, and an oxidizing gas (e.g., H ２ O gas, O ２ In step S201, a reactive gas corresponding to the starting Ga source 105 used can be supplied to the raw material reaction chamber 101. In this embodiment, for example, when metallic Ga is used as the starting Group III element source 105, an oxidizing gas is supplied as the reactive gas from the reactive gas supply pipe 103 to the raw material reaction chamber 101.

[0037] (2) In the Group III element oxide gas generating step S202, the reactive gas supplied to the raw material reaction chamber 101 in the reactive gas supplying step reacts with metal Ga, which is the starting Group III element source 105, to produce Group III oxide gas Ga ２ O gas is generated. Ga ２ The O gas is discharged from the source reaction chamber 101 to the source chamber 100 via the group III oxide gas discharge port 107.２ The O gas is mixed with a first carrier gas supplied from a first carrier gas supply port 102 to the source chamber, and the mixed gas is supplied to a Group III oxide gas and carrier gas outlet port 108. Here, an inert gas or H gas can be used as the first carrier gas.

[0038] In this embodiment, the reactive gas is H 2 , which is an oxidizing gas. ２ When O gas is supplied to the source reaction chamber 101, a group III oxide gas is generated, for example, according to the following formula (1).

[0039]

[0040] Here, the temperature of the first heater 106 is set to Ga ２ The temperature is set to 800° C. or higher in consideration of the boiling point of O gas, and to be lower than 1800° C. so as to be lower than the temperature of the second heater 115. The starting Ga source is placed in the source boat 104. The source boat 104 preferably has a shape that can increase the contact area between the reactive gas and the starting Ga source.

[0041] (3) In the Group III element oxide gas supply step S203, Ga generated in the Group III element oxide gas generation step S202 is supplied. ２ The group III element oxide gas GaO gas is supplied to the growth chamber 111 via the group III oxide gas and carrier gas outlet 108, the connecting pipe 109, and the group III oxide gas and carrier gas supply port 118. In this embodiment, the group III element oxide gas GaO gas is supplied to the growth chamber 111. ２ The amount of O gas can be adjusted.

[0042] Furthermore, when the temperature of the connecting pipe 109 connecting the source chamber 100 and the growth chamber 111 drops below the temperature of the source chamber 100, a reverse reaction of the reaction for producing the Group III oxide gas occurs, and the starting Ga source 105 precipitates inside the connecting pipe 109. Therefore, the connecting pipe 109 is heated by the third heater 110 to a temperature higher than that of the first heater 106 so that the temperature does not drop below that of the source chamber 100.

[0043] (4) In the nitrogen-containing gas supply step S204, a nitrogen-containing gas is supplied to the growth chamber 111 from the nitrogen-containing gas supply port 112. The nitrogen-containing gas may be NH３ Gas, NO Gas, NO ２ Gas, N ２ O gas, N ２ H ２ Gas, N ２ H ４ Gas, etc. can be used.

[0044] (5) In the Group III nitride crystal growth step S205, the source gases supplied into the growth chamber via the various supply steps are synthesized to grow a Group III nitride crystal. The growth chamber 111 is heated by the second heater 115 to a temperature at which the Group III oxide gas and the nitrogen-containing gas react. During this process, the growth chamber 111 is heated so that its temperature does not drop below the temperature of the source chamber 100, in order to prevent a reverse reaction of the reaction that produces the Group III oxide gas.

[0045] In this embodiment, the temperature of the second heater 115 can be set to, for example, 1200° C. or higher. ２ The temperature of the third heater 110 can be set according to the set temperature of the second heater 115 so as to suppress temperature fluctuations in the growth chamber 111 caused by the O gas and the first carrier gas. This allows the support substrate 116 placed in the growth chamber 111 to be maintained at a temperature of 1200°C or higher, allowing GaN crystals to grow on the support substrate 116.

[0046] In this embodiment, in step S205, the Group III oxide gas, Ga, which is supplied to the growth chamber 111 through the Group III element oxide gas supply step S203, is ２ O gas and NH 4 , a nitrogen-containing gas, which is supplied to the growth chamber 111 through the nitrogen-containing gas supply step S204. ３ By mixing the gas with the gas upstream of the support substrate 116, a GaN crystal is grown on the support substrate 116 according to the following formula (2), thereby making it possible to manufacture a GaN semiconductor.

[0047]

[0048] In step S205, for example, a nitrogen-containing gas NH ３With respect to the amount of Group III oxide gas Ga ２ By adjusting the supply amount of O gas, the carrier concentration of the group III nitride GaN crystal to be produced can be adjusted.

[0049] In addition, in order to prevent the nitrogen-containing gas shown in FIG. 3 from being decomposed by heat from the growth chamber 111, it is preferable to cover the nitrogen-containing gas supply port 112 and the outer wall of the growth chamber 111 with a heat insulating material.

[0050] Parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117 can be a problem. Therefore, by controlling the concentrations of the group III oxide gas and the nitrogen-containing gas using the second carrier gas supplied to the growth chamber 111 from the second carrier gas supply port 114, it is possible to suppress the parasitic growth of GaN crystals on the furnace walls of the growth chamber 111 and on the substrate susceptor 117. Here, the second carrier gas can be an inert gas or H ２ A gas can be used.

[0051] (6) In the residual gas exhaust step S206, the carrier gas that does not contribute to the growth of GaN crystals and unreacted gas are exhausted from the exhaust port 117.

[0052] The carrier concentration of a Group III nitride semiconductor depends on the concentration of impurity elements contained in the Group III nitride semiconductor. Of the impurities contained in Group III nitride semiconductors, oxygen, germanium (Ge), or tin (Sn) can be added at the highest concentration and can be contained in the Group III nitride semiconductor. In this embodiment, the GaN semiconductor produced by the OVPE method has oxygen as the impurity with the highest concentration, and has a very high oxygen concentration, thereby allowing it to have a high carrier concentration. In this embodiment, for example, in process 200, a Group III oxide gas Ga ２ By adjusting the supply amount of O gas, the GaN semiconductor fabricated had a SiO2 concentration of 5E+19 / cm ３In this way, a Group III nitride semiconductor produced by OVPE has a carrier concentration equal to or higher than the etching threshold shown in FIG. 1 and can be etched at a high etching rate using electrochemical etching.

[0053] With the OVPE method, the growth temperature and growth time of GaN crystals can be set as needed, allowing GaN crystals to be grown to a desired thickness. Furthermore, while the generation of GaN crystals has been described as an example, the present disclosure is not limited thereto. For example, in the Group III nitride semiconductor fabrication apparatus 150 shown in FIG. 3 , an In source or an Al source can be used as the starting Group III element source 105 in addition to a Ga source. This allows Group III nitride crystals such as InN (indium nitride) and AlN (aluminum nitride) to be grown. In this way, by growing Group III nitride crystals using the OVPE method, it is possible to fabricate, for example, semiconductor films, semiconductor crystal layers, semiconductor wafers, and semiconductor substrates containing nitrides of various Group III elements.

[0054] It should be noted that the preparation of a Group III nitride semiconductor having a carrier concentration equal to or higher than the etching threshold according to the embodiments of the present disclosure is not limited to the OVPE method, and for example, a Group III nitride semiconductor film having a carrier concentration equal to or higher than the etching threshold can also be prepared by a sputtering method.

[0055] (Step S02 of Etching Group III Nitride Semiconductor by Electrochemical Etching) Returning to Fig. 2 , step S02 of etching a desired portion of the prepared Group III nitride semiconductor by electrochemical etching will now be described with reference to Figs. 5 and 6 . Fig. 5 is a schematic diagram illustrating the configuration of an electrochemical etching apparatus 250 for the Group III nitride semiconductor 126. Fig. 6 is a diagram illustrating a cross section of the Group III nitride semiconductor 126A after etching.

[0056] Step S02 is performed using an electrochemical etching apparatus 250 shown in Fig. 5. As shown in Fig. 5, the GaN semiconductor 126 prepared in step S01 is immersed in an electrolytic solution 30 stored in a container 40 of the electrochemical etching apparatus 250. While immersed in the electrolytic solution 30, the GaN semiconductor 126 is connected to the positive terminal of a power supply 60 via a current detector 50, and a platinum (Pt) counter electrode 20 immersed in the electrolytic solution 30 is connected to the negative terminal of the power supply 60. The power supply 60 outputs a DC voltage, and by applying a voltage between the GaN semiconductor 126 and the Pt counter electrode 20, the GaN semiconductor 126 can be etched.

[0057] The current detector 50, which is disposed between the power supply device 60 and the GaN semiconductor 126, detects the current flowing through the etching circuit and sends the detected signal to, for example, a control device (not shown). The control device sends a command signal to the power supply device 60 to change the value of the applied voltage and start or stop the output of the DC voltage, thereby starting or stopping etching. Note that the applied voltage may also be controlled manually based on the detection results of the current detector 50 without using a control device.

[0058] The electrolytic solution 30 can be, for example, a solution of an alkali such as potassium hydroxide (KOH) or sodium hydroxide (NaOH), or an acid such as hydrochloric acid (HCl) dissolved in water, glycol, or the like, and can be kept at a predetermined temperature within the container 40 during etching.

[0059] As shown in FIG. 6, when etching a desired portion of the GaN semiconductor 126, a SiO 2 film is previously formed on the portion of the upper surface 126a of the GaN semiconductor 126 that is not to be etched. ２An etching mask 127 made of a silicon nitride film or an SiN film can be placed on the GaN semiconductor 126A. When a voltage is applied by the power supply 60, etching progresses, and the upper surface 126a of the GaN semiconductor 126 is dissolved by the electrolyte 30 starting from a portion corresponding to the opening 127a of the etching mask, forming a recess 128 in the etched GaN semiconductor 126A. The etching depth D from the upper surface 126a to the bottom surface 128a of the recess 128 can be controlled, for example, by changing the amount of current flowing through the etching circuit.

[0060] By using the above etching method, etching of a group III nitride semiconductor can be achieved using a simple electrochemical etching apparatus 250 as shown in FIG.

[0061] In the above description, the carrier concentration of the Group III nitride semiconductor is described using an example in which oxygen is added as an impurity element, but the present disclosure is not limited to this. For example, the impurity element added to the Group III nitride semiconductor may be germanium (Ge) or tin (Sn) in addition to oxygen, or multiple types of impurity elements may coexist.

[0062] (Etching of Group III nitride semiconductor according to an example) Etching of a Group III nitride semiconductor was carried out using an etching method according to an embodiment of the present disclosure. An example according to an embodiment of the present disclosure will be described below with reference to FIGS. 7A and 7B. FIG. 7A is a cross-sectional SEM image taken by a scanning electron microscope after etching of the Group III nitride semiconductor according to the example. FIG. 7B is a graph showing changes in current density during etching of the Group III nitride semiconductor according to the example.

[0063] In this example, a GaN crystal was grown by oxide vapor phase epitaxy (OVPE) on a commercially available HVPE-GaN substrate 135 fabricated by HVPE, to fabricate an OVPE-GaN semiconductor layer 136. The fabricated sample 130 was immersed in a 1 mol / L KOH aqueous solution, and electrochemical etching was performed at an applied voltage of 7 V, with the OVPE-GaN semiconductor layer side serving as the anode and a platinum (Pt) counter electrode serving as the cathode. After electrochemical etching, the sample 130 was observed using a scanning electron microscope (SEM) to evaluate the etching.

[0064] (Evaluation of Etching of Group III Nitride Semiconductors by Example) The carrier concentration of the sample 130 was measured using a Hall measurement method. In this example, the HVPE-GaN substrate 135 produced by the HVPE method mainly contains silicon (Si) as an impurity, and the carrier concentration is 2E+18 / cm ３ The OVPE-GaN semiconductor layer 136 formed by the OVPE method contains oxygen as the main impurity and has a carrier concentration of 5E+19 / cm ３ and it was found that the carrier concentration was equal to or higher than the etching threshold.

[0065] 7A, the portion indicated by the symbol A is a portion 136A of the OVPE-GaN semiconductor layer having an etching mask disposed thereon, and the portion indicated by the symbol B is a portion 136B of the OVPE-GaN semiconductor layer that has been etched. As shown in the figure, it can be seen that portion 136B has been dissolved by the electrolyte.

[0066] As shown in FIG. 7A , etching progressed to interface 136 a between OVPE-GaN semiconductor layer 136 and HVPE-GaN substrate 135 in portion 136B. In the cross-sectional SEM image of FIG. 7A , the cross-section of portion 136B is etched to interface 136 a, but a "cliff" of portion 136A of the OVPE-GaN semiconductor layer, where the etching mask was placed and remained, is observed in the depth direction. On the other hand, etching did not progress in HVPE-GaN substrate 135, and it can be seen that HVPE-GaN substrate 135, which has a carrier concentration lower than the etching threshold, essentially functioned as an etch stop layer. Observation of the cross-sectional SEM image of FIG. 7A revealed that the etching depth D was approximately 270 μm.

[0067] Next, as shown in FIG. 7B, during a period T1 from the start of etching to approximately 800 seconds, the current density is 2 mA / mm ２ As a result, the etched OVPE-GaN semiconductor layer 136 has a high carrier concentration and exhibits good electrical conductivity. During period T1, the OVPE-GaN semiconductor layer of portion 136B is almost completely etched at a high etching rate.

[0068] At point E1 shown in FIG. 7B, the current density suddenly decreases to 0.5 mA / mm ２ At this time, the etching reached the vicinity of interface 136a between OVPE-GaN semiconductor layer 136 and HVPE-GaN substrate 135, and the thin, initially grown OVPE-GaN semiconductor layer near interface 136a had a relatively low oxygen concentration, which presumably increased the electrical resistance and caused the etching rate to drop sharply.

[0069] During the period T2 from point E1 to point E2, which is about 1600 seconds, etching did not progress at all, and at point E2, etching self-stopped and was completed. Assuming that etching progressed to a depth D of 270 μm during the 800 seconds of period T1 shown in FIG. 7B, in this example, the etching rate of the OVPE-GaN semiconductor layer 136 was about 1227 μm / h, which indicates that an etching rate of 1 mm / h or more was achieved. It should be noted that the carrier concentration is 5E+19 / cm 3 compared to FIG. 1 . ３This is because the electrochemical etching was performed at an applied voltage of 7 V in this example, whereas the results in FIG. 1 were obtained at an applied voltage of 13 V.

[0070] This example confirmed that the etching method according to the embodiment of the present disclosure can be used to etch a Group III nitride semiconductor using a simple etching apparatus, and that a high etching rate can be achieved. Furthermore, the etching method according to the embodiment of the present disclosure can avoid the risk of damage that can occur during mechanical processing, significantly improve the processing speed of the Group III nitride semiconductor, and reduce processing costs.

[0071] The etching method of the present disclosure can be applied to, for example, thinning of a Group III nitride semiconductor wafer, selective etching of a Group III nitride semiconductor substrate, fabrication of an N-polar GaN-HEMT, etc. These application examples will be described below with reference to FIGS.

[0072] (Application Example 1: Thinning of Group III Nitride Semiconductor Wafer) An example in which the etching method of the present disclosure is applied to thinning of a Group III nitride semiconductor wafer is conceptually shown in Figures 8A and 8B. Figure 8A is a schematic cross-sectional view conceptually showing a Group III nitride semiconductor device 300 according to an embodiment of the present disclosure, and Figure 8B is a schematic cross-sectional view conceptually showing an example in which the wafer of Group III nitride semiconductor device 300 of Figure 8A has been thinned using the etching method according to an embodiment.

[0073] Group III nitride semiconductors are widely used in optical semiconductor devices such as light emitting diodes (LEDs) and semiconductor laser diodes (LDs), and electronic devices such as power devices. For example, a group III nitride semiconductor device 300 conceptually shown in FIG. 8A can be constructed by providing a functional layer 320 on the front surface 310a of a semiconductor wafer 310. In the case of an optical semiconductor device, the functional layer 320 can include, for example, a light emitting layer (not shown) containing a group III nitride element, and in the case of a power device, the functional layer 320 can include, for example, a channel layer (not shown) containing a group III nitride element.

[0074] In order to reduce the thermal resistance of these group III nitride semiconductor devices, it is possible to thin the semiconductor wafer 310. However, thinning the semiconductor wafer by mechanical grinding / polishing and chemical mechanical polishing (CMP) requires a long processing time of several hours, which increases costs and also creates a risk of damaging the semiconductor elements in the functional layer during processing.

[0075] Therefore, the etching method according to the embodiment of the present disclosure can be used to thin the wafer of the group III nitride semiconductor device 300. Specifically, for example, a group III nitride semiconductor wafer 310 having a carrier concentration equal to or higher than the etching threshold is fabricated by OVPE, and a functional layer 320 is disposed on the front surface 310a. Next, the group III nitride semiconductor wafer 310 can be thinned by etching it from the back surface 310b using electrochemical etching.

[0076] In electrochemical etching, a Group III nitride semiconductor wafer 310 having a carrier concentration equal to or higher than the etching threshold can achieve a high etching rate ( FIG. 1 ). Therefore, for example, etching to a depth of approximately 300 to 400 μm can be completed within one hour, and a Group III nitride semiconductor wafer 310 having a thickness of 400 to 500 μm can be thinned to a thickness of 50 to 100 μm. Furthermore, because etching can be performed without contacting the functional layer 320 provided on the front surface 310 a of the wafer 310, the risk of damage that may occur during mechanical grinding / polishing or chemical mechanical polishing (CMP) can be significantly reduced.

[0077] The group III nitride semiconductor device 300A conceptually shown in FIG. 8B is constructed by thinning a central portion of a group III nitride semiconductor wafer 310 from thickness H1 to thickness h1, attaching an electrode 330 to the backside 310b, and then mounting the device on a heat dissipation die 350 via highly thermally conductive solder 340. Thinning a portion of the wafer 310 in this manner reduces thermal resistance and maintains sufficient wafer strength by leaving supporting portions. Furthermore, a group III nitride semiconductor wafer 310 with a high carrier concentration fabricated by OVPE can be used to form a satisfactory ohmic electrode without an alloying process. Avoiding thermal degradation during the alloying process allows surface processes such as cleaning and oxide film removal to be performed without constraints, enabling the fabrication of high-performance, high-yield semiconductor devices.

[0078] (Application Example 2: Selective Etching of Group III Nitride Semiconductor Substrate) An example in which the etching method of the present disclosure is applied to selective etching of a Group III nitride semiconductor substrate is conceptually shown in Figures 9A and 9B. Figure 9A is a schematic cross-sectional view conceptually showing a Group III nitride semiconductor stacked device 400 according to an embodiment of the present disclosure, and Figure 9B is a schematic cross-sectional view conceptually showing an example in which the substrate of the Group III nitride semiconductor stacked device 400 of Figure 9A is etched using the etching method according to an embodiment.

[0079] Field-effect transistors are an example of electronic devices using Group III nitride semiconductors. For example, a high electron mobility transistor (HEMT) is constructed by stacking multiple Group III nitride semiconductor layers with different compositions on a semi-insulating freestanding substrate. In the manufacture of HEMTs, contamination of the substrate surface by Si poses a problem. For example, during the manufacture of HEMTs, surface contaminants such as siloxane can cause high concentrations of Si to be incorporated into the interface between the substrate and the Group III nitride semiconductor layer (epitaxial layer), resulting in the formation of a conductive leak path (Si pile-up).

[0080] Furthermore, in high-frequency devices, a process of thinning the substrate is performed for impedance matching. However, when the substrate is thinned by mechanical grinding / polishing and chemical mechanical polishing (CMP), not only does it require a long processing time, but there is also a risk of damaging the epitaxial layer during processing.

[0081] The above-mentioned problems can be addressed by selectively etching a Group III nitride semiconductor substrate using the etching method according to the embodiment of the present disclosure, thereby enabling the manufacture of a HEMT. A Group III nitride semiconductor stacked device 400 conceptually shown in Figure 9A is configured by successively stacking a high-resistance layer 420, a channel layer 430, and an electron supply layer 440, in this order, on the upper surface of a Group III nitride semiconductor substrate 410 fabricated by OVPE and having a carrier concentration equal to or higher than the etching threshold.

[0082] The high-resistance layer 420 may be formed of, for example, an Fe—GaN buffer layer doped with iron (Fe). The channel layer 430 may be formed of, for example, a GaN layer, and the electron supply layer 440 may be formed of, for example, AlGaN. The high-resistance layer 420, the channel layer 430, and the electron supply layer 440 may be successively stacked on the front surface 410 a of the group III nitride semiconductor substrate 410 in an MOCVD apparatus without being exposed to the outside air.

[0083] After the high-resistance layer 420, the channel layer 430, and the electron supply layer 440 are stacked on the front surface 410a of the III-nitride semiconductor substrate 410, the III-nitride semiconductor substrate 410 can be thinned by electrochemical etching from the back surface 410b. For example, a III-nitride semiconductor substrate 410 fabricated by OVPE and having a carrier concentration equal to or higher than the etching threshold can achieve a high etching rate (FIG. 1).

[0084] During the manufacturing process of the stacked device 400, Si may be incorporated into the front surface 410a of the substrate 410. However, the Si can be removed by etching from the back surface 410b of the substrate 410. This effectively suppresses Si pile-up. Furthermore, the high-resistivity layer 420 stacked on the front surface 410a of the substrate 410 has a low carrier concentration and therefore can essentially function as an etch stop layer. Furthermore, by etching the Group III nitride semiconductor substrate 410 using electrochemical etching, the Group III nitride semiconductor substrate can be thinned in a short time, and the risk of damage to the epitaxial layer that may occur during mechanical grinding / polishing or chemical mechanical polishing (CMP) can be avoided.

[0085] 9B, for example, by etching and removing the central portion of a group III nitride semiconductor substrate 410 having a thickness H2 and leaving a substrate portion 410A having a thickness h2 on the periphery, it is possible to thin the substrate and configure a group III nitride semiconductor stacked device 400A that has sufficient handleability. Furthermore, although not shown, it is also possible to completely remove the group III nitride semiconductor substrate 410 using electrochemical etching, thereby realizing a thin-film, Si pile-up-free GaN-on-GaN HEMT.

[0086] In this way, by selectively etching the Group III nitride semiconductor substrate, it is possible to suppress Si pile-up and thin the Group III nitride semiconductor stacked device at low cost without damaging the high-resistance layer 420, thereby enabling the fabrication of a highly efficient and high-output HEMT device.

[0087] (Application Example 3: Fabrication of N-polarity GaN-HEMT) An example in which the etching method of the present disclosure is applied to fabrication of an N-polarity GaN-HEMT will be described with reference to Figures 10A to 10B3. Figure 10A is a schematic cross-sectional view conceptually showing the configuration of an N-polarity GaN-HEMT 500, and Figures 10B1 to 10B3 are each a diagram conceptually showing one step in the fabrication process of an N-polarity GaN-HEMT 500A using the etching method according to the embodiment.

[0088] Conventionally, nitride semiconductor devices have been fabricated on (0001)-plane (+c-plane) GaN. The wurtzite structure is the most stable phase of nitride semiconductors, which lack inversion symmetry in the c-axis direction. Therefore, the c-plane has polarity, with the (0001) plane (+c-plane) being Ga-polar and the opposite (000-1) plane (-c-plane) being N-polar. Hereinafter, HEMTs using Ga-polar GaN and HEMTs using N-polar GaN will be referred to as "Ga-polar GaN-HEMT" and "N-polar GaN-HEMT" (also known as "inverse HEMT"), respectively.

[0089] In recent years, N-polar GaN has been attracting attention. One reason for this is that power amplifiers for fifth-generation mobile communication systems are required to operate at high frequencies, and N-polar GaN-HEMTs are advantageous for high-frequency operation. As conceptually shown in FIG. 10A , an N-polar GaN-HEMT is constructed by heteroepitaxially growing an AlGaN barrier layer 540 and a GaN channel layer 530 in this order on an N-polar semi-insulating substrate 550. At this time, a two-dimensional electron gas (2DEG) with a high electron density is formed at the heterointerface between the AlGaN barrier layer 540 and the GaN channel layer 530.

[0090] To achieve high-frequency device operation, it is necessary to shorten the distance between the gate electrode and the channel. In a Ga-polar GaN-HEMT structure, for example, referring to the device 400 in FIG. 9A as an example of a Ga-polar device configuration, the AlGaN barrier layer (electron supply layer 440) on the channel layer 430 must be thinned to shorten the distance between the gate electrode and the channel. However, as the AlGaN barrier layer becomes thinner, the electron concentration in the 2DEG also decreases, resulting in an increase in electrical resistance. Therefore, in a Ga-polar GaN-HEMT structure, it is difficult to achieve a short channel due to the trade-off between operating frequency and electrical resistance.

[0091] 10A, the distance between the gate electrode 570b and the channel can be shortened by thinning the top GaN channel layer 530 without using the AlGaN barrier layer 540. Therefore, the channel can be shortened while maintaining the thickness of the AlGaN barrier layer 540. Furthermore, in the N-polar GaN-HEMT structure, as shown in the figure, the AlGaN barrier layer 540 is disposed below the GaN channel layer 530, so that the 2DEG is tightly confined in the GaN channel layer 530, and low contact resistance can be expected because the top layer is GaN.

[0092] To commercialize N-polar GaN devices, which are currently attracting attention, high-quality N-polar GaN epitaxial growth technology is required. However, GaN epitaxial growth in the N-polar direction (-C direction) poses significant challenges. One of the challenges is that N-polar GaN is prone to hillock formation on its surface, making it difficult to obtain a flat surface. Furthermore, among the residual impurities that contaminate N-polar GaN, oxygen is the most highly concentrated impurity, and N-polar GaN tends to have a higher oxygen concentration than Ga-polar GaN. Oxygen acts as a shallow donor and adversely affects device characteristics. Therefore, achieving high purity of N-polar GaN crystals is also one of the factors hindering practical application.

[0093] Therefore, by applying the etching method according to the embodiment of the present disclosure, it is possible to fabricate an N-polarity GaN-HEMT while addressing the above-mentioned problems. Hereinafter, a fabrication process for an N-polarity GaN-HEMT 500A using the etching method according to the embodiment of the present disclosure will be described with reference to FIGS. 10B1 to 10B3. In this fabrication process, the N-polarity GaN-HEMT 500A can be fabricated through steps a to c shown in FIGS. 10B1 to 10B3.

[0094] 10B1, an inverse HEMT structure is epitaxially grown on a Ga-polar GaN substrate. The Ga-polar GaN substrate is, for example, the GaN substrate 510 fabricated by the OVPE method described above and having a carrier concentration equal to or higher than the etching threshold. The inverse HEMT structure can be obtained by heteroepitaxially growing, for example, a GaN channel layer 530, an AlGaN barrier layer 540, and an Fe—GaN buffer layer 520 on the OVPE-Ga-polar GaN substrate 510 in this order.

[0095] 10B2, after bonding the top surface of the inverted HEMT structure obtained in step a to a support substrate 560, the OVPE-Ga-polar GaN substrate 510 is completely removed from the back surface 510b by electrochemical etching. Because the Ga-polar GaN substrate 510 produced by the OVPE method has a carrier concentration equal to or higher than the etching threshold, the Ga-polar GaN substrate 510 can be completely removed in a short time at a high etching rate (FIG. 1), thereby exposing the surface 530a of the GaN channel layer 530. At this time, a portion of the Ga-polar GaN film may be left in the area where the ohmic electrode will be formed.

[0096] Subsequently, in step c shown in FIG. 10B3, a source electrode 570a, a gate electrode 570b, and a drain electrode 570c are formed on the surface 530a of the GaN channel layer 530 exposed in step b, thereby completing the N-polarity GaN-HEMT 500A.

[0097] In the fabrication process for the N-polarity GaN-HEMT conceptually shown in Figures 10B1 to 10B3, epitaxial growth is performed in the Ga-polarity direction (+C direction in the figure), which improves the flatness and purity issues that exist in GaN epitaxial growth in the N-polarity direction (-C direction), thereby achieving high-purity, flat epitaxial growth. Furthermore, the use of a GaN substrate 510 reduces defects during heteroepitaxial growth, enabling higher device output. Furthermore, for example, if the support substrate 560 is made of a highly thermally conductive material such as diamond or SiC, an N-polarity GaN-HEMT with excellent heat dissipation properties can be fabricated.

[0098] As described above, the accompanying drawings and detailed description have been provided to explain exemplary embodiments of the technology disclosed herein. Therefore, the components described in the accompanying drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem in order to illustrate the technology. Therefore, the fact that these non-essential components are described in the accompanying drawings or detailed description should not be interpreted as immediately indicating that these non-essential components are essential.

[0099] Although the present disclosure has been fully described in connection with the preferred embodiments with reference to the accompanying drawings, various modifications are possible within the scope of the claims, and such modifications and embodiments obtained by appropriately combining the technical means disclosed in the different embodiments are also included in the technical scope of the present disclosure.

[0100] The present disclosure is applicable to the manufacture of Group III nitride semiconductor devices. According to the method for etching a Group III nitride semiconductor according to the present disclosure, etching of a Group III nitride semiconductor can be achieved using a simple etching apparatus.

[0101] 20 Counter electrode 30 Electrolyte 40 Container 50 Current detector 60 Power supply unit 100 Source chamber 101 Source reaction chamber 102 First carrier gas supply port 103 Reactive gas supply pipe 104 Source boat 105 Starting Group III element source (starting Ga source) 106 First heater 107 Group III oxide gas outlet 108 Group III oxide gas and carrier gas outlet 109 Connecting pipe 110 Third heater 111 Growth chamber 112 Nitrogen element-containing gas supply port 113 Oxidizable gas supply port 114 Second carrier gas supply port 115 Second heater 116 Support substrate 117 Substrate susceptor 118 Group III oxide gas and carrier gas supply port 119 Exhaust port 126 Group III nitride semiconductor 127 Etching mask 128 Recess 130 Sample 135 HVPE-GaN substrate 136 OVPE-GaN semiconductor layer 150 Group III nitride semiconductor fabrication apparatus 200 Group III nitride semiconductor fabrication process 250 Electrochemical etching apparatus 300 Group III nitride semiconductor device 310 Group III nitride semiconductor wafer 320 Functional layer 330 Electrode 340 Solder 350 Heat dissipation die 400 Group III nitride semiconductor stacked device 410 Group III nitride semiconductor substrate 420 High resistance layer 430 Channel layer 440 Electron supply layer 500 N-polar GaN-HEMT 510 Ga-polar GaN substrate 520 Fe-GaN buffer layer 530 GaN channel layer 540 AlGaN barrier layer 550 N-polar semi-insulating substrate 560 Support substrate 570a Source electrode 570b Gate electrode 570c Drain electrode

Claims

1. 1E+19 / cm ３ a first step of preparing a Group III nitride semiconductor having a carrier concentration of at least 1000 ppm; and a second step of applying a voltage between the Group III nitride semiconductor and a counter electrode while the semiconductor is immersed in an electrolyte solution, thereby etching at least a portion of the Group III nitride semiconductor.

2. The carrier concentration is 5E+19 / cm ３ The method for etching a Group III nitride semiconductor according to claim 1 , wherein:

3. The method for etching a Group III nitride semiconductor according to claim 1 or 2, wherein the first step comprises supplying a nitrogen-containing gas and a Group III element oxide gas into a chamber, and growing a Group III nitride crystal in the chamber to produce the Group III nitride semiconductor.

4. The method for etching a Group III nitride semiconductor according to claim 3, wherein the first step further comprises adjusting the amount of the Group III element oxide gas supplied relative to the amount of the nitrogen-containing gas supplied into the chamber.

5. The method for etching a Group III nitride semiconductor according to claim 1 or 2, wherein the second step has an etching rate of 1 mm / h or more.

6. The method for etching a Group III nitride semiconductor according to claim 1 or 2, wherein the Group III nitride semiconductor is gallium nitride, and the impurity contained in the Group III nitride semiconductor has the highest concentration of any one of oxygen, Ge, and Sn.

7. The method for etching a Group III nitride semiconductor according to claim 6, wherein the impurity with the highest concentration is oxygen.

8. The method for etching a Group III nitride semiconductor according to claim 1 or 2, wherein the Group III nitride semiconductor comprises a semiconductor film, a semiconductor crystal layer, a semiconductor wafer, or a semiconductor substrate containing a nitride of a Group III element.

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