Selective ETCH with passivation tuning

Abstract

A method of etching recessed features in a carbon containing stack below a mask is provided. An etch gas is provided. A passivation gas with a sticking coefficient in a range of 0.0001 to 0.25 is provided. The etch gas and passivation gas are transformed into a plasma. The stack is exposed to the plasma wherein the plasma selectively etches the stack with respect to the mask.

Description

SELECTIVE ETCH WITH PASSIVATION TUNINGCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of U.S. Application No. 63 / 695,715, filed September 17, 2024, which is incorporated herein by reference for all purposes.BACKGROUND

[0002] One process frequently employed during the fabrication of semiconductor devices is the formation of a recessed feature in a stack below a carbon containing mask. The stack may be alternating / repeating layers into which the recessed feature is formed, or a thick film of a single layer of material. Example contexts where such a process may occur are in logic metal contact etch applications or memory applications, such as dynamic random access memory (DRAM), and “not and” devices (NAND). In the manufacturing of some semiconductor devices, metal or other materials may be etched below a carbon containing mask. As the semiconductor industry advances and device dimensions become smaller, such recessed features become increasingly harder to etch in a uniform manner, for both high aspect ratio and low aspect ratio features having nonuniform narrow widths.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] To achieve the foregoing and in accordance with the purpose of the present disclosure, a method of etching recessed features in a carbon containing stack below a mask is provided. An etch gas is provided. A passivation gas with a sticking coefficient in a range of 0.0001 to 0.25 is provided. The etch gas and passivation gas are transformed into a plasma. The stack is exposed to the plasma wherein the plasma selectively etches the stack with respect to the mask.

[0005] In another manifestation, an apparatus for etching a plurality of stacks is provided. A substrate support supports a substrate in a process chamber. A power source provides power in the process chamber. A gas source is in fluid connection with the process chamber and comprises an etch gas source and a passivation gas source. A controller is controllablyconnected to the power source and the gas source and is configured to provide an etch gas, provide a low sticking coefficient passivation gas with a sticking coefficient in a range of 0.0001 to 0.25, transforming the etch gas and passivation gas into a plasma, and exposing the stack to the plasma wherein the plasma selectively etches the stack with respect to a mask.

[0006] These and other features of the present disclosure will be described in more detail below in the detailed description and in conjunction with the following figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0008] FIG. 1 illustrates a schematic cross-sectional illustration of a stack processed according to the prior art.

[0009] FIG. 2 depicts a flow chart describing a method of etching recessed features into a stack below a carbon containing mask according to various embodiments.

[0010] FIGS. 3A-3C illustrate a schematic cross-sectional illustration of a stack processed according to some embodiments.

[0011] FIG. 4 shows a semiconductor processing system that may be used in some embodiments.

[0012] FIG. 5 illustrates a computer system for implementing a controller used in some embodiments.

[0013] In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale.DETAILED DESCRIPTION

[0014] The present disclosure will now be described in detail with reference to a few preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process steps and / or structures have not been described in detail in order to not unnecessarily obscure the present disclosure.

[0015] Fabrication of certain semiconductor devices involves etching features into a stack of materials. In some embodiments, the stack of materials includes one or more layers of one or more materials below a carbon containing mask. In some embodiments, at least one layer of the stack contains at least one of silicon, germanium, and metal. Silicon containing layers may contain silicon nitride, silicon oxide, silicon carbide, silicon oxy-nitride, silicon oxy-carbide, polysilicon, or silicon germanium. In one example, the stack includes alternating layers of silicon oxide and polysilicon (OPOP). In some embodiments, the stack comprises an alternating silicon oxide film with silicon nitride films (ONON), a single silicon oxide layer, or a single silicon layer. In some embodiments, the stack may be a conductive or dielectric layer that may be a metal or silicon containing layer below a carbon containing mask. In some embodiments, the carbon containing mask is a carbon containing at least one of a photoresist, a doped carbon, and an amorphous carbon mask. In some embodiments, the stack is a carbon containing stack, such as having an organic layer. The carbon containing stack may be below a dielectric mask, such as a silicon oxide containing mask.

[0016] The features etched into a stack may be cylinders, trenches, or other recessed features. The aspect ratio of such a feature is defined as the ratio of the depth to the lateral critical dimension. As the aspect ratio of such features continues to increase and / or the CD shrinks, several issues arise including (1) insufficient mask selectivity, (2) etch resolution, (3) twisting of the features, (4) non-circularity of the features, (5) aspect-ratio dependent etch rate, (6) bowing etch profile, (7) low etch rate, (8) lack of local CD uniformity, (9) CD shrink capability, and (10) CD loading between different geometry features.

[0017] Insufficient mask selectivity is problematic when the etch process removes an excessive amount of the carbon containing mask, so that no mask remains at the end of the process, or when the amount of mask remaining is insufficient to properly transfer the pattern from the mask to the stack. One common result of insufficient mask selectivity is the degradation of the feature profile near the top of the recessed features. In order to compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and an overall higher aspect ratio, which causes more issues during the etching of both mask and underlayer materials.

[0018] Twisting refers to random deviations between the intended bottom locations of the features and the actual final bottom locations of the features (e.g., with the final location of afeature corresponding to the position of the bottom of the feature after the feature is etched). For instance, in some cases, it is intended that cylindrical features are etched in a regular array.When some or all features randomly deviate at the bottom away from this array, they are understood to have twisted.

[0019] Non-circularity of the features refers to deviations of the bottom hole shape away from a circular hole shape. This issue is relevant when etching circular features such as cylinders, where it is desired that the bottoms of the recessed features are circular. When the bottom hole shape deviates away from a circular shape, it often forms a shape closer to an ellipse, triangle, or irregular polygon. In many cases, these non-circular shapes are not desirable.

[0020] Aspect-ratio dependent etch rate refers to an issue where the etch rate slows down as the aspect ratio of the features increases. In other words, as the features are etched further into the stack, the etching process slows down. This issue is problematic because it can lead to low throughput and associated high processing costs.

[0021] Bowing etch profile refers to the tendency for the features to etch laterally in the stack such that the final profile bows outwards excessively somewhere along the depth of the features. In other words, the actual maximum critical dimension of the features exceeds the desired maximum critical dimension of the features, which can compromise the integrity of the structures being formed or limit the electrical performance of the final devices.

[0022] Low etch rate refers to an etch rate that is slower than desired for a particular application. Low etch rate is problematic because it leads to long etch times, reduced throughput, and high processing costs.

[0023] CD shrink capability is the ability to shrink features. In applications for forming logic devices, shrinking the CD is used to provide devices with a small CD. Improving CD shrink capability allows for smaller feature sizes, tighter pitch between features, and thus access to higher density arrays.

[0024] CD loading between different geometry features provides improved CD and CD shrink uniformity between devices with different geometries, such as devices of different sizes.

[0025] Lack of local CD uniformity is an increasing problem with the requirement for smaller and smaller feature sizes. With such demand being placed on shrinking features there is simultaneously tighter and tighter requirement for the local CD uniformity as well. Therefore, local CD uniformity is becoming a barrier for future logic applications. In some prior art, theselectivity of etching a stack with respect to a carbon containing mask is increased by using a carbon containing passivant to deposit on the sidewalls of the features and the mask. It has been found that carbon containing passivant selectively deposits nearer the tops of the feature and mask with respect to the bottoms of the features. The selective deposition of carbon containing passivant on the mask and the top of the features causes bread loafing, necking, increased tapering, and etch stop. In order to reduce bread loafing, necking, increased tapering, and etch stop, a carbon etchant, such as oxygen, nitrogen, or another carbon etchant, may be provided to remove some of the carbon passivation. The carbon etchant also etches the mask and causes faceting of the mask. As a result, wider features may have an increased tapering and narrow features less tapering, causing a decrease in local CD uniformity. FIG. 1 is a generated simulation schematic cross-sectional view of a stack 104 that has been etched according to prior art. The stack comprises a substrate 108 under an etch layer 112 under a mask. Sometimes, more passivation is deposited on the side walls at the tops of wide features 140 than on the sidewalls at the tops of narrow features 144, causing the wide features 140 to have more necking than the narrow features 144. This difference in necking between the wide features 140 and narrow features 144 causes a decrease in local CD uniformity. The wide features 140 are wider than the narrow features 144.

[0026] Unfortunately, techniques that improve some of these issues, such as insufficient mask selectivity, often make other issues worse. As such, these issues are balanced against one another when designing an etching operation. For example, conventional commercially practiced dielectric etch processes often result in substantial bowing. Previously, such tradeoffs have been difficult to avoid.

[0027] The techniques described herein may be used to etch recessed features into an etch layer of a stack without some or all of the issues identified above. In other words, the disclosed techniques may be used to etch recessed features into an etch layer of a stack below a mask with a high stack to mask selectivity and with reduced mask twisting, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, with reduced nonuniformity, reduced asymmetric mask shadowing, high local CD uniformity, and sufficient etch rate.

[0028] Some embodiments increase local CD uniformity by reducing mask erosion using a highly selective etch process and by preventing the mask profile from degrading (mask faceting)during etch.Flow Chart

[0029] To facilitate understanding, FIG. 2 is a high level flow chart of a method that may be used in some embodiments. A stack with a mask is provided in a process chamber (step 204). FIG. 3A is a schematic cross-sectional view of a stack 304 that may be processed according to some embodiments, where the stack 304, comprises an etch layer 312 under a mask 316. In some embodiments, the etch layer 312 may be formed over a substrate 308. In some embodiments, the etch layer 312 may comprise a carbon containing material. In some embodiments, the carbon containing material is at least one of amorphous carbon, photoresist, and doped carbon, such as metal doped carbon. In some embodiments, a mask 316 of at least one of silicon oxide (SiOz), silicon oxycarbide (SiOC), and silicon oxynitride (SiON).Etch Process

[0030] In some embodiments, a substrate support that supports the stack 304 is maintained at a temperature in the range of -100° C to 100° C. In some embodiments, the substrate support is maintained at a temperature between -100° C and 60° C. In some embodiments, the substrate support is cooled to a temperature below 0° C. An etch gas is provided (step 208). In some embodiments for the carbon containing stack, the etch gas comprises at least one of oxygen gas (O2) and nitrogen gas (N2). A low sticking coefficient passivation gas is provided (step 212). In some embodiments for a carbon containing stack, the low sticking coefficient passivation gas comprises at least one of boron trichloride (BCh), boron hydride (BH3), dimethyl sulfate (DMS), methanethiol (CH3SH), hydrogen sulfide (H2S), silicon tetrachloride (SiClu), and tetramethylsilane (TMS). In some embodiments, a carrier gas such as an inert gas such as argon (Ar), xenon (Xe), Krypton (Kr), or helium (He), may be provided. In some embodiments the etch gas comprises oxygen gas (O2) and the passivation gas comprises BCI3.

[0031] A plasma is generated from the etch gas and passivation gas (step 216). In some embodiments, the plasma is generated by a periodic waveform signal, such as a radio frequency (RF) waveform with a power between about 0.01-2 kilowatts (kW), for example between about 20-800 W. In some embodiments, the plasma is formed in a process chamber. In some embodiments, the plasma is formed remotely outside of the process chamber and then providedinto the process chamber. In some cases, a dual-frequency RF may be used to generate the plasma. Thus, the RF power may be provided at two or more frequency components, for example, a first frequency component at about 400 kilohertz (kHz) and a second frequency component at about 60 megahertz (MHz). Different powers may be provided at each frequency component. For instance, the first frequency component (e.g., about 400 kHz) may be provided at a power between about 20-300 W, and the second frequency component (e.g., about 60 MHz) may be provided at a different power, for example between about 10-1000 W. The power levels can be scaled linearly based on substrate area for additional substrates and / or substrates of other sizes (thereby maintaining a uniform power density delivered to the substrate). In other cases, three- frequency RF power may be used to generate the plasma.

[0032] In some embodiments, the applied RF power is a continuous RF power. In some embodiments, the applied RF power is pulsed.

[0033] In some embodiments, a bias in the range of 10-1000 W is provided to accelerate ions toward the top surfaces of the stack 304. In some embodiments, a bias in the range of 100 W to 1 kW is provided.

[0034] The stack 304 is exposed to the plasma causing recessed features to be etched into the etch layer 312 of the stack 304 (step 220). FIG. 3B is a schematic cross-sectional view of a stack 304 after wide features 340 and narrow features 344 have been completely etched in the etch layer 312 and the stack 304 is removed from the process chamber. The wide features 340 have about the same taper and necking as the narrow features 344. FIG. 3C is a generated simulation schematic cross-sectional view of a stack 304 that has been etched according to an embodiment. Using a passivation gas with a low sticking coefficient prevents a higher deposition of passivation near the tops of the features reducing necking in both the wide features 340 and narrow features 344 and providing a more uniform necking between the wide features 340 and narrow features 344.

[0035] In some embodiments, a mask opening step is provided before etching the stack and providing the etch gas (step 208). In some embodiments, the mask opening step comprises providing an opening gas comprising at least one of hydrogen fluoride (HF), phosphorus trifluoride (PF3). In some embodiments, the opening gas has a leaner chemistry using less or no fluorocarbon or hydrofluorocarbon resulting in less passivation on the mask and a more vertical mask opening.

[0036] In some embodiments, the low sticking coefficient gas has a sticking coefficient of less than 0.25. In some embodiments, the low sticking coefficient gas has a sticking coefficient in the range of 0.0001 to 0.25. In some embodiments, the low sticking coefficient gas has a sticking coefficient in the range of 0.001 to 0.01. The low sticking coefficient of the passivation gas allows control of necking to be decoupled from other etch characteristics, allowing for improved passivation tuning. If the sticking coefficient is too low, there is not sufficient passivation. Some embodiments provide a more uniform etching for features with different geometries. For example, more etch uniformity is provided between narrow features and wide features.

[0037] In some embodiments, the etch is able to provide some features with a CD of less than 50 nanometers (nm). In some embodiments, the etch is able to provide some features with a CD in the range of 5 to 50 nm. In some embodiments, the etch is able to provide some features with a CD of less than 5 nm. In some embodiments, features may be provided in these CD ranges with an acceptable local CD uniformity(LCDU). LCDU is measured by a top down critical dimension scanning electron microscope (CD-SEM). In some embodiments, about 800-1000 holes are measured and the standard deviation of the CD is calculated. The LCDU is usually quoted as the 3*sigma (or 3*standard deviation of the CD). In the specification and claims an acceptable LCDU is defined as when (LCDU / CD)*100%<5 to 10%.

[0038] In some embodiments, the etch layer 312 comprises silicon and oxygen, such as silicon oxide (SiCb), silicon oxy-nitride (SiON), and silicon oxy-carbide (SiOC). In some embodiments, the stack is a plurality of layers. In some embodiments, the etch layer 312 is a plurality of bilayers, trilayers, or more multiple layers. In some embodiments, the etch layer 312 is a dielectric containing etch layer. In some embodiments, the mask 316 is a carbon containing mask. In some embodiments, with an etch layer that comprises silicon and oxygen, the etch gas is a halogen containing gas. In some embodiment, the halogen containing gas of the etch gas, comprises at least one of HF, nitrogen trifluoride (NF3), a fluorocarbon, and a hydrofluorocarbon. In some embodiments, the low sticking coefficient passivation gas comprises at least one of phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), boron trichloride (BCI3), dichloromethane (DCM), and trifluoroiodomethane (CF3I). In some embodiments, the etch gas comprises hydrogen fluoride (HF) and the passivation gas comprises PF3. In some embodiments, the etch gas is the same as the low sticking coefficient passivation gas.Applications

[0039] One application for the disclosed methods is in the context of forming a vertical NAND. In this case, the material into which the feature is etched may have a repeating layered structure. For instance, the material may include alternating layers of silicon oxide and silicon nitride. In other embodiments, the stack may comprise alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or repeating groups of materials. In various cases, the number of pairs or repeating groups may be between about 10-500 (e.g., between about 20- 1000 individual layers). The feature etched into the stack of layers may have a depth between about 2-15 pm, for example between about 5-9 pm. The feature may have a CD width between about 3-500 nm, for example between about 5-100 nm or between about 5-15 nm.

[0040] As used herein, “high aspect ratio” as applied to features in a substrate refers to a depth to width aspect ratio on the order of approximately 60: 1 or higher. More preferably, this range may include ratios greater than 100: 1, 120:1, 140:1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios, such as 30: 1 , or 10: 1. In some embodiments the features may have a depth from 2 microns (pm) to 20 pm.

[0041] The dimensional / parametric details provided herein, such as high aspect ratio, thickness, width, depth, etc., are for example and illustration only. Based on the disclosure described herein, it should be understood that varying dimensions / parameters may also be applicable or used.APPARATUS

[0042] The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools / processes will be used or conducted together in a common fabrication facility.

[0043] Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, e.g., a substrate having a silicon containing film formed thereon, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or other suitable curing tools; (3) exposing the photoresist to visible or ultraviolet (UV) or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove the resist and thereby patternit using a tool such as a wet bench or a spray developer; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some embodiments, an ashable hard mask layer (such as an amorphous carbon layer) and another suitable hard mask (such as an antireflective layer) may be deposited prior to applying the photoresist.

[0044] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. One of ordinary skill in the art would understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of many stages of integrated circuit fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes the embodiments are implemented on a wafer. However, the embodiments are not so limited. The workpiece may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, micromechanical devices, and the like.

[0045] Unless otherwise defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% with respect to a relevant value.

[0046] FIG. 4 is a schematic view of an etch reactor system 400 that may be used in some embodiments. In some embodiments, an etch reactor system 400 comprises a gas distribution plate 406 providing a gas inlet and an electrostatic chuck (ESC) 408, within an etch (or process) chamber 409, enclosed by a chamber wall 452. Within the etch chamber 409, a stack 304 is positioned over the ESC 408 that is used as a substrate support. A bias may be provided to the ESC 408 from an ESC source 448. A gas source 410 is connected to the etch chamber 409 through the gas distribution plate 406. In some embodiments, the gas source 410 comprises an etch gas source 412, a passivation gas source 416, and a source of other gases 418, such as an inert carrier gas. An ESC temperature controller 450 is connected to the ESC 408. A plasma power source 430 provides periodic waveform power to a lower electrode and / or an upper electrode, which in some embodiments are the ESC 408 and the gas distribution plate 406, respectively. In some embodiments, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally, 2 MHz, and 27 MHz power sources make up the plasma power source 430 and the ESC source448. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be in separate power sources or separate power generators may be connected to different electrodes. For example, the upper electrode may have inner and outer electrodes connected to different power sources. Other arrangements of power sources and electrodes may be used in other embodiments. A controller 435 is controllably connected to the plasma power source 430, the ESC source 448, an exhaust pump 420, and the gas source 410. An example of such an etch chamber is the Vantex® etch system manufactured by Lam Research Corporation of Fremont, CA. The process chamber can be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0047] FIG. 5 is a high level block diagram showing a computer system 500, which is suitable for implementing the controller 435 used in embodiments. The computer system 500 may have many physical forms ranging from an integrated circuit, a printed circuit board, and a small handheld device up to a huge supercomputer. The computer system 500 includes one or more processors 502 and further can include an electronic display device 504 (for displaying graphics, text, and other data), a main memory 506 (e.g., random access memory (RAM)), storage device 508 (e.g., hard disk drive), removable storage device 510 (e.g., optical disk drive), user interface devices 512 (e.g., keyboards, touch screens, keypads, mice or other pointing devices, etc.), and a communications interface 514 (e.g., wireless network interface). The communications interface 514 allows software and data to be transferred between the computer system 500 and external devices via a link. The system may also include a communications infrastructure 516 (e.g., a communications bus, cross-over bar, or network) to which the aforementioned devices / modules are connected.

[0048] Information transferred via communications interface 514 may be in the form of signals such as electronic, electromagnetic, optical, or other signals capable of being received by communications interface 514, via a communications link that carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a radio frequency link, and / or other communications channels. With such a communications interface 514, it is contemplated that the one or more processors 502 might receive information from a network or might output information to the network in the course of performing the abovedescribed method steps. Furthermore, method embodiments may execute solely upon theprocessors or may execute over a network such as the Internet, in conjunction with remote processors that share a portion of the processing.

[0049] The term “non-transient computer readable medium” is used generally to refer to media such as main memory, secondary memory, removable storage, and storage devices, such as hard disks, flash memory, disk drive memory, CD-ROM, and other forms of persistent memory and shall not be construed to cover transitory subject matter, such as carrier waves or signals. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that is executed by a computer using an interpreter. Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.

[0050] In some embodiments, the controller 435 is configured to a) provide an etch gas, b) provide a passivation gas with a low sticking coefficient, v) transform the etch gas and passivation gas into a plasma, and d) expose the stack to the plasma.

[0051] It is to be understood that the configurations and / or approaches described herein are exemplary in nature and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above described processes may be changed. Certain references have been incorporated by reference herein. It is understood that any disclaimers or disavowals made in such references do not necessarily apply to the embodiments described herein. Similarly, any features described as necessary in such references may be omitted in the embodiments herein. The subject matter of the present disclosure includes all novel and nonob vious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.CONCLUSION

[0052] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, permutations, and various substitute equivalents, which fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. It is therefore intendedthat the following appended claims be interpreted as including all such alterations, modifications, permutations, and various substitute equivalents as fall within the true spirit and scope of the present disclosure. As used herein, the phrase “A, B, or C” should be construed to mean a logical (“A OR B OR C”), using a non-exclusive logical “OR,” and should not be construed to mean ‘only one of A or B or C. Each step within a process may be an optional step and is not required. Different embodiments may have one or more steps removed or may provide steps in a different order. In addition, various embodiments may provide different steps simultaneously instead of sequentially.

Claims

CLAIMSWhat is claimed is:

1. A method of etching recessed features in a carbon containing stack below a mask, comprising: a. providing an etch gas; b. providing a passivation gas with a sticking coefficient in a range of 0.0001 to 0.25; c. transforming the etch gas and passivation gas into a plasma; and d. exposing the stack to the plasma wherein the plasma selectively etches the stack with respect to the mask.

2. The method of claim 1, wherein the passivation gas comprises at least one of boron trichloride (BCh), boron hydride (BH3), dimethyl sulfate (DMS), methanethiol (CH3SH), hydrogen sulfide (H2S), silicon tetrachloride (SiCL), and tetramethylsilane (TMS).

3. The method of claim 1, further comprising before a, opening the mask, comprising: providing an opening gas; transforming the opening gas into a plasma; and exposing the stack to the plasma resulting in opening the mask.

4. The method of claim 1, wherein the etch gas comprises at least one of an oxygen containing gas and a nitrogen containing gas.

5. The method of claim 1, wherein the etch gas comprises at least one of oxygen gas and nitrogen gas.

6. A method of etching recessed features in an oxygen and silicon containing stack below a mask, comprising: a. providing an etch gas comprising a halogen containing component; b. providing a passivation gas with a sticking coefficient in a range of 0.0001 toc. transforming the etch gas and passivation gas into a plasma; and d. exposing the stack to the plasma wherein the plasma selectively etches the stack with respect to the mask.

7. The method of claim 6, wherein the passivation gas comprises at least one of phosphorus trifluoride (PF3), phosphorus pentafluoride (PF5), boron trichloride (BCI3), dichloromethane (DCM), and trifluoroiodomethane (CF3I).

8. The method of claim 6, wherein the etch gas comprises at least one of HF and PF3.

9. An apparatus for etching a plurality of stacks, comprising: a process chamber; a substrate support for supporting a substrate in the process chamber; a power source for providing power in the process chamber; a gas source in fluid connection with the process chamber, comprising: a etch gas source; and passivation gas source; and a controller, controllably connected to the power source and the gas source, configured to: a. provide an etch gas; b. provide a low sticking coefficient passivation gas with a sticking coefficient in a range of 0.0001 to 0.25; c. transforming the etch gas and passivation gas into a plasma; and d. exposing the stack to the plasma wherein the plasma selectively etches the stack with respect to a mask.

10. The apparatus, as recited in claim 9, further comprising a temperature controller for controlling a temperature of the substrate support, wherein the controller is controllably connected to the temperature controller, and wherein the controller is further configured to maintain the substrate support at a temperature between -100° C and 60° C.

11. The apparatus, as recited in claim 10, wherein the controller is controllably connected to the temperature controller, and wherein the controller is further configured to provide a bias.

12. The apparatus, as recited in claim 9, wherein the passivation gas source is a source of at least one of boron trichloride (BCh), boron hydride (BH3), dimethyl sulfate (DMS), methanethiol (CH3SH), hydrogen sulfide (H2S), silicon tetrachloride (SiCh), and tetramethylsilane (TMS).

13. The apparatus, as recited in claim 9, wherein the passivation gas source is a source of at least one of phosphorus trifluoride (PF3), phosphorus pentafluoride (PFs), boron trichloride (BCh), dichloromethane (DCM), and trifluoroiodomethane (CF3I).

14. The apparatus, as recited in claim 9, wherein the controller is further configured to open a mask before step a.

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