Control circuit for voltage controlled oscillator of phase locked loop and control method of control circuit

Abstract

The invention discloses a control circuit for a voltage controlled oscillator of a phase locked loop and a control method of the control circuit. In the invention, the phase lock speed of the reference voltage and feedback voltage can be increased, whether the operating frequency determined at the beginning is wrong is accurately and quickly judged, and the operating frequency curve of the voltage controlled oscillator is immediately corrected to the optimal operating frequency curve. The control circuit comprises an operating frequency controller and a judgment unit, wherein the operating frequency controller is used for generating a control code to a voltage controlled oscillator to determine the operating frequency curve of the voltage controlled oscillator; the judgment unit is used for generating a judgment signal to the operating frequency controller according to the voltage control signal which is input to the voltage controlled oscillator; and when the frequency is locked, the voltage controlled oscillator operates as a first operating frequency curve, and the operating frequency controller respectively generates a first control code and a second control code, so that the voltage controlled oscillator respectively operates as the second operating frequency curve and the first operating frequency curve.

Description

technical field [0001] The present invention relates to a phase-locked loop, in particular to a control circuit of a voltage-controlled oscillator, a control method of a voltage-controlled oscillator, a phase-locked loop with fast phase convergence, and a phase-locked method with fast phase convergence. Background technique [0002] In the Global System for Mobile Communications (GSM), the transmission and reception of packets are performed alternately, and the transmission and reception of packets use different frequencies, that is, when the GSM system uses a first frequency for transmission After the packet is completed, a phase-locked loop needs to be used to generate a frequency signal having a second frequency, and then the second frequency is used to receive the packet. However, in the GSM specification, there is only a short time (about 300us) between the transmission and reception of the packet to use the phase-locked loop to generate the frequency signal with the se...

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Problems solved by technology

Therefore, generally speaking, the phase-locked loop 100 needs to convert the feedback signal V within 150us~170us fb with reference signal V ref The phases of are adjusted to be the same (that is, figure 2 The tx2 shown is less than 170us), but, as in the above example, at the reference voltage V ref and feedback signal V fb The phase difference is close to 360, the light is the reference voltage V ref The phase catches up with the feedback signal V fb The time tx1 required for the phase needs about 30us. In addition, the output signal V in the GSM system specification osc The precision must be within 0.1ppm, therefore, the phase-locked loop 100 also needs a considerable time to control the voltage V ctrl (or the filtered control voltage V’ ctrl ) voltage level converges, that is, the time point t A The time between the end of the convergence will be very long, therefore, it is possible to violate the GSM system specification requirements because the phase-locking time of the phase-locked loop 100 is too long

And too long lock time will also increase power consumption and compress the correction time allowed by other components in the GSM system, such as DC offset correction

[0008] In addition, a paper "A fast acquisition phase frequency detector for phase-locked loops" in "Proceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2008" mentioned that it can shorten figure 2 time tx1 method shown, however, the method mentioned in this paper is only applicable to the reference voltage V ref and feedback signal V fb When the phase difference is between 180°~360°, therefore, the phase locking time of the phase-locked loop 100 cannot be greatly and comprehensively shortened

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