Data transmission and processing method and device

Abstract

The invention discloses a data transmission and processing method and a data transmission and processing device for eliminating data burst caused by massive lost packet compensation through pseudo wire emulation edge to edge (PWE3) equipment and smoothing the read-write bandwidth utilization rate of an external synchronous dynamic random access memory (SDRAM) so as to improve the integral processing performance of a chip. The data transmission and processing method comprises the following steps of: when data packet loss happens on a time division multiplexing over IP (TDMoIP) data packet transmission channel, recording the TDMoIP data packet transmission channel of the data packet loss; and when the SDRAM is idle, performing data packet compensation on the TDMoIP data packet transmission channel of the data packet loss, and sending the compensated data packets to the SDRAM for processing.

Description

technical field [0001] The present invention relates to the field of communication technologies, in particular to a data transmission processing method and device. Background technique [0002] The end-to-end Pseudo Wire Emulation Edge to Edge (PWE3) working group under the Internet Engineering Task Force (IETF) is dedicated to the research of emulating layer-1 and layer-2 services on a packet-switching network. The PWE3 mechanism provides the possibility to transmit time-division multiplexing (TDM) services in packet networks. [0003] Transmission of TDM (Time Division Multiplexing over Packet, TDMoP) over IP network is a specific implementation technology under the PWE3 mechanism. Transmit TDM services such as quasi-synchronous / synchronous digital hierarchy (PDH / SDH) on switching (MPLS) packet network, metropolitan Ethernet (MEF) and other networks. [0004] PWE3 network reference model such as figure 1 As shown, the PWE3 device completes the circuit emulation function...

AI Technical Summary

Problems solved by technology

[0020] In the prior art, according to the stipulations of the serial protocols of circuit emulation, when a PSN packet data packet is lost, it needs to be filled with the same amount of specific data. The basic processing block diagram is as follows: Figure 4 As shown, first the decapsulation module completes the decapsulation of the data packet, and then sends it to the packet loss detection and compensation module to detect the loss of the PSN packet. data, so when the network performance drops, a large number of PSN packet data packets will be lost in multiple bundle channels at the same time. It can be filled in a burst without pre-filling, and the multi-channel data volume is many times that of a single channel), which will occupy most or even all of the bandwidth of the external cache Synchronous Dynamic Random Access Memory (SDRAM). This makes the already tight SDRAM bandwidth even more tense, resulting in poor chip processing performance, which in turn causes PSN packet loss and affects system performance.

Moreover, when no PSN packet data packet enters the chip, it will also cause the SDRAM processing bandwidth to be idle, wasting the processing bandwidth

Images